@@ -98,14 +98,14 BEGIN -- beh | |||||
98 | BEGIN |
|
98 | BEGIN | |
99 | IF HRESETn = '0' THEN |
|
99 | IF HRESETn = '0' THEN | |
100 | reg_ftt.MEM_IN_SM_wData <= (OTHERS => '0'); |
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100 | reg_ftt.MEM_IN_SM_wData <= (OTHERS => '0'); | |
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101 | ||||
101 | reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); |
|
102 | reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); | |
102 |
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103 | reg_ftt.out_ren <= (OTHERS => '1'); | ||
103 | reg_ftt.out_ren <= (OTHERS => '1'); |
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|||
104 |
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104 | |||
105 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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105 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
106 |
|
106 | |||
107 | reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); |
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107 | reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); | |
108 | reg_ftt.out_ren <= (OTHERS => '1'); |
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108 | reg_ftt.out_ren <= (OTHERS => '1'); | |
109 |
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109 | |||
110 | paddr := "000000"; |
|
110 | paddr := "000000"; | |
111 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
111 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |
@@ -142,13 +142,21 BEGIN -- beh | |||||
142 | WHEN "000010" => reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2) <= apbi.pwdata(31 DOWNTO 0); |
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142 | WHEN "000010" => reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2) <= apbi.pwdata(31 DOWNTO 0); | |
143 | WHEN "000011" => reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3) <= apbi.pwdata(31 DOWNTO 0); |
|
143 | WHEN "000011" => reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3) <= apbi.pwdata(31 DOWNTO 0); | |
144 | WHEN "000100" => reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4) <= apbi.pwdata(31 DOWNTO 0); |
|
144 | WHEN "000100" => reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4) <= apbi.pwdata(31 DOWNTO 0); | |
145 | WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); |
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145 | WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); | |
146 |
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146 | |||
147 | WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); |
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147 | WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); | |
148 |
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148 | |||
149 | WHEN OTHERS => NULL; |
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149 | WHEN OTHERS => NULL; | |
150 | END CASE; |
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150 | END CASE; | |
151 | END IF; |
|
151 | END IF; | |
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152 | ||||
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153 | --IF (apbi.psel(pindex) AND apbi.pwrite AND apbi.penable) = '1' AND paddr(7 DOWNTO 2) = "000101" THEN | |||
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154 | -- reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); | |||
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155 | --ELSE | |||
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156 | -- reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); | |||
|
157 | --END IF; | |||
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158 | ||||
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159 | ||||
152 |
|
|
160 | END IF; | |
153 |
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161 | |||
154 | END IF; |
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162 | END IF; | |
@@ -156,6 +164,6 BEGIN -- beh | |||||
156 |
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164 | |||
157 | apbo.pindex <= pindex; |
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165 | apbo.pindex <= pindex; | |
158 | apbo.pconfig <= pconfig; |
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166 | apbo.pconfig <= pconfig; | |
159 | apbo.prdata <= prdata; |
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167 | apbo.prdata <= prdata ; | |
160 |
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168 | |||
161 | END beh; |
|
169 | END beh; |
@@ -84,7 +84,7 ARCHITECTURE tb OF testbench_ms IS | |||||
84 | ----------------------------------------------------------------------------- |
|
84 | ----------------------------------------------------------------------------- | |
85 | -- FFT |
|
85 | -- FFT | |
86 | ----------------------------------------------------------------------------- |
|
86 | ----------------------------------------------------------------------------- | |
87 |
TYPE fft_tab_type IS ARRAY ( |
|
87 | TYPE fft_tab_type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
88 | SIGNAL fft_1_re : fft_tab_type; |
|
88 | SIGNAL fft_1_re : fft_tab_type; | |
89 | SIGNAL fft_1_im : fft_tab_type; |
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89 | SIGNAL fft_1_im : fft_tab_type; | |
90 | SIGNAL fft_2_re : fft_tab_type; |
|
90 | SIGNAL fft_2_re : fft_tab_type; | |
@@ -101,7 +101,19 ARCHITECTURE tb OF testbench_ms IS | |||||
101 | SIGNAL counter_3 : INTEGER; |
|
101 | SIGNAL counter_3 : INTEGER; | |
102 | SIGNAL counter_4 : INTEGER; |
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102 | SIGNAL counter_4 : INTEGER; | |
103 | SIGNAL counter_5 : INTEGER; |
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103 | SIGNAL counter_5 : INTEGER; | |
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104 | ||||
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105 | SIGNAL not_full : STD_LOGIC; | |||
104 |
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106 | |||
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107 | TYPE ms_component_tab_type IS ARRAY (0 TO 1, 127 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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108 | TYPE spectral_matrix_type IS ARRAY (0 TO 5, 0 TO 5) OF ms_component_tab_type; | |||
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109 | ||||
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110 | SIGNAL spectral_matrix_data : spectral_matrix_type; | |||
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111 | ||||
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112 | CONSTANT DIRAC_FREQ : INTEGER := 0; | |||
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113 | CONSTANT DIRAC_FREQ2 : INTEGER := 10; | |||
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114 | CONSTANT DIRAC_FREQ3 : INTEGER := 127; | |||
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115 | CONSTANT FFT_RE : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0020"; | |||
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116 | CONSTANT FFT_IM : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0010"; | |||
105 |
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117 | |||
106 | BEGIN -- tb |
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118 | BEGIN -- tb | |
107 |
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119 | |||
@@ -112,7 +124,7 BEGIN -- tb | |||||
112 | PROCESS (clk, rstn) |
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124 | PROCESS (clk, rstn) | |
113 | BEGIN |
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125 | BEGIN | |
114 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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126 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
115 |
all_data: FOR i IN |
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127 | all_data: FOR i IN 127 DOWNTO 0 LOOP | |
116 | fft_1_re(I) <= (OTHERS => '0'); |
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128 | fft_1_re(I) <= (OTHERS => '0'); | |
117 | fft_1_im(I) <= (OTHERS => '0'); |
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129 | fft_1_im(I) <= (OTHERS => '0'); | |
118 | fft_2_re(I) <= (OTHERS => '0'); |
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130 | fft_2_re(I) <= (OTHERS => '0'); | |
@@ -124,16 +136,45 BEGIN -- tb | |||||
124 | fft_5_re(I) <= (OTHERS => '0'); |
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136 | fft_5_re(I) <= (OTHERS => '0'); | |
125 | fft_5_im(I) <= (OTHERS => '0'); |
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137 | fft_5_im(I) <= (OTHERS => '0'); | |
126 | END LOOP all_data; |
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138 | END LOOP all_data; | |
127 | fft_1_re(8*0) <= x"0fff"; |
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139 | ||
128 | fft_1_im(8*0) <= x"0010"; |
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140 | fft_1_re(DIRAC_FREQ) <= FFT_RE; | |
129 | fft_2_re(8*1) <= x"0010"; |
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141 | fft_1_im(DIRAC_FREQ) <= FFT_IM; | |
130 | fft_2_im(8*1+1) <= x"0040"; |
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142 | fft_1_re(DIRAC_FREQ) <= FFT_RE; | |
131 | fft_3_re(8*2) <= x"0010"; |
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143 | fft_1_im(DIRAC_FREQ) <= FFT_IM; | |
132 | fft_3_im(8*3) <= x"0100"; |
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144 | fft_2_re(DIRAC_FREQ) <= FFT_RE; | |
133 | fft_4_re(8*4) <= x"0001"; |
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145 | fft_2_im(DIRAC_FREQ) <= FFT_IM; | |
134 | fft_4_im(8*5) <= x"0111"; |
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146 | fft_3_re(DIRAC_FREQ) <= FFT_RE; | |
135 | fft_5_re(8*6) <= x"0033"; |
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147 | fft_3_im(DIRAC_FREQ) <= FFT_IM; | |
136 | fft_5_im(8*7) <= x"0444"; |
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148 | fft_4_re(DIRAC_FREQ) <= FFT_RE; | |
|
149 | fft_4_im(DIRAC_FREQ) <= FFT_IM; | |||
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150 | fft_5_re(DIRAC_FREQ) <= FFT_RE; | |||
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151 | fft_5_im(DIRAC_FREQ) <= FFT_IM; | |||
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152 | ||||
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153 | --fft_1_re(DIRAC_FREQ2) <= FFT_RE; | |||
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154 | --fft_1_im(DIRAC_FREQ2) <= FFT_IM; | |||
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155 | --fft_1_re(DIRAC_FREQ2) <= FFT_RE; | |||
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156 | --fft_1_im(DIRAC_FREQ2) <= FFT_IM; | |||
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157 | --fft_2_re(DIRAC_FREQ2) <= FFT_RE; | |||
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158 | --fft_2_im(DIRAC_FREQ2) <= FFT_IM; | |||
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159 | --fft_3_re(DIRAC_FREQ2) <= FFT_RE; | |||
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160 | --fft_3_im(DIRAC_FREQ2) <= FFT_IM; | |||
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161 | --fft_4_re(DIRAC_FREQ2) <= FFT_RE; | |||
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162 | --fft_4_im(DIRAC_FREQ2) <= FFT_IM; | |||
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163 | --fft_5_re(DIRAC_FREQ2) <= FFT_RE; | |||
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164 | --fft_5_im(DIRAC_FREQ2) <= FFT_IM; | |||
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165 | ||||
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166 | --fft_1_re(DIRAC_FREQ3) <= FFT_RE; | |||
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167 | --fft_1_im(DIRAC_FREQ3) <= FFT_IM; | |||
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168 | --fft_1_re(DIRAC_FREQ3) <= FFT_RE; | |||
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169 | --fft_1_im(DIRAC_FREQ3) <= FFT_IM; | |||
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170 | --fft_2_re(DIRAC_FREQ3) <= FFT_RE; | |||
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171 | --fft_2_im(DIRAC_FREQ3) <= FFT_IM; | |||
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172 | --fft_3_re(DIRAC_FREQ3) <= FFT_RE; | |||
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173 | --fft_3_im(DIRAC_FREQ3) <= FFT_IM; | |||
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174 | --fft_4_re(DIRAC_FREQ3) <= FFT_RE; | |||
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175 | --fft_4_im(DIRAC_FREQ3) <= FFT_IM; | |||
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176 | --fft_5_re(DIRAC_FREQ3) <= FFT_RE; | |||
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177 | --fft_5_im(DIRAC_FREQ3) <= FFT_IM; | |||
137 |
|
178 | |||
138 | counter_1 <= 0; |
|
179 | counter_1 <= 0; | |
139 | counter_2 <= 0; |
|
180 | counter_2 <= 0; | |
@@ -141,28 +182,124 BEGIN -- tb | |||||
141 | counter_4 <= 0; |
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182 | counter_4 <= 0; | |
142 | counter_5 <= 0; |
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183 | counter_5 <= 0; | |
143 |
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184 | |||
144 |
|
|
185 | -- MEM_IN_SM_wen <= (OTHERS => '1'); | |
145 | MEM_OUT_SM_ren <= (OTHERS => '1'); |
|
186 | -- MEM_OUT_SM_ren <= (OTHERS => '1'); | |
146 |
|
187 | |||
147 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
188 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
148 | IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN |
|
189 | --IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN | |
149 | counter_1 <= counter_1 + 1; |
|
190 | -- counter_1 <= counter_1 + 1; | |
150 | MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1); |
|
191 | -- MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1); | |
151 | MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1); |
|
192 | -- MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1); | |
152 | MEM_IN_SM_wen(0) <= '0'; |
|
193 | -- MEM_IN_SM_wen(0) <= '0'; | |
153 | ELSE |
|
194 | --ELSE | |
154 | counter_1 <= 0; |
|
195 | -- counter_1 <= 0; | |
155 | MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X'); |
|
196 | -- MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X'); | |
156 |
|
|
197 | -- MEM_IN_SM_wen(0) <= '1'; | |
157 | END IF; |
|
198 | --END IF; | |
158 |
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199 | |||
159 | END IF; |
|
200 | END IF; | |
160 | END PROCESS; |
|
201 | END PROCESS; | |
161 |
|
202 | |||
162 |
|
203 | PROCESS | ||
|
204 | BEGIN -- PROCESS | |||
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205 | WAIT FOR 1 us; | |||
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206 | not_full <= '0'; | |||
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207 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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208 | loop_DATA_write: FOR I IN 0 TO 127 LOOP | |||
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209 | apbi.pwdata <= fft_1_im(I) & fft_1_re(I); | |||
|
210 | apbi.psel(15) <= '1'; | |||
|
211 | apbi.paddr(7 DOWNTO 2) <= "000000"; | |||
|
212 | apbi.penable <= '1'; | |||
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213 | apbi.pwrite <= '1'; | |||
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214 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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215 | ||||
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216 | apbi.pwdata <= fft_2_im(I) & fft_2_re(I); | |||
|
217 | apbi.psel(15) <= '1'; | |||
|
218 | apbi.paddr(7 DOWNTO 2) <= "000001"; | |||
|
219 | apbi.penable <= '1'; | |||
|
220 | apbi.pwrite <= '1'; | |||
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221 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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222 | ||||
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223 | apbi.pwdata <= fft_3_im(I) & fft_3_re(I); | |||
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224 | apbi.psel(15) <= '1'; | |||
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225 | apbi.paddr(7 DOWNTO 2) <= "000010"; | |||
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226 | apbi.penable <= '1'; | |||
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227 | apbi.pwrite <= '1'; | |||
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228 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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229 | ||||
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230 | apbi.pwdata <= fft_4_im(I) & fft_4_re(I); | |||
|
231 | apbi.psel(15) <= '1'; | |||
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232 | apbi.paddr(7 DOWNTO 2) <= "000011"; | |||
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233 | apbi.penable <= '1'; | |||
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234 | apbi.pwrite <= '1'; | |||
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235 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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236 | ||||
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237 | apbi.pwdata <= fft_5_im(I) & fft_5_re(I); | |||
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238 | apbi.psel(15) <= '1'; | |||
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239 | apbi.paddr(7 DOWNTO 2) <= "000100"; | |||
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240 | apbi.penable <= '1'; | |||
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241 | apbi.pwrite <= '1'; | |||
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242 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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243 | ||||
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244 | apbi.pwdata <= X"FFFFFFE0"; | |||
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245 | apbi.psel(15) <= '1'; | |||
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246 | apbi.paddr(7 DOWNTO 2) <= "000101"; | |||
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247 | apbi.penable <= '1'; | |||
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248 | apbi.pwrite <= '1'; | |||
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249 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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250 | ||||
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251 | apbi.pwrite <= '0'; | |||
|
252 | END LOOP loop_DATA_write; | |||
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253 | ||||
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254 | ||||
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255 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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256 | ||||
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257 | not_full <= '0'; | |||
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258 | ||||
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259 | tant_que_not_full: WHILE not_full = '0' LOOP | |||
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260 | -- apbi.pwdata <= X"FFFFFFE0"; | |||
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261 | apbi.psel(15) <= '1'; | |||
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262 | apbi.paddr(7 DOWNTO 2) <= "001000"; | |||
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263 | apbi.penable <= '1'; | |||
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264 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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265 | not_full <= apbo.prdata(3); | |||
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266 | END LOOP tant_que_not_full; | |||
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267 | ||||
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268 | ||||
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269 | all_data_0: FOR I IN 0 TO 127 LOOP | |||
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270 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
|
271 | --apbi.pwdata <= X"FFFFFFFE"; | |||
|
272 | apbi.psel(15) <= '1'; | |||
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273 | apbi.paddr(7 DOWNTO 2) <= "000110"; | |||
|
274 | apbi.penable <= '1'; | |||
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275 | apbi.pwrite <= '0'; | |||
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276 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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277 | apbi.penable <= '0'; | |||
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278 | spectral_matrix_data(0,0)(0,I) <= apbo.prdata; | |||
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279 | spectral_matrix_data(0,0)(1,I) <= (OTHERS => '0'); | |||
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280 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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281 | apbi.pwdata <= X"FFFFFFFE"; | |||
|
282 | apbi.psel(15) <= '1'; | |||
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283 | apbi.paddr(7 DOWNTO 2) <= "001000"; | |||
|
284 | apbi.penable <= '1'; | |||
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285 | apbi.pwrite <= '1'; | |||
|
286 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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287 | apbi.pwrite <= '0'; | |||
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288 | apbi.penable <= '0'; | |||
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289 | WAIT UNTIL clk = '1' AND clk'EVENT; | |||
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290 | END LOOP all_data_0; | |||
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291 | ||||
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292 | ||||
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293 | ||||
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294 | WAIT FOR 100 us; | |||
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295 | ||||
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296 | REPORT "*** END simulation ***" SEVERITY failure; | |||
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297 | WAIT; | |||
|
298 | ||||
|
299 | END PROCESS; | |||
163 |
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300 | |||
164 |
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301 | |||
165 |
|
302 | |||
166 |
|
303 | |||
167 |
|
304 | |||
168 |
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305 | |||
@@ -170,32 +307,32 BEGIN -- tb | |||||
170 | -- MS ------------------------------------------------------------------------ |
|
307 | -- MS ------------------------------------------------------------------------ | |
171 | ------------------------------------------------------------------------------- |
|
308 | ------------------------------------------------------------------------------- | |
172 |
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309 | |||
173 |
|
|
310 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb | |
174 |
|
|
311 | GENERIC MAP ( | |
175 |
|
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312 | pindex => 15, | |
176 |
|
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313 | paddr => 15, | |
177 |
|
|
314 | pmask => 16#fff#) | |
178 |
|
|
315 | PORT MAP ( | |
179 |
|
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316 | HCLK => clk, | |
180 |
|
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317 | HRESETn => rstn, | |
181 |
|
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318 | apbi => apbi, | |
182 |
|
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319 | apbo => apbo, | |
183 |
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320 | |||
184 |
|
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321 | MEM_IN_SM_wData => MEM_IN_SM_wData, | |
185 |
|
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322 | MEM_IN_SM_wen => MEM_IN_SM_wen, | |
186 |
|
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323 | MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, | |
187 |
|
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324 | MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, | |
188 |
|
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325 | MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, | |
189 |
|
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326 | ||
190 |
|
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327 | MEM_OUT_SM_ren => MEM_OUT_SM_ren , | |
191 |
|
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328 | MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , | |
192 |
|
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329 | MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , | |
193 |
|
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330 | MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , | |
194 |
|
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331 | MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); | |
195 |
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332 | |||
196 | lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb |
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333 | lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb | |
197 | GENERIC MAP ( |
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334 | GENERIC MAP ( | |
198 |
Mem_use => use_ |
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335 | Mem_use => use_RAM)-- use_RAM use_CEL | |
199 | PORT MAP ( |
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336 | PORT MAP ( | |
200 | clk => clk, |
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337 | clk => clk, | |
201 | rstn => rstn, |
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338 | rstn => rstn, |
@@ -19,57 +19,66 | |||||
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | LIBRARY ieee; | |
23 |
|
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23 | USE ieee.std_logic_1164.ALL; | |
24 |
|
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24 | USE IEEE.numeric_std.ALL; | |
25 |
|
25 | |||
26 | entity RAM_CEL is |
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26 | ENTITY RAM_CEL IS | |
27 | generic(DataSz : integer range 1 to 32 := 8; |
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27 | GENERIC( | |
28 | abits : integer range 2 to 12 := 8); |
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28 | DataSz : INTEGER RANGE 1 TO 32 := 8; | |
29 | port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out |
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29 | abits : INTEGER RANGE 2 TO 12 := 8); | |
30 | std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; |
|
30 | PORT( | |
31 | WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in |
|
31 | WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
32 | std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic |
|
32 | RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
33 | ) ; |
|
33 | WEN, REN : IN STD_LOGIC; | |
34 | end RAM_CEL; |
|
34 | WADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0); | |
|
35 | RADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0); | |||
|
36 | RWCLK, RESET : IN STD_LOGIC | |||
|
37 | ) ; | |||
|
38 | END RAM_CEL; | |||
35 |
|
39 | |||
36 |
|
40 | |||
37 |
|
41 | |||
38 | architecture ar_RAM_CEL of RAM_CEL is |
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42 | ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS | |
39 |
|
43 | |||
40 | constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0'); |
|
44 | CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0'); | |
41 | constant MAX : integer := 2**(abits); |
|
45 | CONSTANT MAX : INTEGER := 2**(abits); | |
42 |
|
46 | |||
43 | type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0); |
|
47 | TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
44 |
|
48 | |||
45 |
|
|
49 | SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit); | |
46 | signal RD_int : std_logic_vector(DataSz-1 downto 0); |
|
50 | SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
|
51 | ||||
|
52 | SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); | |||
47 |
|
53 | |||
48 | begin |
|
54 | BEGIN | |
49 |
|
55 | |||
50 |
RD_int |
|
56 | RD_int <= RAMarray(to_integer(UNSIGNED(RADDR))); | |
51 |
|
57 | |||
52 |
|
58 | |||
53 |
|
|
59 | PROCESS(RWclk, reset) | |
54 | begin |
|
60 | BEGIN | |
55 |
|
|
61 | IF reset = '0' THEN | |
56 |
|
|
62 | RD <= VectInit; | |
57 | rst:for i in 0 to MAX-1 loop |
|
63 | rst : FOR i IN 0 TO MAX-1 LOOP | |
58 |
RAMarray(i) |
|
64 | RAMarray(i) <= (OTHERS => '0'); | |
59 | end loop; |
|
65 | END LOOP; | |
60 |
|
66 | |||
61 | elsif RWclk'event and RWclk = '1' then |
|
67 | ELSIF RWclk'EVENT AND RWclk = '1' THEN | |
62 |
|
|
68 | -- IF REN = '0' THEN | |
63 |
|
|
69 | RD <= RD_int; | |
64 | end if; |
|
70 | -- END IF; | |
|
71 | IF REN = '0' THEN | |||
|
72 | RADDR_reg <= RADDR; | |||
|
73 | END IF; | |||
|
74 | ||||
|
75 | IF WEN = '0' THEN | |||
|
76 | RAMarray(to_integer(UNSIGNED(WADDR))) <= WD; | |||
|
77 | END IF; | |||
65 |
|
78 | |||
66 | if WEN = '0' then |
|
79 | END IF; | |
67 | RAMarray(to_integer(unsigned(WADDR))) <= WD; |
|
80 | END PROCESS; | |
68 | end if; |
|
81 | END ar_RAM_CEL; | |
69 |
|
||||
70 | end if; |
|
|||
71 | end process; |
|
|||
72 | end ar_RAM_CEL; |
|
|||
73 |
|
82 | |||
74 |
|
83 | |||
75 |
|
84 |
@@ -42,7 +42,11 ARCHITECTURE beh OF MS_calculation IS | |||||
42 | CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; |
|
42 | CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; | |
43 | CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; |
|
43 | CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; | |
44 |
|
44 | |||
45 |
|
45 | SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); | ||
|
46 | CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; | |||
|
47 | CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; | |||
|
48 | CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; | |||
|
49 | CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; | |||
46 |
|
50 | |||
47 | SIGNAL select_op1 : STD_LOGIC; |
|
51 | SIGNAL select_op1 : STD_LOGIC; | |
48 | SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; |
|
52 | SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; | |
@@ -56,10 +60,21 ARCHITECTURE beh OF MS_calculation IS | |||||
56 | SIGNAL res_wen_reg1 : STD_LOGIC; |
|
60 | SIGNAL res_wen_reg1 : STD_LOGIC; | |
57 | SIGNAL res_wen_reg2 : STD_LOGIC; |
|
61 | SIGNAL res_wen_reg2 : STD_LOGIC; | |
58 | --SIGNAL res_wen_reg3 : STD_LOGIC; |
|
62 | --SIGNAL res_wen_reg3 : STD_LOGIC; | |
|
63 | ||||
|
64 | SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
59 |
|
65 | |||
60 | BEGIN |
|
66 | BEGIN | |
61 |
|
67 | |||
62 |
|
68 | |||
|
69 | PROCESS (clk, rstn) | |||
|
70 | BEGIN -- PROCESS | |||
|
71 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
72 | fifo_in_ren <= "11"; | |||
|
73 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
74 | fifo_in_ren <= fifo_in_ren_s; | |||
|
75 | END IF; | |||
|
76 | END PROCESS; | |||
|
77 | ||||
63 |
|
|
78 | ||
64 | PROCESS (clk, rstn) |
|
79 | PROCESS (clk, rstn) | |
65 | BEGIN |
|
80 | BEGIN | |
@@ -68,16 +83,18 BEGIN | |||||
68 | correlation_begin <= '0'; |
|
83 | correlation_begin <= '0'; | |
69 | correlation_done <= '0'; |
|
84 | correlation_done <= '0'; | |
70 | state <= IDLE; |
|
85 | state <= IDLE; | |
71 | fifo_in_ren <= "11"; |
|
86 | fifo_in_ren_s <= "11"; | |
72 | ALU_CTRL <= ALU_CTRL_NOP; |
|
87 | select_ctrl <= select_ctrl_NOP; | |
|
88 | --ALU_CTRL <= ALU_CTRL_NOP; | |||
73 | select_op1 <= select_R0(0); |
|
89 | select_op1 <= select_R0(0); | |
74 | select_op2 <= select_R0; |
|
90 | select_op2 <= select_R0; | |
75 | res_wen <= '1'; |
|
91 | res_wen <= '1'; | |
76 |
|
92 | |||
77 | ELSIF clk'EVENT AND clk = '1' THEN |
|
93 | ELSIF clk'EVENT AND clk = '1' THEN | |
78 | ALU_CTRL <= ALU_CTRL_NOP; |
|
94 | select_ctrl <= select_ctrl_NOP; | |
|
95 | --ALU_CTRL <= ALU_CTRL_NOP; | |||
79 | correlation_begin <= '0'; |
|
96 | correlation_begin <= '0'; | |
80 | fifo_in_ren <= "11"; |
|
97 | fifo_in_ren_s <= "11"; | |
81 | res_wen <= '1'; |
|
98 | res_wen <= '1'; | |
82 | correlation_done <= '0'; |
|
99 | correlation_done <= '0'; | |
83 | CASE state IS |
|
100 | CASE state IS | |
@@ -89,7 +106,7 BEGIN | |||||
89 | ELSE |
|
106 | ELSE | |
90 | correlation_begin <= '1'; |
|
107 | correlation_begin <= '1'; | |
91 | state <= S1a; |
|
108 | state <= S1a; | |
92 | fifo_in_ren <= "10"; |
|
109 | fifo_in_ren_s <= "10"; | |
93 | END IF; |
|
110 | END IF; | |
94 | ELSE |
|
111 | ELSE | |
95 | IF fifo_out_full = '1' THEN |
|
112 | IF fifo_out_full = '1' THEN | |
@@ -97,7 +114,7 BEGIN | |||||
97 | ELSE |
|
114 | ELSE | |
98 | correlation_begin <= '1'; |
|
115 | correlation_begin <= '1'; | |
99 | state <= S1; |
|
116 | state <= S1; | |
100 | fifo_in_ren <= "00"; |
|
117 | fifo_in_ren_s <= "00"; | |
101 | END IF; |
|
118 | END IF; | |
102 | END IF; |
|
119 | END IF; | |
103 | END IF; |
|
120 | END IF; | |
@@ -109,32 +126,36 BEGIN | |||||
109 | IF fifo_out_full = '0' THEN |
|
126 | IF fifo_out_full = '0' THEN | |
110 | correlation_begin <= '1'; |
|
127 | correlation_begin <= '1'; | |
111 | state <= S1; |
|
128 | state <= S1; | |
112 | fifo_in_ren <= "00"; |
|
129 | fifo_in_ren_s <= "00"; | |
113 | END IF; |
|
130 | END IF; | |
114 | WHEN S1 => |
|
131 | WHEN S1 => | |
115 | ALU_CTRL <= ALU_CTRL_MULT; |
|
132 | select_ctrl <= select_ctrl_MULT; | |
|
133 | --ALU_CTRL <= ALU_CTRL_MULT; | |||
116 | select_op1 <= select_R0(0); |
|
134 | select_op1 <= select_R0(0); | |
117 | select_op2 <= select_R1; |
|
135 | select_op2 <= select_R1; | |
118 | state <= S2; |
|
136 | state <= S2; | |
119 | WHEN S2 => |
|
137 | WHEN S2 => | |
120 | ALU_CTRL <= ALU_CTRL_MAC; |
|
138 | select_ctrl <= select_ctrl_MAC; | |
|
139 | --ALU_CTRL <= ALU_CTRL_MAC; | |||
121 | select_op1 <= select_I0(0); |
|
140 | select_op1 <= select_I0(0); | |
122 | select_op2 <= select_I1; |
|
141 | select_op2 <= select_I1; | |
123 | res_wen <= '0'; |
|
142 | res_wen <= '0'; | |
124 | state <= S3; |
|
143 | state <= S3; | |
125 | WHEN S3 => |
|
144 | WHEN S3 => | |
126 | ALU_CTRL <= ALU_CTRL_MULT; |
|
145 | select_ctrl <= select_ctrl_MULT; | |
|
146 | --ALU_CTRL <= ALU_CTRL_MULT; | |||
127 | select_op1 <= select_I0(0); |
|
147 | select_op1 <= select_I0(0); | |
128 | select_op2 <= select_R1; |
|
148 | select_op2 <= select_R1; | |
129 | state <= S4; |
|
149 | state <= S4; | |
130 | WHEN S4 => |
|
150 | WHEN S4 => | |
131 | ALU_CTRL <= ALU_CTRL_MACn; |
|
151 | select_ctrl <= select_ctrl_MACn; | |
|
152 | --ALU_CTRL <= ALU_CTRL_MACn; | |||
132 | select_op1 <= select_R0(0); |
|
153 | select_op1 <= select_R0(0); | |
133 | select_op2 <= select_I1; |
|
154 | select_op2 <= select_I1; | |
134 | res_wen <= '0'; |
|
155 | res_wen <= '0'; | |
135 | IF fifo_in_empty = "00" THEN |
|
156 | IF fifo_in_empty = "00" THEN | |
136 | state <= S1; |
|
157 | state <= S1; | |
137 | fifo_in_ren <= "00"; |
|
158 | fifo_in_ren_s <= "00"; | |
138 | ELSE |
|
159 | ELSE | |
139 | correlation_done <= '1'; |
|
160 | correlation_done <= '1'; | |
140 | state <= IDLE; |
|
161 | state <= IDLE; | |
@@ -149,21 +170,23 BEGIN | |||||
149 | IF fifo_out_full = '0' THEN |
|
170 | IF fifo_out_full = '0' THEN | |
150 | correlation_begin <= '1'; |
|
171 | correlation_begin <= '1'; | |
151 | state <= S1a; |
|
172 | state <= S1a; | |
152 | fifo_in_ren <= "10"; |
|
173 | fifo_in_ren_s <= "10"; | |
153 | END IF; |
|
174 | END IF; | |
154 | WHEN S1a => |
|
175 | WHEN S1a => | |
155 | ALU_CTRL <= ALU_CTRL_MULT; |
|
176 | select_ctrl <= select_ctrl_MULT; | |
|
177 | --ALU_CTRL <= ALU_CTRL_MULT; | |||
156 | select_op1 <= select_R0(0); |
|
178 | select_op1 <= select_R0(0); | |
157 | select_op2 <= select_R0; |
|
179 | select_op2 <= select_R0; | |
158 | state <= S2a; |
|
180 | state <= S2a; | |
159 | WHEN S2a => |
|
181 | WHEN S2a => | |
160 | ALU_CTRL <= ALU_CTRL_MAC; |
|
182 | select_ctrl <= select_ctrl_MAC; | |
|
183 | --ALU_CTRL <= ALU_CTRL_MAC; | |||
161 | select_op1 <= select_I0(0); |
|
184 | select_op1 <= select_I0(0); | |
162 | select_op2 <= select_I0; |
|
185 | select_op2 <= select_I0; | |
163 | res_wen <= '0'; |
|
186 | res_wen <= '0'; | |
164 | IF fifo_in_empty(0) = '0' THEN |
|
187 | IF fifo_in_empty(0) = '0' THEN | |
165 | state <= S1a; |
|
188 | state <= S1a; | |
166 | fifo_in_ren <= "10"; |
|
189 | fifo_in_ren_s <= "10"; | |
167 | ELSE |
|
190 | ELSE | |
168 | correlation_done <= '1'; |
|
191 | correlation_done <= '1'; | |
169 | state <= IDLE; |
|
192 | state <= IDLE; | |
@@ -176,6 +199,11 BEGIN | |||||
176 | END IF; |
|
199 | END IF; | |
177 | END PROCESS; |
|
200 | END PROCESS; | |
178 |
|
201 | |||
|
202 | ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE | |||
|
203 | ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE | |||
|
204 | ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE | |||
|
205 | ALU_CTRL_MACn; | |||
|
206 | ||||
179 |
|
|
207 | OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE | |
180 | fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE |
|
208 | fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE | |
181 |
|
209 |
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