diff --git a/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd b/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd --- a/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd +++ b/designs/MINI-LFR_testMS/lpp_lfr_apbreg.vhd @@ -98,14 +98,14 @@ BEGIN -- beh BEGIN IF HRESETn = '0' THEN reg_ftt.MEM_IN_SM_wData <= (OTHERS => '0'); + reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); - - reg_ftt.out_ren <= (OTHERS => '1'); + reg_ftt.out_ren <= (OTHERS => '1'); ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); - reg_ftt.out_ren <= (OTHERS => '1'); + reg_ftt.out_ren <= (OTHERS => '1'); paddr := "000000"; paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); @@ -142,13 +142,21 @@ BEGIN -- beh WHEN "000010" => reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2) <= apbi.pwdata(31 DOWNTO 0); WHEN "000011" => reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3) <= apbi.pwdata(31 DOWNTO 0); WHEN "000100" => reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4) <= apbi.pwdata(31 DOWNTO 0); - WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); + WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); - WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); + WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0); WHEN OTHERS => NULL; END CASE; END IF; + + --IF (apbi.psel(pindex) AND apbi.pwrite AND apbi.penable) = '1' AND paddr(7 DOWNTO 2) = "000101" THEN + -- reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0); + --ELSE + -- reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1'); + --END IF; + + END IF; END IF; @@ -156,6 +164,6 @@ BEGIN -- beh apbo.pindex <= pindex; apbo.pconfig <= pconfig; - apbo.prdata <= prdata; + apbo.prdata <= prdata ; END beh; diff --git a/designs/MINI-LFR_testMS/testbench_ms.vhd b/designs/MINI-LFR_testMS/testbench_ms.vhd --- a/designs/MINI-LFR_testMS/testbench_ms.vhd +++ b/designs/MINI-LFR_testMS/testbench_ms.vhd @@ -84,7 +84,7 @@ ARCHITECTURE tb OF testbench_ms IS ----------------------------------------------------------------------------- -- FFT ----------------------------------------------------------------------------- - TYPE fft_tab_type IS ARRAY (255 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); + TYPE fft_tab_type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL fft_1_re : fft_tab_type; SIGNAL fft_1_im : fft_tab_type; SIGNAL fft_2_re : fft_tab_type; @@ -101,7 +101,19 @@ ARCHITECTURE tb OF testbench_ms IS SIGNAL counter_3 : INTEGER; SIGNAL counter_4 : INTEGER; SIGNAL counter_5 : INTEGER; + + SIGNAL not_full : STD_LOGIC; + TYPE ms_component_tab_type IS ARRAY (0 TO 1, 127 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + TYPE spectral_matrix_type IS ARRAY (0 TO 5, 0 TO 5) OF ms_component_tab_type; + + SIGNAL spectral_matrix_data : spectral_matrix_type; + + CONSTANT DIRAC_FREQ : INTEGER := 0; + CONSTANT DIRAC_FREQ2 : INTEGER := 10; + CONSTANT DIRAC_FREQ3 : INTEGER := 127; + CONSTANT FFT_RE : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0020"; + CONSTANT FFT_IM : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0010"; BEGIN -- tb @@ -112,7 +124,7 @@ BEGIN -- tb PROCESS (clk, rstn) BEGIN IF rstn = '0' THEN -- asynchronous reset (active low) - all_data: FOR i IN 255 DOWNTO 0 LOOP + all_data: FOR i IN 127 DOWNTO 0 LOOP fft_1_re(I) <= (OTHERS => '0'); fft_1_im(I) <= (OTHERS => '0'); fft_2_re(I) <= (OTHERS => '0'); @@ -124,16 +136,45 @@ BEGIN -- tb fft_5_re(I) <= (OTHERS => '0'); fft_5_im(I) <= (OTHERS => '0'); END LOOP all_data; - fft_1_re(8*0) <= x"0fff"; - fft_1_im(8*0) <= x"0010"; - fft_2_re(8*1) <= x"0010"; - fft_2_im(8*1+1) <= x"0040"; - fft_3_re(8*2) <= x"0010"; - fft_3_im(8*3) <= x"0100"; - fft_4_re(8*4) <= x"0001"; - fft_4_im(8*5) <= x"0111"; - fft_5_re(8*6) <= x"0033"; - fft_5_im(8*7) <= x"0444"; + + fft_1_re(DIRAC_FREQ) <= FFT_RE; + fft_1_im(DIRAC_FREQ) <= FFT_IM; + fft_1_re(DIRAC_FREQ) <= FFT_RE; + fft_1_im(DIRAC_FREQ) <= FFT_IM; + fft_2_re(DIRAC_FREQ) <= FFT_RE; + fft_2_im(DIRAC_FREQ) <= FFT_IM; + fft_3_re(DIRAC_FREQ) <= FFT_RE; + fft_3_im(DIRAC_FREQ) <= FFT_IM; + fft_4_re(DIRAC_FREQ) <= FFT_RE; + fft_4_im(DIRAC_FREQ) <= FFT_IM; + fft_5_re(DIRAC_FREQ) <= FFT_RE; + fft_5_im(DIRAC_FREQ) <= FFT_IM; + + --fft_1_re(DIRAC_FREQ2) <= FFT_RE; + --fft_1_im(DIRAC_FREQ2) <= FFT_IM; + --fft_1_re(DIRAC_FREQ2) <= FFT_RE; + --fft_1_im(DIRAC_FREQ2) <= FFT_IM; + --fft_2_re(DIRAC_FREQ2) <= FFT_RE; + --fft_2_im(DIRAC_FREQ2) <= FFT_IM; + --fft_3_re(DIRAC_FREQ2) <= FFT_RE; + --fft_3_im(DIRAC_FREQ2) <= FFT_IM; + --fft_4_re(DIRAC_FREQ2) <= FFT_RE; + --fft_4_im(DIRAC_FREQ2) <= FFT_IM; + --fft_5_re(DIRAC_FREQ2) <= FFT_RE; + --fft_5_im(DIRAC_FREQ2) <= FFT_IM; + + --fft_1_re(DIRAC_FREQ3) <= FFT_RE; + --fft_1_im(DIRAC_FREQ3) <= FFT_IM; + --fft_1_re(DIRAC_FREQ3) <= FFT_RE; + --fft_1_im(DIRAC_FREQ3) <= FFT_IM; + --fft_2_re(DIRAC_FREQ3) <= FFT_RE; + --fft_2_im(DIRAC_FREQ3) <= FFT_IM; + --fft_3_re(DIRAC_FREQ3) <= FFT_RE; + --fft_3_im(DIRAC_FREQ3) <= FFT_IM; + --fft_4_re(DIRAC_FREQ3) <= FFT_RE; + --fft_4_im(DIRAC_FREQ3) <= FFT_IM; + --fft_5_re(DIRAC_FREQ3) <= FFT_RE; + --fft_5_im(DIRAC_FREQ3) <= FFT_IM; counter_1 <= 0; counter_2 <= 0; @@ -141,28 +182,124 @@ BEGIN -- tb counter_4 <= 0; counter_5 <= 0; - MEM_IN_SM_wen <= (OTHERS => '1'); - MEM_OUT_SM_ren <= (OTHERS => '1'); +-- MEM_IN_SM_wen <= (OTHERS => '1'); +-- MEM_OUT_SM_ren <= (OTHERS => '1'); ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN - counter_1 <= counter_1 + 1; - MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1); - MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1); - MEM_IN_SM_wen(0) <= '0'; - ELSE - counter_1 <= 0; - MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X'); - MEM_IN_SM_wen(0) <= '1'; - END IF; + --IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN + -- counter_1 <= counter_1 + 1; + -- MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1); + -- MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1); + -- MEM_IN_SM_wen(0) <= '0'; + --ELSE + -- counter_1 <= 0; + -- MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X'); + -- MEM_IN_SM_wen(0) <= '1'; + --END IF; END IF; END PROCESS; - + PROCESS + BEGIN -- PROCESS + WAIT FOR 1 us; + not_full <= '0'; + WAIT UNTIL clk = '1' AND clk'EVENT; + loop_DATA_write: FOR I IN 0 TO 127 LOOP + apbi.pwdata <= fft_1_im(I) & fft_1_re(I); + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000000"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + + apbi.pwdata <= fft_2_im(I) & fft_2_re(I); + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000001"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + + apbi.pwdata <= fft_3_im(I) & fft_3_re(I); + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000010"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + + apbi.pwdata <= fft_4_im(I) & fft_4_re(I); + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000011"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + + apbi.pwdata <= fft_5_im(I) & fft_5_re(I); + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000100"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + + apbi.pwdata <= X"FFFFFFE0"; + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000101"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + + apbi.pwrite <= '0'; + END LOOP loop_DATA_write; + + + WAIT UNTIL clk = '1' AND clk'EVENT; + + not_full <= '0'; + + tant_que_not_full: WHILE not_full = '0' LOOP +-- apbi.pwdata <= X"FFFFFFE0"; + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "001000"; + apbi.penable <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + not_full <= apbo.prdata(3); + END LOOP tant_que_not_full; + + + all_data_0: FOR I IN 0 TO 127 LOOP + WAIT UNTIL clk = '1' AND clk'EVENT; + --apbi.pwdata <= X"FFFFFFFE"; + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "000110"; + apbi.penable <= '1'; + apbi.pwrite <= '0'; + WAIT UNTIL clk = '1' AND clk'EVENT; + apbi.penable <= '0'; + spectral_matrix_data(0,0)(0,I) <= apbo.prdata; + spectral_matrix_data(0,0)(1,I) <= (OTHERS => '0'); + WAIT UNTIL clk = '1' AND clk'EVENT; + apbi.pwdata <= X"FFFFFFFE"; + apbi.psel(15) <= '1'; + apbi.paddr(7 DOWNTO 2) <= "001000"; + apbi.penable <= '1'; + apbi.pwrite <= '1'; + WAIT UNTIL clk = '1' AND clk'EVENT; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + WAIT UNTIL clk = '1' AND clk'EVENT; + END LOOP all_data_0; + + + + WAIT FOR 100 us; + + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + + END PROCESS; - + @@ -170,32 +307,32 @@ BEGIN -- tb -- MS ------------------------------------------------------------------------ ------------------------------------------------------------------------------- - --lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb - -- GENERIC MAP ( - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk, - -- HRESETn => rstn, - -- apbi => apbi, - -- apbo => apbo, + lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb + GENERIC MAP ( + pindex => 15, + paddr => 15, + pmask => 16#fff#) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + apbi => apbi, + apbo => apbo, - -- MEM_IN_SM_wData => MEM_IN_SM_wData, - -- MEM_IN_SM_wen => MEM_IN_SM_wen, - -- MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, - -- MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, - -- MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, - - -- MEM_OUT_SM_ren => MEM_OUT_SM_ren , - -- MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , - -- MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , - -- MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , - -- MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); + MEM_IN_SM_wData => MEM_IN_SM_wData, + MEM_IN_SM_wen => MEM_IN_SM_wen, + MEM_IN_SM_Full_out => MEM_IN_SM_Full_out, + MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out, + MEM_IN_SM_locked_out => MEM_IN_SM_locked_out, + + MEM_OUT_SM_ren => MEM_OUT_SM_ren , + MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out , + MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad , + MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 , + MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad); lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb GENERIC MAP ( - Mem_use => use_CEL) + Mem_use => use_RAM)-- use_RAM use_CEL PORT MAP ( clk => clk, rstn => rstn, diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd @@ -19,57 +19,66 @@ -- Author : Alexis Jeandet -- Mail : alexis.jeandet@lpp.polytechnique.fr ------------------------------------------------------------------------------ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.numeric_std.all; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; -entity RAM_CEL is - generic(DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8); - port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out - std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic; - WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in - std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic - ) ; -end RAM_CEL; +ENTITY RAM_CEL IS + GENERIC( + DataSz : INTEGER RANGE 1 TO 32 := 8; + abits : INTEGER RANGE 2 TO 12 := 8); + PORT( + WD : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + RD : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + WEN, REN : IN STD_LOGIC; + WADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0); + RADDR : IN STD_LOGIC_VECTOR(abits-1 DOWNTO 0); + RWCLK, RESET : IN STD_LOGIC + ) ; +END RAM_CEL; -architecture ar_RAM_CEL of RAM_CEL is +ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS -constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0'); -constant MAX : integer := 2**(abits); + CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0'); + CONSTANT MAX : INTEGER := 2**(abits); -type RAMarrayT is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0); + TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); -signal RAMarray : RAMarrayT:=(others => VectInit); -signal RD_int : std_logic_vector(DataSz-1 downto 0); + SIGNAL RAMarray : RAMarrayT := (OTHERS => VectInit); + SIGNAL RD_int : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + + SIGNAL RADDR_reg : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); -begin +BEGIN -RD_int <= RAMarray(to_integer(unsigned(RADDR))); + RD_int <= RAMarray(to_integer(UNSIGNED(RADDR))); -process(RWclk,reset) -begin -if reset = '0' then - RD <= VectInit; -rst:for i in 0 to MAX-1 loop - RAMarray(i) <= (others => '0'); - end loop; + PROCESS(RWclk, reset) + BEGIN + IF reset = '0' THEN + RD <= VectInit; + rst : FOR i IN 0 TO MAX-1 LOOP + RAMarray(i) <= (OTHERS => '0'); + END LOOP; -elsif RWclk'event and RWclk = '1' then - if REN = '0' then - RD <= RD_int; - end if; + ELSIF RWclk'EVENT AND RWclk = '1' THEN +-- IF REN = '0' THEN + RD <= RD_int; +-- END IF; + IF REN = '0' THEN + RADDR_reg <= RADDR; + END IF; + + IF WEN = '0' THEN + RAMarray(to_integer(UNSIGNED(WADDR))) <= WD; + END IF; - if WEN = '0' then - RAMarray(to_integer(unsigned(WADDR))) <= WD; - end if; - -end if; -end process; -end ar_RAM_CEL; + END IF; + END PROCESS; +END ar_RAM_CEL; diff --git a/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd b/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd --- a/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd +++ b/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd @@ -42,7 +42,11 @@ ARCHITECTURE beh OF MS_calculation IS CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; - + SIGNAL select_ctrl : STD_LOGIC_VECTOR(1 DOWNTO 0); + CONSTANT select_ctrl_NOP : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; + CONSTANT select_ctrl_MULT : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; + CONSTANT select_ctrl_MAC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; + CONSTANT select_ctrl_MACn : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; SIGNAL select_op1 : STD_LOGIC; SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; @@ -56,10 +60,21 @@ ARCHITECTURE beh OF MS_calculation IS SIGNAL res_wen_reg1 : STD_LOGIC; SIGNAL res_wen_reg2 : STD_LOGIC; --SIGNAL res_wen_reg3 : STD_LOGIC; + + SIGNAL fifo_in_ren_s : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + fifo_in_ren <= "11"; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + fifo_in_ren <= fifo_in_ren_s; + END IF; + END PROCESS; + PROCESS (clk, rstn) BEGIN @@ -68,16 +83,18 @@ BEGIN correlation_begin <= '0'; correlation_done <= '0'; state <= IDLE; - fifo_in_ren <= "11"; - ALU_CTRL <= ALU_CTRL_NOP; + fifo_in_ren_s <= "11"; + select_ctrl <= select_ctrl_NOP; + --ALU_CTRL <= ALU_CTRL_NOP; select_op1 <= select_R0(0); select_op2 <= select_R0; res_wen <= '1'; ELSIF clk'EVENT AND clk = '1' THEN - ALU_CTRL <= ALU_CTRL_NOP; + select_ctrl <= select_ctrl_NOP; + --ALU_CTRL <= ALU_CTRL_NOP; correlation_begin <= '0'; - fifo_in_ren <= "11"; + fifo_in_ren_s <= "11"; res_wen <= '1'; correlation_done <= '0'; CASE state IS @@ -89,7 +106,7 @@ BEGIN ELSE correlation_begin <= '1'; state <= S1a; - fifo_in_ren <= "10"; + fifo_in_ren_s <= "10"; END IF; ELSE IF fifo_out_full = '1' THEN @@ -97,7 +114,7 @@ BEGIN ELSE correlation_begin <= '1'; state <= S1; - fifo_in_ren <= "00"; + fifo_in_ren_s <= "00"; END IF; END IF; END IF; @@ -109,32 +126,36 @@ BEGIN IF fifo_out_full = '0' THEN correlation_begin <= '1'; state <= S1; - fifo_in_ren <= "00"; + fifo_in_ren_s <= "00"; END IF; WHEN S1 => - ALU_CTRL <= ALU_CTRL_MULT; + select_ctrl <= select_ctrl_MULT; + --ALU_CTRL <= ALU_CTRL_MULT; select_op1 <= select_R0(0); select_op2 <= select_R1; state <= S2; WHEN S2 => - ALU_CTRL <= ALU_CTRL_MAC; + select_ctrl <= select_ctrl_MAC; + --ALU_CTRL <= ALU_CTRL_MAC; select_op1 <= select_I0(0); select_op2 <= select_I1; res_wen <= '0'; state <= S3; WHEN S3 => - ALU_CTRL <= ALU_CTRL_MULT; + select_ctrl <= select_ctrl_MULT; + --ALU_CTRL <= ALU_CTRL_MULT; select_op1 <= select_I0(0); select_op2 <= select_R1; state <= S4; WHEN S4 => - ALU_CTRL <= ALU_CTRL_MACn; + select_ctrl <= select_ctrl_MACn; + --ALU_CTRL <= ALU_CTRL_MACn; select_op1 <= select_R0(0); select_op2 <= select_I1; res_wen <= '0'; IF fifo_in_empty = "00" THEN state <= S1; - fifo_in_ren <= "00"; + fifo_in_ren_s <= "00"; ELSE correlation_done <= '1'; state <= IDLE; @@ -149,21 +170,23 @@ BEGIN IF fifo_out_full = '0' THEN correlation_begin <= '1'; state <= S1a; - fifo_in_ren <= "10"; + fifo_in_ren_s <= "10"; END IF; WHEN S1a => - ALU_CTRL <= ALU_CTRL_MULT; + select_ctrl <= select_ctrl_MULT; + --ALU_CTRL <= ALU_CTRL_MULT; select_op1 <= select_R0(0); select_op2 <= select_R0; state <= S2a; WHEN S2a => - ALU_CTRL <= ALU_CTRL_MAC; + select_ctrl <= select_ctrl_MAC; + --ALU_CTRL <= ALU_CTRL_MAC; select_op1 <= select_I0(0); select_op2 <= select_I0; res_wen <= '0'; IF fifo_in_empty(0) = '0' THEN state <= S1a; - fifo_in_ren <= "10"; + fifo_in_ren_s <= "10"; ELSE correlation_done <= '1'; state <= IDLE; @@ -176,6 +199,11 @@ BEGIN END IF; END PROCESS; + ALU_CTRL <= ALU_CTRL_NOP WHEN select_ctrl = select_ctrl_NOP ELSE + ALU_CTRL_MULT WHEN select_ctrl = select_ctrl_MULT ELSE + ALU_CTRL_MAC WHEN select_ctrl = select_ctrl_MAC ELSE + ALU_CTRL_MACn; + OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE