HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r577:bcb5a865d2bb

LFR-EQM et MINI-LFR x.1.70

pellion -

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r577:bcb5a865d2bb

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lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd created 644 +213 0

@@ -0,0 +1,213
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com
	22	-------------------------------------------------------------------------------
	23	-- 1.0 - initial version
	24	-------------------------------------------------------------------------------
	25	LIBRARY ieee;
	26	USE ieee.std_logic_1164.ALL;
	27	USE ieee.numeric_std.ALL;
	28	LIBRARY grlib;
	29	USE grlib.amba.ALL;
	30	USE grlib.stdlib.ALL;
	31	USE grlib.devices.ALL;
	32
	33	LIBRARY lpp;
	34	USE lpp.lpp_amba.ALL;
	35	USE lpp.apb_devices_list.ALL;
	36	USE lpp.lpp_memory.ALL;
	37	USE lpp.lpp_dma_pkg.ALL;
	38	USE lpp.general_purpose.ALL;
	39	--USE lpp.lpp_waveform_pkg.ALL;
	40	LIBRARY techmap;
	41	USE techmap.gencomp.ALL;
	42
	43
	44	ENTITY lpp_dma_SEND16B_FIFO2DMA IS
	45	GENERIC (
	46	hindex : INTEGER := 2;
	47	vendorid : IN INTEGER := 0;
	48	deviceid : IN INTEGER := 0;
	49	version : IN INTEGER := 0
	50	);
	51	PORT (
	52	clk : IN STD_LOGIC;
	53	rstn : IN STD_LOGIC;
	54
	55	-- AMBA AHB Master Interface
	56	AHB_Master_In : IN AHB_Mst_In_Type;
	57	AHB_Master_Out : OUT AHB_Mst_Out_Type;
	58
	59	-- FIFO Interface
	60	ren : OUT STD_LOGIC;
	61	data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	62
	63	-- Controls
	64	send : IN STD_LOGIC;
	65	valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
	66	done : OUT STD_LOGIC;
	67	address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
	68	);
	69	END;
	70
	71	ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
	72
	73	CONSTANT HConfig : AHB_Config_Type := (
	74	0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
	75	OTHERS => (OTHERS => '0'));
	76
	77	TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
	78	SIGNAL state : AHB_DMA_FSM_STATE;
	79
	80	SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
	81	SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
	82
	83	SIGNAL data_window : STD_LOGIC;
	84	SIGNAL ctrl_window : STD_LOGIC;
	85
	86	SIGNAL bus_request : STD_LOGIC;
	87	SIGNAL bus_lock : STD_LOGIC;
	88
	89	BEGIN
	90
	91	-----------------------------------------------------------------------------
	92	AHB_Master_Out.HCONFIG <= HConfig;
	93	AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
	94	AHB_Master_Out.HINDEX <= hindex;
	95	AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
	96	AHB_Master_Out.HIRQ <= (OTHERS => '0');
	97	AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
	98	AHB_Master_Out.HWRITE <= '1';
	99
	100	--AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
	101
	102	--AHB_Master_Out.HBUSREQ <= bus_request;
	103	--AHB_Master_Out.HLOCK <= data_window;
	104
	105	--bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
	106	-- '1' WHEN ctrl_window = '1' ELSE
	107	-- '0';
	108
	109	--bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
	110	-- '1' WHEN ctrl_window = '1' ELSE '0';
	111
	112	-----------------------------------------------------------------------------
	113	AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
	114	AHB_Master_Out.HWDATA <= ahbdrivedata(data);
	115
	116	-----------------------------------------------------------------------------
	117	--ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
	118	--ren <= NOT beat;
	119	-----------------------------------------------------------------------------
	120	PROCESS (clk, rstn)
	121	BEGIN -- PROCESS
	122	IF rstn = '0' THEN -- asynchronous reset (active low)
	123	state <= IDLE;
	124	done <= '0';
	125	address_counter_reg <= (OTHERS => '0');
	126	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	127	AHB_Master_Out.HBUSREQ <= '0';
	128	AHB_Master_Out.HLOCK <= '0';
	129	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	130	done <= '0';
	131	CASE state IS
	132	WHEN IDLE =>
	133	AHB_Master_Out.HBUSREQ <= '0';
	134	AHB_Master_Out.HLOCK <= '0';
	135	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	136	address_counter_reg <= (OTHERS => '0');
	137	IF send = '1' THEN
	138	AHB_Master_Out.HBUSREQ <= '1';
	139	AHB_Master_Out.HLOCK <= '1';
	140	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	141	state <= s_ARBITER;
	142	END IF;
	143
	144	WHEN s_ARBITER =>
	145	AHB_Master_Out.HBUSREQ <= '1';
	146	AHB_Master_Out.HLOCK <= '1';
	147	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	148	address_counter_reg <= (OTHERS => '0');
	149
	150	IF AHB_Master_In.HGRANT(hindex) = '1' THEN
	151	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	152	state <= s_CTRL;
	153	END IF;
	154
	155	WHEN s_CTRL =>
	156	AHB_Master_Out.HBUSREQ <= '1';
	157	AHB_Master_Out.HLOCK <= '1';
	158	AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
	159	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	160	AHB_Master_Out.HTRANS <= HTRANS_SEQ;
	161	state <= s_CTRL_DATA;
	162	END IF;
	163
	164	WHEN s_CTRL_DATA =>
	165	AHB_Master_Out.HBUSREQ <= '1';
	166	AHB_Master_Out.HLOCK <= '1';
	167	AHB_Master_Out.HTRANS <= HTRANS_SEQ;
	168	IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
	169	address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
	170	END IF;
	171
	172	IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
	173	AHB_Master_Out.HBUSREQ <= '0';
	174	AHB_Master_Out.HLOCK <= '1';--'0';
	175	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	176	state <= s_DATA;
	177	END IF;
	178
	179	WHEN s_DATA =>
	180	AHB_Master_Out.HBUSREQ <= '0';
	181	AHB_Master_Out.HLOCK <= '0';
	182	AHB_Master_Out.HTRANS <= HTRANS_IDLE;
	183	IF AHB_Master_In.HREADY = '1' THEN
	184	state <= IDLE;
	185	done <= '1';
	186	END IF;
	187
	188	WHEN OTHERS => NULL;
	189	END CASE;
	190	END IF;
	191	END PROCESS;
	192
	193	ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
	194	data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
	195	-----------------------------------------------------------------------------
	196	ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
	197
	198	-----------------------------------------------------------------------------
	199	--PROCESS (clk, rstn)
	200	--BEGIN -- PROCESS
	201	-- IF rstn = '0' THEN -- asynchronous reset (active low)
	202	-- address_counter_reg <= (OTHERS => '0');
	203	-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	204	-- address_counter_reg <= address_counter;
	205	-- END IF;
	206	--END PROCESS;
	207
	208	--address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
	209	-- address_counter_reg;
	210	-----------------------------------------------------------------------------
	211
	212
	213	END Behavioral;

designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"020145")  -- aa.bb.cc version
+                  top_lfr_version        => X"020146")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +29 -13

               --
               SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_SEL    : STD_LOGIC_VECTOR(1 DOWNTO 0);
+              SIGNAL nSRAM_READY : STD_LOGIC;
             BEGIN  -- beh
                   NB_APB_SLAVE      => NB_APB_SLAVE,
                   ADDRESS_SIZE      => 20,
                   USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
-                  BYPASS_EDAC_MEMCTRLR => '1',
+                  BYPASS_EDAC_MEMCTRLR => '0',
                   SRBANKSZ          => 9)
                 PORT MAP (
                   clk         => clk_25,
                   nSRAM_WE    => SRAM_nWE,
                   nSRAM_CE    => SRAM_CE_s,
                   nSRAM_OE    => SRAM_nOE,
-                  nSRAM_READY => '1',
+                  nSRAM_READY => nSRAM_READY,
                   SRAM_MBE    => OPEN,
                   apbi_ext    => apbi_ext,
                   apbo_ext    => apbo_ext,
                   ahbi_m_ext  => ahbi_m_ext,
                   ahbo_m_ext  => ahbo_m_ext);
-            IAP:if USE_IAP_MEMCTRL = 1 GENERATE
+              PROCESS (clk_25, rstn_25)
-              SRAM_CE <= not SRAM_CE_s(0);
+              BEGIN  -- PROCESS
-            END GENERATE;
+                IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
+                  nSRAM_READY <= '1';
+                ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
+                  nSRAM_READY <= '1';
+                  IF IO0 = '1' THEN
+                    nSRAM_READY <= '0';
+                  END IF;
+                END IF;
+              END PROCESS;
-            NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
+              IAP:if USE_IAP_MEMCTRL = 1 GENERATE
-              SRAM_CE <=  SRAM_CE_s(0);
+                SRAM_CE <= not SRAM_CE_s(0);
-            END GENERATE;
+              END GENERATE;
+              NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
+                SRAM_CE <=  SRAM_CE_s(0);
+              END GENERATE;
             -------------------------------------------------------------------------------
             -- APB_LFR_MANAGEMENT ---------------------------------------------------------
             -------------------------------------------------------------------------------
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
-                  FIRST_DIVISION   => 374,      -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
+            --      FIRST_DIVISION   => 374,      -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz         => clk_25,
                   resetn_25MHz     => rstn_25,      --      TODO
-                  clk24_576MHz     => clk_24,       -- 49.152MHz/2
+            --      clk24_576MHz     => clk_24,       -- 49.152MHz/2
-                  resetn_24_576MHz => rstn_24,      --      TODO
+            --      resetn_24_576MHz => rstn_24,      --      TODO
                   grspw_tick       => swno.tickout,
                   apbi             => apbi_ext,
                   apbo             => apbo_ext(6),
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000144")  -- aa.bb.cc version
+                  top_lfr_version        => X"000146")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
               observation_reg(31 DOWNTO 12)     <= (OTHERS => '0');
               observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
               observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
-              IO0                               <= rstn_25;
+            --  IO0                               <= rstn_25;
               IO1                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT data_valid
               IO2                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT ready
               IO3                               <= lfr_debug_vector(0);  -- LFR APBREG error_buffer_full

lib/lpp/lpp_dma/DMA_SubSystem.vhd +43 -18

@@ -3,6 +3,7 USE ieee.std_logic_1164.ALL;
3	USE ieee.numeric_std.ALL;	3	USE ieee.numeric_std.ALL;
4		4
5	LIBRARY lpp;	5	LIBRARY lpp;
		6	USE lpp.apb_devices_list.ALL;
6	USE lpp.lpp_ad_conv.ALL;	7	USE lpp.lpp_ad_conv.ALL;
7	USE lpp.iir_filter.ALL;	8	USE lpp.iir_filter.ALL;
8	USE lpp.FILTERcfg.ALL;	9	USE lpp.FILTERcfg.ALL;
@@ -25,7 +26,8 USE GRLIB.DMA2AHB_Package.ALL;
25	ENTITY DMA_SubSystem IS	26	ENTITY DMA_SubSystem IS
26		27
27	GENERIC (	28	GENERIC (
28	hindex : INTEGER := 2);	29	hindex : INTEGER := 2;
		30	CUSTOM_DMA : INTEGER := 1);
29		31
30	PORT (	32	PORT (
31	clk : IN STD_LOGIC;	33	clk : IN STD_LOGIC;
@@ -116,25 +118,48 BEGIN -- beh
116	-----------------------------------------------------------------------------	118	-----------------------------------------------------------------------------
117	-- DMA	119	-- DMA
118	-----------------------------------------------------------------------------	120	-----------------------------------------------------------------------------
119	lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst	121	GR_DMA : IF CUSTOM_DMA = 0 GENERATE
120	GENERIC MAP (	122	lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
121	tech => inferred,	123	GENERIC MAP (
122	hindex => hindex)	124	tech => inferred,
123	PORT MAP (	125	hindex => hindex)
124	HCLK => clk,	126	PORT MAP (
125	~~HRESETn~~ => ~~rstn~~,	127	HCLK => clk,
126	~~run~~ => run,	128	HRESETn => rstn,
127	AHB_Master_In => ahbi,	129	run => run,
128	AHB_Master_~~Out~~ => ahbo,	130	AHB_Master_In => ahbi,
		131	AHB_Master_Out => ahbo,
		132
		133	send => dma_send,
		134	valid_burst => dma_valid_burst,
		135	done => dma_done,
		136	ren => dma_ren,
		137	address => dma_address,
		138	data => dma_data);
		139	END GENERATE GR_DMA;
129		140
130	send => dma_send,	141	LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
131	valid_burst => dma_valid_burst,	142	lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
132	done => dma_done,	143	GENERIC MAP (
133	ren => dma_ren,	144	hindex => hindex,
134	address => dma_address,	145	vendorid => VENDOR_LPP,
135	data => dma_data);	146	deviceid => 10,
		147	version => 0)
		148	PORT MAP (
		149	clk => clk,
		150	rstn => rstn,
		151	AHB_Master_In => ahbi,
		152	AHB_Master_Out => ahbo,
136		153
137		154	ren => dma_ren,
		155	data => dma_data,
		156	send => dma_send,
		157	valid_burst => dma_valid_burst,
		158	done => dma_done,
		159	address => dma_address);
		160	END GENERATE LPP_DMA_IP;
		161
		162
138	-----------------------------------------------------------------------------	163	-----------------------------------------------------------------------------
139	-- RoundRobin Selection Channel For DMA	164	-- RoundRobin Selection Channel For DMA
140	-----------------------------------------------------------------------------	165	-----------------------------------------------------------------------------

lib/lpp/lpp_dma/lpp_dma_pkg.vhd +21 -1

@@ -223,7 +223,8 PACKAGE lpp_dma_pkg IS
223	-----------------------------------------------------------------------------	223	-----------------------------------------------------------------------------
224	COMPONENT DMA_SubSystem	224	COMPONENT DMA_SubSystem
225	GENERIC (	225	GENERIC (
226	hindex : INTEGER);	226	hindex : INTEGER;
		227	CUSTOM_DMA : INTEGER := 1);
227	PORT (	228	PORT (
228	clk : IN STD_LOGIC;	229	clk : IN STD_LOGIC;
229	rstn : IN STD_LOGIC;	230	rstn : IN STD_LOGIC;
@@ -285,5 +286,24 PACKAGE lpp_dma_pkg IS
285	dma_done : IN STD_LOGIC;	286	dma_done : IN STD_LOGIC;
286	grant_error : OUT STD_LOGIC);	287	grant_error : OUT STD_LOGIC);
287	END COMPONENT;	288	END COMPONENT;
		289
		290	COMPONENT lpp_dma_SEND16B_FIFO2DMA
		291	GENERIC (
		292	hindex : INTEGER;
		293	vendorid : in Integer;
		294	deviceid : in Integer;
		295	version : in Integer);
		296	PORT (
		297	clk : IN STD_LOGIC;
		298	rstn : IN STD_LOGIC;
		299	AHB_Master_In : IN AHB_Mst_In_Type;
		300	AHB_Master_Out : OUT AHB_Mst_Out_Type;
		301	ren : OUT STD_LOGIC;
		302	data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		303	send : IN STD_LOGIC;
		304	valid_burst : IN STD_LOGIC;
		305	done : OUT STD_LOGIC;
		306	address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
		307	END COMPONENT;
288		308
289	END;	309	END;

lib/lpp/lpp_dma/vhdlsyn.txt +1 0

             DMA_SubSystem_GestionBuffer.vhd
             DMA_SubSystem_Arbiter.vhd
             DMA_SubSystem_MUX.vhd
+            lpp_dma_SEND16B_FIFO2DMA.vhd

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +5 -5

               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
-                ahbso(2)    <= ahbs_none;
+                ahbso(0)    <= ahbs_none;
                 dsuo.tstop  <= '0';
                 dsuo.active <= '0';
               END GENERATE;
             ----------------------------------------------------------------------
               ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
                 memctrlr : mctrl GENERIC MAP (
-                  hindex  => 0,
+                  hindex  => 2,
                   pindex  => 0,
                   paddr   => 0,
                   srbanks => 1
                   )
-                  PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
+                  PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
                 memi.bexcn <= '1';
                 memi.brdyn <= '1';
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
-                             ioen    => 0, nahbm => maxahbmsp, nahbs => 8)
+                             ioen    => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
-            END Behavioral;
  No newline at end of file
+            END Behavioral;

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