diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -404,7 +404,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"020145") -- aa.bb.cc version + top_lfr_version => X"020146") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -214,6 +214,8 @@ ARCHITECTURE beh OF MINI_LFR_top IS -- SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL nSRAM_READY : STD_LOGIC; BEGIN -- beh @@ -368,7 +370,7 @@ BEGIN -- beh NB_APB_SLAVE => NB_APB_SLAVE, ADDRESS_SIZE => 20, USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, - BYPASS_EDAC_MEMCTRLR => '1', + BYPASS_EDAC_MEMCTRLR => '0', SRBANKSZ => 9) PORT MAP ( clk => clk_25, @@ -387,7 +389,7 @@ BEGIN -- beh nSRAM_WE => SRAM_nWE, nSRAM_CE => SRAM_CE_s, nSRAM_OE => SRAM_nOE, - nSRAM_READY => '1', + nSRAM_READY => nSRAM_READY, SRAM_MBE => OPEN, apbi_ext => apbi_ext, apbo_ext => apbo_ext, @@ -396,13 +398,27 @@ BEGIN -- beh ahbi_m_ext => ahbi_m_ext, ahbo_m_ext => ahbo_m_ext); -IAP:if USE_IAP_MEMCTRL = 1 GENERATE - SRAM_CE <= not SRAM_CE_s(0); -END GENERATE; + PROCESS (clk_25, rstn_25) + BEGIN -- PROCESS + IF rstn_25 = '0' THEN -- asynchronous reset (active low) + nSRAM_READY <= '1'; + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + nSRAM_READY <= '1'; + IF IO0 = '1' THEN + nSRAM_READY <= '0'; + END IF; + END IF; + END PROCESS; + + -NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE - SRAM_CE <= SRAM_CE_s(0); -END GENERATE; + IAP:if USE_IAP_MEMCTRL = 1 GENERATE + SRAM_CE <= not SRAM_CE_s(0); + END GENERATE; + + NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE + SRAM_CE <= SRAM_CE_s(0); + END GENERATE; ------------------------------------------------------------------------------- -- APB_LFR_MANAGEMENT --------------------------------------------------------- ------------------------------------------------------------------------------- @@ -412,13 +428,13 @@ END GENERATE; pindex => 6, paddr => 6, pmask => 16#fff#, - FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 +-- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set PORT MAP ( clk25MHz => clk_25, resetn_25MHz => rstn_25, -- TODO - clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn_24_576MHz => rstn_24, -- TODO +-- clk24_576MHz => clk_24, -- 49.152MHz/2 +-- resetn_24_576MHz => rstn_24, -- TODO grspw_tick => swno.tickout, apbi => apbi_ext, apbo => apbo_ext(6), @@ -543,7 +559,7 @@ END GENERATE; pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000144") -- aa.bb.cc version + top_lfr_version => X"000146") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, @@ -565,7 +581,7 @@ END GENERATE; observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; - IO0 <= rstn_25; +-- IO0 <= rstn_25; IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full diff --git a/lib/lpp/lpp_dma/DMA_SubSystem.vhd b/lib/lpp/lpp_dma/DMA_SubSystem.vhd --- a/lib/lpp/lpp_dma/DMA_SubSystem.vhd +++ b/lib/lpp/lpp_dma/DMA_SubSystem.vhd @@ -3,6 +3,7 @@ USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lpp; +USE lpp.apb_devices_list.ALL; USE lpp.lpp_ad_conv.ALL; USE lpp.iir_filter.ALL; USE lpp.FILTERcfg.ALL; @@ -25,7 +26,8 @@ USE GRLIB.DMA2AHB_Package.ALL; ENTITY DMA_SubSystem IS GENERIC ( - hindex : INTEGER := 2); + hindex : INTEGER := 2; + CUSTOM_DMA : INTEGER := 1); PORT ( clk : IN STD_LOGIC; @@ -116,25 +118,48 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- DMA ----------------------------------------------------------------------------- - lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst - GENERIC MAP ( - tech => inferred, - hindex => hindex) - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - run => run, - AHB_Master_In => ahbi, - AHB_Master_Out => ahbo, + GR_DMA : IF CUSTOM_DMA = 0 GENERATE + lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst + GENERIC MAP ( + tech => inferred, + hindex => hindex) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + run => run, + AHB_Master_In => ahbi, + AHB_Master_Out => ahbo, + + send => dma_send, + valid_burst => dma_valid_burst, + done => dma_done, + ren => dma_ren, + address => dma_address, + data => dma_data); + END GENERATE GR_DMA; - send => dma_send, - valid_burst => dma_valid_burst, - done => dma_done, - ren => dma_ren, - address => dma_address, - data => dma_data); + LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE + lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 10, + version => 0) + PORT MAP ( + clk => clk, + rstn => rstn, + AHB_Master_In => ahbi, + AHB_Master_Out => ahbo, - + ren => dma_ren, + data => dma_data, + send => dma_send, + valid_burst => dma_valid_burst, + done => dma_done, + address => dma_address); + END GENERATE LPP_DMA_IP; + + ----------------------------------------------------------------------------- -- RoundRobin Selection Channel For DMA ----------------------------------------------------------------------------- diff --git a/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd @@ -0,0 +1,213 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.general_purpose.ALL; +--USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_dma_SEND16B_FIFO2DMA IS + GENERIC ( + hindex : INTEGER := 2; + vendorid : IN INTEGER := 0; + deviceid : IN INTEGER := 0; + version : IN INTEGER := 0 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- FIFO Interface + ren : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Controls + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + done : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS + + CONSTANT HConfig : AHB_Config_Type := ( + 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0), + OTHERS => (OTHERS => '0')); + + TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA); + SIGNAL state : AHB_DMA_FSM_STATE; + + SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_window : STD_LOGIC; + SIGNAL ctrl_window : STD_LOGIC; + + SIGNAL bus_request : STD_LOGIC; + SIGNAL bus_lock : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + AHB_Master_Out.HCONFIG <= HConfig; + AHB_Master_Out.HSIZE <= "010"; --WORDS 32b + AHB_Master_Out.HINDEX <= hindex; + AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS + AHB_Master_Out.HIRQ <= (OTHERS => '0'); + AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16 + AHB_Master_Out.HWRITE <= '1'; + + --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE; + + --AHB_Master_Out.HBUSREQ <= bus_request; + --AHB_Master_Out.HLOCK <= data_window; + + --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE + -- '1' WHEN ctrl_window = '1' ELSE + -- '0'; + + --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE + -- '1' WHEN ctrl_window = '1' ELSE '0'; + + ----------------------------------------------------------------------------- + AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; + AHB_Master_Out.HWDATA <= ahbdrivedata(data); + + ----------------------------------------------------------------------------- + --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); + --ren <= NOT beat; + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + done <= '0'; + address_counter_reg <= (OTHERS => '0'); + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + done <= '0'; + CASE state IS + WHEN IDLE => + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + address_counter_reg <= (OTHERS => '0'); + IF send = '1' THEN + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_ARBITER; + END IF; + + WHEN s_ARBITER => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + address_counter_reg <= (OTHERS => '0'); + + IF AHB_Master_In.HGRANT(hindex) = '1' THEN + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_CTRL; + END IF; + + WHEN s_CTRL => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_NONSEQ; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + AHB_Master_Out.HTRANS <= HTRANS_SEQ; + state <= s_CTRL_DATA; + END IF; + + WHEN s_CTRL_DATA => + AHB_Master_Out.HBUSREQ <= '1'; + AHB_Master_Out.HLOCK <= '1'; + AHB_Master_Out.HTRANS <= HTRANS_SEQ; + IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN + address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1); + END IF; + + IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '1';--'0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + state <= s_DATA; + END IF; + + WHEN s_DATA => + AHB_Master_Out.HBUSREQ <= '0'; + AHB_Master_Out.HLOCK <= '0'; + AHB_Master_Out.HTRANS <= HTRANS_IDLE; + IF AHB_Master_In.HREADY = '1' THEN + state <= IDLE; + done <= '1'; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; + data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; + ----------------------------------------------------------------------------- + ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; + + ----------------------------------------------------------------------------- + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- address_counter_reg <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- address_counter_reg <= address_counter; + -- END IF; + --END PROCESS; + + --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE + -- address_counter_reg; + ----------------------------------------------------------------------------- + + +END Behavioral; diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -223,7 +223,8 @@ PACKAGE lpp_dma_pkg IS ----------------------------------------------------------------------------- COMPONENT DMA_SubSystem GENERIC ( - hindex : INTEGER); + hindex : INTEGER; + CUSTOM_DMA : INTEGER := 1); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -285,5 +286,24 @@ PACKAGE lpp_dma_pkg IS dma_done : IN STD_LOGIC; grant_error : OUT STD_LOGIC); END COMPONENT; + + COMPONENT lpp_dma_SEND16B_FIFO2DMA + GENERIC ( + hindex : INTEGER; + vendorid : in Integer; + deviceid : in Integer; + version : in Integer); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + ren : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; + done : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; END; diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt --- a/lib/lpp/lpp_dma/vhdlsyn.txt +++ b/lib/lpp/lpp_dma/vhdlsyn.txt @@ -9,3 +9,4 @@ DMA_SubSystem.vhd DMA_SubSystem_GestionBuffer.vhd DMA_SubSystem_Arbiter.vhd DMA_SubSystem_MUX.vhd +lpp_dma_SEND16B_FIFO2DMA.vhd diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -375,7 +375,7 @@ BEGIN END GENERATE; nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; + ahbso(0) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; END GENERATE; @@ -397,12 +397,12 @@ BEGIN ---------------------------------------------------------------------- ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE memctrlr : mctrl GENERIC MAP ( - hindex => 0, + hindex => 2, pindex => 0, paddr => 0, srbanks => 1 ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo); memi.bexcn <= '1'; memi.brdyn <= '1'; @@ -489,7 +489,7 @@ BEGIN ahb0 : ahbctrl -- AHB arbiter/multiplexer GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => 0, nahbm => maxahbmsp, nahbs => 8) + ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0) PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- @@ -569,4 +569,4 @@ BEGIN -END Behavioral; \ No newline at end of file +END Behavioral;