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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=TB
6
7 CMD_VLIB=vlib
8 CMD_VMAP=vmap
9 CMD_VCOM=@vcom -quiet -93 -work
10
11 ################## project specific targets ##########################
12
13 all:
14 @echo "make vsim"
15 @echo "make libs"
16 @echo "make clean"
17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18
19 run:
20 @vsim work.TB -do run.do
21 # @vsim work.TB
22 # @vsim lpp.lpp_lfr_ms
23
24 vsim: libs vcom run
25
26 libs:
27 @$(CMD_VLIB) modelsim
28 @$(CMD_VMAP) modelsim modelsim
29 @$(CMD_VLIB) modelsim/techmap
30 @$(CMD_VMAP) techmap modelsim/techmap
31 @$(CMD_VLIB) modelsim/grlib
32 @$(CMD_VMAP) grlib modelsim/grlib
33 @$(CMD_VLIB) modelsim/gaisler
34 @$(CMD_VMAP) gaisler modelsim/gaisler
35 @$(CMD_VLIB) modelsim/work
36 @$(CMD_VMAP) work modelsim/work
37 @$(CMD_VLIB) modelsim/lpp
38 @$(CMD_VMAP) lpp modelsim/lpp
39 @echo "libs done"
40
41
42 clean:
43 @rm -Rf modelsim
44 @rm -Rf modelsim.ini
45 @rm -Rf *~
46 @rm -Rf transcript
47 @rm -Rf wlft*
48 @rm -Rf *.wlf
49 @rm -Rf vish_stacktrace.vstf
50 @rm -Rf libs.do
51
52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
53
54
55 vcom_tb:
56 $(CMD_VCOM) lpp lpp_memory.vhd
57 $(CMD_VCOM) lpp lppFIFOxN.vhd
58 $(CMD_VCOM) lpp lpp_FIFO.vhd
59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
61 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
62 $(CMD_VCOM) work TB.vhd
63 @echo "vcom done"
64
65 vcom_grlib:
66 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
67 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
68 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
100 @echo "vcom grlib done"
101
102 vcom_gaisler:
103 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
104 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
105 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
106 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
107 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
108 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
109 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
111 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
113 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
114 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
116 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
117 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
119 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
133 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
135 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
136 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
138 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
171 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
173 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
174 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
176 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
197 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
199 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
200 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
202 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
215 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
216 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
217 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
218 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
219 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
226 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
227 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
228 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
229 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
230 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
254 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
255 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
256 @echo "vcom gaisler done"
257
258 vcom_techmap:
259 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
260 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
261 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
262 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
263 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
265 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
266 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
267 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
268 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
269 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
270 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
272 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
273 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
274 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
275 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
276 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
278 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
279 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
280 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
281 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
282 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
284 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
285 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
286 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
287 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
288 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
289 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
290 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
291 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
292 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
293 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
294 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
314 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
316 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
317 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
319 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
337 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
338 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
339 @echo "vcom techmap done"
340
341 vcom_lpp:
342 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
343 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
348 @echo "vcom lpp done"
349
350 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
351 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
352 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
353 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
354 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
355 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
356 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
357 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
358 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
359 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
360 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
361 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
362 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
363 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
364 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
365 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
366 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
367 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
368 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
369 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
370 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
371 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
372 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
373 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
374 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
375 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
376 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
377 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
378 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
379 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
380 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
381 # @echo "vcom lpp done"
382
383 #include Makefile_vcom_lpp
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
27 LIBRARY lpp;
28 USE lpp.lpp_memory.ALL;
29 USE lpp.iir_filter.ALL;
30 USE lpp.spectral_matrix_package.ALL;
31 use lpp.lpp_fft.all;
32 use lpp.fft_components.all;
33
34 ENTITY TB IS
35
36
37 END TB;
38
39
40 ARCHITECTURE beh OF TB IS
41
42 COMPONENT lpp_lfr_ms
43 GENERIC (
44 Mem_use : INTEGER);
45 PORT (
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
50 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
51 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
52 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
54 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_valid : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
62 ready_matrix_f0_0 : OUT STD_LOGIC;
63 ready_matrix_f0_1 : OUT STD_LOGIC;
64 ready_matrix_f1 : OUT STD_LOGIC;
65 ready_matrix_f2 : OUT STD_LOGIC;
66 error_anticipating_empty_fifo : OUT STD_LOGIC;
67 error_bad_component_error : OUT STD_LOGIC;
68 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 status_ready_matrix_f0_0 : IN STD_LOGIC;
70 status_ready_matrix_f0_1 : IN STD_LOGIC;
71 status_ready_matrix_f1 : IN STD_LOGIC;
72 status_ready_matrix_f2 : IN STD_LOGIC;
73 status_error_anticipating_empty_fifo : IN STD_LOGIC;
74 status_error_bad_component_error : IN STD_LOGIC;
75 config_active_interruption_onNewMatrix : IN STD_LOGIC;
76 config_active_interruption_onError : IN STD_LOGIC;
77 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
81 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
82 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
83 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
84 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
85 END COMPONENT;
86
87 -----------------------------------------------------------------------------
88 SIGNAL clk25MHz : STD_LOGIC := '0';
89 SIGNAL rstn : STD_LOGIC := '0';
90
91 -----------------------------------------------------------------------------
92 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
93 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
101 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL dma_valid : STD_LOGIC;
103 SIGNAL dma_valid_burst : STD_LOGIC;
104 SIGNAL dma_ren : STD_LOGIC;
105 SIGNAL dma_done : STD_LOGIC;
106 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
107 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
108 SIGNAL ready_matrix_f1 : STD_LOGIC;
109 SIGNAL ready_matrix_f2 : STD_LOGIC;
110 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
111 SIGNAL error_bad_component_error : STD_LOGIC;
112 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
114 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
115 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
116 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
117 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
118 SIGNAL status_error_bad_component_error : STD_LOGIC;
119 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
120 SIGNAL config_active_interruption_onError : STD_LOGIC;
121 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
126 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
127 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
128 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
129
130 -----------------------------------------------------------------------------
131 SIGNAL clk49_152MHz : STD_LOGIC := '0';
132 SIGNAL sample_counter_24k : INTEGER;
133 SIGNAL s_24576Hz : STD_LOGIC;
134
135 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
136 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
137
138 SIGNAL s_24576Hz_sync : STD_LOGIC;
139
140 SIGNAL sample_counter_f1 : INTEGER;
141 SIGNAL sample_counter_f2 : INTEGER;
142 --
143 SIGNAL sample_f0_val : STD_LOGIC;
144 SIGNAL sample_f1_val : STD_LOGIC;
145 SIGNAL sample_f2_val : STD_LOGIC;
146
147 BEGIN -- beh
148
149 clk25MHz <= NOT clk25MHz AFTER 20 ns;
150 clk25MHz <= NOT clk25MHz AFTER 20 ns;
151 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
152
153 PROCESS
154 BEGIN -- PROCESS
155 WAIT UNTIL clk25MHz = '1';
156 WAIT UNTIL clk25MHz = '1';
157 WAIT UNTIL clk25MHz = '1';
158 rstn <= '1';
159 WAIT UNTIL clk25MHz = '1';
160
161
162 WAIT FOR 100 ms;
163
164 REPORT "*** END simulation ***" SEVERITY failure;
165 WAIT;
166
167 END PROCESS;
168
169
170 -----------------------------------------------------------------------------
171 PROCESS (clk49_152MHz, rstn)
172 BEGIN -- PROCESS
173 IF rstn = '0' THEN -- asynchronous reset (active low)
174 sample_counter_24k <= 0;
175 s_24576Hz <= '0';
176 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
177 IF sample_counter_24k = 0 THEN
178 sample_counter_24k <= 2000;
179 s_24576Hz <= NOT s_24576Hz;
180 ELSE
181 sample_counter_24k <= sample_counter_24k - 1;
182 END IF;
183 END IF;
184 END PROCESS;
185
186 PROCESS (clk25MHz, rstn)
187 BEGIN -- PROCESS
188 IF rstn = '0' THEN -- asynchronous reset (active low)
189 s_24_sync_reg_0 <= '0';
190 s_24_sync_reg_1 <= '0';
191 s_24576Hz_sync <= '0';
192 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
193 s_24_sync_reg_0 <= s_24576Hz;
194 s_24_sync_reg_1 <= s_24_sync_reg_0;
195 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
196 END IF;
197 END PROCESS;
198
199 PROCESS (clk25MHz, rstn)
200 BEGIN -- PROCESS
201 IF rstn = '0' THEN -- asynchronous reset (active low)
202 sample_f0_val <= '0';
203 sample_f1_val <= '0';
204 sample_f2_val <= '0';
205
206 sample_counter_f1 <= 0;
207 sample_counter_f2 <= 0;
208 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
209 IF s_24576Hz_sync = '1' THEN
210 sample_f0_val <= '1';
211 IF sample_counter_f1 = 0 THEN
212 sample_f1_val <= '1';
213 sample_counter_f1 <= 5;
214 ELSE
215 sample_f1_val <= '0';
216 sample_counter_f1 <= sample_counter_f1 -1;
217 END IF;
218 IF sample_counter_f2 = 0 THEN
219 sample_f2_val <= '1';
220 sample_counter_f2 <= 95;
221 ELSE
222 sample_f2_val <= '0';
223 sample_counter_f2 <= sample_counter_f2 -1;
224 END IF;
225 ELSE
226 sample_f0_val <= '0';
227 sample_f1_val <= '0';
228 sample_f2_val <= '0';
229 END IF;
230 END IF;
231 END PROCESS;
232
233
234
235 -----------------------------------------------------------------------------
236 coarse_time <= (OTHERS => '0');
237 fine_time <= (OTHERS => '0');
238
239 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
240 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
241 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
242
243 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
244 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
245 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
246 -----------------------------------------------------------------------------
247
248 lpp_lfr_ms_1: ENTITY lpp.lpp_lfr_ms
249 GENERIC MAP (
250 Mem_use => use_CEL)
251 PORT MAP (
252 clk => clk25MHz,
253 rstn => rstn,
254 --
255 coarse_time => coarse_time,
256 fine_time => fine_time,
257 --
258 sample_f0_wen => sample_f0_wen,
259 sample_f0_wdata => sample_f0_wdata,
260 sample_f1_wen => sample_f1_wen,
261 sample_f1_wdata => sample_f1_wdata,
262 sample_f2_wen => sample_f2_wen,
263 sample_f2_wdata => sample_f2_wdata,
264 --
265 dma_addr => dma_addr,
266 dma_data => dma_data,
267 dma_valid => dma_valid,
268 dma_valid_burst => dma_valid_burst,
269 dma_ren => dma_ren,
270 dma_done => dma_done,
271 ready_matrix_f0_0 => ready_matrix_f0_0,
272 ready_matrix_f0_1 => ready_matrix_f0_1,
273 ready_matrix_f1 => ready_matrix_f1,
274 ready_matrix_f2 => ready_matrix_f2,
275 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
276 error_bad_component_error => error_bad_component_error,
277 debug_reg => debug_reg,
278 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
279 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
280 status_ready_matrix_f1 => status_ready_matrix_f1,
281 status_ready_matrix_f2 => status_ready_matrix_f2,
282 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
283 status_error_bad_component_error => status_error_bad_component_error,
284 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
285 config_active_interruption_onError => config_active_interruption_onError,
286 addr_matrix_f0_0 => addr_matrix_f0_0,
287 addr_matrix_f0_1 => addr_matrix_f0_1,
288 addr_matrix_f1 => addr_matrix_f1,
289 addr_matrix_f2 => addr_matrix_f2,
290 matrix_time_f0_0 => matrix_time_f0_0,
291 matrix_time_f0_1 => matrix_time_f0_1,
292 matrix_time_f1 => matrix_time_f1,
293 matrix_time_f2 => matrix_time_f2);
294
295 dma_ren <= '0';
296 dma_done <= '0';
297
298 status_ready_matrix_f0_0 <= '0';
299 status_ready_matrix_f0_1 <= '0';
300 status_ready_matrix_f1 <= '0';
301 status_ready_matrix_f2 <= '0';
302 status_error_anticipating_empty_fifo <= '0';
303 status_error_bad_component_error <= '0';
304
305 config_active_interruption_onNewMatrix <= '0';
306 config_active_interruption_onError <= '0';
307 addr_matrix_f0_0 <= (OTHERS => '0');
308 addr_matrix_f0_1 <= (OTHERS => '0');
309 addr_matrix_f1 <= (OTHERS => '0');
310 addr_matrix_f2 <= (OTHERS => '0');
311
312 END beh;
313
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
28 library techmap;
29 use techmap.gencomp.all;
30
31 entity lppFIFOxN is
32 generic(
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 2 to 12 := 8;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
39 );
40 port(
41 rstn : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 almost_full : out std_logic_vector(FifoCnt-1 downto 0); -- TODO
51 empty : out std_logic_vector(FifoCnt-1 downto 0)
52 );
53 end entity;
54
55
56 architecture ar_lppFIFOxN of lppFIFOxN is
57
58 begin
59
60 fifos: for i in 0 to FifoCnt-1 generate
61 FIFO0 : lpp_fifo
62 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
63 port map(rstn,ReUse(i),
64 rclk,
65 ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,
66 wclk,
67 wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),almost_full(i),open);
68 end generate;
69
70 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30
31 ENTITY lpp_fifo IS
32 GENERIC(
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
35 Enable_ReUse : STD_LOGIC := '0';
36 DataSz : INTEGER RANGE 1 TO 32 := 8;
37 AddrSz : INTEGER RANGE 2 TO 12 := 8
38 );
39 PORT(
40 rstn : IN STD_LOGIC;
41 ReUse : IN STD_LOGIC;
42 rclk : IN STD_LOGIC;
43 ren : IN STD_LOGIC;
44 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
45 empty : OUT STD_LOGIC;
46 raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
47 wclk : IN STD_LOGIC;
48 wen : IN STD_LOGIC;
49 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
50 full : OUT STD_LOGIC;
51 almost_full : OUT STD_LOGIC; -- TODO
52 waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
53 );
54 END ENTITY;
55
56
57 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
58
59 SIGNAL sFull : STD_LOGIC;
60 SIGNAL sFull_s : STD_LOGIC;
61 SIGNAL sEmpty_s : STD_LOGIC;
62
63 SIGNAL sEmpty : STD_LOGIC;
64 SIGNAL sREN : STD_LOGIC;
65 SIGNAL sWEN : STD_LOGIC;
66 SIGNAL sRE : STD_LOGIC;
67 SIGNAL sWE : STD_LOGIC;
68
69 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
70 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
71 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
73
74 SIGNAL almost_full_s : STD_LOGIC;
75 SIGNAL almost_full_r : STD_LOGIC;
76 BEGIN
77
78 --==================================================================================
79 -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\
80 -- A l'inverse de RAM_CEL !!!
81 --==================================================================================
82 memRAM : IF Mem_use = use_RAM GENERATE
83 SRAM : syncram_2p
84 GENERIC MAP(tech, AddrSz, DataSz)
85 PORT MAP(RCLK, sRE, Raddr_vect, rdata, WCLK, sWE, Waddr_vect, wdata);
86 END GENERATE;
87 --==================================================================================
88 memCEL : IF Mem_use = use_CEL GENERATE
89 CRAM : RAM_CEL
90 GENERIC MAP(DataSz, AddrSz)
91 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
92 END GENERATE;
93 --==================================================================================
94
95 --=============================
96 -- Read section
97 --=============================
98 sREN <= REN OR sEmpty;
99 sRE <= NOT sREN;
100
101 sEmpty_s <= '0' WHEN ReUse = '1' AND Enable_ReUse = '1' else
102 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
103 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
104 '0';
105
106 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
107
108 PROCESS (rclk, rstn)
109 BEGIN
110 IF(rstn = '0')then
111 Raddr_vect <= (OTHERS => '0');
112 sempty <= '1';
113 ELSIF(rclk'EVENT AND rclk = '1')then
114 sEmpty <= sempty_s;
115
116 IF(sREN = '0' and sempty = '0')then
117 Raddr_vect <= Raddr_vect_s;
118 END IF;
119
120 END IF;
121 END PROCESS;
122
123 --=============================
124 -- Write section
125 --=============================
126 sWEN <= WEN OR sFull;
127 sWE <= NOT sWEN;
128
129 sFull_s <= '1' WHEN ReUse = '1' AND Enable_ReUse = '1' else
130 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
131 '1' WHEN sFull = '1' AND REN = '1' ELSE
132 '0';
133
134 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
135 '1' WHEN almost_full_r = '1' AND WEN = REN ELSE
136 '0';
137
138 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
139
140 PROCESS (wclk, rstn)
141 BEGIN
142 IF(rstn = '0')then
143 Waddr_vect <= (OTHERS => '0');
144 sfull <= '0';
145 almost_full_r <= '0';
146 ELSIF(wclk'EVENT AND wclk = '1')then
147 sfull <= sfull_s;
148 almost_full_r <= almost_full_s;
149
150 IF(sWEN = '0' and sfull = '0')THEN
151 Waddr_vect <= Waddr_vect_s;
152 END IF;
153
154 END IF;
155 END PROCESS;
156
157 almost_full <= almost_full_s;
158 full <= sFull_s;
159 empty <= sEmpty_s;
160 waddr <= Waddr_vect;
161 raddr <= Raddr_vect;
162
163 END ARCHITECTURE;
164
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9
10 use lpp.lpp_fft.all;
11 use lpp.fft_components.all;
12
13 ENTITY lpp_lfr_ms IS
14 GENERIC (
15 Mem_use : INTEGER := use_RAM
16 );
17 PORT (
18 clk : IN STD_LOGIC;
19 rstn : IN STD_LOGIC;
20
21 ---------------------------------------------------------------------------
22 -- DATA INPUT
23 ---------------------------------------------------------------------------
24 -- TIME
25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27 --
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 --
31 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 --
34 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36
37 ---------------------------------------------------------------------------
38 -- DMA
39 ---------------------------------------------------------------------------
40 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 dma_valid : OUT STD_LOGIC;
43 dma_valid_burst : OUT STD_LOGIC;
44 dma_ren : IN STD_LOGIC;
45 dma_done : IN STD_LOGIC;
46
47 -- Reg out
48 ready_matrix_f0_0 : OUT STD_LOGIC;
49 ready_matrix_f0_1 : OUT STD_LOGIC;
50 ready_matrix_f1 : OUT STD_LOGIC;
51 ready_matrix_f2 : OUT STD_LOGIC;
52 error_anticipating_empty_fifo : OUT STD_LOGIC;
53 error_bad_component_error : OUT STD_LOGIC;
54 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55
56 -- Reg In
57 status_ready_matrix_f0_0 : IN STD_LOGIC;
58 status_ready_matrix_f0_1 : IN STD_LOGIC;
59 status_ready_matrix_f1 : IN STD_LOGIC;
60 status_ready_matrix_f2 : IN STD_LOGIC;
61 status_error_anticipating_empty_fifo : IN STD_LOGIC;
62 status_error_bad_component_error : IN STD_LOGIC;
63
64 config_active_interruption_onNewMatrix : IN STD_LOGIC;
65 config_active_interruption_onError : IN STD_LOGIC;
66 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70
71 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
72 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
73 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
74 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
75
76 );
77 END;
78
79 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
80
81 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86
87 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92
93 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97
98 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99
100 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104
105 SIGNAL error_wen_f0 : STD_LOGIC;
106 SIGNAL error_wen_f1 : STD_LOGIC;
107 SIGNAL error_wen_f2 : STD_LOGIC;
108
109 SIGNAL one_sample_f1_full : STD_LOGIC;
110 SIGNAL one_sample_f1_wen : STD_LOGIC;
111 SIGNAL one_sample_f2_full : STD_LOGIC;
112 SIGNAL one_sample_f2_wen : STD_LOGIC;
113
114 -----------------------------------------------------------------------------
115 -- FSM / SWITCH SELECT CHANNEL
116 -----------------------------------------------------------------------------
117 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
118 SIGNAL state_fsm_select_channel : fsm_select_channel;
119
120 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
121 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
124
125 -----------------------------------------------------------------------------
126 -- FSM LOAD FFT
127 -----------------------------------------------------------------------------
128 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_transition);
129 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
130 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
131
132 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_load : STD_LOGIC;
134 SIGNAL sample_valid : STD_LOGIC;
135 SIGNAL sample_valid_r : STD_LOGIC;
136 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
137
138
139 -----------------------------------------------------------------------------
140 -- FFT
141 -----------------------------------------------------------------------------
142 SIGNAL fft_read : STD_LOGIC;
143 SIGNAL fft_pong : STD_LOGIC;
144 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
145 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
146 SIGNAL fft_data_valid : STD_LOGIC;
147 SIGNAL fft_ready : STD_LOGIC;
148
149 BEGIN
150
151 switch_f0_inst : spectral_matrix_switch_f0
152 PORT MAP (
153 clk => clk,
154 rstn => rstn,
155
156 sample_wen => sample_f0_wen,
157
158 fifo_A_empty => sample_f0_A_empty,
159 fifo_A_full => sample_f0_A_full,
160 fifo_A_wen => sample_f0_A_wen,
161
162 fifo_B_empty => sample_f0_B_empty,
163 fifo_B_full => sample_f0_B_full,
164 fifo_B_wen => sample_f0_B_wen,
165
166 error_wen => error_wen_f0); -- TODO
167
168 -----------------------------------------------------------------------------
169 -- FIFO IN
170 -----------------------------------------------------------------------------
171 lppFIFOxN_f0_a : lppFIFOxN
172 GENERIC MAP (
173 tech => 0,
174 Mem_use => Mem_use,
175 Data_sz => 16,
176 Addr_sz => 8,
177 FifoCnt => 5,
178 Enable_ReUse => '0')
179 PORT MAP (
180 rstn => rstn,
181 wclk => clk,
182 rclk => clk,
183 ReUse => (OTHERS => '0'),
184
185 wen => sample_f0_A_wen, -- IN in
186 ren => sample_f0_A_ren, -- OUT in
187 wdata => sample_f0_wdata, -- IN in
188 rdata => sample_f0_A_rdata, -- OUT in
189 full => sample_f0_A_full, -- IN out
190 almost_full => OPEN, -- IN out
191 empty => sample_f0_A_empty); -- OUT OUT
192
193 lppFIFOxN_f0_b : lppFIFOxN
194 GENERIC MAP (
195 tech => 0,
196 Mem_use => Mem_use,
197 Data_sz => 16,
198 Addr_sz => 8,
199 FifoCnt => 5,
200 Enable_ReUse => '0')
201 PORT MAP (
202 rstn => rstn,
203 wclk => clk,
204 rclk => clk,
205 ReUse => (OTHERS => '0'),
206
207 wen => sample_f0_B_wen, -- IN in
208 ren => sample_f0_B_ren, -- OUT in
209 wdata => sample_f0_wdata, -- IN in
210 rdata => sample_f0_B_rdata, -- OUT in
211 full => sample_f0_B_full, -- IN out
212 almost_full => OPEN, -- IN out
213 empty => sample_f0_B_empty); -- OUT OUT
214
215 lppFIFOxN_f1 : lppFIFOxN
216 GENERIC MAP (
217 tech => 0,
218 Mem_use => Mem_use,
219 Data_sz => 16,
220 Addr_sz => 8,
221 FifoCnt => 5,
222 Enable_ReUse => '0')
223 PORT MAP (
224 rstn => rstn,
225 wclk => clk,
226 rclk => clk,
227 ReUse => (OTHERS => '0'),
228
229 wen => sample_f1_wen, -- IN in
230 ren => sample_f1_ren, -- OUT in
231 wdata => sample_f1_wdata, -- IN in
232 rdata => sample_f1_rdata, -- OUT in
233 full => sample_f1_full, -- IN out
234 almost_full => sample_f1_almost_full, -- IN out
235 empty => sample_f1_empty); -- OUT OUT
236
237
238 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
239
240 PROCESS (clk, rstn)
241 BEGIN -- PROCESS
242 IF rstn = '0' THEN -- asynchronous reset (active low)
243 one_sample_f1_full <= '0';
244 error_wen_f1 <= '0';
245 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
246 IF sample_f1_full = "00000" THEN
247 one_sample_f1_full <= '0';
248 ELSE
249 one_sample_f1_full <= '1';
250 END IF;
251 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
252 END IF;
253 END PROCESS;
254
255
256 lppFIFOxN_f2 : lppFIFOxN
257 GENERIC MAP (
258 tech => 0,
259 Mem_use => Mem_use,
260 Data_sz => 16,
261 Addr_sz => 8,
262 FifoCnt => 5,
263 Enable_ReUse => '0')
264 PORT MAP (
265 rstn => rstn,
266 wclk => clk,
267 rclk => clk,
268 ReUse => (OTHERS => '0'),
269
270 wen => sample_f2_wen, -- IN in
271 ren => sample_f2_ren, -- OUT in
272 wdata => sample_f2_wdata, -- IN in
273 rdata => sample_f2_rdata, -- OUT in
274 full => sample_f2_full, -- IN out
275 almost_full => OPEN, -- IN out
276 empty => sample_f2_empty); -- OUT OUT
277
278
279 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
280
281 PROCESS (clk, rstn)
282 BEGIN -- PROCESS
283 IF rstn = '0' THEN -- asynchronous reset (active low)
284 one_sample_f2_full <= '0';
285 error_wen_f2 <= '0';
286 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
287 IF sample_f2_full = "00000" THEN
288 one_sample_f2_full <= '0';
289 ELSE
290 one_sample_f2_full <= '1';
291 END IF;
292 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
293 END IF;
294 END PROCESS;
295
296 -----------------------------------------------------------------------------
297 -- FSM SELECT CHANNEL
298 -----------------------------------------------------------------------------
299 PROCESS (clk, rstn)
300 BEGIN
301 IF rstn = '0' THEN
302 state_fsm_select_channel <= IDLE;
303 ELSIF clk'EVENT AND clk = '1' THEN
304 CASE state_fsm_select_channel IS
305 WHEN IDLE =>
306 IF sample_f1_full = "11111" THEN
307 state_fsm_select_channel <= SWITCH_F1;
308 ELSIF sample_f1_almost_full = "00000" THEN
309 IF sample_f0_A_full = "11111" THEN
310 state_fsm_select_channel <= SWITCH_F0_A;
311 ELSIF sample_f0_B_full = "11111" THEN
312 state_fsm_select_channel <= SWITCH_F0_B;
313 ELSIF sample_f2_full = "11111" THEN
314 state_fsm_select_channel <= SWITCH_F2;
315 END IF;
316 END IF;
317
318 WHEN SWITCH_F0_A =>
319 IF sample_f0_A_empty = "11111" THEN
320 state_fsm_select_channel <= IDLE;
321 END IF;
322 WHEN SWITCH_F0_B =>
323 IF sample_f0_B_empty = "11111" THEN
324 state_fsm_select_channel <= IDLE;
325 END IF;
326 WHEN SWITCH_F1 =>
327 IF sample_f1_empty = "11111" THEN
328 state_fsm_select_channel <= IDLE;
329 END IF;
330 WHEN SWITCH_F2 =>
331 IF sample_f2_empty = "11111" THEN
332 state_fsm_select_channel <= IDLE;
333 END IF;
334 WHEN OTHERS => NULL;
335 END CASE;
336
337 END IF;
338 END PROCESS;
339
340
341
342 -----------------------------------------------------------------------------
343 -- SWITCH SELECT CHANNEL
344 -----------------------------------------------------------------------------
345 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
346 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
347 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
348 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
349 (OTHERS => '1');
350
351 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
352 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
353 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
354 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
355 (OTHERS => '0');
356
357 sample_rdata <= sample_f0_A_rdata WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
358 sample_f0_B_rdata WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
359 sample_f1_rdata WHEN state_fsm_select_channel = SWITCH_F1 ELSE
360 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
361
362
363 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
364 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
365 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
366 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
367
368 -----------------------------------------------------------------------------
369 -- FSM LOAD FFT
370 -----------------------------------------------------------------------------
371
372 sample_ren <= sample_ren_s;-- OR sample_empty;
373
374 PROCESS (clk, rstn)
375 BEGIN
376 IF rstn = '0' THEN
377 sample_ren_s <= (OTHERS => '1');
378 state_fsm_load_FFT <= IDLE;
379 next_state_fsm_load_FFT <= IDLE;
380 sample_valid <= '0';
381 ELSIF clk'event AND clk = '1' THEN
382 CASE state_fsm_load_FFT IS
383 WHEN IDLE =>
384 sample_valid <= '0';
385 sample_ren_s <= (OTHERS => '1');
386 IF sample_full = "11111" AND sample_load = '1' THEN
387 state_fsm_load_FFT <= FIFO_1;
388 END IF;
389 WHEN FIFO_1 =>
390 sample_ren_s <= "1111" & NOT(sample_load);
391 sample_valid <= '1';
392 IF sample_empty(0) = '1' THEN
393 sample_valid <= '0';
394 sample_ren_s <= (OTHERS => '1');
395 state_fsm_load_FFT <= FIFO_transition;
396 next_state_fsm_load_FFT <= FIFO_2;
397 END IF;
398
399 WHEN FIFO_transition =>
400 sample_valid <= '0';
401 sample_ren_s <= (OTHERS => '1');
402 state_fsm_load_FFT <= next_state_fsm_load_FFT;
403
404 WHEN FIFO_2 =>
405 sample_ren_s <= "111" & NOT(sample_load) & '1';
406 sample_valid <= sample_load;
407 IF sample_empty(1) = '1' THEN
408 sample_valid <= '0';
409 sample_ren_s <= (OTHERS => '1');
410 state_fsm_load_FFT <= FIFO_transition;
411 next_state_fsm_load_FFT <= FIFO_3;
412 END IF;
413 WHEN FIFO_3 =>
414 sample_ren_s <= "11" & NOT(sample_load) & "11";
415 sample_valid <= sample_load;--'1';
416 IF sample_empty(2) = '1' THEN
417 sample_valid <= '0';
418 sample_ren_s <= (OTHERS => '1');
419 state_fsm_load_FFT <= FIFO_transition;
420 next_state_fsm_load_FFT <= FIFO_4;
421 END IF;
422 WHEN FIFO_4 =>
423 sample_ren_s <= '1' & NOT(sample_load) & "111";
424 sample_valid <= sample_load;--'1';
425 IF sample_empty(3) = '1' THEN
426 sample_valid <= '0';
427 sample_ren_s <= (OTHERS => '1');
428 state_fsm_load_FFT <= FIFO_transition;
429 next_state_fsm_load_FFT <= FIFO_5;
430 END IF;
431 WHEN FIFO_5 =>
432 sample_ren_s <= NOT(sample_load) & "1111";
433 sample_valid <= sample_load;--'1';
434 IF sample_empty(4) = '1' THEN
435 sample_valid <= '0';
436 sample_ren_s <= (OTHERS => '1');
437 state_fsm_load_FFT <= FIFO_transition;
438 next_state_fsm_load_FFT <= IDLE;
439 END IF;
440 WHEN OTHERS => NULL;
441 END CASE;
442 END IF;
443 END PROCESS;
444
445 PROCESS (clk, rstn)
446 BEGIN
447 IF rstn = '0' THEN
448 sample_valid_r <= '0';
449 ELSIF clk'event AND clk = '1' THEN
450 sample_valid_r <= sample_valid AND sample_load;
451 END IF;
452 END PROCESS;
453
454 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN state_fsm_load_FFT = FIFO_1 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_2) ELSE
455 sample_rdata(16*2-1 DOWNTO 16*1) WHEN state_fsm_load_FFT = FIFO_2 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_3) ELSE
456 sample_rdata(16*3-1 DOWNTO 16*2) WHEN state_fsm_load_FFT = FIFO_3 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_4) ELSE
457 sample_rdata(16*4-1 DOWNTO 16*3) WHEN state_fsm_load_FFT = FIFO_4 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_5) ELSE
458 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN state_fsm_load_FFT = FIFO_5 ELSE
459
460 -----------------------------------------------------------------------------
461 -- FFT
462 -----------------------------------------------------------------------------
463 CoreFFT_1: CoreFFT
464 GENERIC MAP (
465 LOGPTS => gLOGPTS,
466 LOGLOGPTS => gLOGLOGPTS,
467 WSIZE => gWSIZE,
468 TWIDTH => gTWIDTH,
469 DWIDTH => gDWIDTH,
470 TDWIDTH => gTDWIDTH,
471 RND_MODE => gRND_MODE,
472 SCALE_MODE => gSCALE_MODE,
473 PTS => gPTS,
474 HALFPTS => gHALFPTS,
475 inBuf_RWDLY => gInBuf_RWDLY)
476 PORT MAP (
477 clk => clk,
478 ifiStart => '1',
479 ifiNreset => rstn,
480
481 ifiD_valid => sample_valid_r, -- IN
482 ifiRead_y => fft_read,
483 ifiD_im => (OTHERS => '0'), -- IN
484 ifiD_re => sample_data, -- IN
485 ifoLoad => sample_load, -- IN
486
487 ifoPong => fft_pong,
488 ifoY_im => fft_data_im,
489 ifoY_re => fft_data_re,
490 ifoY_valid => fft_data_valid,
491 ifoY_rdy => fft_ready);
492
493 -----------------------------------------------------------------------------
494 --
495 -----------------------------------------------------------------------------
496 fft_read <= '1';
497 -- fft_read OUT
498 -- fft_pong IN
499 -- fft_data_im IN
500 -- fft_data_re IN
501 -- fft_data_valid IN
502 -- fft_ready IN
503
504 -----------------------------------------------------------------------------
505 --
506 -----------------------------------------------------------------------------
507
508 dma_addr <= (OTHERS => '0');
509 dma_data <= (OTHERS => '0');
510 dma_valid <= '0';
511 dma_valid_burst <= '0';
512
513 ready_matrix_f0_0 <= '0';
514 ready_matrix_f0_1 <= '0';
515 ready_matrix_f1 <= '0';
516 ready_matrix_f2 <= '0';
517 error_anticipating_empty_fifo <= '0';
518 error_bad_component_error <= '0';
519 debug_reg <= (OTHERS => '0');
520
521 matrix_time_f0_0 <= (OTHERS => '0');
522 matrix_time_f0_1 <= (OTHERS => '0');
523 matrix_time_f1 <= (OTHERS => '0');
524 matrix_time_f2 <= (OTHERS => '0');
525
526
527 END Behavioral;
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@@ -0,0 +1,199
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
30 library gaisler;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
33 library techmap;
34 use techmap.gencomp.all;
35
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
37
38 package lpp_memory is
39
40 component APB_FIFO is
41 generic (
42 tech : integer := apa3;
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
54 W : integer := 1
55 );
56 port (
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
73 end component;
74
75 component FIFO_pipeline is
76 generic(
77 tech : integer := 0;
78 Mem_use : integer := use_RAM;
79 fifoCount : integer range 2 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
81 abits : integer range 2 to 12 := 8
82 );
83 port(
84 rstn : in std_logic;
85 ReUse : in std_logic;
86 rclk : in std_logic;
87 ren : in std_logic;
88 rdata : out std_logic_vector(DataSz-1 downto 0);
89 empty : out std_logic;
90 raddr : out std_logic_vector(abits-1 downto 0);
91 wclk : in std_logic;
92 wen : in std_logic;
93 wdata : in std_logic_vector(DataSz-1 downto 0);
94 full : out std_logic;
95 waddr : out std_logic_vector(abits-1 downto 0)
96 );
97 end component;
98
99 component lpp_fifo is
100 generic(
101 tech : integer := 0;
102 Mem_use : integer := use_RAM;
103 Enable_ReUse : std_logic := '0';
104 DataSz : integer range 1 to 32 := 8;
105 AddrSz : integer range 2 to 12 := 8
106 );
107 port(
108 rstn : in std_logic;
109 ReUse : in std_logic; --27/01/12
110 rclk : in std_logic;
111 ren : in std_logic;
112 rdata : out std_logic_vector(DataSz-1 downto 0);
113 empty : out std_logic;
114 raddr : out std_logic_vector(AddrSz-1 downto 0);
115 wclk : in std_logic;
116 wen : in std_logic;
117 wdata : in std_logic_vector(DataSz-1 downto 0);
118 full : out std_logic;
119 almost_full : out std_logic;
120 waddr : out std_logic_vector(AddrSz-1 downto 0)
121 );
122 end component;
123
124
125 component lppFIFOxN is
126 generic(
127 tech : integer := 0;
128 Mem_use : integer := use_RAM;
129 Data_sz : integer range 1 to 32 := 8;
130 Addr_sz : integer range 1 to 32 := 8;
131 FifoCnt : integer := 1;
132 Enable_ReUse : std_logic := '0'
133 );
134 port(
135 rstn : in std_logic;
136 wclk : in std_logic;
137 rclk : in std_logic;
138 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
139 wen : in std_logic_vector(FifoCnt-1 downto 0);
140 ren : in std_logic_vector(FifoCnt-1 downto 0);
141 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
142 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
143 full : out std_logic_vector(FifoCnt-1 downto 0);
144 almost_full : out std_logic_vector(FifoCnt-1 downto 0);
145 empty : out std_logic_vector(FifoCnt-1 downto 0)
146 );
147 end component;
148
149 component FillFifo is
150 generic(
151 Data_sz : integer range 1 to 32 := 16;
152 Fifo_cnt : integer range 1 to 8 := 5
153 );
154 port(
155 clk : in std_logic;
156 raz : in std_logic;
157 write : out std_logic_vector(Fifo_cnt-1 downto 0);
158 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
159 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
160 );
161 end component;
162
163 component Bridge is
164 port(
165 clk : in std_logic;
166 raz : in std_logic;
167 EmptyUp : in std_logic;
168 FullDwn : in std_logic;
169 WriteDwn : out std_logic;
170 ReadUp : out std_logic
171 );
172 end component;
173
174 component ssram_plugin is
175 generic (tech : integer := 0);
176 port
177 (
178 clk : in std_logic;
179 mem_ctrlr_o : in memory_out_type;
180 SSRAM_CLK : out std_logic;
181 nBWa : out std_logic;
182 nBWb : out std_logic;
183 nBWc : out std_logic;
184 nBWd : out std_logic;
185 nBWE : out std_logic;
186 nADSC : out std_logic;
187 nADSP : out std_logic;
188 nADV : out std_logic;
189 nGW : out std_logic;
190 nCE1 : out std_logic;
191 CE2 : out std_logic;
192 nCE3 : out std_logic;
193 nOE : out std_logic;
194 MODE : out std_logic;
195 ZZ : out std_logic
196 );
197 end component;
198
199 end;
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@@ -0,0 +1,3
1 log -R *
2 do wave.do
3 run -all No newline at end of file
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@@ -0,0 +1,20
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 PACKAGE spectral_matrix_package IS
5
6 COMPONENT spectral_matrix_switch_f0
7 PORT (
8 clk : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
10 sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
11 fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
12 fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
13 fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 error_wen : OUT STD_LOGIC);
18 END COMPONENT;
19
20 END spectral_matrix_package;
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@@ -0,0 +1,99
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 ENTITY spectral_matrix_switch_f0 IS
6
7 PORT (
8 clk : IN STD_LOGIC;
9 rstn : IN STD_LOGIC;
10 --INPUT
11 sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
12 --OUTPUT A
13 fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
16 --OUTPUT B
17 fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
18 fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
19 fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
20 --ERROR
21 error_wen : OUT STD_LOGIC
22 );
23
24 END spectral_matrix_switch_f0;
25
26 ARCHITECTURE beh OF spectral_matrix_switch_f0 IS
27 SIGNAL ALL_1_sample_wen : STD_LOGIC;
28
29 SIGNAL ALL_1_fifo_A_empty : STD_LOGIC;
30 SIGNAL ALL_1_fifo_A_full : STD_LOGIC;
31 SIGNAL ALL_1_fifo_B_empty : STD_LOGIC;
32 SIGNAL ALL_1_fifo_B_full : STD_LOGIC;
33
34 TYPE state_fsm_switch_f0 IS (state_A,state_B,state_AtoB,state_BtoA);
35 SIGNAL state_fsm : state_fsm_switch_f0;
36
37 BEGIN -- beh
38 ALL_1_sample_wen <= '1' WHEN sample_wen = "11111" ELSE '0';
39
40 ALL_1_fifo_A_empty <= '1' WHEN fifo_A_empty = "11111" ELSE '0';
41 ALL_1_fifo_A_full <= '1' WHEN fifo_A_full = "11111" ELSE '0';
42 ALL_1_fifo_B_empty <= '1' WHEN fifo_B_empty = "11111" ELSE '0';
43 ALL_1_fifo_B_full <= '1' WHEN fifo_B_full = "11111" ELSE '0';
44
45 fifo_A_wen <= sample_wen WHEN state_fsm = state_A ELSE (OTHERS => '1');
46 fifo_B_wen <= sample_wen WHEN state_fsm = state_B ELSE (OTHERS => '1');
47
48 PROCESS (clk, rstn)
49 BEGIN
50 IF rstn = '0' THEN
51 state_fsm <= state_A;
52 error_wen <= '0';
53
54 ELSIF clk'event AND clk = '1' THEN
55 CASE state_fsm IS
56
57 WHEN state_A =>
58 error_wen <= '0';
59 IF ALL_1_fifo_A_full = '1' THEN
60 --error_wen <= NOT ALL_1_sample_wen;
61 IF ALL_1_fifo_B_empty = '1' THEN
62 state_fsm <= state_B;
63 ELSE
64 state_fsm <= state_AtoB;
65 END IF;
66 END IF;
67
68 WHEN state_B =>
69 error_wen <= '0';
70 IF ALL_1_fifo_B_full = '1' THEN
71 --error_wen <= NOT ALL_1_sample_wen;
72 IF ALL_1_fifo_A_empty = '1' THEN
73 state_fsm <= state_A;
74 ELSE
75 state_fsm <= state_BtoA;
76 END IF;
77 END IF;
78
79 WHEN state_AtoB =>
80 error_wen <= NOT ALL_1_sample_wen;
81 IF ALL_1_fifo_B_empty = '1' THEN
82 state_fsm <= state_B;
83 END IF;
84
85 WHEN state_BtoA =>
86 error_wen <= NOT ALL_1_sample_wen;
87 IF ALL_1_fifo_A_empty = '1' THEN
88 state_fsm <= state_A;
89 END IF;
90
91 WHEN OTHERS => NULL;
92 END CASE;
93
94
95 END IF;
96 END PROCESS;
97
98
99 END beh;
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@@ -0,0 +1,64
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
6 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
7 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
8 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
9 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
10 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
11 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
12 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
13 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
14 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
15 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
16 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
17 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
19 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
20 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
21 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
22 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
23 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
24 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
25 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
26 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
27 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
28 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
29 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
30 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
31 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload
32 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im
33 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re
34 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid
35 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset
36 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart
37 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
38 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
39 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
40 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y
41 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
42 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
43 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
44 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
45 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
46 TreeUpdate [SetDefaultTree]
47 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {27617887437 ps} 0} {{Cursor 3} {10382020000 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {95613018769 ps} 0}
48 configure wave -namecolwidth 402
49 configure wave -valuecolwidth 199
50 configure wave -justifyvalue left
51 configure wave -signalnamewidth 0
52 configure wave -snapdistance 10
53 configure wave -datasetprefix 0
54 configure wave -rowmargin 4
55 configure wave -childrowmargin 2
56 configure wave -gridoffset 0
57 configure wave -gridperiod 1
58 configure wave -griddelta 40
59 configure wave -timeline 0
60 configure wave -timelineunits ps
61 update
62 WaveRestoreZoom {10380205948 ps} {10383691010 ps}
63 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
64 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
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@@ -1,117 +1,117
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
1 set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
2 set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
3 set_io reset -pinname N18 -fixed yes -DIRECTION Inout
4
4
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
5 set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
6 set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
7 set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
8 set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
9 set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
10 set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
11 set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
12 set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
13 set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
14 set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
15 set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
16 set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
17 set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
18 set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
19 set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
20 set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
21 set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
22 set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
23 set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
24 set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
25
25
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
26 set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
27 set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
28 set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
29 set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
30 set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
31 set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
32 set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
33 set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
34 set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
35 set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
36 set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
37 set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
38 set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
39 set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
40 set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
41 set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
42 set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
43 set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
44 set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
45 set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
46 set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
47 set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
48 set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
49 set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
50 set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
51 set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
52 set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
53 set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
54 set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
55 set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
56 set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
57 set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
58
58
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
59 set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
60 set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
61 set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
62 set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
63 set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
64 set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
65 set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
66
66
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
67 set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
68 set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
76
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
80
80
81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
81 set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
82 set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
83 set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
84 set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
85 #set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
86 #set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
87 #set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
88 set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
89 #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
90
90
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
91 set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
92
92
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
93 set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
94 set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
95 set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
96 set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
97 set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
98 set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
99 set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
100 set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
101
101
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
102 set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
103
103
104 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
104 set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
105 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
105 set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
106 set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
107 set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
108 set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
109 set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
110 set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
111 set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
112 set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
113 set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
114 set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
115 set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
116 set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
117 set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout
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@@ -1,587 +1,587
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176
176
177 BEGIN -- beh
177 BEGIN -- beh
178
178
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180 -- CLK
180 -- CLK
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182
182
183 PROCESS(clk_50)
183 PROCESS(clk_50)
184 BEGIN
184 BEGIN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
186 clk_50_s <= NOT clk_50_s;
186 clk_50_s <= NOT clk_50_s;
187 END IF;
187 END IF;
188 END PROCESS;
188 END PROCESS;
189
189
190 PROCESS(clk_50_s)
190 PROCESS(clk_50_s)
191 BEGIN
191 BEGIN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
193 clk_25 <= NOT clk_25;
193 clk_25 <= NOT clk_25;
194 END IF;
194 END IF;
195 END PROCESS;
195 END PROCESS;
196
196
197 PROCESS(clk_49)
197 PROCESS(clk_49)
198 BEGIN
198 BEGIN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
200 clk_24 <= NOT clk_24;
200 clk_24 <= NOT clk_24;
201 END IF;
201 END IF;
202 END PROCESS;
202 END PROCESS;
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205
205
206 PROCESS (clk_25, reset)
206 PROCESS (clk_25, reset)
207 BEGIN -- PROCESS
207 BEGIN -- PROCESS
208 IF reset = '0' THEN -- asynchronous reset (active low)
208 IF reset = '0' THEN -- asynchronous reset (active low)
209 LED0 <= '0';
209 LED0 <= '0';
210 LED1 <= '0';
210 LED1 <= '0';
211 LED2 <= '0';
211 LED2 <= '0';
212 --IO1 <= '0';
212 --IO1 <= '0';
213 --IO2 <= '1';
213 --IO2 <= '1';
214 --IO3 <= '0';
214 --IO3 <= '0';
215 --IO4 <= '0';
215 --IO4 <= '0';
216 --IO5 <= '0';
216 --IO5 <= '0';
217 --IO6 <= '0';
217 --IO6 <= '0';
218 --IO7 <= '0';
218 --IO7 <= '0';
219 --IO8 <= '0';
219 --IO8 <= '0';
220 --IO9 <= '0';
220 --IO9 <= '0';
221 --IO10 <= '0';
221 --IO10 <= '0';
222 --IO11 <= '0';
222 --IO11 <= '0';
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
224 LED0 <= '0';
224 LED0 <= '0';
225 LED1 <= '1';
225 LED1 <= '1';
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
227 --IO1 <= '1';
227 --IO1 <= '1';
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
229 --IO3 <= ADC_SDO(0);
229 --IO3 <= ADC_SDO(0);
230 --IO4 <= ADC_SDO(1);
230 --IO4 <= ADC_SDO(1);
231 --IO5 <= ADC_SDO(2);
231 --IO5 <= ADC_SDO(2);
232 --IO6 <= ADC_SDO(3);
232 --IO6 <= ADC_SDO(3);
233 --IO7 <= ADC_SDO(4);
233 --IO7 <= ADC_SDO(4);
234 --IO8 <= ADC_SDO(5);
234 --IO8 <= ADC_SDO(5);
235 --IO9 <= ADC_SDO(6);
235 --IO9 <= ADC_SDO(6);
236 --IO10 <= ADC_SDO(7);
236 --IO10 <= ADC_SDO(7);
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
238 END IF;
238 END IF;
239 END PROCESS;
239 END PROCESS;
240
240
241 PROCESS (clk_24, reset)
241 PROCESS (clk_24, reset)
242 BEGIN -- PROCESS
242 BEGIN -- PROCESS
243 IF reset = '0' THEN -- asynchronous reset (active low)
243 IF reset = '0' THEN -- asynchronous reset (active low)
244 I00_s <= '0';
244 I00_s <= '0';
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
246 I00_s <= NOT I00_s ;
246 I00_s <= NOT I00_s ;
247 END IF;
247 END IF;
248 END PROCESS;
248 END PROCESS;
249 -- IO0 <= I00_s;
249 -- IO0 <= I00_s;
250
250
251 --UARTs
251 --UARTs
252 nCTS1 <= '1';
252 nCTS1 <= '1';
253 nCTS2 <= '1';
253 nCTS2 <= '1';
254 nDCD2 <= '1';
254 nDCD2 <= '1';
255
255
256 --EXT CONNECTOR
256 --EXT CONNECTOR
257
257
258 --SPACE WIRE
258 --SPACE WIRE
259
259
260 leon3_soc_1 : leon3_soc
260 leon3_soc_1 : leon3_soc
261 GENERIC MAP (
261 GENERIC MAP (
262 fabtech => apa3e,
262 fabtech => apa3e,
263 memtech => apa3e,
263 memtech => apa3e,
264 padtech => inferred,
264 padtech => inferred,
265 clktech => inferred,
265 clktech => inferred,
266 disas => 0,
266 disas => 0,
267 dbguart => 0,
267 dbguart => 0,
268 pclow => 2,
268 pclow => 2,
269 clk_freq => 25000,
269 clk_freq => 25000,
270 NB_CPU => 1,
270 NB_CPU => 1,
271 ENABLE_FPU => 1,
271 ENABLE_FPU => 1,
272 FPU_NETLIST => 0,
272 FPU_NETLIST => 0,
273 ENABLE_DSU => 1,
273 ENABLE_DSU => 1,
274 ENABLE_AHB_UART => 1,
274 ENABLE_AHB_UART => 1,
275 ENABLE_APB_UART => 1,
275 ENABLE_APB_UART => 1,
276 ENABLE_IRQMP => 1,
276 ENABLE_IRQMP => 1,
277 ENABLE_GPT => 1,
277 ENABLE_GPT => 1,
278 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_MASTER => NB_AHB_MASTER,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
280 NB_APB_SLAVE => NB_APB_SLAVE)
280 NB_APB_SLAVE => NB_APB_SLAVE)
281 PORT MAP (
281 PORT MAP (
282 clk => clk_25,
282 clk => clk_25,
283 reset => reset,
283 reset => reset,
284 errorn => errorn,
284 errorn => errorn,
285 ahbrxd => TXD1,
285 ahbrxd => TXD1,
286 ahbtxd => RXD1,
286 ahbtxd => RXD1,
287 urxd1 => TXD2,
287 urxd1 => TXD2,
288 utxd1 => RXD2,
288 utxd1 => RXD2,
289 address => SRAM_A,
289 address => SRAM_A,
290 data => SRAM_DQ,
290 data => SRAM_DQ,
291 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE0 => SRAM_nBE(0),
292 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE1 => SRAM_nBE(1),
293 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE2 => SRAM_nBE(2),
294 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_BE3 => SRAM_nBE(3),
295 nSRAM_WE => SRAM_nWE,
295 nSRAM_WE => SRAM_nWE,
296 nSRAM_CE => SRAM_CE,
296 nSRAM_CE => SRAM_CE,
297 nSRAM_OE => SRAM_nOE,
297 nSRAM_OE => SRAM_nOE,
298
298
299 apbi_ext => apbi_ext,
299 apbi_ext => apbi_ext,
300 apbo_ext => apbo_ext,
300 apbo_ext => apbo_ext,
301 ahbi_s_ext => ahbi_s_ext,
301 ahbi_s_ext => ahbi_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
303 ahbi_m_ext => ahbi_m_ext,
303 ahbi_m_ext => ahbi_m_ext,
304 ahbo_m_ext => ahbo_m_ext);
304 ahbo_m_ext => ahbo_m_ext);
305
305
306 -------------------------------------------------------------------------------
306 -------------------------------------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 apb_lfr_time_management_1 : apb_lfr_time_management
309 apb_lfr_time_management_1 : apb_lfr_time_management
310 GENERIC MAP (
310 GENERIC MAP (
311 pindex => 6,
311 pindex => 6,
312 paddr => 6,
312 paddr => 6,
313 pmask => 16#fff#,
313 pmask => 16#fff#,
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
316 PORT MAP (
316 PORT MAP (
317 clk25MHz => clk_25,
317 clk25MHz => clk_25,
318 clk24_576MHz => clk_24, -- 49.152MHz/2
318 clk24_576MHz => clk_24, -- 49.152MHz/2
319 resetn => reset,
319 resetn => reset,
320 grspw_tick => swno.tickout,
320 grspw_tick => swno.tickout,
321 apbi => apbi_ext,
321 apbi => apbi_ext,
322 apbo => apbo_ext(6),
322 apbo => apbo_ext(6),
323 coarse_time => coarse_time,
323 coarse_time => coarse_time,
324 fine_time => fine_time);
324 fine_time => fine_time);
325
325
326 -----------------------------------------------------------------------
326 -----------------------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329
329
330 SPW_EN <= '1';
330 SPW_EN <= '1';
331
331
332 spw_clk <= clk_50_s;
332 spw_clk <= clk_50_s;
333 spw_rxtxclk <= spw_clk;
333 spw_rxtxclk <= spw_clk;
334 spw_rxclkn <= NOT spw_rxtxclk;
334 spw_rxclkn <= NOT spw_rxtxclk;
335
335
336 -- PADS for SPW1
336 -- PADS for SPW1
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_SIN, stmp(0));
340 PORT MAP (SPW_NOM_SIN, stmp(0));
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
345 -- PADS FOR SPW2
345 -- PADS FOR SPW2
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 PORT MAP (SPW_RED_SIN, dtmp(1));
347 PORT MAP (SPW_RED_SIN, dtmp(1));
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_DIN, stmp(1));
349 PORT MAP (SPW_RED_DIN, stmp(1));
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
354
354
355 -- GRSPW PHY
355 -- GRSPW PHY
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
358 spw_phy0 : grspw_phy
358 spw_phy0 : grspw_phy
359 GENERIC MAP(
359 GENERIC MAP(
360 tech => apa3e,
360 tech => apa3e,
361 rxclkbuftype => 1,
361 rxclkbuftype => 1,
362 scantest => 0)
362 scantest => 0)
363 PORT MAP(
363 PORT MAP(
364 rxrst => swno.rxrst,
364 rxrst => swno.rxrst,
365 di => dtmp(j),
365 di => dtmp(j),
366 si => stmp(j),
366 si => stmp(j),
367 rxclko => spw_rxclk(j),
367 rxclko => spw_rxclk(j),
368 do => swni.d(j),
368 do => swni.d(j),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
371 END GENERATE spw_inputloop;
371 END GENERATE spw_inputloop;
372
372
373 -- SPW core
373 -- SPW core
374 sw0 : grspwm GENERIC MAP(
374 sw0 : grspwm GENERIC MAP(
375 tech => apa3e,
375 tech => apa3e,
376 hindex => 1,
376 hindex => 1,
377 pindex => 5,
377 pindex => 5,
378 paddr => 5,
378 paddr => 5,
379 pirq => 11,
379 pirq => 11,
380 sysfreq => 25000, -- CPU_FREQ
380 sysfreq => 25000, -- CPU_FREQ
381 rmap => 1,
381 rmap => 1,
382 rmapcrc => 1,
382 rmapcrc => 1,
383 fifosize1 => 16,
383 fifosize1 => 16,
384 fifosize2 => 16,
384 fifosize2 => 16,
385 rxclkbuftype => 1,
385 rxclkbuftype => 1,
386 rxunaligned => 0,
386 rxunaligned => 0,
387 rmapbufs => 4,
387 rmapbufs => 4,
388 ft => 0,
388 ft => 0,
389 netlist => 0,
389 netlist => 0,
390 ports => 2,
390 ports => 2,
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
392 memtech => apa3e,
392 memtech => apa3e,
393 destkey => 2,
393 destkey => 2,
394 spwcore => 1
394 spwcore => 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
398 )
398 )
399 PORT MAP(reset, clk_25, spw_rxclk(0),
399 PORT MAP(reset, clk_25, spw_rxclk(0),
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
402 swni, swno);
402 swni, swno);
403
403
404 swni.tickin <= '0';
404 swni.tickin <= '0';
405 swni.rmapen <= '1';
405 swni.rmapen <= '1';
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
407 swni.tickinraw <= '0';
407 swni.tickinraw <= '0';
408 swni.timein <= (OTHERS => '0');
408 swni.timein <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
411
411
412 -------------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 lpp_lfr_1 : lpp_lfr
415 lpp_lfr_1 : lpp_lfr
416 GENERIC MAP (
416 GENERIC MAP (
417 Mem_use => use_RAM,
417 Mem_use => use_RAM,
418 nb_data_by_buffer_size => 32,
418 nb_data_by_buffer_size => 32,
419 nb_word_by_buffer_size => 30,
419 nb_word_by_buffer_size => 30,
420 nb_snapshot_param_size => 32,
420 nb_snapshot_param_size => 32,
421 delta_vector_size => 32,
421 delta_vector_size => 32,
422 delta_vector_size_f0_2 => 7, -- log2(96)
422 delta_vector_size_f0_2 => 7, -- log2(96)
423 pindex => 15,
423 pindex => 15,
424 paddr => 15,
424 paddr => 15,
425 pmask => 16#fff#,
425 pmask => 16#fff#,
426 pirq_ms => 6,
426 pirq_ms => 6,
427 pirq_wfp => 14,
427 pirq_wfp => 14,
428 hindex => 2,
428 hindex => 2,
429 top_lfr_version => X"00010A") -- aa.bb.cc version
429 top_lfr_version => X"00010B") -- aa.bb.cc version
430 PORT MAP (
430 PORT MAP (
431 clk => clk_25,
431 clk => clk_25,
432 rstn => reset,
432 rstn => reset,
433 sample_B => sample_s(2 DOWNTO 0),
433 sample_B => sample_s(2 DOWNTO 0),
434 sample_E => sample_s(7 DOWNTO 3),
434 sample_E => sample_s(7 DOWNTO 3),
435 sample_val => sample_val,
435 sample_val => sample_val,
436 apbi => apbi_ext,
436 apbi => apbi_ext,
437 apbo => apbo_ext(15),
437 apbo => apbo_ext(15),
438 ahbi => ahbi_m_ext,
438 ahbi => ahbi_m_ext,
439 ahbo => ahbo_m_ext(2),
439 ahbo => ahbo_m_ext(2),
440 coarse_time => coarse_time,
440 coarse_time => coarse_time,
441 fine_time => fine_time,
441 fine_time => fine_time,
442 data_shaping_BW => bias_fail_sw_sig,
442 data_shaping_BW => bias_fail_sw_sig,
443 observation_reg => observation_reg);
443 observation_reg => observation_reg);
444
444
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 sample_s(I) <= sample(I) & '0' & '0';
446 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
447 END GENERATE all_sample;
447 END GENERATE all_sample;
448
448
449
449
450
450
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
452 GENERIC MAP(
452 GENERIC MAP(
453 ChannelCount => 8,
453 ChannelCount => 8,
454 SampleNbBits => 14,
454 SampleNbBits => 14,
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
457 PORT MAP (
457 PORT MAP (
458 -- CONV
458 -- CONV
459 cnv_clk => clk_24,
459 cnv_clk => clk_24,
460 cnv_rstn => reset,
460 cnv_rstn => reset,
461 cnv => ADC_nCS_sig,
461 cnv => ADC_nCS_sig,
462 -- DATA
462 -- DATA
463 clk => clk_25,
463 clk => clk_25,
464 rstn => reset,
464 rstn => reset,
465 sck => ADC_CLK_sig,
465 sck => ADC_CLK_sig,
466 sdo => ADC_SDO_sig,
466 sdo => ADC_SDO_sig,
467 -- SAMPLE
467 -- SAMPLE
468 sample => sample,
468 sample => sample,
469 sample_val => sample_val);
469 sample_val => sample_val);
470
470
471 --IO10 <= ADC_SDO_sig(5);
471 --IO10 <= ADC_SDO_sig(5);
472 --IO9 <= ADC_SDO_sig(4);
472 --IO9 <= ADC_SDO_sig(4);
473 --IO8 <= ADC_SDO_sig(3);
473 --IO8 <= ADC_SDO_sig(3);
474
474
475 ADC_nCS <= ADC_nCS_sig;
475 ADC_nCS <= ADC_nCS_sig;
476 ADC_CLK <= ADC_CLK_sig;
476 ADC_CLK <= ADC_CLK_sig;
477 ADC_SDO_sig <= ADC_SDO;
477 ADC_SDO_sig <= ADC_SDO;
478
478
479 ----------------------------------------------------------------------
479 ----------------------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
481 ----------------------------------------------------------------------
481 ----------------------------------------------------------------------
482
482
483 grgpio0 : grgpio
483 grgpio0 : grgpio
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
486
486
487 --pio_pad_0 : iopad
487 --pio_pad_0 : iopad
488 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- GENERIC MAP (tech => CFG_PADTECH)
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
490 --pio_pad_1 : iopad
490 --pio_pad_1 : iopad
491 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
493 --pio_pad_2 : iopad
493 --pio_pad_2 : iopad
494 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
496 --pio_pad_3 : iopad
496 --pio_pad_3 : iopad
497 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
499 --pio_pad_4 : iopad
499 --pio_pad_4 : iopad
500 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
502 --pio_pad_5 : iopad
502 --pio_pad_5 : iopad
503 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
505 --pio_pad_6 : iopad
505 --pio_pad_6 : iopad
506 -- GENERIC MAP (tech => CFG_PADTECH)
506 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
508 --pio_pad_7 : iopad
508 --pio_pad_7 : iopad
509 -- GENERIC MAP (tech => CFG_PADTECH)
509 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
511
511
512 PROCESS (clk_25, reset)
512 PROCESS (clk_25, reset)
513 BEGIN -- PROCESS
513 BEGIN -- PROCESS
514 IF reset = '0' THEN -- asynchronous reset (active low)
514 IF reset = '0' THEN -- asynchronous reset (active low)
515 IO0 <= '0';
515 IO0 <= '0';
516 IO1 <= '0';
516 IO1 <= '0';
517 IO2 <= '0';
517 IO2 <= '0';
518 IO3 <= '0';
518 IO3 <= '0';
519 IO4 <= '0';
519 IO4 <= '0';
520 IO5 <= '0';
520 IO5 <= '0';
521 IO6 <= '0';
521 IO6 <= '0';
522 IO7 <= '0';
522 IO7 <= '0';
523 IO8 <= '0';
523 IO8 <= '0';
524 IO9 <= '0';
524 IO9 <= '0';
525 IO10 <= '0';
525 IO10 <= '0';
526 IO11 <= '0';
526 IO11 <= '0';
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
528 CASE gpioo.dout(1 DOWNTO 0) IS
528 CASE gpioo.dout(1 DOWNTO 0) IS
529 WHEN "00" =>
529 WHEN "00" =>
530 IO0 <= observation_reg(0 );
530 IO0 <= observation_reg(0 );
531 IO1 <= observation_reg(1 );
531 IO1 <= observation_reg(1 );
532 IO2 <= observation_reg(2 );
532 IO2 <= observation_reg(2 );
533 IO3 <= observation_reg(3 );
533 IO3 <= observation_reg(3 );
534 IO4 <= observation_reg(4 );
534 IO4 <= observation_reg(4 );
535 IO5 <= observation_reg(5 );
535 IO5 <= observation_reg(5 );
536 IO6 <= observation_reg(6 );
536 IO6 <= observation_reg(6 );
537 IO7 <= observation_reg(7 );
537 IO7 <= observation_reg(7 );
538 IO8 <= observation_reg(8 );
538 IO8 <= observation_reg(8 );
539 IO9 <= observation_reg(9 );
539 IO9 <= observation_reg(9 );
540 IO10 <= observation_reg(10);
540 IO10 <= observation_reg(10);
541 IO11 <= observation_reg(11);
541 IO11 <= observation_reg(11);
542 WHEN "01" =>
542 WHEN "01" =>
543 IO0 <= observation_reg(0 + 12);
543 IO0 <= observation_reg(0 + 12);
544 IO1 <= observation_reg(1 + 12);
544 IO1 <= observation_reg(1 + 12);
545 IO2 <= observation_reg(2 + 12);
545 IO2 <= observation_reg(2 + 12);
546 IO3 <= observation_reg(3 + 12);
546 IO3 <= observation_reg(3 + 12);
547 IO4 <= observation_reg(4 + 12);
547 IO4 <= observation_reg(4 + 12);
548 IO5 <= observation_reg(5 + 12);
548 IO5 <= observation_reg(5 + 12);
549 IO6 <= observation_reg(6 + 12);
549 IO6 <= observation_reg(6 + 12);
550 IO7 <= observation_reg(7 + 12);
550 IO7 <= observation_reg(7 + 12);
551 IO8 <= observation_reg(8 + 12);
551 IO8 <= observation_reg(8 + 12);
552 IO9 <= observation_reg(9 + 12);
552 IO9 <= observation_reg(9 + 12);
553 IO10 <= observation_reg(10 + 12);
553 IO10 <= observation_reg(10 + 12);
554 IO11 <= observation_reg(11 + 12);
554 IO11 <= observation_reg(11 + 12);
555 WHEN "10" =>
555 WHEN "10" =>
556 IO0 <= observation_reg(0 + 12 + 12);
556 IO0 <= observation_reg(0 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
564 IO8 <= '0';
564 IO8 <= '0';
565 IO9 <= '0';
565 IO9 <= '0';
566 IO10 <= '0';
566 IO10 <= '0';
567 IO11 <= '0';
567 IO11 <= '0';
568 WHEN "11" =>
568 WHEN "11" =>
569 IO0 <= '0';
569 IO0 <= '0';
570 IO1 <= '0';
570 IO1 <= '0';
571 IO2 <= '0';
571 IO2 <= '0';
572 IO3 <= '0';
572 IO3 <= '0';
573 IO4 <= '0';
573 IO4 <= '0';
574 IO5 <= '0';
574 IO5 <= '0';
575 IO6 <= '0';
575 IO6 <= '0';
576 IO7 <= '0';
576 IO7 <= '0';
577 IO8 <= '0';
577 IO8 <= '0';
578 IO9 <= '0';
578 IO9 <= '0';
579 IO10 <= '0';
579 IO10 <= '0';
580 IO11 <= '0';
580 IO11 <= '0';
581 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
582 END CASE;
582 END CASE;
583
583
584 END IF;
584 END IF;
585 END PROCESS;
585 END PROCESS;
586
586
587 END beh;
587 END beh;
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