diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc --- a/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc +++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc @@ -21,7 +21,7 @@ set_io {address[15]} -pinname N1 -fixed set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout -set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout +set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -426,7 +426,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00010A") -- aa.bb.cc version + top_lfr_version => X"00010B") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, @@ -443,7 +443,7 @@ BEGIN -- beh observation_reg => observation_reg); all_sample: FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; + sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; END GENERATE all_sample; diff --git a/designs/Validation_LFR_SpectralMatrix/Makefile b/designs/Validation_LFR_SpectralMatrix/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/Makefile @@ -0,0 +1,383 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ + +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=TB + +CMD_VLIB=vlib +CMD_VMAP=vmap +CMD_VCOM=@vcom -quiet -93 -work + +################## project specific targets ########################## + +all: + @echo "make vsim" + @echo "make libs" + @echo "make clean" + @echo "make vcom_grlib vcom_lpp vcom_tb" + +run: + @vsim work.TB -do run.do +# @vsim work.TB +# @vsim lpp.lpp_lfr_ms + +vsim: libs vcom run + +libs: + @$(CMD_VLIB) modelsim + @$(CMD_VMAP) modelsim modelsim + @$(CMD_VLIB) modelsim/techmap + @$(CMD_VMAP) techmap modelsim/techmap + @$(CMD_VLIB) modelsim/grlib + @$(CMD_VMAP) grlib modelsim/grlib + @$(CMD_VLIB) modelsim/gaisler + @$(CMD_VMAP) gaisler modelsim/gaisler + @$(CMD_VLIB) modelsim/work + @$(CMD_VMAP) work modelsim/work + @$(CMD_VLIB) modelsim/lpp + @$(CMD_VMAP) lpp modelsim/lpp + @echo "libs done" + + +clean: + @rm -Rf modelsim + @rm -Rf modelsim.ini + @rm -Rf *~ + @rm -Rf transcript + @rm -Rf wlft* + @rm -Rf *.wlf + @rm -Rf vish_stacktrace.vstf + @rm -Rf libs.do + +vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb + + +vcom_tb: + $(CMD_VCOM) lpp lpp_memory.vhd + $(CMD_VCOM) lpp lppFIFOxN.vhd + $(CMD_VCOM) lpp lpp_FIFO.vhd + $(CMD_VCOM) lpp spectral_matrix_package.vhd + $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd + $(CMD_VCOM) lpp lpp_lfr_ms.vhd + $(CMD_VCOM) work TB.vhd + @echo "vcom done" + +vcom_grlib: + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd + $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd + @echo "vcom grlib done" + +vcom_gaisler: + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd +# # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd +## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd + $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd +# $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd + @echo "vcom gaisler done" + +vcom_techmap: + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd + $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd +# $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd + @echo "vcom techmap done" + +vcom_lpp: + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd + @echo "vcom lpp done" + +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd +# $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd +# @echo "vcom lpp done" + +#include Makefile_vcom_lpp diff --git a/designs/Validation_LFR_SpectralMatrix/TB.vhd b/designs/Validation_LFR_SpectralMatrix/TB.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/TB.vhd @@ -0,0 +1,313 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +use lpp.lpp_fft.all; +use lpp.fft_components.all; + +ENTITY TB IS + + +END TB; + + +ARCHITECTURE beh OF TB IS + + COMPONENT lpp_lfr_ms + GENERIC ( + Mem_use : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : IN STD_LOGIC; + status_ready_matrix_f0_1 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + status_error_anticipating_empty_fifo : IN STD_LOGIC; + status_error_bad_component_error : IN STD_LOGIC; + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + SIGNAL clk25MHz : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_valid : STD_LOGIC; + SIGNAL dma_valid_burst : STD_LOGIC; + SIGNAL dma_ren : STD_LOGIC; + SIGNAL dma_done : STD_LOGIC; + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL sample_counter_24k : INTEGER; + SIGNAL s_24576Hz : STD_LOGIC; + + SIGNAL s_24_sync_reg_0 : STD_LOGIC; + SIGNAL s_24_sync_reg_1 : STD_LOGIC; + + SIGNAL s_24576Hz_sync : STD_LOGIC; + + SIGNAL sample_counter_f1 : INTEGER; + SIGNAL sample_counter_f2 : INTEGER; + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f2_val : STD_LOGIC; + +BEGIN -- beh + + clk25MHz <= NOT clk25MHz AFTER 20 ns; + clk25MHz <= NOT clk25MHz AFTER 20 ns; + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + rstn <= '1'; + WAIT UNTIL clk25MHz = '1'; + + + WAIT FOR 100 ms; + + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + + END PROCESS; + + + ----------------------------------------------------------------------------- + PROCESS (clk49_152MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_counter_24k <= 0; + s_24576Hz <= '0'; + ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge + IF sample_counter_24k = 0 THEN + sample_counter_24k <= 2000; + s_24576Hz <= NOT s_24576Hz; + ELSE + sample_counter_24k <= sample_counter_24k - 1; + END IF; + END IF; + END PROCESS; + + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + s_24_sync_reg_0 <= '0'; + s_24_sync_reg_1 <= '0'; + s_24576Hz_sync <= '0'; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + s_24_sync_reg_0 <= s_24576Hz; + s_24_sync_reg_1 <= s_24_sync_reg_0; + s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1; + END IF; + END PROCESS; + + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f2_val <= '0'; + + sample_counter_f1 <= 0; + sample_counter_f2 <= 0; + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + IF s_24576Hz_sync = '1' THEN + sample_f0_val <= '1'; + IF sample_counter_f1 = 0 THEN + sample_f1_val <= '1'; + sample_counter_f1 <= 5; + ELSE + sample_f1_val <= '0'; + sample_counter_f1 <= sample_counter_f1 -1; + END IF; + IF sample_counter_f2 = 0 THEN + sample_f2_val <= '1'; + sample_counter_f2 <= 95; + ELSE + sample_f2_val <= '0'; + sample_counter_f2 <= sample_counter_f2 -1; + END IF; + ELSE + sample_f0_val <= '0'; + sample_f1_val <= '0'; + sample_f2_val <= '0'; + END IF; + END IF; + END PROCESS; + + + + ----------------------------------------------------------------------------- + coarse_time <= (OTHERS => '0'); + fine_time <= (OTHERS => '0'); + + sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444"; + sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444"; + sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444"; + + sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val); + sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val); + sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val); + ----------------------------------------------------------------------------- + + lpp_lfr_ms_1: ENTITY lpp.lpp_lfr_ms + GENERIC MAP ( + Mem_use => use_CEL) + PORT MAP ( + clk => clk25MHz, + rstn => rstn, + -- + coarse_time => coarse_time, + fine_time => fine_time, + -- + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + -- + dma_addr => dma_addr, + dma_data => dma_data, + dma_valid => dma_valid, + dma_valid_burst => dma_valid_burst, + dma_ren => dma_ren, + dma_done => dma_done, + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + matrix_time_f0_0 => matrix_time_f0_0, + matrix_time_f0_1 => matrix_time_f0_1, + matrix_time_f1 => matrix_time_f1, + matrix_time_f2 => matrix_time_f2); + + dma_ren <= '0'; + dma_done <= '0'; + + status_ready_matrix_f0_0 <= '0'; + status_ready_matrix_f0_1 <= '0'; + status_ready_matrix_f1 <= '0'; + status_ready_matrix_f2 <= '0'; + status_error_anticipating_empty_fifo <= '0'; + status_error_bad_component_error <= '0'; + + config_active_interruption_onNewMatrix <= '0'; + config_active_interruption_onError <= '0'; + addr_matrix_f0_0 <= (OTHERS => '0'); + addr_matrix_f0_1 <= (OTHERS => '0'); + addr_matrix_f1 <= (OTHERS => '0'); + addr_matrix_f2 <= (OTHERS => '0'); + +END beh; + diff --git a/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd b/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/lppFIFOxN.vhd @@ -0,0 +1,70 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_memory.all; +use lpp.iir_filter.all; +library techmap; +use techmap.gencomp.all; + +entity lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 2 to 12 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rstn : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + almost_full : out std_logic_vector(FifoCnt-1 downto 0); -- TODO + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end entity; + + +architecture ar_lppFIFOxN of lppFIFOxN is + +begin + +fifos: for i in 0 to FifoCnt-1 generate + FIFO0 : lpp_fifo + generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) + port map(rstn,ReUse(i), + rclk, + ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open, + wclk, + wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),almost_full(i),open); +end generate; + +end architecture; diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/lpp_FIFO.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_fifo IS + GENERIC( + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM; + Enable_ReUse : STD_LOGIC := '0'; + DataSz : INTEGER RANGE 1 TO 32 := 8; + AddrSz : INTEGER RANGE 2 TO 12 := 8 + ); + PORT( + rstn : IN STD_LOGIC; + ReUse : IN STD_LOGIC; + rclk : IN STD_LOGIC; + ren : IN STD_LOGIC; + rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + empty : OUT STD_LOGIC; + raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0); + wclk : IN STD_LOGIC; + wen : IN STD_LOGIC; + wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); + full : OUT STD_LOGIC; + almost_full : OUT STD_LOGIC; -- TODO + waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS + + SIGNAL sFull : STD_LOGIC; + SIGNAL sFull_s : STD_LOGIC; + SIGNAL sEmpty_s : STD_LOGIC; + + SIGNAL sEmpty : STD_LOGIC; + SIGNAL sREN : STD_LOGIC; + SIGNAL sWEN : STD_LOGIC; + SIGNAL sRE : STD_LOGIC; + SIGNAL sWE : STD_LOGIC; + + SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0'); + + SIGNAL almost_full_s : STD_LOGIC; + SIGNAL almost_full_r : STD_LOGIC; +BEGIN + +--================================================================================== +-- /!\ syncram_2p Write et Read actif a l'état haut /!\ +-- A l'inverse de RAM_CEL !!! +--================================================================================== + memRAM : IF Mem_use = use_RAM GENERATE + SRAM : syncram_2p + GENERIC MAP(tech, AddrSz, DataSz) + PORT MAP(RCLK, sRE, Raddr_vect, rdata, WCLK, sWE, Waddr_vect, wdata); + END GENERATE; +--================================================================================== + memCEL : IF Mem_use = use_CEL GENERATE + CRAM : RAM_CEL + GENERIC MAP(DataSz, AddrSz) + PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); + END GENERATE; +--================================================================================== + +--============================= +-- Read section +--============================= + sREN <= REN OR sEmpty; + sRE <= NOT sREN; + + sEmpty_s <= '0' WHEN ReUse = '1' AND Enable_ReUse = '1' else + '1' WHEN sEmpty = '1' AND Wen = '1' ELSE + '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE + '0'; + + Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1); + + PROCESS (rclk, rstn) + BEGIN + IF(rstn = '0')then + Raddr_vect <= (OTHERS => '0'); + sempty <= '1'; + ELSIF(rclk'EVENT AND rclk = '1')then + sEmpty <= sempty_s; + + IF(sREN = '0' and sempty = '0')then + Raddr_vect <= Raddr_vect_s; + END IF; + + END IF; + END PROCESS; + +--============================= +-- Write section +--============================= + sWEN <= WEN OR sFull; + sWE <= NOT sWEN; + + sFull_s <= '1' WHEN ReUse = '1' AND Enable_ReUse = '1' else + '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE + '1' WHEN sFull = '1' AND REN = '1' ELSE + '0'; + + almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE + '1' WHEN almost_full_r = '1' AND WEN = REN ELSE + '0'; + + Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1); + + PROCESS (wclk, rstn) + BEGIN + IF(rstn = '0')then + Waddr_vect <= (OTHERS => '0'); + sfull <= '0'; + almost_full_r <= '0'; + ELSIF(wclk'EVENT AND wclk = '1')then + sfull <= sfull_s; + almost_full_r <= almost_full_s; + + IF(sWEN = '0' and sfull = '0')THEN + Waddr_vect <= Waddr_vect_s; + END IF; + + END IF; + END PROCESS; + + almost_full <= almost_full_s; + full <= sFull_s; + empty <= sEmpty_s; + waddr <= Waddr_vect; + raddr <= Raddr_vect; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd @@ -0,0 +1,527 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; + +use lpp.lpp_fft.all; +use lpp.fft_components.all; + +ENTITY lpp_lfr_ms IS + GENERIC ( + Mem_use : INTEGER := use_RAM + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- DATA INPUT + --------------------------------------------------------------------------- + -- TIME + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo + -- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- DMA + --------------------------------------------------------------------------- + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + + -- Reg out + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0_0 : IN STD_LOGIC; + status_ready_matrix_f0_1 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + status_error_anticipating_empty_fifo : IN STD_LOGIC; + status_error_bad_component_error : IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms IS + + SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL error_wen_f0 : STD_LOGIC; + SIGNAL error_wen_f1 : STD_LOGIC; + SIGNAL error_wen_f2 : STD_LOGIC; + + SIGNAL one_sample_f1_full : STD_LOGIC; + SIGNAL one_sample_f1_wen : STD_LOGIC; + SIGNAL one_sample_f2_full : STD_LOGIC; + SIGNAL one_sample_f2_wen : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- FSM / SWITCH SELECT CHANNEL + ----------------------------------------------------------------------------- + TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); + SIGNAL state_fsm_select_channel : fsm_select_channel; + + SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- FSM LOAD FFT + ----------------------------------------------------------------------------- + TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_transition); + SIGNAL state_fsm_load_FFT : fsm_load_FFT; + SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; + + SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_load : STD_LOGIC; + SIGNAL sample_valid : STD_LOGIC; + SIGNAL sample_valid_r : STD_LOGIC; + SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + + + ----------------------------------------------------------------------------- + -- FFT + ----------------------------------------------------------------------------- + SIGNAL fft_read : STD_LOGIC; + SIGNAL fft_pong : STD_LOGIC; + SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_valid : STD_LOGIC; + SIGNAL fft_ready : STD_LOGIC; + +BEGIN + + switch_f0_inst : spectral_matrix_switch_f0 + PORT MAP ( + clk => clk, + rstn => rstn, + + sample_wen => sample_f0_wen, + + fifo_A_empty => sample_f0_A_empty, + fifo_A_full => sample_f0_A_full, + fifo_A_wen => sample_f0_A_wen, + + fifo_B_empty => sample_f0_B_empty, + fifo_B_full => sample_f0_B_full, + fifo_B_wen => sample_f0_B_wen, + + error_wen => error_wen_f0); -- TODO + + ----------------------------------------------------------------------------- + -- FIFO IN + ----------------------------------------------------------------------------- + lppFIFOxN_f0_a : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f0_A_wen, -- IN in + ren => sample_f0_A_ren, -- OUT in + wdata => sample_f0_wdata, -- IN in + rdata => sample_f0_A_rdata, -- OUT in + full => sample_f0_A_full, -- IN out + almost_full => OPEN, -- IN out + empty => sample_f0_A_empty); -- OUT OUT + + lppFIFOxN_f0_b : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f0_B_wen, -- IN in + ren => sample_f0_B_ren, -- OUT in + wdata => sample_f0_wdata, -- IN in + rdata => sample_f0_B_rdata, -- OUT in + full => sample_f0_B_full, -- IN out + almost_full => OPEN, -- IN out + empty => sample_f0_B_empty); -- OUT OUT + + lppFIFOxN_f1 : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f1_wen, -- IN in + ren => sample_f1_ren, -- OUT in + wdata => sample_f1_wdata, -- IN in + rdata => sample_f1_rdata, -- OUT in + full => sample_f1_full, -- IN out + almost_full => sample_f1_almost_full, -- IN out + empty => sample_f1_empty); -- OUT OUT + + + one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + one_sample_f1_full <= '0'; + error_wen_f1 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sample_f1_full = "00000" THEN + one_sample_f1_full <= '0'; + ELSE + one_sample_f1_full <= '1'; + END IF; + error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; + END IF; + END PROCESS; + + + lppFIFOxN_f2 : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rstn => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f2_wen, -- IN in + ren => sample_f2_ren, -- OUT in + wdata => sample_f2_wdata, -- IN in + rdata => sample_f2_rdata, -- OUT in + full => sample_f2_full, -- IN out + almost_full => OPEN, -- IN out + empty => sample_f2_empty); -- OUT OUT + + + one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + one_sample_f2_full <= '0'; + error_wen_f2 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sample_f2_full = "00000" THEN + one_sample_f2_full <= '0'; + ELSE + one_sample_f2_full <= '1'; + END IF; + error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- FSM SELECT CHANNEL + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_fsm_select_channel <= IDLE; + ELSIF clk'EVENT AND clk = '1' THEN + CASE state_fsm_select_channel IS + WHEN IDLE => + IF sample_f1_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F1; + ELSIF sample_f1_almost_full = "00000" THEN + IF sample_f0_A_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F0_A; + ELSIF sample_f0_B_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F0_B; + ELSIF sample_f2_full = "11111" THEN + state_fsm_select_channel <= SWITCH_F2; + END IF; + END IF; + + WHEN SWITCH_F0_A => + IF sample_f0_A_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F0_B => + IF sample_f0_B_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F1 => + IF sample_f1_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN SWITCH_F2 => + IF sample_f2_empty = "11111" THEN + state_fsm_select_channel <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + + + ----------------------------------------------------------------------------- + -- SWITCH SELECT CHANNEL + ----------------------------------------------------------------------------- + sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE + (OTHERS => '1'); + + sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE + (OTHERS => '0'); + + sample_rdata <= sample_f0_A_rdata WHEN state_fsm_select_channel = SWITCH_F0_A ELSE + sample_f0_B_rdata WHEN state_fsm_select_channel = SWITCH_F0_B ELSE + sample_f1_rdata WHEN state_fsm_select_channel = SWITCH_F1 ELSE + sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE + + + sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); + sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); + sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); + sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); + + ----------------------------------------------------------------------------- + -- FSM LOAD FFT + ----------------------------------------------------------------------------- + + sample_ren <= sample_ren_s;-- OR sample_empty; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= IDLE; + next_state_fsm_load_FFT <= IDLE; + sample_valid <= '0'; + ELSIF clk'event AND clk = '1' THEN + CASE state_fsm_load_FFT IS + WHEN IDLE => + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + IF sample_full = "11111" AND sample_load = '1' THEN + state_fsm_load_FFT <= FIFO_1; + END IF; + WHEN FIFO_1 => + sample_ren_s <= "1111" & NOT(sample_load); + sample_valid <= '1'; + IF sample_empty(0) = '1' THEN + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_transition; + next_state_fsm_load_FFT <= FIFO_2; + END IF; + + WHEN FIFO_transition => + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= next_state_fsm_load_FFT; + + WHEN FIFO_2 => + sample_ren_s <= "111" & NOT(sample_load) & '1'; + sample_valid <= sample_load; + IF sample_empty(1) = '1' THEN + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_transition; + next_state_fsm_load_FFT <= FIFO_3; + END IF; + WHEN FIFO_3 => + sample_ren_s <= "11" & NOT(sample_load) & "11"; + sample_valid <= sample_load;--'1'; + IF sample_empty(2) = '1' THEN + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_transition; + next_state_fsm_load_FFT <= FIFO_4; + END IF; + WHEN FIFO_4 => + sample_ren_s <= '1' & NOT(sample_load) & "111"; + sample_valid <= sample_load;--'1'; + IF sample_empty(3) = '1' THEN + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_transition; + next_state_fsm_load_FFT <= FIFO_5; + END IF; + WHEN FIFO_5 => + sample_ren_s <= NOT(sample_load) & "1111"; + sample_valid <= sample_load;--'1'; + IF sample_empty(4) = '1' THEN + sample_valid <= '0'; + sample_ren_s <= (OTHERS => '1'); + state_fsm_load_FFT <= FIFO_transition; + next_state_fsm_load_FFT <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_valid_r <= '0'; + ELSIF clk'event AND clk = '1' THEN + sample_valid_r <= sample_valid AND sample_load; + END IF; + END PROCESS; + + sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN state_fsm_load_FFT = FIFO_1 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_2) ELSE + sample_rdata(16*2-1 DOWNTO 16*1) WHEN state_fsm_load_FFT = FIFO_2 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_3) ELSE + sample_rdata(16*3-1 DOWNTO 16*2) WHEN state_fsm_load_FFT = FIFO_3 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_4) ELSE + sample_rdata(16*4-1 DOWNTO 16*3) WHEN state_fsm_load_FFT = FIFO_4 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_5) ELSE + sample_rdata(16*5-1 DOWNTO 16*4); --WHEN state_fsm_load_FFT = FIFO_5 ELSE + + ----------------------------------------------------------------------------- + -- FFT + ----------------------------------------------------------------------------- + CoreFFT_1: CoreFFT + GENERIC MAP ( + LOGPTS => gLOGPTS, + LOGLOGPTS => gLOGLOGPTS, + WSIZE => gWSIZE, + TWIDTH => gTWIDTH, + DWIDTH => gDWIDTH, + TDWIDTH => gTDWIDTH, + RND_MODE => gRND_MODE, + SCALE_MODE => gSCALE_MODE, + PTS => gPTS, + HALFPTS => gHALFPTS, + inBuf_RWDLY => gInBuf_RWDLY) + PORT MAP ( + clk => clk, + ifiStart => '1', + ifiNreset => rstn, + + ifiD_valid => sample_valid_r, -- IN + ifiRead_y => fft_read, + ifiD_im => (OTHERS => '0'), -- IN + ifiD_re => sample_data, -- IN + ifoLoad => sample_load, -- IN + + ifoPong => fft_pong, + ifoY_im => fft_data_im, + ifoY_re => fft_data_re, + ifoY_valid => fft_data_valid, + ifoY_rdy => fft_ready); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + fft_read <= '1'; + -- fft_read OUT + -- fft_pong IN + -- fft_data_im IN + -- fft_data_re IN + -- fft_data_valid IN + -- fft_ready IN + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + + dma_addr <= (OTHERS => '0'); + dma_data <= (OTHERS => '0'); + dma_valid <= '0'; + dma_valid_burst <= '0'; + + ready_matrix_f0_0 <= '0'; + ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_anticipating_empty_fifo <= '0'; + error_bad_component_error <= '0'; + debug_reg <= (OTHERS => '0'); + + matrix_time_f0_0 <= (OTHERS => '0'); + matrix_time_f0_1 <= (OTHERS => '0'); + matrix_time_f1 <= (OTHERS => '0'); + matrix_time_f2 <= (OTHERS => '0'); + + +END Behavioral; diff --git a/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd b/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/lpp_memory.vhd @@ -0,0 +1,199 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.iir_filter.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; +library techmap; +use techmap.gencomp.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_memory is + +component APB_FIFO is +generic ( + tech : integer := apa3; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + FifoCnt : integer := 2; + Data_sz : integer := 16; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; + Mem_use : integer := use_RAM; + R : integer := 1; + W : integer := 1 + ); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end component; + +component FIFO_pipeline is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + fifoCount : integer range 2 to 32 := 8; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + ReUse : in std_logic; + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); +end component; + +component lpp_fifo is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Enable_ReUse : std_logic := '0'; + DataSz : integer range 1 to 32 := 8; + AddrSz : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + ReUse : in std_logic; --27/01/12 + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(AddrSz-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + almost_full : out std_logic; + waddr : out std_logic_vector(AddrSz-1 downto 0) +); +end component; + + +component lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rstn : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + almost_full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end component; + +component FillFifo is +generic( + Data_sz : integer range 1 to 32 := 16; + Fifo_cnt : integer range 1 to 8 := 5 + ); +port( + clk : in std_logic; + raz : in std_logic; + write : out std_logic_vector(Fifo_cnt-1 downto 0); + reuse : out std_logic_vector(Fifo_cnt-1 downto 0); + data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) +); +end component; + +component Bridge is + port( + clk : in std_logic; + raz : in std_logic; + EmptyUp : in std_logic; + FullDwn : in std_logic; + WriteDwn : out std_logic; + ReadUp : out std_logic + ); +end component; + +component ssram_plugin is +generic (tech : integer := 0); +port +( + clk : in std_logic; + mem_ctrlr_o : in memory_out_type; + SSRAM_CLK : out std_logic; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + ZZ : out std_logic +); +end component; + +end; diff --git a/designs/Validation_LFR_SpectralMatrix/run.do b/designs/Validation_LFR_SpectralMatrix/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/run.do @@ -0,0 +1,3 @@ +log -R * +do wave.do +run -all \ No newline at end of file diff --git a/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd b/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/spectral_matrix_package.vhd @@ -0,0 +1,20 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +PACKAGE spectral_matrix_package IS + + COMPONENT spectral_matrix_switch_f0 + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + error_wen : OUT STD_LOGIC); + END COMPONENT; + +END spectral_matrix_package; diff --git a/designs/Validation_LFR_SpectralMatrix/spectral_matrix_switch_f0.vhd b/designs/Validation_LFR_SpectralMatrix/spectral_matrix_switch_f0.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/spectral_matrix_switch_f0.vhd @@ -0,0 +1,99 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + + +ENTITY spectral_matrix_switch_f0 IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --INPUT + sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + --OUTPUT A + fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + --OUTPUT B + fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + --ERROR + error_wen : OUT STD_LOGIC + ); + +END spectral_matrix_switch_f0; + +ARCHITECTURE beh OF spectral_matrix_switch_f0 IS + SIGNAL ALL_1_sample_wen : STD_LOGIC; + + SIGNAL ALL_1_fifo_A_empty : STD_LOGIC; + SIGNAL ALL_1_fifo_A_full : STD_LOGIC; + SIGNAL ALL_1_fifo_B_empty : STD_LOGIC; + SIGNAL ALL_1_fifo_B_full : STD_LOGIC; + + TYPE state_fsm_switch_f0 IS (state_A,state_B,state_AtoB,state_BtoA); + SIGNAL state_fsm : state_fsm_switch_f0; + +BEGIN -- beh + ALL_1_sample_wen <= '1' WHEN sample_wen = "11111" ELSE '0'; + + ALL_1_fifo_A_empty <= '1' WHEN fifo_A_empty = "11111" ELSE '0'; + ALL_1_fifo_A_full <= '1' WHEN fifo_A_full = "11111" ELSE '0'; + ALL_1_fifo_B_empty <= '1' WHEN fifo_B_empty = "11111" ELSE '0'; + ALL_1_fifo_B_full <= '1' WHEN fifo_B_full = "11111" ELSE '0'; + + fifo_A_wen <= sample_wen WHEN state_fsm = state_A ELSE (OTHERS => '1'); + fifo_B_wen <= sample_wen WHEN state_fsm = state_B ELSE (OTHERS => '1'); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_fsm <= state_A; + error_wen <= '0'; + + ELSIF clk'event AND clk = '1' THEN + CASE state_fsm IS + + WHEN state_A => + error_wen <= '0'; + IF ALL_1_fifo_A_full = '1' THEN + --error_wen <= NOT ALL_1_sample_wen; + IF ALL_1_fifo_B_empty = '1' THEN + state_fsm <= state_B; + ELSE + state_fsm <= state_AtoB; + END IF; + END IF; + + WHEN state_B => + error_wen <= '0'; + IF ALL_1_fifo_B_full = '1' THEN + --error_wen <= NOT ALL_1_sample_wen; + IF ALL_1_fifo_A_empty = '1' THEN + state_fsm <= state_A; + ELSE + state_fsm <= state_BtoA; + END IF; + END IF; + + WHEN state_AtoB => + error_wen <= NOT ALL_1_sample_wen; + IF ALL_1_fifo_B_empty = '1' THEN + state_fsm <= state_B; + END IF; + + WHEN state_BtoA => + error_wen <= NOT ALL_1_sample_wen; + IF ALL_1_fifo_A_empty = '1' THEN + state_fsm <= state_A; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + + END IF; + END PROCESS; + + +END beh; diff --git a/designs/Validation_LFR_SpectralMatrix/wave.do b/designs/Validation_LFR_SpectralMatrix/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR_SpectralMatrix/wave.do @@ -0,0 +1,64 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata +add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata +add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata +add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen +add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full +add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full +add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty +add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren +add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen +add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full +add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full +add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty +add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren +add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen +add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full +add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full +add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty +add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren +add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen +add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full +add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full +add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty +add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren +add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel +add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft +add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload +add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re +add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid +add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset +add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart +add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0 +add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1 +add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2 +add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y +add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong +add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy +add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid +add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_im +add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_re +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {27617887437 ps} 0} {{Cursor 3} {10382020000 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {95613018769 ps} 0} +configure wave -namecolwidth 402 +configure wave -valuecolwidth 199 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {10380205948 ps} {10383691010 ps} +bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 +bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0