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Add Driver ADS7886 + MINI_LFR_WFRM-GPIO (release 206 porté sur MINI-LFR)
pellion -
r287:b49f9ec9e95a JC
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39
40 FILESKIP = i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48
49 ################## project specific targets ##########################
50
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1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8
9 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
10
11 vcom -quiet -93 -work lpp testbench_package.vhd
12
13 vcom -quiet -93 -work work tb_waveform.vhd
14
15 vsim work.testbench
16
17 log -r *
18
19 do tb_waveform.do
20
21 run -all
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1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
4 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
5 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
6 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
7 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
8 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
9 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
10 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
11 add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
12 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_t
13 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_t
14 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
15 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
16 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
17 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data
18 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay
19 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done
20 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex
21 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn
22 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren
23 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run
24 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send
25 add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
26 add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
27 add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
28 add wave -noupdate -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
29 add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data
30 add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant
31 add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
32 TreeUpdate [SetDefaultTree]
33 WaveRestoreCursors {{Cursor 1} {12032365000 ps} 0}
34 configure wave -namecolwidth 540
35 configure wave -valuecolwidth 316
36 configure wave -justifyvalue left
37 configure wave -signalnamewidth 0
38 configure wave -snapdistance 10
39 configure wave -datasetprefix 0
40 configure wave -rowmargin 4
41 configure wave -childrowmargin 2
42 configure wave -gridoffset 0
43 configure wave -gridperiod 1
44 configure wave -griddelta 40
45 configure wave -timeline 0
46 configure wave -timelineunits ns
47 update
48 WaveRestoreZoom {0 ps} {162198702750 ps}
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1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 ------------------------------------------------------------------------------
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 --
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 -- IN ADVANCE IN WRITING.
11 ------------------------------------------------------------------------------
12
13 LIBRARY ieee;
14 USE ieee.std_logic_1164.ALL;
15
16 --LIBRARY std;
17 --USE std.textio.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 LIBRARY gaisler;
23 USE gaisler.memctrl.ALL;
24 USE gaisler.leon3.ALL;
25 USE gaisler.uart.ALL;
26 USE gaisler.misc.ALL;
27 USE gaisler.libdcom.ALL;
28 USE gaisler.sim.ALL;
29 USE gaisler.jtagtst.ALL;
30 USE gaisler.misc.ALL;
31 LIBRARY techmap;
32 USE techmap.gencomp.ALL;
33 LIBRARY esa;
34 USE esa.memoryctrl.ALL;
35 --LIBRARY micron;
36 --USE micron.components.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.testbench_package.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
46
47 ENTITY testbench IS
48 END;
49
50 ARCHITECTURE behav OF testbench IS
51 -- REG ADDRESS
52 CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15;
53 CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15;
54 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
55 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
56 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
57 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
58 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
59 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
60 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
61 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
62 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
63 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
64 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
65 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
66 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
67 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
68 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
69 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
70 -- RAM ADDRESS
71 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
72 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
73 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
74 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
75
76
77 -- Common signal
78 SIGNAL clk49_152MHz : STD_LOGIC := '0';
79 SIGNAL clk25MHz : STD_LOGIC := '0';
80 SIGNAL rstn : STD_LOGIC := '0';
81
82 -- ADC interface
83 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
84 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
85 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
86
87 -- AD Converter RHF1401
88 SIGNAL sample : Samples14v(7 DOWNTO 0);
89 SIGNAL sample_val : STD_LOGIC;
90
91 -- AHB/APB SIGNAL
92 SIGNAL apbi : apb_slv_in_type;
93 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
94 SIGNAL ahbsi : ahb_slv_in_type;
95 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
96 SIGNAL ahbmi : ahb_mst_in_type;
97 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
98
99 SIGNAL bias_fail_bw : STD_LOGIC;
100
101 -----------------------------------------------------------------------------
102 -- LPP_WAVEFORM
103 -----------------------------------------------------------------------------
104 CONSTANT data_size : INTEGER := 96;
105 CONSTANT nb_burst_available_size : INTEGER := 50;
106 CONSTANT nb_snapshot_param_size : INTEGER := 2;
107 CONSTANT delta_vector_size : INTEGER := 2;
108 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
109
110 SIGNAL reg_run : STD_LOGIC;
111 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
112 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL enable_f0 : STD_LOGIC;
118 SIGNAL enable_f1 : STD_LOGIC;
119 SIGNAL enable_f2 : STD_LOGIC;
120 SIGNAL enable_f3 : STD_LOGIC;
121 SIGNAL burst_f0 : STD_LOGIC;
122 SIGNAL burst_f1 : STD_LOGIC;
123 SIGNAL burst_f2 : STD_LOGIC;
124 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
125 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
126 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL data_f0_in_valid : STD_LOGIC;
134 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL data_f1_in_valid : STD_LOGIC;
137 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL data_f2_in_valid : STD_LOGIC;
140 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL data_f3_in_valid : STD_LOGIC;
143 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL data_f0_data_out_valid : STD_LOGIC;
147 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
148 SIGNAL data_f0_data_out_ack : STD_LOGIC;
149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
153 SIGNAL data_f1_data_out_ack : STD_LOGIC;
154 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL data_f2_data_out_valid : STD_LOGIC;
157 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
158 SIGNAL data_f2_data_out_ack : STD_LOGIC;
159 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f3_data_out_valid : STD_LOGIC;
162 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f3_data_out_ack : STD_LOGIC;
164
165 --MEM CTRLR
166 SIGNAL memi : memory_in_type;
167 SIGNAL memo : memory_out_type;
168 SIGNAL wpo : wprot_out_type;
169 SIGNAL sdo : sdram_out_type;
170
171 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0);
172 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL nSRAM_BE0 : STD_LOGIC;
174 SIGNAL nSRAM_BE1 : STD_LOGIC;
175 SIGNAL nSRAM_BE2 : STD_LOGIC;
176 SIGNAL nSRAM_BE3 : STD_LOGIC;
177 SIGNAL nSRAM_WE : STD_LOGIC;
178 SIGNAL nSRAM_CE : STD_LOGIC;
179 SIGNAL nSRAM_OE : STD_LOGIC;
180
181 CONSTANT padtech : INTEGER := inferred;
182 SIGNAL not_ramsn_0 : STD_LOGIC;
183
184
185 BEGIN
186
187 -----------------------------------------------------------------------------
188
189 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
190 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
191
192 -----------------------------------------------------------------------------
193
194 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
195 TestModule_RHF1401_1 : TestModule_RHF1401
196 GENERIC MAP (
197 freq => 24*(I+1),
198 amplitude => 8000/(I+1),
199 impulsion => 0)
200 PORT MAP (
201 ADC_smpclk => ADC_smpclk,
202 ADC_OEB_bar => ADC_OEB_bar_CH(I),
203 ADC_data => ADC_data);
204 END GENERATE MODULE_RHF1401;
205
206 -----------------------------------------------------------------------------
207
208 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
209 GENERIC MAP (
210 ChanelCount => 8,
211 ncycle_cnv_high => 79,
212 ncycle_cnv => 500)
213 PORT MAP (
214 cnv_clk => clk49_152MHz,
215 cnv_rstn => rstn,
216 cnv => ADC_smpclk,
217 clk => clk25MHz,
218 rstn => rstn,
219 ADC_data => ADC_data,
220 ADC_nOE => ADC_OEB_bar_CH,
221 sample => sample,
222 sample_val => sample_val);
223
224 -----------------------------------------------------------------------------
225
226 lpp_lfr_1 : lpp_lfr
227 GENERIC MAP (
228 Mem_use => use_CEL, -- use_RAM
229 nb_data_by_buffer_size => 32,
230 nb_word_by_buffer_size => 30,
231 nb_snapshot_param_size => 32,
232 delta_vector_size => 32,
233 delta_vector_size_f0_2 => 32,
234 pindex => INDEX_WAVEFORM_PICKER,
235 paddr => ADDR_WAVEFORM_PICKER,
236 pmask => 16#fff#,
237 pirq_ms => 6,
238 pirq_wfp => 14,
239 hindex => 0,
240 top_lfr_version => X"00000001")
241 PORT MAP (
242 clk => clk25MHz,
243 rstn => rstn,
244 sample_B => sample(2 DOWNTO 0),
245 sample_E => sample(7 DOWNTO 3),
246 sample_val => sample_val,
247 apbi => apbi,
248 apbo => apbo(15),
249 ahbi => ahbmi,
250 ahbo => ahbmo(0),
251 coarse_time => coarse_time,
252 fine_time => fine_time,
253 data_shaping_BW => bias_fail_bw);
254
255 -----------------------------------------------------------------------------
256 --- AHB CONTROLLER -------------------------------------------------
257 ahb0 : ahbctrl -- AHB arbiter/multiplexer
258 GENERIC MAP (defmast => 0, split => 0,
259 rrobin => 1, ioaddr => 16#FFF#,
260 ioen => 0, nahbm => 1, nahbs => 1)
261 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
262
263 --- AHB RAM ----------------------------------------------------------
264 --ahbram0 : ahbram
265 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
266 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
267 --ahbram1 : ahbram
268 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
269 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
270 --ahbram2 : ahbram
271 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
272 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
273 --ahbram3 : ahbram
274 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
275 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
276
277 -----------------------------------------------------------------------------
278 ----------------------------------------------------------------------
279 --- Memory controllers ---------------------------------------------
280 ----------------------------------------------------------------------
281 memctrlr : mctrl GENERIC MAP (
282 hindex => 0,
283 pindex => 0,
284 paddr => 0,
285 srbanks => 1
286 )
287 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
288
289 memi.brdyn <= '1';
290 memi.bexcn <= '1';
291 memi.writen <= '1';
292 memi.wrn <= "1111";
293 memi.bwidth <= "10";
294
295 bdr : FOR i IN 0 TO 3 GENERATE
296 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
297 PORT MAP (
298 data(31-i*8 DOWNTO 24-i*8),
299 memo.data(31-i*8 DOWNTO 24-i*8),
300 memo.bdrive(i),
301 memi.data(31-i*8 DOWNTO 24-i*8));
302 END GENERATE;
303
304 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
305 PORT MAP (address, memo.address(21 DOWNTO 2));
306
307 not_ramsn_0 <= NOT(memo.ramsn(0));
308
309 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
310 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
311 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
312 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
313 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
314 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
315 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
316
317 async_1Mx16_0: CY7C1061DV33
318 GENERIC MAP (
319 ADDR_BITS => 20,
320 DATA_BITS => 16,
321 depth => 1048576,
322 TimingInfo => TRUE,
323 TimingChecks => '1')
324 PORT MAP (
325 CE1_b => '0',
326 CE2 => nSRAM_CE,
327 WE_b => nSRAM_WE,
328 OE_b => nSRAM_OE,
329 BHE_b => nSRAM_BE1,
330 BLE_b => nSRAM_BE0,
331 A => address,
332 DQ => data(15 DOWNTO 0));
333
334 async_1Mx16_1: CY7C1061DV33
335 GENERIC MAP (
336 ADDR_BITS => 20,
337 DATA_BITS => 16,
338 depth => 1048576,
339 TimingInfo => TRUE,
340 TimingChecks => '1')
341 PORT MAP (
342 CE1_b => '0',
343 CE2 => nSRAM_CE,
344 WE_b => nSRAM_WE,
345 OE_b => nSRAM_OE,
346 BHE_b => nSRAM_BE3,
347 BLE_b => nSRAM_BE2,
348 A => address,
349 DQ => data(31 DOWNTO 16));
350
351
352 -----------------------------------------------------------------------------
353
354 WaveGen_Proc : PROCESS
355 BEGIN
356
357 -- insert signal assignments here
358 WAIT UNTIL clk25MHz = '1';
359 rstn <= '0';
360 apbi.psel(15) <= '0';
361 apbi.pwrite <= '0';
362 apbi.penable <= '0';
363 apbi.paddr <= (OTHERS => '0');
364 apbi.pwdata <= (OTHERS => '0');
365 fine_time <= (OTHERS => '0');
366 coarse_time <= (OTHERS => '0');
367 WAIT UNTIL clk25MHz = '1';
368 -- ahbmi.HGRANT(2) <= '1';
369 -- ahbmi.HREADY <= '1';
370 -- ahbmi.HRESP <= HRESP_OKAY;
371
372 WAIT UNTIL clk25MHz = '1';
373 WAIT UNTIL clk25MHz = '1';
374 rstn <= '1';
375 WAIT UNTIL clk25MHz = '1';
376 WAIT UNTIL clk25MHz = '1';
377 ---------------------------------------------------------------------------
378 -- CONFIGURATION STEP
379 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
380 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40200000");
381 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40400000");
382 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40800000");
383
384 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000002");--"00000020"
385 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000002");--"00000019"
386 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000001");--"00000007"
387 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000020");--"00000019"
388 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
389
390 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
391 --
392 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
393 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
394 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
395
396
397 WAIT UNTIL clk25MHz = '1';
398 WAIT UNTIL clk25MHz = '1';
399 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000081");
400 WAIT UNTIL clk25MHz = '1';
401 WAIT UNTIL clk25MHz = '1';
402 WAIT UNTIL clk25MHz = '1';
403 WAIT UNTIL clk25MHz = '1';
404 WAIT UNTIL clk25MHz = '1';
405 WAIT UNTIL clk25MHz = '1';
406 WAIT FOR 1 us;
407 coarse_time <= X"00000001";
408 ---------------------------------------------------------------------------
409 -- RUN STEP
410 WAIT FOR 200 ms;
411 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
412 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
413 WAIT FOR 10 us;
414 WAIT UNTIL clk25MHz = '1';
415 WAIT UNTIL clk25MHz = '1';
416 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
417 WAIT UNTIL clk25MHz = '1';
418 coarse_time <= X"00000010";
419 WAIT FOR 100 ms;
420 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
421 WAIT FOR 10 us;
422 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
423 WAIT FOR 200 ms;
424 REPORT "*** END simulation ***" SEVERITY failure;
425
426
427 WAIT;
428
429 END PROCESS WaveGen_Proc;
430 -----------------------------------------------------------------------------
431
432 -----------------------------------------------------------------------------
433 -- IRQ
434 -----------------------------------------------------------------------------
435 PROCESS (clk25MHz, rstn)
436 BEGIN -- PROCESS
437 IF rstn = '0' THEN -- asynchronous reset (active low)
438
439 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
440
441 END IF;
442 END PROCESS;
443 -----------------------------------------------------------------------------
444
445 END;
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
7 --LIBRARY gaisler;
8 --USE gaisler.libdcom.ALL;
9 --USE gaisler.sim.ALL;
10 --USE gaisler.jtagtst.ALL;
11 --LIBRARY techmap;
12 --USE techmap.gencomp.ALL;
13
14
15 PACKAGE testbench_package IS
16
17
18 PROCEDURE APB_WRITE (
19 SIGNAL clk : IN STD_LOGIC;
20 CONSTANT pindex : IN INTEGER;
21 SIGNAL apbi : OUT apb_slv_in_type;
22 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
23 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
24 );
25
26 END testbench_package;
27
28 PACKAGE BODY testbench_package IS
29
30 PROCEDURE APB_WRITE (
31
32 SIGNAL clk : IN STD_LOGIC;
33 CONSTANT pindex : IN INTEGER;
34 SIGNAL apbi : OUT apb_slv_in_type;
35 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
36 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
37 ) IS
38 BEGIN
39 apbi.psel(pindex) <= '1';
40 apbi.pwrite <= '1';
41 apbi.penable <= '1';
42 apbi.paddr <= paddr;
43 apbi.pwdata <= pwdata;
44 WAIT UNTIL clk = '1';
45 apbi.psel(pindex) <= '0';
46 apbi.pwrite <= '0';
47 apbi.penable <= '0';
48 apbi.paddr <= (OTHERS => '0');
49 apbi.pwdata <= (OTHERS => '0');
50
51 END APB_WRITE;
52
53 END testbench_package;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 --USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 --
122 SIGNAL errorn : STD_LOGIC;
123 -- UART AHB ---------------------------------------------------------------
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126
127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
131 SIGNAL I00_s : STD_LOGIC;
132
133 -- CONSTANTS
134 constant CFG_PADTECH : integer := inferred;
135 --
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139
140 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
142 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
144 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
146
147 -- Spacewire signals
148 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxtxclk : std_ulogic;
152 SIGNAL spw_rxclkn : std_ulogic;
153 SIGNAL spw_clk : std_logic;
154 SIGNAL swni : grspw_in_type;
155 SIGNAL swno : grspw_out_type;
156 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL txclk : STD_ULOGIC;
158
159 --GPIO
160 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioo : gpio_out_type;
162
163 -- AD Converter ADS7886
164 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169
170 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171
172 BEGIN -- beh
173
174 -----------------------------------------------------------------------------
175 -- CLK
176 -----------------------------------------------------------------------------
177
178 PROCESS(clk_50)
179 BEGIN
180 IF clk_50'EVENT AND clk_50 = '1' THEN
181 clk_50_s <= NOT clk_50_s;
182 END IF;
183 END PROCESS;
184
185 PROCESS(clk_50_s)
186 BEGIN
187 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
188 clk_25 <= NOT clk_25;
189 END IF;
190 END PROCESS;
191
192 -----------------------------------------------------------------------------
193
194 PROCESS (clk_25, reset)
195 BEGIN -- PROCESS
196 IF reset = '0' THEN -- asynchronous reset (active low)
197 LED0 <= '0';
198 LED1 <= '0';
199 LED2 <= '0';
200 --IO1 <= '0';
201 --IO2 <= '1';
202 --IO3 <= '0';
203 --IO4 <= '0';
204 --IO5 <= '0';
205 --IO6 <= '0';
206 --IO7 <= '0';
207 --IO8 <= '0';
208 --IO9 <= '0';
209 --IO10 <= '0';
210 --IO11 <= '0';
211 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
212 LED0 <= '0';
213 LED1 <= '1';
214 LED2 <= BP0;
215 --IO1 <= '1';
216 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
217 --IO3 <= ADC_SDO(0);
218 --IO4 <= ADC_SDO(1);
219 --IO5 <= ADC_SDO(2);
220 --IO6 <= ADC_SDO(3);
221 --IO7 <= ADC_SDO(4);
222 --IO8 <= ADC_SDO(5);
223 --IO9 <= ADC_SDO(6);
224 --IO10 <= ADC_SDO(7);
225 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 END IF;
227 END PROCESS;
228
229 PROCESS (clk_49, reset)
230 BEGIN -- PROCESS
231 IF reset = '0' THEN -- asynchronous reset (active low)
232 I00_s <= '0';
233 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
234 I00_s <= NOT I00_s;
235 END IF;
236 END PROCESS;
237 -- IO0 <= I00_s;
238
239 --UARTs
240 nCTS1 <= '1';
241 nCTS2 <= '1';
242 nDCD2 <= '1';
243
244 --EXT CONNECTOR
245
246 --SPACE WIRE
247
248 leon3_soc_1: leon3_soc
249 GENERIC MAP (
250 fabtech => apa3e,
251 memtech => apa3e,
252 padtech => inferred,
253 clktech => inferred,
254 disas => 0,
255 dbguart => 0,
256 pclow => 2,
257 clk_freq => 25000,
258 NB_CPU => 1,
259 ENABLE_FPU => 1,
260 FPU_NETLIST => 0,
261 ENABLE_DSU => 1,
262 ENABLE_AHB_UART => 1,
263 ENABLE_APB_UART => 1,
264 ENABLE_IRQMP => 1,
265 ENABLE_GPT => 1,
266 NB_AHB_MASTER => NB_AHB_MASTER,
267 NB_AHB_SLAVE => NB_AHB_SLAVE,
268 NB_APB_SLAVE => NB_APB_SLAVE)
269 PORT MAP (
270 clk => clk_25,
271 reset => reset,
272 errorn => errorn,
273 ahbrxd => TXD1,
274 ahbtxd => RXD1,
275 urxd1 => TXD2,
276 utxd1 => RXD2,
277 address => SRAM_A,
278 data => SRAM_DQ,
279 nSRAM_BE0 => SRAM_nBE(0),
280 nSRAM_BE1 => SRAM_nBE(1),
281 nSRAM_BE2 => SRAM_nBE(2),
282 nSRAM_BE3 => SRAM_nBE(3),
283 nSRAM_WE => SRAM_nWE,
284 nSRAM_CE => SRAM_CE,
285 nSRAM_OE => SRAM_nOE,
286
287 apbi_ext => apbi_ext,
288 apbo_ext => apbo_ext,
289 ahbi_s_ext => ahbi_s_ext,
290 ahbo_s_ext => ahbo_s_ext,
291 ahbi_m_ext => ahbi_m_ext,
292 ahbo_m_ext => ahbo_m_ext);
293
294 -------------------------------------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -------------------------------------------------------------------------------
297 apb_lfr_time_management_1: apb_lfr_time_management
298 GENERIC MAP (
299 pindex => 6,
300 paddr => 6,
301 pmask => 16#fff#,
302 pirq => 12)
303 PORT MAP (
304 clk25MHz => clk_25,
305 clk49_152MHz => clk_49,
306 resetn => reset,
307 grspw_tick => swno.tickout,
308 apbi => apbi_ext,
309 apbo => apbo_ext(6),
310 coarse_time => coarse_time,
311 fine_time => fine_time);
312
313 -----------------------------------------------------------------------
314 --- SpaceWire --------------------------------------------------------
315 -----------------------------------------------------------------------
316
317 SPW_EN <= '1';
318
319 spw_clk <= clk_50_s;
320 spw_rxtxclk <= spw_clk;
321 spw_rxclkn <= not spw_rxtxclk;
322
323 -- PADS for SPW1
324 spw1_rxd_pad : inpad generic map (tech => inferred)
325 port map (SPW_NOM_DIN, dtmp(0));
326 spw1_rxs_pad : inpad generic map (tech => inferred)
327 port map (SPW_NOM_SIN, stmp(0));
328 spw1_txd_pad : outpad generic map (tech => inferred)
329 port map (SPW_NOM_DOUT, swno.d(0));
330 spw1_txs_pad : outpad generic map (tech => inferred)
331 port map (SPW_NOM_SOUT, swno.s(0));
332 -- PADS FOR SPW2
333 spw2_rxd_pad : inpad generic map (tech => inferred) -- bad naming of the MINI-LFR /!\
334 port map (SPW_RED_SIN, dtmp(1));
335 spw2_rxs_pad : inpad generic map (tech => inferred) -- bad naming of the MINI-LFR /!\
336 port map (SPW_RED_DIN, stmp(1));
337 spw2_txd_pad : outpad generic map (tech => inferred)
338 port map (SPW_RED_DOUT, swno.d(1));
339 spw2_txs_pad : outpad generic map (tech => inferred)
340 port map (SPW_RED_SOUT, swno.s(1));
341
342 -- GRSPW PHY
343 --spw1_input: if CFG_SPW_GRSPW = 1 generate
344 spw_inputloop: for j in 0 to 1 generate
345 spw_phy0 : grspw_phy
346 generic map(
347 tech => apa3e,
348 rxclkbuftype => 1,
349 scantest => 0)
350 port map(
351 rxrst => swno.rxrst,
352 di => dtmp(j),
353 si => stmp(j),
354 rxclko => spw_rxclk(j),
355 do => swni.d(j),
356 ndo => swni.nd(j*5+4 downto j*5),
357 dconnect => swni.dconnect(j*2+1 downto j*2));
358 end generate spw_inputloop;
359
360 -- SPW core
361 sw0 : grspwm generic map(
362 tech => apa3e,
363 hindex => 1,
364 pindex => 5,
365 paddr => 5,
366 pirq => 11,
367 sysfreq => 25000, -- CPU_FREQ
368 rmap => 1,
369 rmapcrc => 1,
370 fifosize1 => 16,
371 fifosize2 => 16,
372 rxclkbuftype => 1,
373 rxunaligned => 0,
374 rmapbufs => 4,
375 ft => 0,
376 netlist => 0,
377 ports => 2,
378 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
379 memtech => apa3e,
380 destkey => 2,
381 spwcore => 1
382 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
383 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
384 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
385 )
386 port map(reset, clk_25, spw_rxclk(0),
387 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
388 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
389 swni, swno);
390
391 swni.tickin <= '0';
392 swni.rmapen <= '1';
393 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
394 swni.tickinraw <= '0';
395 swni.timein <= (others => '0');
396 swni.dcrstval <= (others => '0');
397 swni.timerrstval <= (others => '0');
398
399 -------------------------------------------------------------------------------
400 -- LFR ------------------------------------------------------------------------
401 -------------------------------------------------------------------------------
402 -- lpp_lfr_1 : lpp_lfr
403 -- GENERIC MAP (
404 -- Mem_use => use_RAM,
405 -- nb_data_by_buffer_size => 32,
406 -- nb_word_by_buffer_size => 30,
407 -- nb_snapshot_param_size => 32,
408 -- delta_vector_size => 32,
409 -- delta_vector_size_f0_2 => 7, -- log2(96)
410 -- pindex => 6,
411 -- paddr => 6,
412 -- pmask => 16#fff#,
413 -- pirq_ms => 6,
414 -- pirq_wfp => 14,
415 -- hindex => 2,
416 -- top_lfr_version => X"00000005")
417 -- PORT MAP (
418 -- clk => clk_25,
419 -- rstn => reset,
420 -- sample_B => sample(2 DOWNTO 0),
421 -- sample_E => sample(7 DOWNTO 3),
422 -- sample_val => sample_val,
423 -- apbi => apbi_ext,
424 -- apbo => apbo_ext(6),
425 -- ahbi => ahbi_m_ext,
426 -- ahbo => ahbo_m_ext(2),
427 -- coarse_time => coarse_time,
428 -- fine_time => fine_time,
429 -- data_shaping_BW => bias_fail_sw_sig);
430
431 waveform_picker0 : top_wf_picker
432 GENERIC MAP(
433 hindex => 2,
434 pindex => 15,
435 paddr => 15,
436 pmask => 16#fff#,
437 pirq => 14,
438 tech => apa3e,
439 nb_burst_available_size => 12, -- size of the register holding the nb of burst
440 nb_snapshot_param_size => 12, -- size of the register holding the snapshots size
441 delta_snapshot_size => 16, -- snapshots period
442 delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts
443 delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot
444 ENABLE_FILTER => '1'
445 )
446 PORT MAP(
447 cnv_clk => clk_25,
448 cnv_rstn => reset,
449 -- SAMPLES
450 sample_B => sample(2 DOWNTO 0),
451 sample_E => sample(7 DOWNTO 3),
452 sample_val => sample_val,
453 -- AMBA AHB system signals
454 HCLK => clk_25,
455 HRESETn => reset,
456 -- AMBA APB Slave Interface
457 apbi => apbi_ext,
458 apbo => apbo_ext(15),
459 -- AMBA AHB Master Interface
460 AHB_Master_In => ahbi_m_ext,
461 AHB_Master_Out => ahbo_m_ext(2),
462 --
463 coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time
464 --
465 data_shaping_BW => bias_fail_sw_sig
466 );
467
468 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
469 GENERIC MAP(
470 ChannelCount => 8,
471 SampleNbBits => 14,
472 ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
473 ncycle_cnv => 500) -- 49 152 000 / 98304
474 PORT MAP (
475 -- CONV
476 cnv_clk => clk_49,
477 cnv_rstn => reset,
478 cnv => ADC_nCS_sig,
479 -- DATA
480 clk => clk_25,
481 rstn => reset,
482 sck => ADC_CLK_sig,
483 sdo => ADC_SDO_sig,
484 -- SAMPLE
485 sample => sample,
486 sample_val => sample_val);
487
488 IO10 <= ADC_SDO_sig(5);
489 IO9 <= ADC_SDO_sig(4);
490 IO8 <= ADC_SDO_sig(3);
491
492 ADC_nCS <= ADC_nCS_sig;
493 ADC_CLK <= ADC_CLK_sig;
494 ADC_SDO_sig <= ADC_SDO;
495
496 ----------------------------------------------------------------------
497 --- GPIO -----------------------------------------------------------
498 ----------------------------------------------------------------------
499
500 grgpio0: grgpio
501 generic map( pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
502 port map( reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
503
504 pio_pad_0 : iopad
505 generic map (tech => CFG_PADTECH)
506 port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
507 pio_pad_1 : iopad
508 generic map (tech => CFG_PADTECH)
509 port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
510 pio_pad_2 : iopad
511 generic map (tech => CFG_PADTECH)
512 port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
513 pio_pad_3 : iopad
514 generic map (tech => CFG_PADTECH)
515 port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
516 pio_pad_4 : iopad
517 generic map (tech => CFG_PADTECH)
518 port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
519 pio_pad_5 : iopad
520 generic map (tech => CFG_PADTECH)
521 port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
522 pio_pad_6 : iopad
523 generic map (tech => CFG_PADTECH)
524 port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
525 pio_pad_7 : iopad
526 generic map (tech => CFG_PADTECH)
527 port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
528
529 END beh; No newline at end of file
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./dsp/lpp_fft \
31 ./lpp_bootloader \
32 ./lpp_cna \
33 ./lpp_demux \
34 ./lpp_matrix \
35 ./lpp_uart \
36 ./lpp_usb \
37 ./lpp_Header \
38 ./lpp_sim/CY7C1061DV33 \
39
40 FILESKIP =lpp_lfr_ms.vhd \
41 i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd
46
47 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/software/leon3/Makefile
49
50 ################## project specific targets ##########################
51
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 -- MODIFIED by Paul LEROY
27 -- paul.leroy@lpp.polytechnique.fr
28 -------------------------------------------------------------------------------
29
30 LIBRARY IEEE;
31 USE IEEE.STD_LOGIC_1164.ALL;
32 LIBRARY lpp;
33 USE lpp.lpp_ad_conv.ALL;
34
35 ENTITY ADS7886_drvr_v2 IS
36 GENERIC(
37 ChannelCount : INTEGER := 8;
38 NbBitsSamples : INTEGER := 16);
39 PORT (
40 -- CONV --
41 cnv_clk : IN STD_LOGIC;
42 cnv_rstn : IN STD_LOGIC;
43 -- DATA --
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
48 -- SAMPLE --
49 sample : OUT Samples(ChannelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
51 );
52 END ADS7886_drvr_v2;
53
54 ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS7886_drvr_v2 IS
55
56 SIGNAL cnv_sync : STD_LOGIC;
57 SIGNAL cnv_sync_r : STD_LOGIC;
58 SIGNAL cnv_done : STD_LOGIC;
59 SIGNAL sample_bit_counter : INTEGER;
60 SIGNAL shift_reg : Samples(ChannelCount-1 DOWNTO 0);
61
62 BEGIN
63
64 cnv_sync <= cnv_clk;
65
66 PROCESS (clk, rstn) -- falling edge detection on cnv_sync
67 BEGIN
68 IF rstn = '0' THEN
69 cnv_sync_r <= '1';
70 cnv_done <= '0';
71 ELSIF clk'EVENT AND clk = '1' THEN
72 cnv_sync_r <= cnv_sync;
73 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
74 END IF;
75 END PROCESS;
76
77 -----------------------------------------------------------------------------
78 -- DATA
79 -----------------------------------------------------------------------------
80
81 PROCESS (clk, rstn)
82 BEGIN -- PROCESS
83 IF rstn = '0' THEN
84 FOR k IN 0 TO ChannelCount-1 LOOP
85 shift_reg(k)(15 downto 0) <= (OTHERS => '0');
86 sample(k)(15 downto 0) <= (OTHERS => '0');
87 END LOOP;
88 sample_bit_counter <= 0;
89 sample_val <= '0';
90 SCK <= '1';
91 ELSIF clk'EVENT AND clk = '1' THEN
92 IF (cnv_done = '1') AND (sample_bit_counter = 0) THEN
93 sample_bit_counter <= 1;
94 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 31 THEN
95 sample_bit_counter <= sample_bit_counter + 1;
96 ELSIF sample_bit_counter = 31 THEN
97 sample_val <= '1';
98 FOR k IN 0 TO ChannelCount-1 LOOP
99 sample(k)(0) <= sdo(k);
100 sample(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
101 END LOOP;
102 sample_bit_counter <= 0;
103 ELSE
104 sample_val <= '0';
105 END IF;
106
107 IF (sample_bit_counter MOD 2) = 1 THEN -- get data on each channel
108 FOR k IN 0 TO ChannelCount-1 LOOP
109 shift_reg(k)(0) <= sdo(k);
110 shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
111 END LOOP;
112 SCK <= '0';
113 ELSE
114 SCK <= '1';
115 END IF;
116 END IF;
117 END PROCESS;
118
119 END ar_ADS7886_drvr_v2; No newline at end of file
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1
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.NUMERIC_STD.ALL;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
8
9 ENTITY top_ad_conv_ADS7886_v2 IS
10 GENERIC(
11 ChannelCount : INTEGER := 8;
12 SampleNbBits : INTEGER := 14;
13 ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
14 ncycle_cnv : INTEGER := 500);
15 PORT (
16 -- CONV
17 cnv_clk : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 -- DATA
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sck : OUT STD_LOGIC;
24 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
25 -- SAMPLE
26 sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
27 sample_val : OUT STD_LOGIC
28 );
29 END top_ad_conv_ADS7886_v2;
30
31 ARCHITECTURE ar_top_ad_conv_ADS7886_v2 OF top_ad_conv_ADS7886_v2 IS
32
33 SIGNAL cnv_cycle_counter : INTEGER;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync_not : STD_LOGIC;
37
38 SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0);
39 SIGNAL sample_val_adc : STD_LOGIC;
40
41 BEGIN
42
43
44 -----------------------------------------------------------------------------
45 -- CONV
46 -----------------------------------------------------------------------------
47 PROCESS (cnv_clk, cnv_rstn)
48 BEGIN -- PROCESS
49 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
50 cnv_cycle_counter <= 0;
51 cnv_s <= '0';
52 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
53 -- IF cnv_run = '1' THEN
54 IF cnv_cycle_counter < ncycle_cnv THEN
55 cnv_cycle_counter <= cnv_cycle_counter +1;
56 IF cnv_cycle_counter < ncycle_cnv_high THEN
57 cnv_s <= '1';
58 ELSE
59 cnv_s <= '0';
60 END IF;
61 ELSE
62 cnv_s <= '1';
63 cnv_cycle_counter <= 0;
64 END IF;
65 --ELSE
66 -- cnv_s <= '0';
67 -- cnv_cycle_counter <= 0;
68 --END IF;
69 END IF;
70 END PROCESS;
71
72 cnv <= not(cnv_s);
73
74 -----------------------------------------------------------------------------
75 -- SYNC CNV
76 -----------------------------------------------------------------------------
77
78 SYNC_FF_cnv : SYNC_FF
79 GENERIC MAP (
80 NB_FF_OF_SYNC => 2)
81 PORT MAP (
82 clk => clk,
83 rstn => rstn,
84 A => cnv_s, -- the data fetching begins immediately
85 A_sync => cnv_sync);
86
87 -----------------------------------------------------------------------------
88
89 cnv_sync_not <= not(cnv_sync);
90
91 ADS7886_drvr_v2_1 : ADS7886_drvr_v2
92 GENERIC MAP(
93 ChannelCount => 8,
94 NbBitsSamples => 16)
95 PORT MAP(
96 -- CONV --
97 cnv_clk => cnv_sync_not,
98 cnv_rstn => rstn,
99 -- DATA --
100 clk => clk, -- master clock, 25 MHz
101 rstn => rstn,
102 sck => sck,
103 sdo => sdo,
104 -- SAMPLE --
105 sample => sample_adc,
106 sample_val => sample_val_adc);
107
108 PROCESS (clk, rstn)
109 BEGIN -- PROCESS
110 IF rstn = '0' THEN -- asynchronous reset (active low)
111 FOR k IN 0 TO ChannelCount-1 LOOP
112 sample(k)(13 downto 0) <= (OTHERS => '0');
113 END LOOP;
114 sample_val <= '0';
115 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
116 IF sample_val_adc ='1' THEN
117 FOR k IN 0 TO ChannelCount-1 LOOP
118 IF ( unsigned(sample_adc(k)(11 downto 0)) >= 2048) THEN
119 sample(k)(13 downto 0) <= "00" &
120 std_logic_vector( unsigned(sample_adc(k)(11 downto 0)) - 2048 );
121 ELSE
122 sample(k)(13 downto 0) <= "11" &
123 std_logic_vector( unsigned(sample_adc(k)(11 downto 0)) - 2048 );
124 END IF;
125 END LOOP;
126 -- FOR k IN 0 TO ChannelCount-1 LOOP
127 -- sample(k) <= sample_adc(k)(13 downto 0);
128 -- END LOOP;
129 sample_val <= sample_val_adc;
130 ELSE
131 sample_val <= '0';
132 END IF;
133 END IF;
134 END PROCESS;
135
136 END ar_top_ad_conv_ADS7886_v2; No newline at end of file
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1 --************************************************************************
2 --** MODEL : async_1Mx16.vhd **
3 --** COMPANY : Cypress Semiconductor **
4 --** REVISION: 1.0 Created new base model **
5 --************************************************************************
6
7 -------------------------------------------------------------------------------JC\/
8 --Library ieee,work;
9 LIBRARY ieee;
10 -------------------------------------------------------------------------------JC/\
11 USE IEEE.Std_Logic_1164.ALL;
12 USE IEEE.Std_Logic_unsigned.ALL;
13
14 -------------------------------------------------------------------------------JC\/
15 --use work.package_timing.all;
16 --use work.package_utility.all;
17 LIBRARY lpp;
18 USE lpp.package_timing.ALL;
19 USE lpp.package_utility.ALL;
20 -------------------------------------------------------------------------------JC/\
21
22 ------------------------
23 -- Entity Description
24 ------------------------
25
26 ENTITY CY7C1061DV33 IS
27 GENERIC
28 (ADDR_BITS : INTEGER := 20;
29 DATA_BITS : INTEGER := 16;
30 depth : INTEGER := 1048576;
31
32 TimingInfo : BOOLEAN := true;
33 TimingChecks : STD_LOGIC := '1'
34 );
35 PORT (
36 CE1_b : IN STD_LOGIC; -- Chip Enable CE1#
37 CE2 : IN STD_LOGIC; -- Chip Enable CE2
38 WE_b : IN STD_LOGIC; -- Write Enable WE#
39 OE_b : IN STD_LOGIC; -- Output Enable OE#
40 BHE_b : IN STD_LOGIC; -- Byte Enable High BHE#
41 BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE#
42 A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A
43 DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO;
44 );
45 END CY7C1061DV33;
46
47 -----------------------------
48 -- End Entity Description
49 -----------------------------
50 -----------------------------
51 -- Architecture Description
52 -----------------------------
53
54 ARCHITECTURE behave_arch OF CY7C1061DV33 IS
55
56 TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
57
58 SIGNAL write_enable : STD_LOGIC;
59 SIGNAL read_enable : STD_LOGIC;
60 SIGNAL byte_enable : STD_LOGIC;
61 SIGNAL CE_b : STD_LOGIC;
62
63 SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
64
65 SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0);
66
67 CONSTANT tSD_dataskew : TIME := tSD - 1 ns;
68 CONSTANT tskew : TIME := 1 ns;
69
70 -------------------------------------------------------------------------------JC\/
71 TYPE mem_array_type_t IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
72 SIGNAL mem_array_t : mem_array_type_t;
73 -------------------------------------------------------------------------------JC/\
74
75
76
77 BEGIN
78 CE_b <= CE1_b OR NOT(CE2);
79 byte_enable <= NOT(BHE_b AND BLE_b);
80 write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b);
81 read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b);
82
83 data_skew <= DQ AFTER 1 ns; -- changed on feb 15
84 address_skew <= A AFTER 1 ns;
85
86 PROCESS (OE_b)
87 BEGIN
88 IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN
89 DQ <= (OTHERS => 'Z') after tHZOE;
90 END IF;
91 END PROCESS;
92
93 PROCESS (CE_b)
94 BEGIN
95 IF (CE_b'EVENT AND CE_b = '1') THEN
96 DQ <= (OTHERS => 'Z') after tHZCE;
97 END IF;
98 END PROCESS;
99
100 PROCESS (write_enable'DELAYED(tHA))
101 BEGIN
102 IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN
103 ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA)
104 REPORT "Address hold time tHA violated";
105 END IF;
106 END PROCESS;
107
108 PROCESS (write_enable'DELAYED(tHD))
109 BEGIN
110 IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN
111 ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns)
112 REPORT "Data hold time tHD violated";
113 END IF;
114 END PROCESS;
115
116 -- main process
117 PROCESS
118
119 VARIABLE mem_array : mem_array_type;
120
121 --- Variables for timing checks
122 VARIABLE tPWE_chk : TIME := -10 ns;
123 VARIABLE tAW_chk : TIME := -10 ns;
124 VARIABLE tSD_chk : TIME := -10 ns;
125 VARIABLE tRC_chk : TIME := 0 ns;
126 VARIABLE tBAW_chk : TIME := 0 ns;
127 VARIABLE tBBW_chk : TIME := 0 ns;
128 VARIABLE tBCW_chk : TIME := 0 ns;
129 VARIABLE tBDW_chk : TIME := 0 ns;
130 VARIABLE tSA_chk : TIME := 0 ns;
131 VARIABLE tSA_skew : TIME := 0 ns;
132 VARIABLE tAint_chk : TIME := -10 ns;
133
134 VARIABLE write_flag : BOOLEAN := true;
135
136 VARIABLE accesstime : TIME := 0 ns;
137
138 BEGIN
139 IF (address_skew'EVENT) THEN
140 tSA_skew := NOW;
141 END IF;
142
143 -- start of write
144 IF (write_enable = '1' AND write_enable'EVENT) THEN
145
146 DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE;
147
148 IF (A'LAST_EVENT >= tSA) THEN
149 address_internal <= A;
150 tPWE_chk := NOW;
151 tAW_chk := A'LAST_EVENT;
152 tAint_chk := NOW;
153 write_flag := true;
154
155 ELSE
156 IF (TimingInfo) THEN
157 ASSERT false
158 REPORT "Address setup violated";
159 END IF;
160 write_flag := false;
161
162 END IF;
163
164 -- end of write (with CE high or WE high)
165 ELSIF (write_enable = '0' AND write_enable'EVENT) THEN
166
167 --- check for pulse width
168 IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN
169 --- pulse width OK, do nothing
170 ELSE
171 IF (TimingInfo) THEN
172 ASSERT false
173 REPORT "Pulse Width violation";
174 END IF;
175
176 write_flag := false;
177 END IF;
178
179
180 IF (NOW > 0 ns) THEN
181 IF (tSA_skew - tAint_chk > tskew) THEN
182 ASSERT false
183 REPORT "Negative address setup";
184 write_flag := false;
185 END IF;
186 END IF;
187
188 --- check for address setup with write end, i.e., tAW
189 IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN
190 --- tAW OK, do nothing
191 ELSE
192 IF (TimingInfo) THEN
193 ASSERT false
194 REPORT "Address setup tAW violation";
195 END IF;
196
197 write_flag := false;
198 END IF;
199
200 --- check for data setup with write end, i.e., tSD
201 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
202 --- tSD OK, do nothing
203 ELSE
204 IF (TimingInfo) THEN
205 ASSERT false
206 REPORT "Data setup tSD violation";
207 END IF;
208 write_flag := false;
209 END IF;
210
211 -- perform write operation if no violations
212 IF (write_flag = true) THEN
213
214 IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
215 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
216 END IF;
217
218 IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
219 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
220 END IF;
221
222 IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN
223 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
224 ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN
225 ASSERT false REPORT "Insufficient pulse width for lower byte to be written";
226 END IF;
227
228 IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN
229 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
230 ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN
231 ASSERT false REPORT "Insufficient pulse width for higher byte to be written";
232 END IF;
233
234
235 -------------------------------------------------------------------------------JC\/
236 all_mem_array_obs: FOR I IN 0 TO 127 LOOP
237 IF I < depth THEN
238 mem_array_t(I) <= mem_array(I);
239 END IF;
240 END LOOP all_mem_array_obs;
241 -------------------------------------------------------------------------------JC/\
242
243 END IF;
244
245 -- end of write (with BLE high)
246 ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN
247
248 IF (BLE_b = '0') THEN
249
250 --- Reset timing variables
251 tAW_chk := A'LAST_EVENT;
252 tBAW_chk := NOW;
253 write_flag := true;
254
255 ELSIF (BLE_b = '1') THEN
256
257 --- check for pulse width
258 IF (NOW - tPWE_chk >= tPWE) THEN
259 --- tPWE OK, do nothing
260 ELSE
261 IF (TimingInfo) THEN
262 ASSERT false
263 REPORT "Pulse Width violation";
264 END IF;
265
266 write_flag := false;
267 END IF;
268
269 --- check for address setup with write end, i.e., tAW
270 IF (NOW - tAW_chk >= tAW) THEN
271 --- tAW OK, do nothing
272 ELSE
273 IF (TimingInfo) THEN
274 ASSERT false
275 REPORT "Address setup tAW violation for Lower Byte Write";
276 END IF;
277
278 write_flag := false;
279 END IF;
280
281 --- check for byte write setup with write end, i.e., tBW
282 IF (NOW - tBAW_chk >= tBW) THEN
283 --- tBW OK, do nothing
284 ELSE
285 IF (TimingInfo) THEN
286 ASSERT false
287 REPORT "Lower Byte setup tBW violation";
288 END IF;
289
290 write_flag := false;
291 END IF;
292
293 --- check for data setup with write end, i.e., tSD
294 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
295 --- tSD OK, do nothing
296 ELSE
297 IF (TimingInfo) THEN
298 ASSERT false
299 REPORT "Data setup tSD violation for Lower Byte Write";
300 END IF;
301
302 write_flag := false;
303 END IF;
304
305 --- perform WRITE operation if no violations
306 IF (write_flag = true) THEN
307 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
308 IF (BHE_b = '0') THEN
309 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
310 END IF;
311 END IF;
312
313 --- Reset timing variables
314 tAW_chk := A'LAST_EVENT;
315 tBAW_chk := NOW;
316 write_flag := true;
317
318 END IF;
319
320 -- end of write (with BHE high)
321 ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN
322
323 IF (BHE_b = '0') THEN
324
325 --- Reset timing variables
326 tAW_chk := A'LAST_EVENT;
327 tBBW_chk := NOW;
328 write_flag := true;
329
330 ELSIF (BHE_b = '1') THEN
331
332 --- check for pulse width
333 IF (NOW - tPWE_chk >= tPWE) THEN
334 --- tPWE OK, do nothing
335 ELSE
336 IF (TimingInfo) THEN
337 ASSERT false
338 REPORT "Pulse Width violation";
339 END IF;
340
341 write_flag := false;
342 END IF;
343
344 --- check for address setup with write end, i.e., tAW
345 IF (NOW - tAW_chk >= tAW) THEN
346 --- tAW OK, do nothing
347 ELSE
348 IF (TimingInfo) THEN
349 ASSERT false
350 REPORT "Address setup tAW violation for Upper Byte Write";
351 END IF;
352 write_flag := false;
353 END IF;
354
355 --- check for byte setup with write end, i.e., tBW
356 IF (NOW - tBBW_chk >= tBW) THEN
357 --- tBW OK, do nothing
358 ELSE
359 IF (TimingInfo) THEN
360 ASSERT false
361 REPORT "Upper Byte setup tBW violation";
362 END IF;
363
364 write_flag := false;
365 END IF;
366
367 --- check for data setup with write end, i.e., tSD
368 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
369 --- tSD OK, do nothing
370 ELSE
371 IF (TimingInfo) THEN
372 ASSERT false
373 REPORT "Data setup tSD violation for Upper Byte Write";
374 END IF;
375
376 write_flag := false;
377 END IF;
378
379 --- perform WRITE operation if no violations
380
381 IF (write_flag = true) THEN
382 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
383 IF (BLE_b = '0') THEN
384 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
385 END IF;
386
387 END IF;
388
389 --- Reset timing variables
390 tAW_chk := A'LAST_EVENT;
391 tBBW_chk := NOW;
392 write_flag := true;
393
394 END IF;
395
396 END IF;
397 --- END OF WRITE
398
399 IF (data_skew'EVENT AND read_enable /= '1') THEN
400 tSD_chk := NOW;
401 END IF;
402
403 --- START of READ
404
405 --- Tri-state the data bus if CE or OE disabled
406 IF (read_enable = '0' AND read_enable'EVENT) THEN
407 IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN
408 DQ <= (OTHERS => 'Z') after tHZCE;
409 ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN
410 DQ <= (OTHERS => 'Z') after tHZOE;
411 END IF;
412 END IF;
413
414 --- Address-controlled READ operation
415 IF (A'EVENT) THEN
416 IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN
417 DQ <= (OTHERS => 'Z') after tHZCE;
418 END IF;
419
420 IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN
421 --- tRC OK, do nothing
422 ELSE
423
424 IF (TimingInfo) THEN
425 ASSERT false
426 REPORT "Read Cycle time tRC violation";
427 END IF;
428
429 END IF;
430
431 IF (read_enable = '1') THEN
432
433 IF (BLE_b = '0') THEN
434 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA;
435 END IF;
436
437 IF (BHE_b = '0') THEN
438 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA;
439 END IF;
440
441 tRC_chk := NOW;
442
443 END IF;
444
445 IF (write_enable = '1') THEN
446 --- do nothing
447 END IF;
448
449 END IF;
450
451 IF (read_enable = '0' AND read_enable'EVENT) THEN
452 DQ <= (OTHERS => 'Z') after tHZCE;
453 IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN
454 --- tRC_chk needs to be reset when read ends
455 tRC_CHK := 0 ns;
456 ELSE
457 IF (TimingInfo) THEN
458 ASSERT false
459 REPORT "Read Cycle time tRC violation";
460 END IF;
461 tRC_CHK := 0 ns;
462 END IF;
463
464 END IF;
465
466 --- READ operation triggered by CE/OE/BHE/BLE
467 IF (read_enable = '1' AND read_enable'EVENT) THEN
468
469 tRC_chk := NOW;
470
471 --- CE triggered READ
472 IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2
473
474 IF (BLE_b = '0') THEN
475 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
476 END IF;
477
478 IF (BHE_b = '0') THEN
479 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
480 END IF;
481
482 END IF;
483
484
485 --- OE triggered READ
486 IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
487
488 -- if address or CE changes before OE such that tAA/tACE > tDOE
489 IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN
490
491 IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN
492
493 accesstime := tAA-A'LAST_EVENT;
494 IF (BLE_b = '0') THEN
495 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
496 END IF;
497
498 IF (BHE_b = '0') THEN
499 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
500 END IF;
501
502 ELSE
503 accesstime := tACE-CE_b'LAST_EVENT;
504 IF (BLE_b = '0') THEN
505 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
506 END IF;
507
508 IF (BHE_b = '0') THEN
509 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
510 END IF;
511 END IF;
512
513 -- if address changes before OE such that tAA > tDOE
514 ELSIF (A'LAST_EVENT < tAA - tDOE) THEN
515
516 accesstime := tAA-A'LAST_EVENT;
517 IF (BLE_b = '0') THEN
518 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
519 END IF;
520
521 IF (BHE_b = '0') THEN
522 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
523 END IF;
524
525 -- if CE changes before OE such that tACE > tDOE
526 ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN
527
528 accesstime := tACE-CE_b'LAST_EVENT;
529 IF (BLE_b = '0') THEN
530 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
531 END IF;
532
533 IF (BHE_b = '0') THEN
534 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
535 END IF;
536
537 -- if OE changes such that tDOE > tAA/tACE
538 ELSE
539 IF (BLE_b = '0') THEN
540 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE;
541 END IF;
542
543 IF (BHE_b = '0') THEN
544 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE;
545 END IF;
546
547 END IF;
548
549 END IF;
550 --- END of OE triggered READ
551
552 --- BLE/BHE triggered READ
553 IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
554
555 -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE
556 IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN
557
558 IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN
559 accesstime := tAA-A'LAST_EVENT;
560
561 IF (BLE_b = '0') THEN
562 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
563 END IF;
564
565 IF (BHE_b = '0') THEN
566 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
567 END IF;
568
569 ELSE
570 accesstime := tACE-CE_b'LAST_EVENT;
571
572 IF (BLE_b = '0') THEN
573 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
574 END IF;
575
576 IF (BHE_b = '0') THEN
577 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
578 END IF;
579 END IF;
580
581 -- if address changes before BHE/BLE such that tAA > tDBE
582 ELSIF (A'LAST_EVENT < tAA - tDBE) THEN
583 accesstime := tAA-A'LAST_EVENT;
584
585 IF (BLE_b = '0') THEN
586 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
587 END IF;
588
589 IF (BHE_b = '0') THEN
590 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
591 END IF;
592
593 -- if CE changes before BHE/BLE such that tACE > tDBE
594 ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN
595 accesstime := tACE-CE_b'LAST_EVENT;
596
597 IF (BLE_b = '0') THEN
598 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
599 END IF;
600
601 IF (BHE_b = '0') THEN
602 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
603 END IF;
604
605 -- if BHE/BLE changes such that tDBE > tAA/tACE
606 ELSE
607 IF (BLE_b = '0') THEN
608 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
609 END IF;
610
611 IF (BHE_b = '0') THEN
612 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
613 END IF;
614
615 END IF;
616
617 END IF;
618 -- END of BHE/BLE controlled READ
619
620 IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
621
622 IF (BLE_b = '0') THEN
623 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
624 END IF;
625
626 IF (BHE_b = '0') THEN
627 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
628 END IF;
629
630 END IF;
631
632 END IF;
633 --- END OF CE/OE/BHE/BLE controlled READ
634
635 --- If either BHE or BLE toggle during read mode
636 IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
637 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
638 END IF;
639
640 IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
641 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
642 END IF;
643
644 --- tri-state bus depending on BHE/BLE
645 IF (BLE_b'EVENT AND BLE_b = '1') THEN
646 DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE;
647 END IF;
648
649 IF (BHE_b'EVENT AND BHE_b = '1') THEN
650 DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE;
651 END IF;
652
653 WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew;
654
655 END PROCESS;
656
657
658 END behave_arch;
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1 --************************************************************************
2 --** MODEL : async_1Mx16.vhd **
3 --** COMPANY : Cypress Semiconductor **
4 --** REVISION: 1.0 Created new base model **
5 --************************************************************************
6
7 -------------------------------------------------------------------------------JC\/
8 --Library ieee,work;
9 Library ieee;
10 -------------------------------------------------------------------------------JC/\
11 Use IEEE.Std_Logic_1164.All;
12 use IEEE.Std_Logic_unsigned.All;
13
14 -------------------------------------------------------------------------------JC\/
15 --use work.package_timing.all;
16 --use work.package_utility.all;
17 Library lpp;
18 use lpp.package_timing.all;
19 use lpp.package_utility.all;
20 -------------------------------------------------------------------------------JC/\
21
22 ------------------------
23 -- Entity Description
24 ------------------------
25
26 Entity CY7C1061DV33 is
27 generic
28 (ADDR_BITS : integer := 20;
29 DATA_BITS : integer := 16;
30 depth : integer := 1048576;
31
32 TimingInfo : BOOLEAN := TRUE;
33 TimingChecks : std_logic := '1'
34 );
35 Port (
36 CE1_b : IN Std_Logic; -- Chip Enable CE1#
37 CE2 : IN Std_Logic; -- Chip Enable CE2
38 WE_b : IN Std_Logic; -- Write Enable WE#
39 OE_b : IN Std_Logic; -- Output Enable OE#
40 BHE_b : IN std_logic; -- Byte Enable High BHE#
41 BLE_b : IN std_logic; -- Byte Enable Low BLE#
42 A : IN Std_Logic_Vector(addr_bits-1 downto 0); -- Address Inputs A
43 DQ : INOUT Std_Logic_Vector(DATA_BITS-1 downto 0):=(others=>'Z') -- Read/Write Data IO
44 );
45 End CY7C1061DV33;
46
47 -----------------------------
48 -- End Entity Description
49 -----------------------------
50 -----------------------------
51 -- Architecture Description
52 -----------------------------
53
54 Architecture behave_arch Of CY7C1061DV33 Is
55
56 Type mem_array_type Is array (depth-1 downto 0) of std_logic_vector(DATA_BITS-1 downto 0);
57
58 signal write_enable : std_logic;
59 signal read_enable : std_logic;
60 signal byte_enable : std_logic;
61 signal CE_b :std_logic;
62
63 signal data_skew : Std_Logic_Vector(DATA_BITS-1 downto 0);
64
65 signal address_internal,address_skew: Std_Logic_Vector(addr_bits-1 downto 0);
66
67 constant tSD_dataskew : time := tSD - 1 ns;
68 constant tskew :time := 1 ns;
69
70 begin
71 CE_b <= CE1_b or not(CE2);
72 byte_enable <= not(BHE_b and BLE_b);
73 write_enable <= not(CE1_b) and CE2 and not(WE_b) and not(BHE_b and BLE_b);
74 read_enable <= not(CE1_b) and CE2 and (WE_b) and not(OE_b) and not(BHE_b and BLE_b);
75
76 data_skew <= DQ after 1 ns; -- changed on feb 15
77 address_skew <= A after 1 ns;
78
79 process (OE_b)
80 begin
81 if (OE_b'event and OE_b = '1' and write_enable /= '1') then
82 DQ <=(others=>'Z') after tHZOE;
83 end if;
84 end process;
85
86 process (CE_b)
87 begin
88 if (CE_b'event and CE_b = '1') then
89 DQ <=(others=>'Z') after tHZCE;
90 end if;
91 end process;
92
93 process (write_enable'delayed(tHA))
94 begin
95 if (write_enable'delayed(tHA) = '0' and TimingInfo) then
96 assert (A'last_event = 0 ns) or (A'last_event > tHA)
97 report "Address hold time tHA violated";
98 end if;
99 end process;
100
101 process (write_enable'delayed(tHD))
102 begin
103 if (write_enable'delayed(tHD) = '0' and TimingInfo) then
104 assert (DQ'last_event > tHD) or (DQ'last_event = 0 ns)
105 report "Data hold time tHD violated";
106 end if;
107 end process;
108
109 -- main process
110 process
111
112 VARIABLE mem_array: mem_array_type;
113
114 --- Variables for timing checks
115 VARIABLE tPWE_chk : TIME := -10 ns;
116 VARIABLE tAW_chk : TIME := -10 ns;
117 VARIABLE tSD_chk : TIME := -10 ns;
118 VARIABLE tRC_chk : TIME := 0 ns;
119 VARIABLE tBAW_chk : TIME := 0 ns;
120 VARIABLE tBBW_chk : TIME := 0 ns;
121 VARIABLE tBCW_chk : TIME := 0 ns;
122 VARIABLE tBDW_chk : TIME := 0 ns;
123 VARIABLE tSA_chk : TIME := 0 ns;
124 VARIABLE tSA_skew : TIME := 0 ns;
125 VARIABLE tAint_chk : TIME := -10 ns;
126
127 VARIABLE write_flag : BOOLEAN := TRUE;
128
129 VARIABLE accesstime : TIME := 0 ns;
130
131 begin
132 if (address_skew'event) then
133 tSA_skew := NOW;
134 end if;
135
136 -- start of write
137 if (write_enable = '1' and write_enable'event) then
138
139 DQ(DATA_BITS-1 downto 0)<=(others=>'Z') after tHZWE;
140
141 if (A'last_event >= tSA) then
142 address_internal <= A;
143 tPWE_chk := NOW;
144 tAW_chk := A'last_event;
145 tAint_chk := NOW;
146 write_flag := TRUE;
147
148 else
149 if (TimingInfo) then
150 assert FALSE
151 report "Address setup violated";
152 end if;
153 write_flag := FALSE;
154
155 end if;
156
157 -- end of write (with CE high or WE high)
158 elsif (write_enable = '0' and write_enable'event) then
159
160 --- check for pulse width
161 if (NOW - tPWE_chk >= tPWE or NOW - tPWE_chk <= 0.1 ns or NOW = 0 ns) then
162 --- pulse width OK, do nothing
163 else
164 if (TimingInfo) then
165 assert FALSE
166 report "Pulse Width violation";
167 end if;
168
169 write_flag := FALSE;
170 end if;
171
172
173 if (NOW > 0 ns) then
174 if (tSA_skew - tAint_chk > tskew ) then
175 assert FALSE
176 report "Negative address setup";
177 write_flag := FALSE;
178 end if;
179 end if;
180
181 --- check for address setup with write end, i.e., tAW
182 if (NOW - tAW_chk >= tAW or NOW = 0 ns) then
183 --- tAW OK, do nothing
184 else
185 if (TimingInfo) then
186 assert FALSE
187 report "Address setup tAW violation";
188 end if;
189
190 write_flag := FALSE;
191 end if;
192
193 --- check for data setup with write end, i.e., tSD
194 if (NOW - tSD_chk >= tSD_dataskew or NOW - tSD_chk <= 0.1 ns or NOW = 0 ns) then
195 --- tSD OK, do nothing
196 else
197 if (TimingInfo) then
198 assert FALSE
199 report "Data setup tSD violation";
200 end if;
201 write_flag := FALSE;
202 end if;
203
204 -- perform write operation if no violations
205 if (write_flag = TRUE) then
206
207 if (BLE_b = '1' and BLE_b'last_event = write_enable'last_event and NOW /= 0 ns) then
208 mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0);
209 end if;
210
211 if (BHE_b = '1' and BHE_b'last_event = write_enable'last_event and NOW /= 0 ns) then
212 mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8);
213 end if;
214
215 if (BLE_b = '0' and NOW - tBAW_chk >= tBW) then
216 mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0);
217 elsif (NOW - tBAW_chk < tBW and NOW - tBAW_chk > 0.1 ns and NOW > 0 ns) then
218 assert FALSE report "Insufficient pulse width for lower byte to be written";
219 end if;
220
221 if (BHE_b = '0' and NOW - tBBW_chk >= tBW) then
222 mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8);
223 elsif (NOW - tBBW_chk < tBW and NOW - tBBW_chk > 0.1 ns and NOW > 0 ns) then
224 assert FALSE report "Insufficient pulse width for higher byte to be written";
225 end if;
226
227 end if;
228
229 -- end of write (with BLE high)
230 elsif (BLE_b'event and not(BHE_b'event) and write_enable = '1') then
231
232 if (BLE_b = '0') then
233
234 --- Reset timing variables
235 tAW_chk := A'last_event;
236 tBAW_chk := NOW;
237 write_flag := TRUE;
238
239 elsif (BLE_b = '1') then
240
241 --- check for pulse width
242 if (NOW - tPWE_chk >= tPWE) then
243 --- tPWE OK, do nothing
244 else
245 if (TimingInfo) then
246 assert FALSE
247 report "Pulse Width violation";
248 end if;
249
250 write_flag := FALSE;
251 end if;
252
253 --- check for address setup with write end, i.e., tAW
254 if (NOW - tAW_chk >= tAW) then
255 --- tAW OK, do nothing
256 else
257 if (TimingInfo) then
258 assert FALSE
259 report "Address setup tAW violation for Lower Byte Write";
260 end if;
261
262 write_flag := FALSE;
263 end if;
264
265 --- check for byte write setup with write end, i.e., tBW
266 if (NOW - tBAW_chk >= tBW) then
267 --- tBW OK, do nothing
268 else
269 if (TimingInfo) then
270 assert FALSE
271 report "Lower Byte setup tBW violation";
272 end if;
273
274 write_flag := FALSE;
275 end if;
276
277 --- check for data setup with write end, i.e., tSD
278 if (NOW - tSD_chk >= tSD_dataskew or NOW - tSD_chk <= 0.1 ns or NOW = 0 ns) then
279 --- tSD OK, do nothing
280 else
281 if (TimingInfo) then
282 assert FALSE
283 report "Data setup tSD violation for Lower Byte Write";
284 end if;
285
286 write_flag := FALSE;
287 end if;
288
289 --- perform WRITE operation if no violations
290 if (write_flag = TRUE) then
291 mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0);
292 if (BHE_b = '0') then
293 mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8);
294 end if;
295 end if;
296
297 --- Reset timing variables
298 tAW_chk := A'last_event;
299 tBAW_chk := NOW;
300 write_flag := TRUE;
301
302 end if;
303
304 -- end of write (with BHE high)
305 elsif (BHE_b'event and not(BLE_b'event) and write_enable = '1') then
306
307 if (BHE_b = '0') then
308
309 --- Reset timing variables
310 tAW_chk := A'last_event;
311 tBBW_chk := NOW;
312 write_flag := TRUE;
313
314 elsif (BHE_b = '1') then
315
316 --- check for pulse width
317 if (NOW - tPWE_chk >= tPWE) then
318 --- tPWE OK, do nothing
319 else
320 if (TimingInfo) then
321 assert FALSE
322 report "Pulse Width violation";
323 end if;
324
325 write_flag := FALSE;
326 end if;
327
328 --- check for address setup with write end, i.e., tAW
329 if (NOW - tAW_chk >= tAW) then
330 --- tAW OK, do nothing
331 else
332 if (TimingInfo) then
333 assert FALSE
334 report "Address setup tAW violation for Upper Byte Write";
335 end if;
336 write_flag := FALSE;
337 end if;
338
339 --- check for byte setup with write end, i.e., tBW
340 if (NOW - tBBW_chk >= tBW) then
341 --- tBW OK, do nothing
342 else
343 if (TimingInfo) then
344 assert FALSE
345 report "Upper Byte setup tBW violation";
346 end if;
347
348 write_flag := FALSE;
349 end if;
350
351 --- check for data setup with write end, i.e., tSD
352 if (NOW - tSD_chk >= tSD_dataskew or NOW - tSD_chk <= 0.1 ns or NOW = 0 ns) then
353 --- tSD OK, do nothing
354 else
355 if (TimingInfo) then
356 assert FALSE
357 report "Data setup tSD violation for Upper Byte Write";
358 end if;
359
360 write_flag := FALSE;
361 end if;
362
363 --- perform WRITE operation if no violations
364
365 if (write_flag = TRUE) then
366 mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8);
367 if (BLE_b = '0') then
368 mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0);
369 end if;
370
371 end if;
372
373 --- Reset timing variables
374 tAW_chk := A'last_event;
375 tBBW_chk := NOW;
376 write_flag := TRUE;
377
378 end if;
379
380 end if;
381 --- END OF WRITE
382
383 if (data_skew'event and read_enable /= '1') then
384 tSD_chk := NOW;
385 end if;
386
387 --- START of READ
388
389 --- Tri-state the data bus if CE or OE disabled
390 if (read_enable = '0' and read_enable'event) then
391 if (OE_b'last_event >= CE_b'last_event) then
392 DQ <=(others=>'Z') after tHZCE;
393 elsif (CE_b'last_event > OE_b'last_event) then
394 DQ <=(others=>'Z') after tHZOE;
395 end if;
396 end if;
397
398 --- Address-controlled READ operation
399 if (A'event) then
400 if (A'last_event = CE_b'last_event and CE_b = '1') then
401 DQ <=(others=>'Z') after tHZCE;
402 end if;
403
404 if (NOW - tRC_chk >= tRC or NOW - tRC_chk <= 0.1 ns or tRC_chk = 0 ns) then
405 --- tRC OK, do nothing
406 else
407
408 if (TimingInfo) then
409 assert FALSE
410 report "Read Cycle time tRC violation";
411 end if;
412
413 end if;
414
415 if (read_enable = '1') then
416
417 if (BLE_b = '0') then
418 DQ (7 downto 0) <= mem_array (conv_integer1(A))(7 downto 0) after tAA;
419 end if;
420
421 if (BHE_b = '0') then
422 DQ (15 downto 8) <= mem_array (conv_integer1(A))(15 downto 8) after tAA;
423 end if;
424
425 tRC_chk := NOW;
426
427 end if;
428
429 if (write_enable = '1') then
430 --- do nothing
431 end if;
432
433 end if;
434
435 if (read_enable = '0' and read_enable'event) then
436 DQ <=(others=>'Z') after tHZCE;
437 if (NOW - tRC_chk >= tRC or tRC_chk = 0 ns or A'last_event = read_enable'last_event) then
438 --- tRC_chk needs to be reset when read ends
439 tRC_CHK := 0 ns;
440 else
441 if (TimingInfo) then
442 assert FALSE
443 report "Read Cycle time tRC violation";
444 end if;
445 tRC_CHK := 0 ns;
446 end if;
447
448 end if;
449
450 --- READ operation triggered by CE/OE/BHE/BLE
451 if (read_enable = '1' and read_enable'event) then
452
453 tRC_chk := NOW;
454
455 --- CE triggered READ
456 if (CE_b'last_event = read_enable'last_event ) then -- changed rev2
457
458 if (BLE_b = '0') then
459 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tACE;
460 end if;
461
462 if (BHE_b = '0') then
463 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tACE;
464 end if;
465
466 end if;
467
468
469 --- OE triggered READ
470 if (OE_b'last_event = read_enable'last_event) then
471
472 -- if address or CE changes before OE such that tAA/tACE > tDOE
473 if (CE_b'last_event < tACE - tDOE and A'last_event < tAA - tDOE) then
474
475 if (A'last_event < CE_b'last_event) then
476
477 accesstime:=tAA-A'last_event;
478 if (BLE_b = '0') then
479 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
480 end if;
481
482 if (BHE_b = '0') then
483 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
484 end if;
485
486 else
487 accesstime:=tACE-CE_b'last_event;
488 if (BLE_b = '0') then
489 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
490 end if;
491
492 if (BHE_b = '0') then
493 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
494 end if;
495 end if;
496
497 -- if address changes before OE such that tAA > tDOE
498 elsif (A'last_event < tAA - tDOE) then
499
500 accesstime:=tAA-A'last_event;
501 if (BLE_b = '0') then
502 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
503 end if;
504
505 if (BHE_b = '0') then
506 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
507 end if;
508
509 -- if CE changes before OE such that tACE > tDOE
510 elsif (CE_b'last_event < tACE - tDOE) then
511
512 accesstime:=tACE-CE_b'last_event;
513 if (BLE_b = '0') then
514 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
515 end if;
516
517 if (BHE_b = '0') then
518 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
519 end if;
520
521 -- if OE changes such that tDOE > tAA/tACE
522 else
523 if (BLE_b = '0') then
524 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tDOE;
525 end if;
526
527 if (BHE_b = '0') then
528 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tDOE;
529 end if;
530
531 end if;
532
533 end if;
534 --- END of OE triggered READ
535
536 --- BLE/BHE triggered READ
537 if (BLE_b'last_event = read_enable'last_event or BHE_b'last_event = read_enable'last_event) then
538
539 -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE
540 if (CE_b'last_event < tACE - tDBE and A'last_event < tAA - tDBE) then
541
542 if (A'last_event < BLE_b'last_event) then
543 accesstime:=tAA-A'last_event;
544
545 if (BLE_b = '0') then
546 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
547 end if;
548
549 if (BHE_b = '0') then
550 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
551 end if;
552
553 else
554 accesstime:=tACE-CE_b'last_event;
555
556 if (BLE_b = '0') then
557 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
558 end if;
559
560 if (BHE_b = '0') then
561 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
562 end if;
563 end if;
564
565 -- if address changes before BHE/BLE such that tAA > tDBE
566 elsif (A'last_event < tAA - tDBE) then
567 accesstime:=tAA-A'last_event;
568
569 if (BLE_b = '0') then
570 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
571 end if;
572
573 if (BHE_b = '0') then
574 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
575 end if;
576
577 -- if CE changes before BHE/BLE such that tACE > tDBE
578 elsif (CE_b'last_event < tACE - tDBE) then
579 accesstime:=tACE-CE_b'last_event;
580
581 if (BLE_b = '0') then
582 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime;
583 end if;
584
585 if (BHE_b = '0') then
586 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime;
587 end if;
588
589 -- if BHE/BLE changes such that tDBE > tAA/tACE
590 else
591 if (BLE_b = '0') then
592 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tDBE;
593 end if;
594
595 if (BHE_b = '0') then
596 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tDBE;
597 end if;
598
599 end if;
600
601 end if;
602 -- END of BHE/BLE controlled READ
603
604 if (WE_b'last_event = read_enable'last_event) then
605
606 if (BLE_b = '0') then
607 DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tACE;
608 end if;
609
610 if (BHE_b = '0') then
611 DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tACE;
612 end if;
613
614 end if;
615
616 end if;
617 --- END OF CE/OE/BHE/BLE controlled READ
618
619 --- If either BHE or BLE toggle during read mode
620 if (BLE_b'event and BLE_b = '0' and read_enable = '1' and not(read_enable'event)) then
621 DQ (7 downto 0) <= mem_array (conv_integer1(A)) (7 downto 0) after tDBE;
622 end if;
623
624 if (BHE_b'event and BHE_b = '0' and read_enable = '1' and not(read_enable'event)) then
625 DQ (15 downto 8) <= mem_array (conv_integer1(A)) (15 downto 8) after tDBE;
626 end if;
627
628 --- tri-state bus depending on BHE/BLE
629 if (BLE_b'event and BLE_b = '1') then
630 DQ (7 downto 0) <= (others=>'Z') after tHZBE;
631 end if;
632
633 if (BHE_b'event and BHE_b = '1') then
634 DQ (15 downto 8) <=(others=>'Z') after tHZBE;
635 end if;
636
637 wait on write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew,address_skew;
638
639 end process;
640 end behave_arch;
Show file before | Show file after | Hide comments
@@ -0,0 +1,75
1 --************************************************************************
2 --** MODEL : package_timing.vhd **
3 --** COMPANY : Cypress Semiconductor **
4 --** REVISION: 1.0 (Created new timing package model) **
5 --************************************************************************
6
7
8 library IEEE,std;
9 use IEEE.std_logic_1164.all;
10 use IEEE.std_logic_arith.all;
11 use IEEE.std_logic_unsigned.all;
12 use ieee.std_logic_textio.all ;
13 use std.textio.all ;
14
15 --****************************************************************
16
17 package package_timing is
18
19 ------------------------------------------------------------------------------------------------
20 -- Read Cycle timing
21 ------------------------------------------------------------------------------------------------
22 constant tRC : TIME := 10 ns; -- Read Cycle Time
23 constant tAA : TIME := 10 ns; -- Address to Data Valid
24 constant tOHA : TIME := 3 ns; -- Data Hold from Address Change
25 constant tACE : TIME := 10 ns; -- Random access CEb Low to Data Valid
26 constant tDOE : TIME := 5 ns; -- OE Low to Data Valid
27 constant tLZOE : TIME := 1 ns; -- OE Low to LOW Z
28 constant tHZOE : TIME := 5 ns; -- OE High to HIGH Z
29 constant tLZCE : TIME := 3 ns; -- CEb LOW to LOW Z
30 constant tHZCE : TIME := 5 ns; -- CEb HIGH to HIGH Z
31
32 constant tDBE : TIME := 5 ns; -- BHE/BLE LOW to Data Valid
33 constant tLZBE : TIME := 1 ns; -- BHE/BLE LOW to LOW Z
34 constant tHZBE : TIME := 5 ns; -- BHE/BLE HIGH to HIGH Z
35
36 ------------------------------------------------------------------------------------------------
37 -- Write Cycle timing
38 ------------------------------------------------------------------------------------------------
39 constant tWC : TIME := 10 ns; -- Write Cycle Time
40 constant tSCE : TIME := 7 ns; -- CEb LOW to Write End
41
42 constant tAW : TIME := 7 ns; -- Address Setup to Write End
43 constant tSA : TIME := 0 ns; -- Address Setup to Write Start
44 constant tHA : TIME := 0 ns; -- Address Hold from Write End
45
46 constant tPWE : TIME := 7 ns; -- WEb pulse width
47
48 constant tSD : TIME := 5.5 ns; -- Data Setup to Write End
49 constant tHD : TIME := 0 ns; -- Data Hold from Write End
50
51 constant tBW : TIME := 7 ns; -- BHE BLE Setup to Write End
52
53 constant tLZWE : TIME := 3 ns; -- WEb Low to High Z
54 constant tHZWE : TIME := 5 ns; -- WEb High to Low Z
55
56 end package_timing;
57
58 package body package_timing is
59
60 end package_timing;
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Show file before | Show file after | Hide comments
@@ -0,0 +1,4
1 package_utility.vhd
2 package_timing.vhd
3 CY7C1061DV33_pkg.vhd
4 CY7C1061DV33.vhd
Show file before | Show file after | Hide comments
@@ -27,7 +27,6 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29
29
30
31 PACKAGE lpp_ad_conv IS
30 PACKAGE lpp_ad_conv IS
32
31
33
32
@@ -35,23 +34,21 PACKAGE lpp_ad_conv IS
35 --CONSTANT ADS7886 : INTEGER := 1;
34 --CONSTANT ADS7886 : INTEGER := 1;
36
35
37
36
38 TYPE AD7688_out IS
37 --TYPE AD7688_out IS
39 RECORD
38 --RECORD
40 CNV : STD_LOGIC;
39 -- CNV : STD_LOGIC;
41 SCK : STD_LOGIC;
40 -- SCK : STD_LOGIC;
42 END RECORD;
41 --END RECORD;
43
42
44 TYPE AD7688_in_element IS
43 --TYPE AD7688_in_element IS
45 RECORD
44 --RECORD
46 SDI : STD_LOGIC;
45 -- SDI : STD_LOGIC;
47 END RECORD;
46 --END RECORD;
48
47
49 TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
48 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
50
49
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52
51
53 -----------------------------------------------------------------------------
54 -----------------------------------------------------------------------------
55 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
52 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
56
53
57 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
54 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -76,6 +73,24 PACKAGE lpp_ad_conv IS
76
73
77 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
74 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
78
75
76 COMPONENT AD7688_drvr
77 GENERIC (
78 ChanelCount : INTEGER;
79 ncycle_cnv_high : INTEGER := 79;
80 ncycle_cnv : INTEGER := 500);
81 PORT (
82 cnv_clk : IN STD_LOGIC;
83 cnv_rstn : IN STD_LOGIC;
84 cnv_run : IN STD_LOGIC;
85 cnv : OUT STD_LOGIC;
86 clk : IN STD_LOGIC;
87 rstn : IN STD_LOGIC;
88 sck : OUT STD_LOGIC;
89 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
90 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
91 sample_val : OUT STD_LOGIC);
92 END COMPONENT;
93
79 COMPONENT RHF1401_drvr IS
94 COMPONENT RHF1401_drvr IS
80 GENERIC(
95 GENERIC(
81 ChanelCount : INTEGER := 8);
96 ChanelCount : INTEGER := 8);
@@ -108,6 +123,23 PACKAGE lpp_ad_conv IS
108 sample_val : OUT STD_LOGIC);
123 sample_val : OUT STD_LOGIC);
109 END COMPONENT;
124 END COMPONENT;
110
125
126
127 COMPONENT AD7688_drvr_sync
128 GENERIC (
129 ChanelCount : INTEGER;
130 ncycle_cnv_high : INTEGER;
131 ncycle_cnv : INTEGER);
132 PORT (
133 cnv_clk : IN STD_LOGIC;
134 cnv_rstn : IN STD_LOGIC;
135 cnv_run : IN STD_LOGIC;
136 cnv : OUT STD_LOGIC;
137 sck : OUT STD_LOGIC;
138 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
139 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
140 sample_val : OUT STD_LOGIC);
141 END COMPONENT;
142
111 COMPONENT TestModule_RHF1401
143 COMPONENT TestModule_RHF1401
112 GENERIC (
144 GENERIC (
113 freq : INTEGER;
145 freq : INTEGER;
@@ -119,51 +151,30 PACKAGE lpp_ad_conv IS
119 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
151 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
120 END COMPONENT;
152 END COMPONENT;
121
153
122 -----------------------------------------------------------------------------
154 --COMPONENT AD7688_drvr IS
123 -----------------------------------------------------------------------------
155 -- GENERIC(ChanelCount : INTEGER;
124
156 -- clkkHz : INTEGER);
125 COMPONENT ADS7886_drvr
157 -- PORT (clk : IN STD_LOGIC;
126 GENERIC (
158 -- rstn : IN STD_LOGIC;
127 ChanelCount : INTEGER;
159 -- enable : IN STD_LOGIC;
128 ncycle_cnv_high : INTEGER := 79;
160 -- smplClk : IN STD_LOGIC;
129 ncycle_cnv : INTEGER := 500);
161 -- DataReady : OUT STD_LOGIC;
130 PORT (
162 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
131 cnv_clk : IN STD_LOGIC;
163 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
132 cnv_rstn : IN STD_LOGIC;
164 -- AD_out : OUT AD7688_out);
133 cnv_run : IN STD_LOGIC;
165 --END COMPONENT;
134 cnv : OUT STD_LOGIC;
135 clk : IN STD_LOGIC;
136 rstn : IN STD_LOGIC;
137 sck : OUT STD_LOGIC;
138 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
139 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
140 sample_val : OUT STD_LOGIC);
141 END COMPONENT;
142
143 COMPONENT AD7688_drvr IS
144 GENERIC(ChanelCount : INTEGER;
145 clkkHz : INTEGER);
146 PORT (clk : IN STD_LOGIC;
147 rstn : IN STD_LOGIC;
148 enable : IN STD_LOGIC;
149 smplClk : IN STD_LOGIC;
150 DataReady : OUT STD_LOGIC;
151 smpout : OUT Samples(ChanelCount-1 DOWNTO 0);
152 AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
153 AD_out : OUT AD7688_out);
154 END COMPONENT;
155
166
156
167
157 COMPONENT AD7688_spi_if IS
168 --COMPONENT AD7688_spi_if IS
158 GENERIC(ChanelCount : INTEGER);
169 -- GENERIC(ChanelCount : INTEGER);
159 PORT(clk : IN STD_LOGIC;
170 -- PORT(clk : IN STD_LOGIC;
160 reset : IN STD_LOGIC;
171 -- reset : IN STD_LOGIC;
161 cnv : IN STD_LOGIC;
172 -- cnv : IN STD_LOGIC;
162 DataReady : OUT STD_LOGIC;
173 -- DataReady : OUT STD_LOGIC;
163 sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
174 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
164 smpout : OUT Samples(ChanelCount-1 DOWNTO 0)
175 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
165 );
176 -- );
166 END COMPONENT;
177 --END COMPONENT;
167
178
168
179
169 --COMPONENT lpp_apb_ad_conv
180 --COMPONENT lpp_apb_ad_conv
@@ -217,73 +228,116 PACKAGE lpp_ad_conv IS
217 --======================= ADS 127X =========================|
228 --======================= ADS 127X =========================|
218 --===========================================================|
229 --===========================================================|
219
230
220 Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic;
231 TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
221 constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
232 CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
222 constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
233 CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
223
234
224 Type ADS127X_MODE_Type is array(1 downto 0) of std_logic;
235 TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
225 constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
236 CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
226 constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
237 CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
227 constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
238 CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
228
239
229 Type ADS127X_config is
240 TYPE ADS127X_config IS
230 record
241 RECORD
231 SYNC : std_logic;
242 SYNC : STD_LOGIC;
232 CLKDIV : std_logic;
243 CLKDIV : STD_LOGIC;
233 FORMAT : ADS127X_FORMAT_Type;
244 FORMAT : ADS127X_FORMAT_Type;
234 MODE : ADS127X_MODE_Type;
245 MODE : ADS127X_MODE_Type;
235 end record;
246 END RECORD;
236
247
237 COMPONENT ADS1274_DRIVER is
248 COMPONENT ADS1274_DRIVER IS
238 generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
249 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
239 port(
250 PORT(
240 Clk : in std_logic;
251 Clk : IN STD_LOGIC;
241 reset : in std_logic;
252 reset : IN STD_LOGIC;
242 SpiClk : out std_logic;
253 SpiClk : OUT STD_LOGIC;
243 DIN : in std_logic_vector(3 downto 0);
254 DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
244 Ready : in std_logic;
255 Ready : IN STD_LOGIC;
245 Format : out std_logic_vector(2 downto 0);
256 Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
246 Mode : out std_logic_vector(1 downto 0);
257 Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
247 ClkDiv : out std_logic;
258 ClkDiv : OUT STD_LOGIC;
248 PWDOWN : out std_logic_vector(3 downto 0);
259 PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249 SmplClk : in std_logic;
260 SmplClk : IN STD_LOGIC;
250 OUT0 : out std_logic_vector(23 downto 0);
261 OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
251 OUT1 : out std_logic_vector(23 downto 0);
262 OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
252 OUT2 : out std_logic_vector(23 downto 0);
263 OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
253 OUT3 : out std_logic_vector(23 downto 0);
264 OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
254 FSynch : out std_logic;
265 FSynch : OUT STD_LOGIC;
255 test : out std_logic
266 test : OUT STD_LOGIC
256 );
267 );
257 end COMPONENT;
268 END COMPONENT;
258
269
259 -- todo clean file
270 -- todo clean file
260 COMPONENT DUAL_ADS1278_DRIVER is
271 COMPONENT DUAL_ADS1278_DRIVER IS
261 port(
272 PORT(
262 Clk : in std_logic;
273 Clk : IN STD_LOGIC;
263 reset : in std_logic;
274 reset : IN STD_LOGIC;
264 SpiClk : out std_logic;
275 SpiClk : OUT STD_LOGIC;
265 DIN : in std_logic_vector(1 downto 0);
276 DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
266 SmplClk : in std_logic;
277 SmplClk : IN STD_LOGIC;
267 OUT00 : out std_logic_vector(23 downto 0);
278 OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
268 OUT01 : out std_logic_vector(23 downto 0);
279 OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
269 OUT02 : out std_logic_vector(23 downto 0);
280 OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
270 OUT03 : out std_logic_vector(23 downto 0);
281 OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
271 OUT04 : out std_logic_vector(23 downto 0);
282 OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
272 OUT05 : out std_logic_vector(23 downto 0);
283 OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
273 OUT06 : out std_logic_vector(23 downto 0);
284 OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
274 OUT07 : out std_logic_vector(23 downto 0);
285 OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
275 OUT10 : out std_logic_vector(23 downto 0);
286 OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
276 OUT11 : out std_logic_vector(23 downto 0);
287 OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
277 OUT12 : out std_logic_vector(23 downto 0);
288 OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
278 OUT13 : out std_logic_vector(23 downto 0);
289 OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
279 OUT14 : out std_logic_vector(23 downto 0);
290 OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
280 OUT15 : out std_logic_vector(23 downto 0);
291 OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
281 OUT16 : out std_logic_vector(23 downto 0);
292 OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
282 OUT17 : out std_logic_vector(23 downto 0);
293 OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
283 FSynch : out std_logic
294 FSynch : OUT STD_LOGIC
284 );
295 );
285 end COMPONENT;
296 END COMPONENT;
286
297
298 --===========================================================|
299 -- DRIVER ADS7886
300 --===========================================================|
301 COMPONENT top_ad_conv_ADS7886_v2 IS
302 GENERIC(
303 ChannelCount : INTEGER := 8;
304 SampleNbBits : INTEGER := 14;
305 ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
306 ncycle_cnv : INTEGER := 500);
307 PORT (
308 -- CONV
309 cnv_clk : IN STD_LOGIC;
310 cnv_rstn : IN STD_LOGIC;
311 cnv : OUT STD_LOGIC;
312 -- DATA
313 clk : IN STD_LOGIC;
314 rstn : IN STD_LOGIC;
315 sck : OUT STD_LOGIC;
316 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
317 -- SAMPLE
318 sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
319 sample_val : OUT STD_LOGIC
320 );
321 END COMPONENT;
322
323 COMPONENT ADS7886_drvr_v2 IS
324 GENERIC(
325 ChannelCount : INTEGER := 8;
326 NbBitsSamples : INTEGER := 16);
327 PORT (
328 -- CONV --
329 cnv_clk : IN STD_LOGIC;
330 cnv_rstn : IN STD_LOGIC;
331 -- DATA --
332 clk : IN STD_LOGIC;
333 rstn : IN STD_LOGIC;
334 sck : OUT STD_LOGIC;
335 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
336 -- SAMPLE --
337 sample : OUT Samples(ChannelCount-1 DOWNTO 0);
338 sample_val : OUT STD_LOGIC
339 );
340 END COMPONENT;
287
341
288 END lpp_ad_conv;
342 END lpp_ad_conv;
289
343
Show file before | Show file after | Hide comments
@@ -1,4 +1,10
1 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr_sync.vhd
4 WriteGen_ADC.vhd
5 TestModule_ADS7886.vhd
2 RHF1401.vhd
6 RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
7 top_ad_conv_RHF1401.vhd
4 TestModule_RHF1401.vhd
8 TestModule_RHF1401.vhd
9 top_ad_conv_ADS7886_v2.vhd
10 ADS7886_drvr_v2.vhd
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