# HG changeset patch # User pellion # Date 2014-01-21 08:29:57 # Node ID b49f9ec9e95a13c12f2edb67644243b886615fd0 # Parent 8b7f4967459cde763ba3c151fcde923adc29fa46 Add Driver ADS7886 + MINI_LFR_WFRM-GPIO (release 206 porté sur MINI-LFR) diff --git a/designs/LFR_simu/Makefile b/designs/LFR_simu/Makefile new file mode 100644 --- /dev/null +++ b/designs/LFR_simu/Makefile @@ -0,0 +1,50 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES=config.vhd leon3mp.vhd +VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/LFR_simu/run_tb_waveform.do b/designs/LFR_simu/run_tb_waveform.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu/run_tb_waveform.do @@ -0,0 +1,21 @@ +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd + +vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd + +vcom -quiet -93 -work lpp testbench_package.vhd + +vcom -quiet -93 -work work tb_waveform.vhd + +vsim work.testbench + +log -r * + +do tb_waveform.do + +run -all diff --git a/designs/LFR_simu/tb_waveform.do b/designs/LFR_simu/tb_waveform.do new file mode 100644 --- /dev/null +++ b/designs/LFR_simu/tb_waveform.do @@ -0,0 +1,48 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid +add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid +add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd +add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_1/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_1/mem_array_t +add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_t(127) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(126) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(125) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(124) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(123) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(122) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(121) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(120) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(119) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(118) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(117) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(116) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(115) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(114) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(113) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(112) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(111) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(110) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(109) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(108) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(107) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(106) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(105) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(104) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(103) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(102) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(101) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(100) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(99) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(98) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(97) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(96) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(95) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(94) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(93) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(92) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(91) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(90) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(89) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(88) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(87) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(86) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(85) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(84) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(83) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(82) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(81) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(80) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(79) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(78) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(77) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(76) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(75) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(74) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(73) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(72) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(71) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(70) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(69) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(68) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(67) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(66) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(65) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(64) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(63) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(62) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(61) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(60) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(59) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(58) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(57) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(56) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(55) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(54) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(53) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(52) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(51) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(50) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(49) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(48) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(47) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(46) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(45) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(44) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(43) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(42) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(41) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(40) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(39) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(38) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(37) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(36) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(35) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(34) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(33) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(32) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(31) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(30) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(29) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(28) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(27) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(26) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(25) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(24) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(23) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(22) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(21) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(20) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(19) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(18) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(17) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(16) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(15) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(14) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(13) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(12) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(11) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(10) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(9) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(8) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(7) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(6) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(5) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(4) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(3) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(2) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(1) {-radix hexadecimal} /testbench/async_1mx16_0/mem_array_t(0) {-radix hexadecimal}} /testbench/async_1mx16_0/mem_array_t +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send +add wave -noupdate -expand -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst +add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin +add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout +add wave -noupdate -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain +add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data +add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant +add wave -noupdate -expand /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {12032365000 ps} 0} +configure wave -namecolwidth 540 +configure wave -valuecolwidth 316 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {162198702750 ps} diff --git a/designs/LFR_simu/tb_waveform.vhd b/designs/LFR_simu/tb_waveform.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu/tb_waveform.vhd @@ -0,0 +1,445 @@ +------------------------------------------------------------------------------ +-- LEON3 Demonstration design test bench +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved. +-- +-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN +-- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED +-- IN ADVANCE IN WRITING. +------------------------------------------------------------------------------ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +--LIBRARY std; +--USE std.textio.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.libdcom.ALL; +USE gaisler.sim.ALL; +USE gaisler.jtagtst.ALL; +USE gaisler.misc.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +--LIBRARY micron; +--USE micron.components.ALL; +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.testbench_package.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + -- REG ADDRESS + CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15; + CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; + CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; + CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; + CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; + CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; + CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; + CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; + CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; + -- RAM ADDRESS + CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#; + CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; + CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; + CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; + + + -- Common signal + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL clk25MHz : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + + -- ADC interface + SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT + SIGNAL ADC_smpclk : STD_LOGIC; -- OUT + SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN + + -- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + + -- AHB/APB SIGNAL + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + + SIGNAL bias_fail_bw : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- LPP_WAVEFORM + ----------------------------------------------------------------------------- + CONSTANT data_size : INTEGER := 96; + CONSTANT nb_burst_available_size : INTEGER := 50; + CONSTANT nb_snapshot_param_size : INTEGER := 2; + CONSTANT delta_vector_size : INTEGER := 2; + CONSTANT delta_vector_size_f0_2 : INTEGER := 2; + + SIGNAL reg_run : STD_LOGIC; + SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); + SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_in_valid : STD_LOGIC; + SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_in_valid : STD_LOGIC; + SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_in_valid : STD_LOGIC; + SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_in_valid : STD_LOGIC; + SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out_valid : STD_LOGIC; + SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f0_data_out_ack : STD_LOGIC; + SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out_valid : STD_LOGIC; + SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f1_data_out_ack : STD_LOGIC; + SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out_valid : STD_LOGIC; + SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f2_data_out_ack : STD_LOGIC; + SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out_valid : STD_LOGIC; + SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f3_data_out_ack : STD_LOGIC; + + --MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + + SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nSRAM_BE0 : STD_LOGIC; + SIGNAL nSRAM_BE1 : STD_LOGIC; + SIGNAL nSRAM_BE2 : STD_LOGIC; + SIGNAL nSRAM_BE3 : STD_LOGIC; + SIGNAL nSRAM_WE : STD_LOGIC; + SIGNAL nSRAM_CE : STD_LOGIC; + SIGNAL nSRAM_OE : STD_LOGIC; + + CONSTANT padtech : INTEGER := inferred; + SIGNAL not_ramsn_0 : STD_LOGIC; + + +BEGIN + + ----------------------------------------------------------------------------- + + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz + + ----------------------------------------------------------------------------- + + MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE + TestModule_RHF1401_1 : TestModule_RHF1401 + GENERIC MAP ( + freq => 24*(I+1), + amplitude => 8000/(I+1), + impulsion => 0) + PORT MAP ( + ADC_smpclk => ADC_smpclk, + ADC_OEB_bar => ADC_OEB_bar_CH(I), + ADC_data => ADC_data); + END GENERATE MODULE_RHF1401; + + ----------------------------------------------------------------------------- + + top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk49_152MHz, + cnv_rstn => rstn, + cnv => ADC_smpclk, + clk => clk25MHz, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_CEL, -- use_RAM + nb_data_by_buffer_size => 32, + nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 32, + pindex => INDEX_WAVEFORM_PICKER, + paddr => ADDR_WAVEFORM_PICKER, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 0, + top_lfr_version => X"00000001") + PORT MAP ( + clk => clk25MHz, + rstn => rstn, + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi, + apbo => apbo(15), + ahbi => ahbmi, + ahbo => ahbmo(0), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_bw); + + ----------------------------------------------------------------------------- + --- AHB CONTROLLER ------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => 0, split => 0, + rrobin => 1, ioaddr => 16#FFF#, + ioen => 0, nahbm => 1, nahbs => 1) + PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); + + --- AHB RAM ---------------------------------------------------------- + --ahbram0 : ahbram + -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); + --ahbram1 : ahbram + -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); + --ahbram2 : ahbram + -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); + --ahbram3 : ahbram + -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); + + ----------------------------------------------------------------------------- +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + not_ramsn_0 <= NOT(memo.ramsn(0)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + + async_1Mx16_0: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE1, + BLE_b => nSRAM_BE0, + A => address, + DQ => data(15 DOWNTO 0)); + + async_1Mx16_1: CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + TimingInfo => TRUE, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE3, + BLE_b => nSRAM_BE2, + A => address, + DQ => data(31 DOWNTO 16)); + + + ----------------------------------------------------------------------------- + + WaveGen_Proc : PROCESS + BEGIN + + -- insert signal assignments here + WAIT UNTIL clk25MHz = '1'; + rstn <= '0'; + apbi.psel(15) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + fine_time <= (OTHERS => '0'); + coarse_time <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; +-- ahbmi.HGRANT(2) <= '1'; +-- ahbmi.HREADY <= '1'; +-- ahbmi.HRESP <= HRESP_OKAY; + + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + rstn <= '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + --------------------------------------------------------------------------- + -- CONFIGURATION STEP + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40200000"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40400000"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40800000"); + + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000002");--"00000020" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000002");--"00000019" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000001");--"00000007" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000020");--"00000019" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" + + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" + -- + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); + + + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000081"); + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT FOR 1 us; + coarse_time <= X"00000001"; + --------------------------------------------------------------------------- + -- RUN STEP + WAIT FOR 200 ms; + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); + WAIT FOR 10 us; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); + WAIT UNTIL clk25MHz = '1'; + coarse_time <= X"00000010"; + WAIT FOR 100 ms; + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); + WAIT FOR 10 us; + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); + WAIT FOR 200 ms; + REPORT "*** END simulation ***" SEVERITY failure; + + + WAIT; + + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- IRQ + ----------------------------------------------------------------------------- + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge + + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + +END; diff --git a/designs/LFR_simu/testbench_package.vhd b/designs/LFR_simu/testbench_package.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR_simu/testbench_package.vhd @@ -0,0 +1,53 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +--LIBRARY gaisler; +--USE gaisler.libdcom.ALL; +--USE gaisler.sim.ALL; +--USE gaisler.jtagtst.ALL; +--LIBRARY techmap; +--USE techmap.gencomp.ALL; + + +PACKAGE testbench_package IS + + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + + END APB_WRITE; + +END testbench_package; diff --git a/designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd b/designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR-WFRM-GPIO/MINI_LFR_top.vhd @@ -0,0 +1,529 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +--USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib +USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY MINI_LFR_top IS + + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END MINI_LFR_top; + + +ARCHITECTURE beh OF MINI_LFR_top IS + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- UART AHB --------------------------------------------------------------- + SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data + SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data + SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data + -- + SIGNAL I00_s : STD_LOGIC; + + -- CONSTANTS + constant CFG_PADTECH : integer := inferred; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : std_ulogic; + SIGNAL spw_rxclkn : std_ulogic; + SIGNAL spw_clk : std_logic; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; +-- SIGNAL clkmn : STD_ULOGIC; +-- SIGNAL txclk : STD_ULOGIC; + +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; + +-- AD Converter ADS7886 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL ADC_nCS_sig : STD_LOGIC; + SIGNAL ADC_CLK_sig : STD_LOGIC; + SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + + SIGNAL bias_fail_sw_sig : STD_LOGIC; + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + + PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + + PROCESS(clk_50_s) + BEGIN + IF clk_50_s'EVENT AND clk_50_s = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + --IO1 <= '0'; + --IO2 <= '1'; + --IO3 <= '0'; + --IO4 <= '0'; + --IO5 <= '0'; + --IO6 <= '0'; + --IO7 <= '0'; + --IO8 <= '0'; + --IO9 <= '0'; + --IO10 <= '0'; + --IO11 <= '0'; + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0; + --IO1 <= '1'; + --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; + --IO3 <= ADC_SDO(0); + --IO4 <= ADC_SDO(1); + --IO5 <= ADC_SDO(2); + --IO6 <= ADC_SDO(3); + --IO7 <= ADC_SDO(4); + --IO8 <= ADC_SDO(5); + --IO9 <= ADC_SDO(6); + --IO10 <= ADC_SDO(7); + IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk_49, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; +-- IO0 <= I00_s; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + + --EXT CONNECTOR + + --SPACE WIRE + + leon3_soc_1: leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + NB_CPU => 1, + ENABLE_FPU => 1, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE) + PORT MAP ( + clk => clk_25, + reset => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1: apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + pirq => 12) + PORT MAP ( + clk25MHz => clk_25, + clk49_152MHz => clk_49, + resetn => reset, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + SPW_EN <= '1'; + + spw_clk <= clk_50_s; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= not spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad generic map (tech => inferred) + port map (SPW_NOM_DIN, dtmp(0)); + spw1_rxs_pad : inpad generic map (tech => inferred) + port map (SPW_NOM_SIN, stmp(0)); + spw1_txd_pad : outpad generic map (tech => inferred) + port map (SPW_NOM_DOUT, swno.d(0)); + spw1_txs_pad : outpad generic map (tech => inferred) + port map (SPW_NOM_SOUT, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad generic map (tech => inferred) -- bad naming of the MINI-LFR /!\ + port map (SPW_RED_SIN, dtmp(1)); + spw2_rxs_pad : inpad generic map (tech => inferred) -- bad naming of the MINI-LFR /!\ + port map (SPW_RED_DIN, stmp(1)); + spw2_txd_pad : outpad generic map (tech => inferred) + port map (SPW_RED_DOUT, swno.d(1)); + spw2_txs_pad : outpad generic map (tech => inferred) + port map (SPW_RED_SOUT, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop: for j in 0 to 1 generate + spw_phy0 : grspw_phy + generic map( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + port map( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 downto j*5), + dconnect => swni.dconnect(j*2+1 downto j*2)); + end generate spw_inputloop; + + -- SPW core + sw0 : grspwm generic map( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + port map(reset, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (others => '0'); + swni.dcrstval <= (others => '0'); + swni.timerrstval <= (others => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- +-- lpp_lfr_1 : lpp_lfr +-- GENERIC MAP ( +-- Mem_use => use_RAM, +-- nb_data_by_buffer_size => 32, +-- nb_word_by_buffer_size => 30, +-- nb_snapshot_param_size => 32, +-- delta_vector_size => 32, +-- delta_vector_size_f0_2 => 7, -- log2(96) +-- pindex => 6, +-- paddr => 6, +-- pmask => 16#fff#, +-- pirq_ms => 6, +-- pirq_wfp => 14, +-- hindex => 2, +-- top_lfr_version => X"00000005") +-- PORT MAP ( +-- clk => clk_25, +-- rstn => reset, +-- sample_B => sample(2 DOWNTO 0), +-- sample_E => sample(7 DOWNTO 3), +-- sample_val => sample_val, +-- apbi => apbi_ext, +-- apbo => apbo_ext(6), +-- ahbi => ahbi_m_ext, +-- ahbo => ahbo_m_ext(2), +-- coarse_time => coarse_time, +-- fine_time => fine_time, +-- data_shaping_BW => bias_fail_sw_sig); + + waveform_picker0 : top_wf_picker + GENERIC MAP( + hindex => 2, + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq => 14, + tech => apa3e, + nb_burst_available_size => 12, -- size of the register holding the nb of burst + nb_snapshot_param_size => 12, -- size of the register holding the snapshots size + delta_snapshot_size => 16, -- snapshots period + delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts + delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot + ENABLE_FILTER => '1' + ) + PORT MAP( + cnv_clk => clk_25, + cnv_rstn => reset, + -- SAMPLES + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + -- AMBA AHB system signals + HCLK => clk_25, + HRESETn => reset, + -- AMBA APB Slave Interface + apbi => apbi_ext, + apbo => apbo_ext(15), + -- AMBA AHB Master Interface + AHB_Master_In => ahbi_m_ext, + AHB_Master_Out => ahbo_m_ext(2), + -- + coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time + -- + data_shaping_BW => bias_fail_sw_sig + ); + + top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 + GENERIC MAP( + ChannelCount => 8, + SampleNbBits => 14, + ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 + ncycle_cnv => 500) -- 49 152 000 / 98304 + PORT MAP ( + -- CONV + cnv_clk => clk_49, + cnv_rstn => reset, + cnv => ADC_nCS_sig, + -- DATA + clk => clk_25, + rstn => reset, + sck => ADC_CLK_sig, + sdo => ADC_SDO_sig, + -- SAMPLE + sample => sample, + sample_val => sample_val); + + IO10 <= ADC_SDO_sig(5); + IO9 <= ADC_SDO_sig(4); + IO8 <= ADC_SDO_sig(3); + + ADC_nCS <= ADC_nCS_sig; + ADC_CLK <= ADC_CLK_sig; + ADC_SDO_sig <= ADC_SDO; + +---------------------------------------------------------------------- +--- GPIO ----------------------------------------------------------- +---------------------------------------------------------------------- + +grgpio0: grgpio + generic map( pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) + port map( reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); + +pio_pad_0 : iopad + generic map (tech => CFG_PADTECH) + port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); +pio_pad_1 : iopad + generic map (tech => CFG_PADTECH) + port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); +pio_pad_2 : iopad + generic map (tech => CFG_PADTECH) + port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); +pio_pad_3 : iopad + generic map (tech => CFG_PADTECH) + port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); +pio_pad_4 : iopad + generic map (tech => CFG_PADTECH) + port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); +pio_pad_5 : iopad + generic map (tech => CFG_PADTECH) + port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); +pio_pad_6 : iopad + generic map (tech => CFG_PADTECH) + port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); +pio_pad_7 : iopad + generic map (tech => CFG_PADTECH) + port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); + +END beh; \ No newline at end of file diff --git a/designs/MINI-LFR-WFRM-GPIO/Makefile b/designs/MINI-LFR-WFRM-GPIO/Makefile new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR-WFRM-GPIO/Makefile @@ -0,0 +1,51 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=MINI_LFR_top +BOARD=MINI-LFR +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +VHDLSYNFILES= MINI_LFR_top.vhd + +PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./dsp/lpp_fft \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_demux \ + ./lpp_matrix \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_Header \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP =lpp_lfr_ms.vhd \ + i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_SIMPLE_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd b/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd @@ -0,0 +1,119 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +-- MODIFIED by Jean-christophe PELLION +-- jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- MODIFIED by Paul LEROY +-- paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; + +ENTITY ADS7886_drvr_v2 IS + GENERIC( + ChannelCount : INTEGER := 8; + NbBitsSamples : INTEGER := 16); + PORT ( + -- CONV -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + -- DATA -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); + -- SAMPLE -- + sample : OUT Samples(ChannelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END ADS7886_drvr_v2; + +ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS7886_drvr_v2 IS + + SIGNAL cnv_sync : STD_LOGIC; + SIGNAL cnv_sync_r : STD_LOGIC; + SIGNAL cnv_done : STD_LOGIC; + SIGNAL sample_bit_counter : INTEGER; + SIGNAL shift_reg : Samples(ChannelCount-1 DOWNTO 0); + +BEGIN + +cnv_sync <= cnv_clk; + + PROCESS (clk, rstn) -- falling edge detection on cnv_sync + BEGIN + IF rstn = '0' THEN + cnv_sync_r <= '1'; + cnv_done <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + cnv_sync_r <= cnv_sync; + cnv_done <= (NOT cnv_sync) AND cnv_sync_r; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN + FOR k IN 0 TO ChannelCount-1 LOOP + shift_reg(k)(15 downto 0) <= (OTHERS => '0'); + sample(k)(15 downto 0) <= (OTHERS => '0'); + END LOOP; + sample_bit_counter <= 0; + sample_val <= '0'; + SCK <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN + IF (cnv_done = '1') AND (sample_bit_counter = 0) THEN + sample_bit_counter <= 1; + ELSIF sample_bit_counter > 0 AND sample_bit_counter < 31 THEN + sample_bit_counter <= sample_bit_counter + 1; + ELSIF sample_bit_counter = 31 THEN + sample_val <= '1'; + FOR k IN 0 TO ChannelCount-1 LOOP + sample(k)(0) <= sdo(k); + sample(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0); + END LOOP; + sample_bit_counter <= 0; + ELSE + sample_val <= '0'; + END IF; + + IF (sample_bit_counter MOD 2) = 1 THEN -- get data on each channel + FOR k IN 0 TO ChannelCount-1 LOOP + shift_reg(k)(0) <= sdo(k); + shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0); + END LOOP; + SCK <= '0'; + ELSE + SCK <= '1'; + END IF; + END IF; + END PROCESS; + +END ar_ADS7886_drvr_v2; \ No newline at end of file diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -27,7 +27,6 @@ USE grlib.amba.ALL; USE grlib.stdlib.ALL; USE grlib.devices.ALL; - PACKAGE lpp_ad_conv IS @@ -35,23 +34,21 @@ PACKAGE lpp_ad_conv IS --CONSTANT ADS7886 : INTEGER := 1; - TYPE AD7688_out IS - RECORD - CNV : STD_LOGIC; - SCK : STD_LOGIC; - END RECORD; + --TYPE AD7688_out IS + --RECORD + -- CNV : STD_LOGIC; + -- SCK : STD_LOGIC; + --END RECORD; - TYPE AD7688_in_element IS - RECORD - SDI : STD_LOGIC; - END RECORD; + --TYPE AD7688_in_element IS + --RECORD + -- SDI : STD_LOGIC; + --END RECORD; - TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; + --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0); SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -76,6 +73,24 @@ PACKAGE lpp_ad_conv IS TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8; + COMPONENT AD7688_drvr + GENERIC ( + ChanelCount : INTEGER; + ncycle_cnv_high : INTEGER := 79; + ncycle_cnv : INTEGER := 500); + PORT ( + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + sample : OUT Samples(ChanelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC); + END COMPONENT; + COMPONENT RHF1401_drvr IS GENERIC( ChanelCount : INTEGER := 8); @@ -108,6 +123,23 @@ PACKAGE lpp_ad_conv IS sample_val : OUT STD_LOGIC); END COMPONENT; + + COMPONENT AD7688_drvr_sync + GENERIC ( + ChanelCount : INTEGER; + ncycle_cnv_high : INTEGER; + ncycle_cnv : INTEGER); + PORT ( + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + sample : OUT Samples(ChanelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC); + END COMPONENT; + COMPONENT TestModule_RHF1401 GENERIC ( freq : INTEGER; @@ -119,51 +151,30 @@ PACKAGE lpp_ad_conv IS ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)); END COMPONENT; - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - - COMPONENT ADS7886_drvr - GENERIC ( - ChanelCount : INTEGER; - ncycle_cnv_high : INTEGER := 79; - ncycle_cnv : INTEGER := 500); - PORT ( - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - sample : OUT Samples(ChanelCount-1 DOWNTO 0); - sample_val : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT AD7688_drvr IS - GENERIC(ChanelCount : INTEGER; - clkkHz : INTEGER); - PORT (clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - enable : IN STD_LOGIC; - smplClk : IN STD_LOGIC; - DataReady : OUT STD_LOGIC; - smpout : OUT Samples(ChanelCount-1 DOWNTO 0); - AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); - AD_out : OUT AD7688_out); - END COMPONENT; + --COMPONENT AD7688_drvr IS + -- GENERIC(ChanelCount : INTEGER; + -- clkkHz : INTEGER); + -- PORT (clk : IN STD_LOGIC; + -- rstn : IN STD_LOGIC; + -- enable : IN STD_LOGIC; + -- smplClk : IN STD_LOGIC; + -- DataReady : OUT STD_LOGIC; + -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); + -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); + -- AD_out : OUT AD7688_out); + --END COMPONENT; - COMPONENT AD7688_spi_if IS - GENERIC(ChanelCount : INTEGER); - PORT(clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - cnv : IN STD_LOGIC; - DataReady : OUT STD_LOGIC; - sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); - smpout : OUT Samples(ChanelCount-1 DOWNTO 0) - ); - END COMPONENT; + --COMPONENT AD7688_spi_if IS + -- GENERIC(ChanelCount : INTEGER); + -- PORT(clk : IN STD_LOGIC; + -- reset : IN STD_LOGIC; + -- cnv : IN STD_LOGIC; + -- DataReady : OUT STD_LOGIC; + -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); + -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0) + -- ); + --END COMPONENT; --COMPONENT lpp_apb_ad_conv @@ -217,74 +228,117 @@ PACKAGE lpp_ad_conv IS --======================= ADS 127X =========================| --===========================================================| -Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic; -constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010"; -constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101"; + TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC; + CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010"; + CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101"; -Type ADS127X_MODE_Type is array(1 downto 0) of std_logic; -constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10"; -constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11"; -constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01"; + TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC; + CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10"; + CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11"; + CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01"; -Type ADS127X_config is - record - SYNC : std_logic; - CLKDIV : std_logic; - FORMAT : ADS127X_FORMAT_Type; - MODE : ADS127X_MODE_Type; -end record; + TYPE ADS127X_config IS + RECORD + SYNC : STD_LOGIC; + CLKDIV : STD_LOGIC; + FORMAT : ADS127X_FORMAT_Type; + MODE : ADS127X_MODE_Type; + END RECORD; -COMPONENT ADS1274_DRIVER is -generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); -port( - Clk : in std_logic; - reset : in std_logic; - SpiClk : out std_logic; - DIN : in std_logic_vector(3 downto 0); - Ready : in std_logic; - Format : out std_logic_vector(2 downto 0); - Mode : out std_logic_vector(1 downto 0); - ClkDiv : out std_logic; - PWDOWN : out std_logic_vector(3 downto 0); - SmplClk : in std_logic; - OUT0 : out std_logic_vector(23 downto 0); - OUT1 : out std_logic_vector(23 downto 0); - OUT2 : out std_logic_vector(23 downto 0); - OUT3 : out std_logic_vector(23 downto 0); - FSynch : out std_logic; - test : out std_logic -); -end COMPONENT; + COMPONENT ADS1274_DRIVER IS + GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); + PORT( + Clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + SpiClk : OUT STD_LOGIC; + DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + Ready : IN STD_LOGIC; + Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ClkDiv : OUT STD_LOGIC; + PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SmplClk : IN STD_LOGIC; + OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + FSynch : OUT STD_LOGIC; + test : OUT STD_LOGIC + ); + END COMPONENT; -- todo clean file -COMPONENT DUAL_ADS1278_DRIVER is -port( - Clk : in std_logic; - reset : in std_logic; - SpiClk : out std_logic; - DIN : in std_logic_vector(1 downto 0); - SmplClk : in std_logic; - OUT00 : out std_logic_vector(23 downto 0); - OUT01 : out std_logic_vector(23 downto 0); - OUT02 : out std_logic_vector(23 downto 0); - OUT03 : out std_logic_vector(23 downto 0); - OUT04 : out std_logic_vector(23 downto 0); - OUT05 : out std_logic_vector(23 downto 0); - OUT06 : out std_logic_vector(23 downto 0); - OUT07 : out std_logic_vector(23 downto 0); - OUT10 : out std_logic_vector(23 downto 0); - OUT11 : out std_logic_vector(23 downto 0); - OUT12 : out std_logic_vector(23 downto 0); - OUT13 : out std_logic_vector(23 downto 0); - OUT14 : out std_logic_vector(23 downto 0); - OUT15 : out std_logic_vector(23 downto 0); - OUT16 : out std_logic_vector(23 downto 0); - OUT17 : out std_logic_vector(23 downto 0); - FSynch : out std_logic -); -end COMPONENT; + COMPONENT DUAL_ADS1278_DRIVER IS + PORT( + Clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + SpiClk : OUT STD_LOGIC; + DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + SmplClk : IN STD_LOGIC; + OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + FSynch : OUT STD_LOGIC + ); + END COMPONENT; +--===========================================================| +-- DRIVER ADS7886 +--===========================================================| +COMPONENT top_ad_conv_ADS7886_v2 IS + GENERIC( + ChannelCount : INTEGER := 8; + SampleNbBits : INTEGER := 14; + ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles + ncycle_cnv : INTEGER := 500); + PORT ( + -- CONV + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + -- DATA + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); + -- SAMPLE + sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END COMPONENT; +COMPONENT ADS7886_drvr_v2 IS + GENERIC( + ChannelCount : INTEGER := 8; + NbBitsSamples : INTEGER := 16); + PORT ( + -- CONV -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + -- DATA -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); + -- SAMPLE -- + sample : OUT Samples(ChannelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END COMPONENT; + END lpp_ad_conv; diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd @@ -0,0 +1,136 @@ + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.general_purpose.SYNC_FF; + +ENTITY top_ad_conv_ADS7886_v2 IS + GENERIC( + ChannelCount : INTEGER := 8; + SampleNbBits : INTEGER := 14; + ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles + ncycle_cnv : INTEGER := 500); + PORT ( + -- CONV + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + -- DATA + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); + -- SAMPLE + sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END top_ad_conv_ADS7886_v2; + +ARCHITECTURE ar_top_ad_conv_ADS7886_v2 OF top_ad_conv_ADS7886_v2 IS + + SIGNAL cnv_cycle_counter : INTEGER; + SIGNAL cnv_s : STD_LOGIC; + SIGNAL cnv_sync : STD_LOGIC; + SIGNAL cnv_sync_not : STD_LOGIC; + + SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0); + SIGNAL sample_val_adc : STD_LOGIC; + +BEGIN + + + ----------------------------------------------------------------------------- + -- CONV + ----------------------------------------------------------------------------- + PROCESS (cnv_clk, cnv_rstn) + BEGIN -- PROCESS + IF cnv_rstn = '0' THEN -- asynchronous reset (active low) + cnv_cycle_counter <= 0; + cnv_s <= '0'; + ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge +-- IF cnv_run = '1' THEN + IF cnv_cycle_counter < ncycle_cnv THEN + cnv_cycle_counter <= cnv_cycle_counter +1; + IF cnv_cycle_counter < ncycle_cnv_high THEN + cnv_s <= '1'; + ELSE + cnv_s <= '0'; + END IF; + ELSE + cnv_s <= '1'; + cnv_cycle_counter <= 0; + END IF; + --ELSE + -- cnv_s <= '0'; + -- cnv_cycle_counter <= 0; + --END IF; + END IF; + END PROCESS; + + cnv <= not(cnv_s); + + ----------------------------------------------------------------------------- + -- SYNC CNV + ----------------------------------------------------------------------------- + + SYNC_FF_cnv : SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + A => cnv_s, -- the data fetching begins immediately + A_sync => cnv_sync); + + ----------------------------------------------------------------------------- + +cnv_sync_not <= not(cnv_sync); + + ADS7886_drvr_v2_1 : ADS7886_drvr_v2 + GENERIC MAP( + ChannelCount => 8, + NbBitsSamples => 16) + PORT MAP( + -- CONV -- + cnv_clk => cnv_sync_not, + cnv_rstn => rstn, + -- DATA -- + clk => clk, -- master clock, 25 MHz + rstn => rstn, + sck => sck, + sdo => sdo, + -- SAMPLE -- + sample => sample_adc, + sample_val => sample_val_adc); + +PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + FOR k IN 0 TO ChannelCount-1 LOOP + sample(k)(13 downto 0) <= (OTHERS => '0'); + END LOOP; + sample_val <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_val_adc ='1' THEN + FOR k IN 0 TO ChannelCount-1 LOOP + IF ( unsigned(sample_adc(k)(11 downto 0)) >= 2048) THEN + sample(k)(13 downto 0) <= "00" & + std_logic_vector( unsigned(sample_adc(k)(11 downto 0)) - 2048 ); + ELSE + sample(k)(13 downto 0) <= "11" & + std_logic_vector( unsigned(sample_adc(k)(11 downto 0)) - 2048 ); + END IF; + END LOOP; +-- FOR k IN 0 TO ChannelCount-1 LOOP +-- sample(k) <= sample_adc(k)(13 downto 0); +-- END LOOP; + sample_val <= sample_val_adc; + ELSE + sample_val <= '0'; + END IF; + END IF; +END PROCESS; + +END ar_top_ad_conv_ADS7886_v2; \ No newline at end of file diff --git a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt --- a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt +++ b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt @@ -1,4 +1,10 @@ lpp_ad_Conv.vhd +AD7688_drvr.vhd +AD7688_drvr_sync.vhd +WriteGen_ADC.vhd +TestModule_ADS7886.vhd RHF1401.vhd top_ad_conv_RHF1401.vhd TestModule_RHF1401.vhd +top_ad_conv_ADS7886_v2.vhd +ADS7886_drvr_v2.vhd diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd b/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd @@ -0,0 +1,658 @@ +--************************************************************************ +--** MODEL : async_1Mx16.vhd ** +--** COMPANY : Cypress Semiconductor ** +--** REVISION: 1.0 Created new base model ** +--************************************************************************ + +-------------------------------------------------------------------------------JC\/ +--Library ieee,work; +LIBRARY ieee; +-------------------------------------------------------------------------------JC/\ +USE IEEE.Std_Logic_1164.ALL; +USE IEEE.Std_Logic_unsigned.ALL; + +-------------------------------------------------------------------------------JC\/ +--use work.package_timing.all; +--use work.package_utility.all; +LIBRARY lpp; +USE lpp.package_timing.ALL; +USE lpp.package_utility.ALL; +-------------------------------------------------------------------------------JC/\ + +------------------------ +-- Entity Description +------------------------ + +ENTITY CY7C1061DV33 IS + GENERIC + (ADDR_BITS : INTEGER := 20; + DATA_BITS : INTEGER := 16; + depth : INTEGER := 1048576; + + TimingInfo : BOOLEAN := true; + TimingChecks : STD_LOGIC := '1' + ); + PORT ( + CE1_b : IN STD_LOGIC; -- Chip Enable CE1# + CE2 : IN STD_LOGIC; -- Chip Enable CE2 + WE_b : IN STD_LOGIC; -- Write Enable WE# + OE_b : IN STD_LOGIC; -- Output Enable OE# + BHE_b : IN STD_LOGIC; -- Byte Enable High BHE# + BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE# + A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A + DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO; + ); +END CY7C1061DV33; + +----------------------------- +-- End Entity Description +----------------------------- +----------------------------- +-- Architecture Description +----------------------------- + +ARCHITECTURE behave_arch OF CY7C1061DV33 IS + + TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); + + SIGNAL write_enable : STD_LOGIC; + SIGNAL read_enable : STD_LOGIC; + SIGNAL byte_enable : STD_LOGIC; + SIGNAL CE_b : STD_LOGIC; + + SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); + + SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); + + CONSTANT tSD_dataskew : TIME := tSD - 1 ns; + CONSTANT tskew : TIME := 1 ns; + + -------------------------------------------------------------------------------JC\/ + TYPE mem_array_type_t IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); + SIGNAL mem_array_t : mem_array_type_t; + -------------------------------------------------------------------------------JC/\ + + + +BEGIN + CE_b <= CE1_b OR NOT(CE2); + byte_enable <= NOT(BHE_b AND BLE_b); + write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b); + read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b); + + data_skew <= DQ AFTER 1 ns; -- changed on feb 15 + address_skew <= A AFTER 1 ns; + + PROCESS (OE_b) + BEGIN + IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN + DQ <= (OTHERS => 'Z') after tHZOE; + END IF; + END PROCESS; + + PROCESS (CE_b) + BEGIN + IF (CE_b'EVENT AND CE_b = '1') THEN + DQ <= (OTHERS => 'Z') after tHZCE; + END IF; + END PROCESS; + + PROCESS (write_enable'DELAYED(tHA)) + BEGIN + IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN + ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA) + REPORT "Address hold time tHA violated"; + END IF; + END PROCESS; + + PROCESS (write_enable'DELAYED(tHD)) + BEGIN + IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN + ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns) + REPORT "Data hold time tHD violated"; + END IF; + END PROCESS; + +-- main process + PROCESS + + VARIABLE mem_array : mem_array_type; + +--- Variables for timing checks + VARIABLE tPWE_chk : TIME := -10 ns; + VARIABLE tAW_chk : TIME := -10 ns; + VARIABLE tSD_chk : TIME := -10 ns; + VARIABLE tRC_chk : TIME := 0 ns; + VARIABLE tBAW_chk : TIME := 0 ns; + VARIABLE tBBW_chk : TIME := 0 ns; + VARIABLE tBCW_chk : TIME := 0 ns; + VARIABLE tBDW_chk : TIME := 0 ns; + VARIABLE tSA_chk : TIME := 0 ns; + VARIABLE tSA_skew : TIME := 0 ns; + VARIABLE tAint_chk : TIME := -10 ns; + + VARIABLE write_flag : BOOLEAN := true; + + VARIABLE accesstime : TIME := 0 ns; + + BEGIN + IF (address_skew'EVENT) THEN + tSA_skew := NOW; + END IF; + + -- start of write + IF (write_enable = '1' AND write_enable'EVENT) THEN + + DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE; + + IF (A'LAST_EVENT >= tSA) THEN + address_internal <= A; + tPWE_chk := NOW; + tAW_chk := A'LAST_EVENT; + tAint_chk := NOW; + write_flag := true; + + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Address setup violated"; + END IF; + write_flag := false; + + END IF; + + -- end of write (with CE high or WE high) + ELSIF (write_enable = '0' AND write_enable'EVENT) THEN + + --- check for pulse width + IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN + --- pulse width OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Pulse Width violation"; + END IF; + + write_flag := false; + END IF; + + + IF (NOW > 0 ns) THEN + IF (tSA_skew - tAint_chk > tskew) THEN + ASSERT false + REPORT "Negative address setup"; + write_flag := false; + END IF; + END IF; + + --- check for address setup with write end, i.e., tAW + IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN + --- tAW OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Address setup tAW violation"; + END IF; + + write_flag := false; + END IF; + + --- check for data setup with write end, i.e., tSD + IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN + --- tSD OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Data setup tSD violation"; + END IF; + write_flag := false; + END IF; + + -- perform write operation if no violations + IF (write_flag = true) THEN + + IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN + mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); + END IF; + + IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN + mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); + END IF; + + IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN + mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); + ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN + ASSERT false REPORT "Insufficient pulse width for lower byte to be written"; + END IF; + + IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN + mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); + ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN + ASSERT false REPORT "Insufficient pulse width for higher byte to be written"; + END IF; + + + -------------------------------------------------------------------------------JC\/ + all_mem_array_obs: FOR I IN 0 TO 127 LOOP + IF I < depth THEN + mem_array_t(I) <= mem_array(I); + END IF; + END LOOP all_mem_array_obs; + -------------------------------------------------------------------------------JC/\ + + END IF; + + -- end of write (with BLE high) + ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN + + IF (BLE_b = '0') THEN + + --- Reset timing variables + tAW_chk := A'LAST_EVENT; + tBAW_chk := NOW; + write_flag := true; + + ELSIF (BLE_b = '1') THEN + + --- check for pulse width + IF (NOW - tPWE_chk >= tPWE) THEN + --- tPWE OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Pulse Width violation"; + END IF; + + write_flag := false; + END IF; + + --- check for address setup with write end, i.e., tAW + IF (NOW - tAW_chk >= tAW) THEN + --- tAW OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Address setup tAW violation for Lower Byte Write"; + END IF; + + write_flag := false; + END IF; + + --- check for byte write setup with write end, i.e., tBW + IF (NOW - tBAW_chk >= tBW) THEN + --- tBW OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Lower Byte setup tBW violation"; + END IF; + + write_flag := false; + END IF; + + --- check for data setup with write end, i.e., tSD + IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN + --- tSD OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Data setup tSD violation for Lower Byte Write"; + END IF; + + write_flag := false; + END IF; + + --- perform WRITE operation if no violations + IF (write_flag = true) THEN + mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); + IF (BHE_b = '0') THEN + mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); + END IF; + END IF; + + --- Reset timing variables + tAW_chk := A'LAST_EVENT; + tBAW_chk := NOW; + write_flag := true; + + END IF; + + -- end of write (with BHE high) + ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN + + IF (BHE_b = '0') THEN + + --- Reset timing variables + tAW_chk := A'LAST_EVENT; + tBBW_chk := NOW; + write_flag := true; + + ELSIF (BHE_b = '1') THEN + + --- check for pulse width + IF (NOW - tPWE_chk >= tPWE) THEN + --- tPWE OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Pulse Width violation"; + END IF; + + write_flag := false; + END IF; + + --- check for address setup with write end, i.e., tAW + IF (NOW - tAW_chk >= tAW) THEN + --- tAW OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Address setup tAW violation for Upper Byte Write"; + END IF; + write_flag := false; + END IF; + + --- check for byte setup with write end, i.e., tBW + IF (NOW - tBBW_chk >= tBW) THEN + --- tBW OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Upper Byte setup tBW violation"; + END IF; + + write_flag := false; + END IF; + + --- check for data setup with write end, i.e., tSD + IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN + --- tSD OK, do nothing + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Data setup tSD violation for Upper Byte Write"; + END IF; + + write_flag := false; + END IF; + + --- perform WRITE operation if no violations + + IF (write_flag = true) THEN + mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8); + IF (BLE_b = '0') THEN + mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0); + END IF; + + END IF; + + --- Reset timing variables + tAW_chk := A'LAST_EVENT; + tBBW_chk := NOW; + write_flag := true; + + END IF; + + END IF; + --- END OF WRITE + + IF (data_skew'EVENT AND read_enable /= '1') THEN + tSD_chk := NOW; + END IF; + + --- START of READ + + --- Tri-state the data bus if CE or OE disabled + IF (read_enable = '0' AND read_enable'EVENT) THEN + IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN + DQ <= (OTHERS => 'Z') after tHZCE; + ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN + DQ <= (OTHERS => 'Z') after tHZOE; + END IF; + END IF; + + --- Address-controlled READ operation + IF (A'EVENT) THEN + IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN + DQ <= (OTHERS => 'Z') after tHZCE; + END IF; + + IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN + --- tRC OK, do nothing + ELSE + + IF (TimingInfo) THEN + ASSERT false + REPORT "Read Cycle time tRC violation"; + END IF; + + END IF; + + IF (read_enable = '1') THEN + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA; + END IF; + + tRC_chk := NOW; + + END IF; + + IF (write_enable = '1') THEN + --- do nothing + END IF; + + END IF; + + IF (read_enable = '0' AND read_enable'EVENT) THEN + DQ <= (OTHERS => 'Z') after tHZCE; + IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN + --- tRC_chk needs to be reset when read ends + tRC_CHK := 0 ns; + ELSE + IF (TimingInfo) THEN + ASSERT false + REPORT "Read Cycle time tRC violation"; + END IF; + tRC_CHK := 0 ns; + END IF; + + END IF; + + --- READ operation triggered by CE/OE/BHE/BLE + IF (read_enable = '1' AND read_enable'EVENT) THEN + + tRC_chk := NOW; + + --- CE triggered READ + IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2 + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; + END IF; + + END IF; + + + --- OE triggered READ + IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN + + -- if address or CE changes before OE such that tAA/tACE > tDOE + IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN + + IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN + + accesstime := tAA-A'LAST_EVENT; + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + + ELSE + accesstime := tACE-CE_b'LAST_EVENT; + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + END IF; + + -- if address changes before OE such that tAA > tDOE + ELSIF (A'LAST_EVENT < tAA - tDOE) THEN + + accesstime := tAA-A'LAST_EVENT; + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + + -- if CE changes before OE such that tACE > tDOE + ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN + + accesstime := tACE-CE_b'LAST_EVENT; + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + + -- if OE changes such that tDOE > tAA/tACE + ELSE + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE; + END IF; + + END IF; + + END IF; + --- END of OE triggered READ + + --- BLE/BHE triggered READ + IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN + + -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE + IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN + + IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN + accesstime := tAA-A'LAST_EVENT; + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + + ELSE + accesstime := tACE-CE_b'LAST_EVENT; + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + END IF; + + -- if address changes before BHE/BLE such that tAA > tDBE + ELSIF (A'LAST_EVENT < tAA - tDBE) THEN + accesstime := tAA-A'LAST_EVENT; + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + + -- if CE changes before BHE/BLE such that tACE > tDBE + ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN + accesstime := tACE-CE_b'LAST_EVENT; + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime; + END IF; + + -- if BHE/BLE changes such that tDBE > tAA/tACE + ELSE + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; + END IF; + + END IF; + + END IF; + -- END of BHE/BLE controlled READ + + IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN + + IF (BLE_b = '0') THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE; + END IF; + + IF (BHE_b = '0') THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE; + END IF; + + END IF; + + END IF; + --- END OF CE/OE/BHE/BLE controlled READ + + --- If either BHE or BLE toggle during read mode + IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN + DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE; + END IF; + + IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN + DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE; + END IF; + + --- tri-state bus depending on BHE/BLE + IF (BLE_b'EVENT AND BLE_b = '1') THEN + DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE; + END IF; + + IF (BHE_b'EVENT AND BHE_b = '1') THEN + DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE; + END IF; + + WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew; + + END PROCESS; + + +END behave_arch; diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/async_1Mx16.vhd b/lib/lpp/lpp_sim/CY7C1061DV33/async_1Mx16.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/CY7C1061DV33/async_1Mx16.vhd @@ -0,0 +1,640 @@ +--************************************************************************ +--** MODEL : async_1Mx16.vhd ** +--** COMPANY : Cypress Semiconductor ** +--** REVISION: 1.0 Created new base model ** +--************************************************************************ + +-------------------------------------------------------------------------------JC\/ +--Library ieee,work; +Library ieee; +-------------------------------------------------------------------------------JC/\ +Use IEEE.Std_Logic_1164.All; +use IEEE.Std_Logic_unsigned.All; + +-------------------------------------------------------------------------------JC\/ +--use work.package_timing.all; +--use work.package_utility.all; +Library lpp; +use lpp.package_timing.all; +use lpp.package_utility.all; +-------------------------------------------------------------------------------JC/\ + +------------------------ +-- Entity Description +------------------------ + +Entity CY7C1061DV33 is +generic + (ADDR_BITS : integer := 20; + DATA_BITS : integer := 16; + depth : integer := 1048576; + + TimingInfo : BOOLEAN := TRUE; + TimingChecks : std_logic := '1' + ); +Port ( + CE1_b : IN Std_Logic; -- Chip Enable CE1# + CE2 : IN Std_Logic; -- Chip Enable CE2 + WE_b : IN Std_Logic; -- Write Enable WE# + OE_b : IN Std_Logic; -- Output Enable OE# + BHE_b : IN std_logic; -- Byte Enable High BHE# + BLE_b : IN std_logic; -- Byte Enable Low BLE# + A : IN Std_Logic_Vector(addr_bits-1 downto 0); -- Address Inputs A + DQ : INOUT Std_Logic_Vector(DATA_BITS-1 downto 0):=(others=>'Z') -- Read/Write Data IO + ); +End CY7C1061DV33; + +----------------------------- +-- End Entity Description +----------------------------- +----------------------------- +-- Architecture Description +----------------------------- + +Architecture behave_arch Of CY7C1061DV33 Is + +Type mem_array_type Is array (depth-1 downto 0) of std_logic_vector(DATA_BITS-1 downto 0); + +signal write_enable : std_logic; +signal read_enable : std_logic; +signal byte_enable : std_logic; +signal CE_b :std_logic; + +signal data_skew : Std_Logic_Vector(DATA_BITS-1 downto 0); + +signal address_internal,address_skew: Std_Logic_Vector(addr_bits-1 downto 0); + +constant tSD_dataskew : time := tSD - 1 ns; +constant tskew :time := 1 ns; + +begin +CE_b <= CE1_b or not(CE2); +byte_enable <= not(BHE_b and BLE_b); +write_enable <= not(CE1_b) and CE2 and not(WE_b) and not(BHE_b and BLE_b); +read_enable <= not(CE1_b) and CE2 and (WE_b) and not(OE_b) and not(BHE_b and BLE_b); + +data_skew <= DQ after 1 ns; -- changed on feb 15 +address_skew <= A after 1 ns; + +process (OE_b) +begin + if (OE_b'event and OE_b = '1' and write_enable /= '1') then + DQ <=(others=>'Z') after tHZOE; + end if; +end process; + +process (CE_b) +begin + if (CE_b'event and CE_b = '1') then + DQ <=(others=>'Z') after tHZCE; + end if; +end process; + +process (write_enable'delayed(tHA)) +begin + if (write_enable'delayed(tHA) = '0' and TimingInfo) then + assert (A'last_event = 0 ns) or (A'last_event > tHA) + report "Address hold time tHA violated"; + end if; +end process; + +process (write_enable'delayed(tHD)) +begin + if (write_enable'delayed(tHD) = '0' and TimingInfo) then + assert (DQ'last_event > tHD) or (DQ'last_event = 0 ns) + report "Data hold time tHD violated"; + end if; +end process; + +-- main process +process + +VARIABLE mem_array: mem_array_type; + +--- Variables for timing checks +VARIABLE tPWE_chk : TIME := -10 ns; +VARIABLE tAW_chk : TIME := -10 ns; +VARIABLE tSD_chk : TIME := -10 ns; +VARIABLE tRC_chk : TIME := 0 ns; +VARIABLE tBAW_chk : TIME := 0 ns; +VARIABLE tBBW_chk : TIME := 0 ns; +VARIABLE tBCW_chk : TIME := 0 ns; +VARIABLE tBDW_chk : TIME := 0 ns; +VARIABLE tSA_chk : TIME := 0 ns; +VARIABLE tSA_skew : TIME := 0 ns; +VARIABLE tAint_chk : TIME := -10 ns; + +VARIABLE write_flag : BOOLEAN := TRUE; + +VARIABLE accesstime : TIME := 0 ns; + +begin + if (address_skew'event) then + tSA_skew := NOW; + end if; + + -- start of write + if (write_enable = '1' and write_enable'event) then + + DQ(DATA_BITS-1 downto 0)<=(others=>'Z') after tHZWE; + + if (A'last_event >= tSA) then + address_internal <= A; + tPWE_chk := NOW; + tAW_chk := A'last_event; + tAint_chk := NOW; + write_flag := TRUE; + + else + if (TimingInfo) then + assert FALSE + report "Address setup violated"; + end if; + write_flag := FALSE; + + end if; + + -- end of write (with CE high or WE high) + elsif (write_enable = '0' and write_enable'event) then + + --- check for pulse width + if (NOW - tPWE_chk >= tPWE or NOW - tPWE_chk <= 0.1 ns or NOW = 0 ns) then + --- pulse width OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Pulse Width violation"; + end if; + + write_flag := FALSE; + end if; + + + if (NOW > 0 ns) then + if (tSA_skew - tAint_chk > tskew ) then + assert FALSE + report "Negative address setup"; + write_flag := FALSE; + end if; + end if; + + --- check for address setup with write end, i.e., tAW + if (NOW - tAW_chk >= tAW or NOW = 0 ns) then + --- tAW OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Address setup tAW violation"; + end if; + + write_flag := FALSE; + end if; + + --- check for data setup with write end, i.e., tSD + if (NOW - tSD_chk >= tSD_dataskew or NOW - tSD_chk <= 0.1 ns or NOW = 0 ns) then + --- tSD OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Data setup tSD violation"; + end if; + write_flag := FALSE; + end if; + + -- perform write operation if no violations + if (write_flag = TRUE) then + + if (BLE_b = '1' and BLE_b'last_event = write_enable'last_event and NOW /= 0 ns) then + mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0); + end if; + + if (BHE_b = '1' and BHE_b'last_event = write_enable'last_event and NOW /= 0 ns) then + mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8); + end if; + + if (BLE_b = '0' and NOW - tBAW_chk >= tBW) then + mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0); + elsif (NOW - tBAW_chk < tBW and NOW - tBAW_chk > 0.1 ns and NOW > 0 ns) then + assert FALSE report "Insufficient pulse width for lower byte to be written"; + end if; + + if (BHE_b = '0' and NOW - tBBW_chk >= tBW) then + mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8); + elsif (NOW - tBBW_chk < tBW and NOW - tBBW_chk > 0.1 ns and NOW > 0 ns) then + assert FALSE report "Insufficient pulse width for higher byte to be written"; + end if; + + end if; + + -- end of write (with BLE high) + elsif (BLE_b'event and not(BHE_b'event) and write_enable = '1') then + + if (BLE_b = '0') then + + --- Reset timing variables + tAW_chk := A'last_event; + tBAW_chk := NOW; + write_flag := TRUE; + + elsif (BLE_b = '1') then + + --- check for pulse width + if (NOW - tPWE_chk >= tPWE) then + --- tPWE OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Pulse Width violation"; + end if; + + write_flag := FALSE; + end if; + + --- check for address setup with write end, i.e., tAW + if (NOW - tAW_chk >= tAW) then + --- tAW OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Address setup tAW violation for Lower Byte Write"; + end if; + + write_flag := FALSE; + end if; + + --- check for byte write setup with write end, i.e., tBW + if (NOW - tBAW_chk >= tBW) then + --- tBW OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Lower Byte setup tBW violation"; + end if; + + write_flag := FALSE; + end if; + + --- check for data setup with write end, i.e., tSD + if (NOW - tSD_chk >= tSD_dataskew or NOW - tSD_chk <= 0.1 ns or NOW = 0 ns) then + --- tSD OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Data setup tSD violation for Lower Byte Write"; + end if; + + write_flag := FALSE; + end if; + + --- perform WRITE operation if no violations + if (write_flag = TRUE) then + mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0); + if (BHE_b = '0') then + mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8); + end if; + end if; + + --- Reset timing variables + tAW_chk := A'last_event; + tBAW_chk := NOW; + write_flag := TRUE; + + end if; + + -- end of write (with BHE high) + elsif (BHE_b'event and not(BLE_b'event) and write_enable = '1') then + + if (BHE_b = '0') then + + --- Reset timing variables + tAW_chk := A'last_event; + tBBW_chk := NOW; + write_flag := TRUE; + + elsif (BHE_b = '1') then + + --- check for pulse width + if (NOW - tPWE_chk >= tPWE) then + --- tPWE OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Pulse Width violation"; + end if; + + write_flag := FALSE; + end if; + + --- check for address setup with write end, i.e., tAW + if (NOW - tAW_chk >= tAW) then + --- tAW OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Address setup tAW violation for Upper Byte Write"; + end if; + write_flag := FALSE; + end if; + + --- check for byte setup with write end, i.e., tBW + if (NOW - tBBW_chk >= tBW) then + --- tBW OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Upper Byte setup tBW violation"; + end if; + + write_flag := FALSE; + end if; + + --- check for data setup with write end, i.e., tSD + if (NOW - tSD_chk >= tSD_dataskew or NOW - tSD_chk <= 0.1 ns or NOW = 0 ns) then + --- tSD OK, do nothing + else + if (TimingInfo) then + assert FALSE + report "Data setup tSD violation for Upper Byte Write"; + end if; + + write_flag := FALSE; + end if; + + --- perform WRITE operation if no violations + + if (write_flag = TRUE) then + mem_array(conv_integer1(address_internal))(15 downto 8) := data_skew(15 downto 8); + if (BLE_b = '0') then + mem_array(conv_integer1(address_internal))(7 downto 0) := data_skew(7 downto 0); + end if; + + end if; + + --- Reset timing variables + tAW_chk := A'last_event; + tBBW_chk := NOW; + write_flag := TRUE; + + end if; + + end if; + --- END OF WRITE + + if (data_skew'event and read_enable /= '1') then + tSD_chk := NOW; + end if; + + --- START of READ + + --- Tri-state the data bus if CE or OE disabled + if (read_enable = '0' and read_enable'event) then + if (OE_b'last_event >= CE_b'last_event) then + DQ <=(others=>'Z') after tHZCE; + elsif (CE_b'last_event > OE_b'last_event) then + DQ <=(others=>'Z') after tHZOE; + end if; + end if; + + --- Address-controlled READ operation + if (A'event) then + if (A'last_event = CE_b'last_event and CE_b = '1') then + DQ <=(others=>'Z') after tHZCE; + end if; + + if (NOW - tRC_chk >= tRC or NOW - tRC_chk <= 0.1 ns or tRC_chk = 0 ns) then + --- tRC OK, do nothing + else + + if (TimingInfo) then + assert FALSE + report "Read Cycle time tRC violation"; + end if; + + end if; + + if (read_enable = '1') then + + if (BLE_b = '0') then + DQ (7 downto 0) <= mem_array (conv_integer1(A))(7 downto 0) after tAA; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8) <= mem_array (conv_integer1(A))(15 downto 8) after tAA; + end if; + + tRC_chk := NOW; + + end if; + + if (write_enable = '1') then + --- do nothing + end if; + + end if; + + if (read_enable = '0' and read_enable'event) then + DQ <=(others=>'Z') after tHZCE; + if (NOW - tRC_chk >= tRC or tRC_chk = 0 ns or A'last_event = read_enable'last_event) then + --- tRC_chk needs to be reset when read ends + tRC_CHK := 0 ns; + else + if (TimingInfo) then + assert FALSE + report "Read Cycle time tRC violation"; + end if; + tRC_CHK := 0 ns; + end if; + + end if; + + --- READ operation triggered by CE/OE/BHE/BLE + if (read_enable = '1' and read_enable'event) then + + tRC_chk := NOW; + + --- CE triggered READ + if (CE_b'last_event = read_enable'last_event ) then -- changed rev2 + + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tACE; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tACE; + end if; + + end if; + + + --- OE triggered READ + if (OE_b'last_event = read_enable'last_event) then + + -- if address or CE changes before OE such that tAA/tACE > tDOE + if (CE_b'last_event < tACE - tDOE and A'last_event < tAA - tDOE) then + + if (A'last_event < CE_b'last_event) then + + accesstime:=tAA-A'last_event; + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + + else + accesstime:=tACE-CE_b'last_event; + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + end if; + + -- if address changes before OE such that tAA > tDOE + elsif (A'last_event < tAA - tDOE) then + + accesstime:=tAA-A'last_event; + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + + -- if CE changes before OE such that tACE > tDOE + elsif (CE_b'last_event < tACE - tDOE) then + + accesstime:=tACE-CE_b'last_event; + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + + -- if OE changes such that tDOE > tAA/tACE + else + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tDOE; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tDOE; + end if; + + end if; + + end if; + --- END of OE triggered READ + + --- BLE/BHE triggered READ + if (BLE_b'last_event = read_enable'last_event or BHE_b'last_event = read_enable'last_event) then + + -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE + if (CE_b'last_event < tACE - tDBE and A'last_event < tAA - tDBE) then + + if (A'last_event < BLE_b'last_event) then + accesstime:=tAA-A'last_event; + + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + + else + accesstime:=tACE-CE_b'last_event; + + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + end if; + + -- if address changes before BHE/BLE such that tAA > tDBE + elsif (A'last_event < tAA - tDBE) then + accesstime:=tAA-A'last_event; + + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + + -- if CE changes before BHE/BLE such that tACE > tDBE + elsif (CE_b'last_event < tACE - tDBE) then + accesstime:=tACE-CE_b'last_event; + + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after accesstime; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after accesstime; + end if; + + -- if BHE/BLE changes such that tDBE > tAA/tACE + else + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tDBE; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tDBE; + end if; + + end if; + + end if; + -- END of BHE/BLE controlled READ + + if (WE_b'last_event = read_enable'last_event) then + + if (BLE_b = '0') then + DQ (7 downto 0)<= mem_array (conv_integer1(A)) (7 downto 0) after tACE; + end if; + + if (BHE_b = '0') then + DQ (15 downto 8)<= mem_array (conv_integer1(A)) (15 downto 8) after tACE; + end if; + + end if; + + end if; + --- END OF CE/OE/BHE/BLE controlled READ + + --- If either BHE or BLE toggle during read mode + if (BLE_b'event and BLE_b = '0' and read_enable = '1' and not(read_enable'event)) then + DQ (7 downto 0) <= mem_array (conv_integer1(A)) (7 downto 0) after tDBE; + end if; + + if (BHE_b'event and BHE_b = '0' and read_enable = '1' and not(read_enable'event)) then + DQ (15 downto 8) <= mem_array (conv_integer1(A)) (15 downto 8) after tDBE; + end if; + + --- tri-state bus depending on BHE/BLE + if (BLE_b'event and BLE_b = '1') then + DQ (7 downto 0) <= (others=>'Z') after tHZBE; + end if; + + if (BHE_b'event and BHE_b = '1') then + DQ (15 downto 8) <=(others=>'Z') after tHZBE; + end if; + + wait on write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew,address_skew; + +end process; +end behave_arch; diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd b/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/CY7C1061DV33/package_timing.vhd @@ -0,0 +1,75 @@ +--************************************************************************ +--** MODEL : package_timing.vhd ** +--** COMPANY : Cypress Semiconductor ** +--** REVISION: 1.0 (Created new timing package model) ** +--************************************************************************ + + +library IEEE,std; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; +use IEEE.std_logic_unsigned.all; +use ieee.std_logic_textio.all ; +use std.textio.all ; + +--**************************************************************** + +package package_timing is + +------------------------------------------------------------------------------------------------ +-- Read Cycle timing +------------------------------------------------------------------------------------------------ +constant tRC : TIME := 10 ns; -- Read Cycle Time +constant tAA : TIME := 10 ns; -- Address to Data Valid +constant tOHA : TIME := 3 ns; -- Data Hold from Address Change +constant tACE : TIME := 10 ns; -- Random access CEb Low to Data Valid +constant tDOE : TIME := 5 ns; -- OE Low to Data Valid +constant tLZOE : TIME := 1 ns; -- OE Low to LOW Z +constant tHZOE : TIME := 5 ns; -- OE High to HIGH Z +constant tLZCE : TIME := 3 ns; -- CEb LOW to LOW Z +constant tHZCE : TIME := 5 ns; -- CEb HIGH to HIGH Z + +constant tDBE : TIME := 5 ns; -- BHE/BLE LOW to Data Valid +constant tLZBE : TIME := 1 ns; -- BHE/BLE LOW to LOW Z +constant tHZBE : TIME := 5 ns; -- BHE/BLE HIGH to HIGH Z + +------------------------------------------------------------------------------------------------ +-- Write Cycle timing +------------------------------------------------------------------------------------------------ +constant tWC : TIME := 10 ns; -- Write Cycle Time +constant tSCE : TIME := 7 ns; -- CEb LOW to Write End + +constant tAW : TIME := 7 ns; -- Address Setup to Write End +constant tSA : TIME := 0 ns; -- Address Setup to Write Start +constant tHA : TIME := 0 ns; -- Address Hold from Write End + +constant tPWE : TIME := 7 ns; -- WEb pulse width + +constant tSD : TIME := 5.5 ns; -- Data Setup to Write End +constant tHD : TIME := 0 ns; -- Data Hold from Write End + +constant tBW : TIME := 7 ns; -- BHE BLE Setup to Write End + +constant tLZWE : TIME := 3 ns; -- WEb Low to High Z +constant tHZWE : TIME := 5 ns; -- WEb High to Low Z + +end package_timing; + +package body package_timing is + +end package_timing; + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsyn.txt b/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/CY7C1061DV33/vhdlsyn.txt @@ -0,0 +1,4 @@ +package_utility.vhd +package_timing.vhd +CY7C1061DV33_pkg.vhd +CY7C1061DV33.vhd