HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r180:b44cc8ef726a

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lib/lpp/dirs.txt +1 0

             ./amba_lcd_16x2_ctrlr
             ./general_purpose
             ./general_purpose/lpp_AMR
             ./general_purpose/lpp_balise
             ./general_purpose/lpp_delay
             ./lpp_amba
             ./dsp/iir_filter
             ./dsp/lpp_downsampling
             ./dsp/lpp_fft
             ./lfr_time_management
             ./lpp_ad_Conv
             ./lpp_bootloader
             ./lpp_cna
             ./lpp_demux
             ./lpp_matrix
             ./lpp_memory
             ./lpp_dma
             ./lpp_uart
             ./lpp_usb
             ./lpp_waveform
             ./lpp_top_lfr
+            ./lpp_Header

lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +1 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY RAM_CTRLR_v2 IS
               GENERIC(
                 tech       : INTEGER := 0;
                 Input_SZ_1 : INTEGER := 16;
                 Mem_use    : INTEGER := use_RAM
                 );
               PORT(
                 rstn : IN STD_LOGIC;
                 clk  : IN STD_LOGIC;
                 -- R/W Ctrl
                 ram_write : IN STD_LOGIC;
                 ram_read  : IN STD_LOGIC;
                 -- ADDR Ctrl
                 raddr_rst  : IN STD_LOGIC;
                 raddr_add1 : IN STD_LOGIC;
                 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 -- Data
                 sample_in  : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
                 );
             END RAM_CTRLR_v2;
             ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
               SIGNAL WD       : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
               SIGNAL RD       : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
               SIGNAL WEN, REN : STD_LOGIC;
               SIGNAL RADDR    : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL WADDR    : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL counter  : STD_LOGIC_VECTOR(7 DOWNTO 0);
             BEGIN
               sample_out                <= RD(Input_SZ_1-1 DOWNTO 0);
               WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
               -----------------------------------------------------------------------------
               -- RAM
               -----------------------------------------------------------------------------
               memCEL : IF Mem_use = use_CEL GENERATE
                 WEN <= NOT ram_write;
                 REN <= NOT ram_read;
+            --    RAMblk : RAM_CEL_N
                 RAMblk : RAM_CEL_N
                   GENERIC MAP(Input_SZ_1)
                   PORT MAP(
                     WD    => WD,
                     RD    => RD,
                     WEN   => WEN,
                     REN   => REN,
                     WADDR => WADDR,
                     RADDR => RADDR,
                     RWCLK => clk,
                     RESET => rstn
                     ) ;
               END GENERATE;
               memRAM : IF Mem_use = use_RAM GENERATE
                 SRAM : syncram_2p
                   GENERIC MAP(tech, 8, Input_SZ_1)
                   PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
               END GENERATE;
               -----------------------------------------------------------------------------
               -- RADDR
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   counter <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF raddr_rst = '1' THEN
                     counter <= (OTHERS => '0');
                   ELSIF raddr_add1 = '1' THEN
                     counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
                   END IF;
                 END IF;
               END PROCESS;
               RADDR <= counter;
               -----------------------------------------------------------------------------
               -- WADDR
               -----------------------------------------------------------------------------
               WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
                        STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
                        STD_LOGIC_VECTOR(UNSIGNED(counter));
             END ar_RAM_CTRLR_v2;

lib/lpp/dsp/lpp_fft/vhdlsyn.txt +1 -1

+            lpp_fft.vhd
             APB_FFT.vhd
             APB_FFT_half.vhd
             Driver_FFT.vhd
             FFT.vhd
             FFTamont.vhd
             FFTaval.vhd
             Flag_Extremum.vhd
             Linker_FFT.vhd
-            lpp_fft.vhd

lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +2 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_top_lfr_pkg IS
               COMPONENT lpp_top_acq
               GENERIC(
                 tech : INTEGER := 0
                 );
               PORT (
                 -- ADS7886
                 cnv_run         : IN  STD_LOGIC;
                 cnv             : OUT STD_LOGIC;
                 sck             : OUT STD_LOGIC;
                 sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 --
                 cnv_clk         : IN  STD_LOGIC;    -- 49 MHz
                 cnv_rstn        : IN  STD_LOGIC;
                 --
                 clk             : IN  STD_LOGIC;    -- 25 MHz
                 rstn            : IN  STD_LOGIC;
                 --
                 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f3_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
                 );
               END COMPONENT;
               COMPONENT lpp_top_apbreg
                 GENERIC (
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq                    : INTEGER);
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   apbi                                   : IN  apb_slv_in_type;
                   apbo                                   : OUT apb_slv_out_type;
                   ready_matrix_f0_0                      : IN  STD_LOGIC;
                   ready_matrix_f0_1                      : IN  STD_LOGIC;
                   ready_matrix_f1                        : IN  STD_LOGIC;
                   ready_matrix_f2                        : IN  STD_LOGIC;
                   error_anticipating_empty_fifo          : IN  STD_LOGIC;
                   error_bad_component_error              : IN  STD_LOGIC;
                   debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : OUT STD_LOGIC;
                   status_ready_matrix_f0_1               : OUT STD_LOGIC;
                   status_ready_matrix_f1                 : OUT STD_LOGIC;
                   status_ready_matrix_f2                 : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo   : OUT STD_LOGIC;
                   status_error_bad_component_error       : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err                         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW                        : OUT STD_LOGIC;
                   data_shaping_SP0                       : OUT STD_LOGIC;
                   data_shaping_SP1                       : OUT STD_LOGIC;
                   data_shaping_R0                        : OUT STD_LOGIC;
                   data_shaping_R1                        : OUT STD_LOGIC;
                   delta_snapshot                         : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                   delta_f2_f1                            : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                   delta_f2_f0                            : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                   nb_burst_available                     : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                   nb_snapshot_param                      : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0                              : OUT STD_LOGIC;
                   enable_f1                              : OUT STD_LOGIC;
                   enable_f2                              : OUT STD_LOGIC;
                   enable_f3                              : OUT STD_LOGIC;
                   burst_f0                               : OUT STD_LOGIC;
                   burst_f1                               : OUT STD_LOGIC;
                   burst_f2                               : OUT STD_LOGIC;
                   addr_data_f0                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_top_lfr_wf_picker
                 GENERIC (
                   hindex                  : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq                    : INTEGER;
                   tech                    : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER);
                 PORT (
                   cnv_run         : IN  STD_LOGIC;
                   cnv             : OUT STD_LOGIC;
                   sck             : OUT STD_LOGIC;
                   sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                   cnv_clk         : IN  STD_LOGIC;
                   cnv_rstn        : IN  STD_LOGIC;
                   HCLK            : IN  STD_ULOGIC;
                   HRESETn         : IN  STD_ULOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   AHB_Master_In   : IN  AHB_Mst_In_Type;
                   AHB_Master_Out  : OUT AHB_Mst_Out_Type;
                   coarse_time_0   : IN  STD_LOGIC;
                   data_shaping_BW : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_top_lfr_wf_picker_ip
                 GENERIC (
                   hindex                  : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
-                  tech                    : INTEGER);
+                  tech                    : INTEGER;
+                  Mem_use                 : INTEGER);
                 PORT (
                   cnv_run            : IN  STD_LOGIC;
                   cnv                : OUT STD_LOGIC;
                   sck                : OUT STD_LOGIC;
                   sdo                : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                   cnv_clk            : IN  STD_LOGIC;
                   cnv_rstn           : IN  STD_LOGIC;
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   sample_f0_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f0_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f1_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f2_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f3_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   AHB_Master_In      : IN  AHB_Mst_In_Type;
                   AHB_Master_Out     : OUT AHB_Mst_Out_Type;
                   coarse_time_0      : IN  STD_LOGIC;
                   data_shaping_SP0   : IN  STD_LOGIC;
                   data_shaping_SP1   : IN  STD_LOGIC;
                   data_shaping_R0    : IN  STD_LOGIC;
                   data_shaping_R1    : IN  STD_LOGIC;
                   delta_snapshot     : IN  STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                   delta_f2_f1        : IN  STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                   delta_f2_f0        : IN  STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                   enable_f0          : IN  STD_LOGIC;
                   enable_f1          : IN  STD_LOGIC;
                   enable_f2          : IN  STD_LOGIC;
                   enable_f3          : IN  STD_LOGIC;
                   burst_f0           : IN  STD_LOGIC;
                   burst_f1           : IN  STD_LOGIC;
                   burst_f2           : IN  STD_LOGIC;
                   nb_burst_available : IN  STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                   nb_snapshot_param  : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_full        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   addr_data_f0       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
             END lpp_top_lfr_pkg;

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +3 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_top_lfr_wf_picker IS
               GENERIC (
                 hindex                 : INTEGER := 2;
                 pindex                 : INTEGER := 4;
                 paddr  : INTEGER := 4;
                 pmask  : INTEGER := 16#fff#;
                 pirq   : INTEGER := 0;
                 tech                   : INTEGER := 0;
                 nb_burst_available_size : INTEGER := 11;
                 nb_snapshot_param_size  : INTEGER := 11;
                 delta_snapshot_size     : INTEGER := 16;
                 delta_f2_f0_size        : INTEGER := 10;
                 delta_f2_f1_size        : INTEGER := 10
                 );
               PORT (
                 -- ADS7886
                 cnv_run         : IN  STD_LOGIC;
                 cnv             : OUT STD_LOGIC;
                 sck             : OUT STD_LOGIC;
                 sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 --
                 cnv_clk         : IN  STD_LOGIC;
                 cnv_rstn        : IN  STD_LOGIC;
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
                 -- AMBA APB Slave Interface
                 apbi : IN  apb_slv_in_type;
                 apbo : OUT apb_slv_out_type;
                 -- AMBA AHB Master Interface
                 AHB_Master_In  : IN  AHB_Mst_In_Type;
                 AHB_Master_Out : OUT AHB_Mst_Out_Type;
                 --
                 coarse_time_0 : IN STD_LOGIC;
                 --
                 data_shaping_BW  : OUT STD_LOGIC
                 );
             END lpp_top_lfr_wf_picker;
             ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
               SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
               SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
               SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
               SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
               SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_full                            : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack                        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err                        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err                         : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL data_shaping_SP0                       : STD_LOGIC;
               SIGNAL data_shaping_SP1                       : STD_LOGIC;
               SIGNAL data_shaping_R0                        : STD_LOGIC;
               SIGNAL data_shaping_R1                        : STD_LOGIC;
               SIGNAL delta_snapshot                         : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
               SIGNAL delta_f2_f1                            : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
               SIGNAL delta_f2_f0                            : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
               SIGNAL nb_burst_available                     : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param                      : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0                              : STD_LOGIC;
               SIGNAL enable_f1                              : STD_LOGIC;
               SIGNAL enable_f2                              : STD_LOGIC;
               SIGNAL enable_f3                              : STD_LOGIC;
               SIGNAL burst_f0                               : STD_LOGIC;
               SIGNAL burst_f1                               : STD_LOGIC;
               SIGNAL burst_f2                               : STD_LOGIC;
               SIGNAL addr_data_f0                           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f1                           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f2                           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f3                           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL sample_f0_wen      : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f0_wdata    : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wen      : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f1_wdata    : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wen      : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f2_wdata    : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_wen      : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f3_wdata    : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
             BEGIN
               lpp_top_apbreg_1: lpp_top_apbreg
                 GENERIC MAP (
                   nb_burst_available_size => nb_burst_available_size,
                   nb_snapshot_param_size  => nb_snapshot_param_size,
                   delta_snapshot_size     => delta_snapshot_size,
                   delta_f2_f0_size        => delta_f2_f0_size,
                   delta_f2_f1_size        => delta_f2_f1_size,
                   pindex                  => pindex,
                   paddr                   => paddr,
                   pmask                   => pmask,
                   pirq                    => pirq)
                 PORT MAP (
                   HCLK                                   => HCLK,
                   HRESETn                                => HRESETn,
                   apbi                                   => apbi,
                   apbo                                   => apbo,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0_0                       => addr_matrix_f0_0,
                   addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
                   status_full                            => status_full,
                   status_full_ack                        => status_full_ack,
                   status_full_err                        => status_full_err,
                   status_new_err                         => status_new_err,
                   data_shaping_BW                        => data_shaping_BW,
                   data_shaping_SP0                       => data_shaping_SP0,
                   data_shaping_SP1                       => data_shaping_SP1,
                   data_shaping_R0                        => data_shaping_R0,
                   data_shaping_R1                        => data_shaping_R1,
                   delta_snapshot                         => delta_snapshot,
                   delta_f2_f1                            => delta_f2_f1,
                   delta_f2_f0                            => delta_f2_f0,
                   nb_burst_available                     => nb_burst_available,
                   nb_snapshot_param                      => nb_snapshot_param,
                   enable_f0                              => enable_f0,
                   enable_f1                              => enable_f1,
                   enable_f2                              => enable_f2,
                   enable_f3                              => enable_f3,
                   burst_f0                               => burst_f0,
                   burst_f1                               => burst_f1,
                   burst_f2                               => burst_f2,
                   addr_data_f0                           => addr_data_f0,
                   addr_data_f1                           => addr_data_f1,
                   addr_data_f2                           => addr_data_f2,
                   addr_data_f3                           => addr_data_f3);
               lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip
                 GENERIC MAP (
                   hindex                  => hindex,
                   nb_burst_available_size => nb_burst_available_size,
                   nb_snapshot_param_size  => nb_snapshot_param_size,
                   delta_snapshot_size     => delta_snapshot_size,
                   delta_f2_f0_size        => delta_f2_f0_size,
                   delta_f2_f1_size        => delta_f2_f1_size,
-                  tech                    => tech)
+                  tech                    => tech,
+                  Mem_use                   => use_RAM
+                  )
                 PORT MAP (
                   cnv_run            => cnv_run,
                   cnv                => cnv,
                   sck                => sck,
                   sdo                => sdo,
                   cnv_clk            => cnv_clk,
                   cnv_rstn           => cnv_rstn,
                   clk                => HCLK,
                   rstn               => HRESETn,
                   sample_f0_wen      => sample_f0_wen,
                   sample_f0_wdata    => sample_f0_wdata,
                   sample_f1_wen      => sample_f1_wen,
                   sample_f1_wdata    => sample_f1_wdata,
                   sample_f2_wen      => sample_f2_wen,
                   sample_f2_wdata    => sample_f2_wdata,
                   sample_f3_wen      => sample_f3_wen,
                   sample_f3_wdata    => sample_f3_wdata,
                   AHB_Master_In      => AHB_Master_In,
                   AHB_Master_Out     => AHB_Master_Out,
                   coarse_time_0      => coarse_time_0,
                   data_shaping_SP0   => data_shaping_SP0,
                   data_shaping_SP1   => data_shaping_SP1,
                   data_shaping_R0    => data_shaping_R0,
                   data_shaping_R1    => data_shaping_R1,
                   delta_snapshot     => delta_snapshot,
                   delta_f2_f1        => delta_f2_f1,
                   delta_f2_f0        => delta_f2_f0,
                   enable_f0          => enable_f0,
                   enable_f1          => enable_f1,
                   enable_f2          => enable_f2,
                   enable_f3          => enable_f3,
                   burst_f0           => burst_f0,
                   burst_f1           => burst_f1,
                   burst_f2           => burst_f2,
                   nb_burst_available => nb_burst_available,
                   nb_snapshot_param  => nb_snapshot_param,
                   status_full        => status_full,
                   status_full_ack    => status_full_ack,
                   status_full_err    => status_full_err,
                   status_new_err     => status_new_err,
                   addr_data_f0       => addr_data_f0,
                   addr_data_f1       => addr_data_f1,
                   addr_data_f2       => addr_data_f2,
                   addr_data_f3       => addr_data_f3);
             END tb;

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +6 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_top_lfr_wf_picker_ip IS
               GENERIC(
                 hindex                 : INTEGER := 2;
                 nb_burst_available_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_snapshot_size    : INTEGER := 16;
                 delta_f2_f0_size       : INTEGER := 10;
                 delta_f2_f1_size       : INTEGER := 10;
-                tech                   : INTEGER := 0
+                tech                   : INTEGER := 0;
+                Mem_use                : INTEGER := use_RAM
                 );
               PORT (
                 -- ADS7886
                 cnv_run         : IN  STD_LOGIC;
                 cnv             : OUT STD_LOGIC;
                 sck             : OUT STD_LOGIC;
                 sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 --
                 cnv_clk         : IN  STD_LOGIC;
                 cnv_rstn        : IN  STD_LOGIC;
                 --
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 --
                 sample_f0_wen   : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 --
                 sample_f3_wen   : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 -- AMBA AHB Master Interface
                 AHB_Master_In  : IN  AHB_Mst_In_Type;
                 AHB_Master_Out : OUT AHB_Mst_Out_Type;
                 coarse_time_0 : IN STD_LOGIC;
                 --config
                 data_shaping_SP0 : IN STD_LOGIC;
                 data_shaping_SP1 : IN STD_LOGIC;
                 data_shaping_R0  : IN STD_LOGIC;
                 data_shaping_R1  : IN STD_LOGIC;
                 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                 delta_f2_f1    : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                 delta_f2_f0    : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                 enable_f0 : IN STD_LOGIC;
                 enable_f1 : IN STD_LOGIC;
                 enable_f2 : IN STD_LOGIC;
                 enable_f3 : IN STD_LOGIC;
                 burst_f0 : IN STD_LOGIC;
                 burst_f1 : IN STD_LOGIC;
                 burst_f2 : IN STD_LOGIC;
                 nb_burst_available : IN  STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                 nb_snapshot_param : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 status_full       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_ack   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_err   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- New data f(i) before the current data is write by dma
                 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END lpp_top_lfr_wf_picker_ip;
             ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
               COMPONENT Downsampling
                 GENERIC (
                   ChanelCount : INTEGER;
                   SampleSize  : INTEGER;
                   DivideParam : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   sample_in_val  : IN  STD_LOGIC;
                   sample_in      : IN  samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
                   sample_out_val : OUT STD_LOGIC;
                   sample_out     : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               CONSTANT ChanelCount     : INTEGER := 8;
               CONSTANT ncycle_cnv_high : INTEGER := 79;
               CONSTANT ncycle_cnv      : INTEGER := 500;
               -----------------------------------------------------------------------------
               SIGNAL   sample           : Samples(ChanelCount-1 DOWNTO 0);
               SIGNAL   sample_val       : STD_LOGIC;
               SIGNAL   sample_val_delay : STD_LOGIC;
               -----------------------------------------------------------------------------
               CONSTANT Coef_SZ          : INTEGER := 9;
               CONSTANT CoefCntPerCel    : INTEGER := 6;
               CONSTANT CoefPerCel       : INTEGER := 5;
               CONSTANT Cels_count       : INTEGER := 5;
               SIGNAL coefs                    : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
               SIGNAL coefs_v2                 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
               SIGNAL sample_filter_in         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_filter_out        : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               --
               SIGNAL sample_filter_v2_out_val : STD_LOGIC;
               SIGNAL sample_filter_v2_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_data_shaping_out_val : STD_LOGIC;
               SIGNAL sample_data_shaping_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_data_shaping_f0_s    : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f1_s    : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f2_s    : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
               SIGNAL sample_filter_v2_out_s   : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_val            : STD_LOGIC;
               SIGNAL sample_f0                : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f0_s              : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               --
               SIGNAL sample_f1_val            : STD_LOGIC;
               SIGNAL sample_f1                : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f1_s              : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               --
               SIGNAL sample_f2_val            : STD_LOGIC;
               SIGNAL sample_f2                : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               --
               SIGNAL sample_f3_val            : STD_LOGIC;
               SIGNAL sample_f3                : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               -----------------------------------------------------------------------------
               SIGNAL  sample_f0_wdata_s :  STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL  sample_f1_wdata_s :  STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL  sample_f2_wdata_s :  STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL  sample_f3_wdata_s :  STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
             BEGIN
               -- component instantiation
               -----------------------------------------------------------------------------
               DIGITAL_acquisition : AD7688_drvr
                 GENERIC MAP (
                   ChanelCount     => ChanelCount,
                   ncycle_cnv_high => ncycle_cnv_high,
                   ncycle_cnv      => ncycle_cnv)
                 PORT MAP (
                   cnv_clk    => cnv_clk,                      --
                   cnv_rstn   => cnv_rstn,                     --
                   cnv_run    => cnv_run,                      --
                   cnv        => cnv,                          --
                   clk        => clk,                          --
                   rstn       => rstn,                         --
                   sck        => sck,                          --
                   sdo        => sdo(ChanelCount-1 DOWNTO 0),  --
                   sample     => sample,
                   sample_val => sample_val);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_val_delay <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   sample_val_delay <= sample_val;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
                 SampleLoop : FOR j IN 0 TO 15 GENERATE
                   sample_filter_in(i, j) <= sample(i)(j);
                 END GENERATE;
                 sample_filter_in(i, 16) <= sample(i)(15);
                 sample_filter_in(i, 17) <= sample(i)(15);
               END GENERATE;
               coefs_v2 <= CoefsInitValCst_v2;
               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => 0,
-                  Mem_use      => use_RAM,          -- use_RAM
+                  Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
                   Coef_Nb      => 25,
                   Coef_sel_SZ  => 5,
                   Cels_count   => Cels_count,
                   ChanelsCount => ChanelCount)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   virg_pos       => 7,
                   coefs          => coefs_v2,
                   sample_in_val  => sample_val_delay,
                   sample_in      => sample_filter_in,
                   sample_out_val => sample_filter_v2_out_val,
                   sample_out     => sample_filter_v2_out);
               -----------------------------------------------------------------------------
               -- DATA_SHAPING
               -----------------------------------------------------------------------------
               all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE
                 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I);
                 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I);
                 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I);
               END GENERATE all_data_shaping_in_loop;
               sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
               sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_data_shaping_out_val <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   sample_data_shaping_out_val <= sample_filter_v2_out_val;
                 END IF;
               END PROCESS;
               SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                       sample_data_shaping_out(0,j) <= '0';
                       sample_data_shaping_out(1,j) <= '0';
                       sample_data_shaping_out(2,j) <= '0';
                       sample_data_shaping_out(3,j) <= '0';
                       sample_data_shaping_out(4,j) <= '0';
                       sample_data_shaping_out(5,j) <= '0';
                       sample_data_shaping_out(6,j) <= '0';
                       sample_data_shaping_out(7,j) <= '0';
                   ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                     sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j);
                     IF data_shaping_SP0 = '1' THEN
                       sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j);
                     ELSE
                       sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j);
                     END IF;
                     IF data_shaping_SP1 = '1' THEN
                       sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j);
                     ELSE
                       sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j);
                     END IF;
                     sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j);
                     sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j);
                     sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j);
                     sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j);
                   END IF;
                 END PROCESS;
               END GENERATE;
               sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
               ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
                 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
                   sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j);
                 END GENERATE;
               END GENERATE;
               -----------------------------------------------------------------------------
               -- F0 -- @24.576 kHz
               -----------------------------------------------------------------------------
               Downsampling_f0 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 8,
                   SampleSize  => 16,
                   DivideParam => 4)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_filter_v2_out_val_s,
                   sample_in      => sample_filter_v2_out_s,
                   sample_out_val => sample_f0_val,
                   sample_out     => sample_f0);
               all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_wdata_s(I)      <= sample_f0(0, I);  -- V
                 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I);  -- E1
                 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I);  -- E2
                 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I);  -- B1
                 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I);  -- B2
                 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I);  -- B3
               END GENERATE all_bit_sample_f0;
               sample_f0_wen <= NOT(sample_f0_val) &
                                NOT(sample_f0_val) &
                                NOT(sample_f0_val) &
                                NOT(sample_f0_val) &
                                NOT(sample_f0_val) &
                                NOT(sample_f0_val);
               -----------------------------------------------------------------------------
               -- F1 -- @4096 Hz
               -----------------------------------------------------------------------------
               Downsampling_f1 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 8,
                   SampleSize  => 16,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f0_val ,
                   sample_in      => sample_f0,
                   sample_out_val => sample_f1_val,
                   sample_out     => sample_f1);
               all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f1_wdata_s(I)      <= sample_f1(0, I);  -- V
                 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
                 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
                 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I);  -- B1
                 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I);  -- B2
                 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I);  -- B3
               END GENERATE all_bit_sample_f1;
               sample_f1_wen <= NOT(sample_f1_val) &
                                NOT(sample_f1_val) &
                                NOT(sample_f1_val) &
                                NOT(sample_f1_val) &
                                NOT(sample_f1_val) &
                                NOT(sample_f1_val);
               -----------------------------------------------------------------------------
               -- F2 -- @256 Hz
               -----------------------------------------------------------------------------
               all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_s(0, I) <= sample_f0(0, I);  -- V
                 sample_f0_s(1, I) <= sample_f0(1, I);  -- E1
                 sample_f0_s(2, I) <= sample_f0(2, I);  -- E2
                 sample_f0_s(3, I) <= sample_f0(5, I);  -- B1
                 sample_f0_s(4, I) <= sample_f0(6, I);  -- B2
                 sample_f0_s(5, I) <= sample_f0(7, I);  -- B3
               END GENERATE all_bit_sample_f0_s;
               Downsampling_f2 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 16,
                   DivideParam => 96)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f0_val ,
                   sample_in      => sample_f0_s,
                   sample_out_val => sample_f2_val,
                   sample_out     => sample_f2);
               sample_f2_wen <= NOT(sample_f2_val) &
                                NOT(sample_f2_val) &
                                NOT(sample_f2_val) &
                                NOT(sample_f2_val) &
                                NOT(sample_f2_val) &
                                NOT(sample_f2_val);
               all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f2_wdata_s(I)      <= sample_f2(0, I);
                 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
                 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
                 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
                 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
                 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
               END GENERATE all_bit_sample_f2;
               -----------------------------------------------------------------------------
               -- F3 -- @16 Hz
               -----------------------------------------------------------------------------
               all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f1_s(0, I) <= sample_f1(0, I);  -- V
                 sample_f1_s(1, I) <= sample_f1(1, I);  -- E1
                 sample_f1_s(2, I) <= sample_f1(2, I);  -- E2
                 sample_f1_s(3, I) <= sample_f1(5, I);  -- B1
                 sample_f1_s(4, I) <= sample_f1(6, I);  -- B2
                 sample_f1_s(5, I) <= sample_f1(7, I);  -- B3
               END GENERATE all_bit_sample_f1_s;
               Downsampling_f3 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 16,
                   DivideParam => 256)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f1_val ,
                   sample_in      => sample_f1_s,
                   sample_out_val => sample_f3_val,
                   sample_out     => sample_f3);
               sample_f3_wen <= (NOT sample_f3_val) &
                                (NOT sample_f3_val) &
                                (NOT sample_f3_val) &
                                (NOT sample_f3_val) &
                                (NOT sample_f3_val) &
                                (NOT sample_f3_val);
               all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f3_wdata_s(I)      <= sample_f3(0, I);
                 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
                 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
                 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
                 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
                 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
               END GENERATE all_bit_sample_f3;
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   hindex                 => hindex,
                   tech                   => tech,
                   data_size              => 160,
                   nb_burst_available_size => nb_burst_available_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_snapshot_size    => delta_snapshot_size,
                   delta_f2_f0_size       => delta_f2_f0_size,
                   delta_f2_f1_size       => delta_f2_f1_size)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   AHB_Master_In  => AHB_Master_In,
                   AHB_Master_Out => AHB_Master_Out,
                   coarse_time_0     => coarse_time_0,    -- IN
                   delta_snapshot    => delta_snapshot,   -- IN
                   delta_f2_f1       => delta_f2_f1,      -- IN
                   delta_f2_f0       => delta_f2_f0,      -- IN
                   enable_f0         => enable_f0,        -- IN
                   enable_f1         => enable_f1,        -- IN
                   enable_f2         => enable_f2,        -- IN
                   enable_f3         => enable_f3,        -- IN
                   burst_f0          => burst_f0,         -- IN
                   burst_f1          => burst_f1,         -- IN
                   burst_f2          => burst_f2,         -- IN
                   nb_burst_available => nb_burst_available,
                   nb_snapshot_param => nb_snapshot_param,
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,  -- IN
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   addr_data_f0 => addr_data_f0,     -- IN
                   addr_data_f1 => addr_data_f1,     -- IN
                   addr_data_f2 => addr_data_f2,     -- IN
                   addr_data_f3 => addr_data_f3,     -- IN
                   data_f0_in       => data_f0_in_valid,
                   data_f1_in       => data_f1_in_valid,
                   data_f2_in       => data_f2_in_valid,
                   data_f3_in       => data_f3_in_valid,
                   data_f0_in_valid => sample_f0_val,
                   data_f1_in_valid => sample_f1_val,
                   data_f2_in_valid => sample_f2_val,
                   data_f3_in_valid => sample_f3_val);
               data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
               data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
               data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
               data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0');
               data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
               data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
               data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
               data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
               sample_f0_wdata <= sample_f0_wdata_s;
               sample_f1_wdata <= sample_f1_wdata_s;
               sample_f2_wdata <= sample_f2_wdata_s;
               sample_f3_wdata <= sample_f3_wdata_s;
-            END tb;
  No newline at end of file
+            END tb;

lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +25 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             -- 1.0 - initial version
             -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY lpp;
             USE lpp.lpp_amba.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_waveform_dma IS
               GENERIC (
                 data_size               : INTEGER := 160;
                 tech                    : INTEGER := inferred;
                 hindex                  : INTEGER := 2;
                 nb_burst_available_size : INTEGER := 11
                 );
               PORT (
                 -- AMBA AHB system signals
                 HCLK               : IN  STD_ULOGIC;
                 HRESETn            : IN  STD_ULOGIC;
                 -- AMBA AHB Master Interface
                 AHB_Master_In      : IN  AHB_Mst_In_Type;
                 AHB_Master_Out     : OUT AHB_Mst_Out_Type;
                 --
                 data_ready         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);   -- todo
                 data               : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 data_data_ren      : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);   -- todo
                 data_time_ren      : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);   -- todo
                 -- Reg
                 nb_burst_available : IN  STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                 status_full        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_ack    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             --    status_new_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- New data f(i) before the current data is write by dma
                 addr_data_f0       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f1       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_waveform_dma IS
               -----------------------------------------------------------------------------
               SIGNAL DMAIn  : DMA_In_Type;
               SIGNAL DMAOut : DMA_OUt_Type;
               -----------------------------------------------------------------------------
               TYPE state_DMAWriteBurst IS (IDLE,
                                              SEND_TIME_0, WAIT_TIME_0,
                                              SEND_TIME_1, WAIT_TIME_1,
                                              SEND_5_TIME,
                                              SEND_DATA, WAIT_DATA);
               SIGNAL state                : state_DMAWriteBurst := IDLE;
               -----------------------------------------------------------------------------
               -- CONTROL
               SIGNAL sel_data_s           : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL sel_data             : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL update               : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL time_select          : STD_LOGIC;
               SIGNAL time_write           : STD_LOGIC;
               SIGNAL time_already_send    : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_already_send_s  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SEND TIME MODULE
               SIGNAL time_dmai            : DMA_In_Type;
               SIGNAL time_send            : STD_LOGIC;
               SIGNAL time_send_ok         : STD_LOGIC;
               SIGNAL time_send_ko         : STD_LOGIC;
               SIGNAL time_fifo_ren        : STD_LOGIC;
               SIGNAL time_ren             : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SEND DATA MODULE
               SIGNAL data_dmai            : DMA_In_Type;
               SIGNAL data_send            : STD_LOGIC;
               SIGNAL data_send_ok         : STD_LOGIC;
               SIGNAL data_send_ko         : STD_LOGIC;
               SIGNAL data_fifo_ren        : STD_LOGIC;
               SIGNAL data_ren             : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SELECT ADDRESS
               SIGNAL data_address         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL update_and_sel       : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL addr_data_vector     : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               -----------------------------------------------------------------------------
-              SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0);
+              SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
+              SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
+              -----------------------------------------------------------------------------
+              SIGNAL send_16_3_time       : STD_LOGIC;
               SIGNAL count_send_time      : INTEGER;
             BEGIN
               -----------------------------------------------------------------------------
               -- DMA to AHB interface
               DMA2AHB_1 : DMA2AHB
                 GENERIC MAP (
                   hindex   => hindex,
                   vendorid => VENDOR_LPP,
                   deviceid => 0,
                   version  => 0,
                   syncrst  => 1,
                   boundary => 1)                    -- FIX 11/01/2013
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => DMAIn,
                   DMAOut  => DMAOut,
                   AHBIn   => AHB_Master_In,
                   AHBOut  => AHB_Master_Out);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- This module memorises when the Times info are write. When FSM send
               -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
               all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
                 PROCESS (HCLK, HRESETn)
                 BEGIN  -- PROCESS
                   IF HRESETn = '0' THEN                 -- asynchronous reset (active low)
                     time_already_send(I) <= '0';
                   ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
                     IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
                       time_already_send(I) <= '1';
                     ELSIF status_full_ack(I) = '1' THEN
                       time_already_send(I) <= '0';
                     END IF;
                   END IF;
                 END PROCESS;
               END GENERATE all_time_write;
               -----------------------------------------------------------------------------
               sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
                             "01" WHEN data_ready(1) = '1' ELSE
                             "10" WHEN data_ready(2) = '1' ELSE
                             "11";
               time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
                                      time_already_send(1) WHEN data_ready(1) = '1' ELSE
                                      time_already_send(2) WHEN data_ready(2) = '1' ELSE
                                      time_already_send(3);
+              send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
+                                send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
+                                send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
+                                send_16_3_time_reg(9) ;
+              all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
+                send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
+                  send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
+                  send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
+              END GENERATE all_send_16_3;
               -- DMA control
               DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
               BEGIN  -- PROCESS DMAWriteBurst_p
                 IF HRESETn = '0' THEN
                   state <= IDLE;
                   sel_data       <= "00";
                   update         <= "00";
                   time_select    <= '0';
                   time_fifo_ren  <= '1';
                   data_send      <= '0';
                   time_send      <= '0';
                   time_write     <= '0';
-                  send_16_3_time <= "001";
+                  --send_16_3_time <= "001";
+                  send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
+                  send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
+                  send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
+                  send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN
                   CASE state IS
                     WHEN IDLE =>
                       count_send_time <= 0;
                       sel_data        <= "00";
                       update          <= "00";
                       time_select     <= '0';
                       time_fifo_ren   <= '1';
                       data_send       <= '0';
                       time_send       <= '0';
                       time_write      <= '0';
                       IF data_ready = "0000" THEN
                         state <= IDLE;
                       ELSE
                         sel_data            <= sel_data_s;
-                        send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2);
+                        send_16_3_time_reg  <= send_16_3_time_reg_s;
-                        IF send_16_3_time(0) = '1' THEN
+                        IF send_16_3_time = '1' THEN
                           state <= SEND_TIME_0;
                         ELSE
                           state <= SEND_5_TIME;
                         END IF;
                       END IF;
                     WHEN SEND_TIME_0 =>
                       time_select <= '1';
                       IF time_already_send_s = '0' THEN
                         time_send <= '1';
                         state     <= WAIT_TIME_0;
                       ELSE
                         time_send <= '0';
                         state     <= SEND_TIME_1;
                       END IF;
                       time_fifo_ren <= '0';
                     WHEN WAIT_TIME_0 =>
                       time_fifo_ren <= '1';
                       update        <= "00";
                       time_send     <= '0';
                       IF time_send_ok = '1' OR time_send_ko = '1' THEN
                         update <= "01";
                         state  <= SEND_TIME_1;
                       END IF;
                     WHEN SEND_TIME_1 =>
                       time_select <= '1';
                       IF time_already_send_s = '0' THEN
                         time_send <= '1';
                         state     <= WAIT_TIME_1;
                       ELSE
                         time_send <= '0';
                         state     <= SEND_5_TIME;
                       END IF;
                       time_fifo_ren <= '0';
                     WHEN WAIT_TIME_1 =>
                       time_fifo_ren <= '1';
                       update        <= "00";
                       time_send     <= '0';
                       IF time_send_ok = '1' OR time_send_ko = '1' THEN
                         time_write <= '1';
                         update     <= "01";
                         state      <= SEND_5_TIME;
                       END IF;
                     WHEN SEND_5_TIME =>
                       update          <= "00";
                       time_select     <= '1';
                       time_fifo_ren   <= '0';
                       count_send_time <= count_send_time + 1;
                       IF count_send_time = 10 THEN
                         state <= SEND_DATA;
                       END IF;
                     WHEN SEND_DATA =>
                       time_fifo_ren <= '1';
                       time_write    <= '0';
                       time_send     <= '0';
                       time_select <= '0';
                       data_send   <= '1';
                       update      <= "00";
                       state       <= WAIT_DATA;
                     WHEN WAIT_DATA =>
                       data_send <= '0';
                       IF data_send_ok = '1' OR data_send_ko = '1' THEN
                         state  <= IDLE;
                         update <= "10";
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS DMAWriteFSM_p;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SEND 1 word by DMA
               -----------------------------------------------------------------------------
               lpp_dma_send_1word_1 : lpp_dma_send_1word
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => time_dmai,
                   DMAOut  => DMAOut,
                   send    => time_send,
                   address => data_address,
                   data    => data,
                   send_ok => time_send_ok,
                   send_ko => time_send_ko
                   );
               -----------------------------------------------------------------------------
               -- SEND 16 word by DMA (in burst mode)
               -----------------------------------------------------------------------------
               lpp_dma_send_16word_1 : lpp_dma_send_16word
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   DMAIn   => data_dmai,
                   DMAOut  => DMAOut,
                   send    => data_send,
                   address => data_address,
                   data    => data,
                   ren     => data_fifo_ren,
                   send_ok => data_send_ok,
                   send_ko => data_send_ko);
               DMAIn    <= time_dmai     WHEN time_select = '1' ELSE data_dmai;
               data_ren <= '1'           WHEN time_select = '1' ELSE data_fifo_ren;
               time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
               all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
                 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
                 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
               END GENERATE all_data_ren;
               -----------------------------------------------------------------------------
               -- SELECT ADDRESS
               addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
               gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
                 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
                 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
                   GENERIC MAP (
                     nb_burst_available_size => nb_burst_available_size)
                   PORT MAP (
                     HCLK               => HCLK,
                     HRESETn            => HRESETn,
                     update             => update_and_sel((2*I)+1 DOWNTO 2*I),
                     nb_burst_available => nb_burst_available,
                     addr_data_reg      => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
                     addr_data          => addr_data_vector(32*I+31 DOWNTO 32*I),
                     status_full        => status_full(I),
                     status_full_ack    => status_full_ack(I),
                     status_full_err    => status_full_err(I));
               END GENERATE gen_select_address;
               data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
                               addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
                               addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
                               addr_data_vector(32*3+31 DOWNTO 32*3);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +1 -1

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE ieee.numeric_std.ALL;
             ENTITY lpp_waveform_snapshot_controler IS
               GENERIC (
                 delta_snapshot_size : INTEGER := 16;
                 delta_f2_f0_size    : INTEGER := 10;
                 delta_f2_f1_size    : INTEGER := 10);
               PORT (
                 clk               : IN STD_LOGIC;
                 rstn              : IN STD_LOGIC;
                 --config
                 delta_snapshot    : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                 delta_f2_f1       : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                 delta_f2_f0       : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                 --input
                 coarse_time_0     : IN STD_LOGIC;
                 data_f0_in_valid  : IN STD_LOGIC;
                 data_f2_in_valid  : IN STD_LOGIC;
                 --output
                 start_snapshot_f0 : OUT STD_LOGIC;
                 start_snapshot_f1 : OUT STD_LOGIC;
                 start_snapshot_f2 : OUT STD_LOGIC
                 );
             END lpp_waveform_snapshot_controler;
             ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
               SIGNAL counter_delta_snapshot : INTEGER;
               SIGNAL counter_delta_f0       : INTEGER;
               SIGNAL coarse_time_0_r : STD_LOGIC;
               SIGNAL start_snapshot_f2_temp : STD_LOGIC;
               SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
               SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC;
             BEGIN  -- beh
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   start_snapshot_f0 <= '0';
                   start_snapshot_f1 <= '0';
                   start_snapshot_f2 <= '0';
                   counter_delta_snapshot <= 0;
                   counter_delta_f0 <= 0;
                   coarse_time_0_r <=  '0';
                   start_snapshot_f2_temp <=  '0';
                   start_snapshot_fothers_temp <=  '0';
                   start_snapshot_fothers_temp2 <=  '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
                     start_snapshot_f2_temp <=   '1';
                   ELSE
                     start_snapshot_f2_temp <= '0';
                   END IF;
                   -------------------------------------------------------------------------
                   IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0'  THEN
                     start_snapshot_f2 <= '1';
                   ELSE
                     start_snapshot_f2 <= '0';
                   END IF;
                   -------------------------------------------------------------------------
                   coarse_time_0_r <= coarse_time_0;
-                  IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN
+                  IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
                     IF counter_delta_snapshot = 0  THEN
                       counter_delta_snapshot <=  to_integer(UNSIGNED(delta_snapshot));
                     ELSE
                       counter_delta_snapshot <=  counter_delta_snapshot - 1;
                     END IF;
                   END IF;
                   -------------------------------------------------------------------------
                   IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
                     start_snapshot_f1 <= '1';
                   ELSE
                     start_snapshot_f1 <= '0';
                   END IF;
                   IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
                     start_snapshot_f0 <= '1';
                   ELSE
                     start_snapshot_f0 <= '0';
                   END IF;
                   IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
                     AND start_snapshot_f2_temp = '0'
                   THEN --
                     start_snapshot_fothers_temp <= '1';
                   ELSIF counter_delta_f0 > 0 THEN
                     start_snapshot_fothers_temp <= '0';
                   END IF;
                   -------------------------------------------------------------------------
                   IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
                     --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0'  THEN --
                     --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
                     counter_delta_f0  <= to_integer(UNSIGNED(delta_f2_f0));  --0;
                   ELSE
                     IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
                         counter_delta_f0  <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
                     END IF;
                   END IF;
                   -------------------------------------------------------------------------
                 END IF;
               END PROCESS;
             END beh;

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