@@ -1,21 +1,22 | |||||
1 | ./amba_lcd_16x2_ctrlr |
|
1 | ./amba_lcd_16x2_ctrlr | |
2 | ./general_purpose |
|
2 | ./general_purpose | |
3 | ./general_purpose/lpp_AMR |
|
3 | ./general_purpose/lpp_AMR | |
4 | ./general_purpose/lpp_balise |
|
4 | ./general_purpose/lpp_balise | |
5 | ./general_purpose/lpp_delay |
|
5 | ./general_purpose/lpp_delay | |
6 | ./lpp_amba |
|
6 | ./lpp_amba | |
7 | ./dsp/iir_filter |
|
7 | ./dsp/iir_filter | |
8 | ./dsp/lpp_downsampling |
|
8 | ./dsp/lpp_downsampling | |
9 | ./dsp/lpp_fft |
|
9 | ./dsp/lpp_fft | |
10 | ./lfr_time_management |
|
10 | ./lfr_time_management | |
11 | ./lpp_ad_Conv |
|
11 | ./lpp_ad_Conv | |
12 | ./lpp_bootloader |
|
12 | ./lpp_bootloader | |
13 | ./lpp_cna |
|
13 | ./lpp_cna | |
14 | ./lpp_demux |
|
14 | ./lpp_demux | |
15 | ./lpp_matrix |
|
15 | ./lpp_matrix | |
16 | ./lpp_memory |
|
16 | ./lpp_memory | |
17 | ./lpp_dma |
|
17 | ./lpp_dma | |
18 | ./lpp_uart |
|
18 | ./lpp_uart | |
19 | ./lpp_usb |
|
19 | ./lpp_usb | |
20 | ./lpp_waveform |
|
20 | ./lpp_waveform | |
21 | ./lpp_top_lfr |
|
21 | ./lpp_top_lfr | |
|
22 | ./lpp_Header |
@@ -1,120 +1,121 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY lpp; |
|
25 | LIBRARY lpp; | |
26 | USE lpp.iir_filter.ALL; |
|
26 | USE lpp.iir_filter.ALL; | |
27 | USE lpp.FILTERcfg.ALL; |
|
27 | USE lpp.FILTERcfg.ALL; | |
28 | USE lpp.general_purpose.ALL; |
|
28 | USE lpp.general_purpose.ALL; | |
29 | LIBRARY techmap; |
|
29 | LIBRARY techmap; | |
30 | USE techmap.gencomp.ALL; |
|
30 | USE techmap.gencomp.ALL; | |
31 |
|
31 | |||
32 | ENTITY RAM_CTRLR_v2 IS |
|
32 | ENTITY RAM_CTRLR_v2 IS | |
33 | GENERIC( |
|
33 | GENERIC( | |
34 | tech : INTEGER := 0; |
|
34 | tech : INTEGER := 0; | |
35 | Input_SZ_1 : INTEGER := 16; |
|
35 | Input_SZ_1 : INTEGER := 16; | |
36 | Mem_use : INTEGER := use_RAM |
|
36 | Mem_use : INTEGER := use_RAM | |
37 | ); |
|
37 | ); | |
38 | PORT( |
|
38 | PORT( | |
39 | rstn : IN STD_LOGIC; |
|
39 | rstn : IN STD_LOGIC; | |
40 | clk : IN STD_LOGIC; |
|
40 | clk : IN STD_LOGIC; | |
41 | -- R/W Ctrl |
|
41 | -- R/W Ctrl | |
42 | ram_write : IN STD_LOGIC; |
|
42 | ram_write : IN STD_LOGIC; | |
43 | ram_read : IN STD_LOGIC; |
|
43 | ram_read : IN STD_LOGIC; | |
44 | -- ADDR Ctrl |
|
44 | -- ADDR Ctrl | |
45 | raddr_rst : IN STD_LOGIC; |
|
45 | raddr_rst : IN STD_LOGIC; | |
46 | raddr_add1 : IN STD_LOGIC; |
|
46 | raddr_add1 : IN STD_LOGIC; | |
47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
48 | -- Data |
|
48 | -- Data | |
49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
|
50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
51 | ); |
|
51 | ); | |
52 | END RAM_CTRLR_v2; |
|
52 | END RAM_CTRLR_v2; | |
53 |
|
53 | |||
54 |
|
54 | |||
55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS |
|
55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS | |
56 |
|
56 | |||
57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
59 | SIGNAL WEN, REN : STD_LOGIC; |
|
59 | SIGNAL WEN, REN : STD_LOGIC; | |
60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
63 |
|
63 | |||
64 | BEGIN |
|
64 | BEGIN | |
65 |
|
65 | |||
66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); |
|
66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); | |
67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; |
|
67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; | |
68 | ----------------------------------------------------------------------------- |
|
68 | ----------------------------------------------------------------------------- | |
69 | -- RAM |
|
69 | -- RAM | |
70 | ----------------------------------------------------------------------------- |
|
70 | ----------------------------------------------------------------------------- | |
71 |
|
71 | |||
72 | memCEL : IF Mem_use = use_CEL GENERATE |
|
72 | memCEL : IF Mem_use = use_CEL GENERATE | |
73 | WEN <= NOT ram_write; |
|
73 | WEN <= NOT ram_write; | |
74 | REN <= NOT ram_read; |
|
74 | REN <= NOT ram_read; | |
|
75 | -- RAMblk : RAM_CEL_N | |||
75 | RAMblk : RAM_CEL_N |
|
76 | RAMblk : RAM_CEL_N | |
76 | GENERIC MAP(Input_SZ_1) |
|
77 | GENERIC MAP(Input_SZ_1) | |
77 | PORT MAP( |
|
78 | PORT MAP( | |
78 | WD => WD, |
|
79 | WD => WD, | |
79 | RD => RD, |
|
80 | RD => RD, | |
80 | WEN => WEN, |
|
81 | WEN => WEN, | |
81 | REN => REN, |
|
82 | REN => REN, | |
82 | WADDR => WADDR, |
|
83 | WADDR => WADDR, | |
83 | RADDR => RADDR, |
|
84 | RADDR => RADDR, | |
84 | RWCLK => clk, |
|
85 | RWCLK => clk, | |
85 | RESET => rstn |
|
86 | RESET => rstn | |
86 | ) ; |
|
87 | ) ; | |
87 | END GENERATE; |
|
88 | END GENERATE; | |
88 |
|
89 | |||
89 | memRAM : IF Mem_use = use_RAM GENERATE |
|
90 | memRAM : IF Mem_use = use_RAM GENERATE | |
90 | SRAM : syncram_2p |
|
91 | SRAM : syncram_2p | |
91 | GENERIC MAP(tech, 8, Input_SZ_1) |
|
92 | GENERIC MAP(tech, 8, Input_SZ_1) | |
92 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); |
|
93 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); | |
93 | END GENERATE; |
|
94 | END GENERATE; | |
94 |
|
95 | |||
95 | ----------------------------------------------------------------------------- |
|
96 | ----------------------------------------------------------------------------- | |
96 | -- RADDR |
|
97 | -- RADDR | |
97 | ----------------------------------------------------------------------------- |
|
98 | ----------------------------------------------------------------------------- | |
98 | PROCESS (clk, rstn) |
|
99 | PROCESS (clk, rstn) | |
99 | BEGIN -- PROCESS |
|
100 | BEGIN -- PROCESS | |
100 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
101 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
101 | counter <= (OTHERS => '0'); |
|
102 | counter <= (OTHERS => '0'); | |
102 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
103 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
103 | IF raddr_rst = '1' THEN |
|
104 | IF raddr_rst = '1' THEN | |
104 | counter <= (OTHERS => '0'); |
|
105 | counter <= (OTHERS => '0'); | |
105 | ELSIF raddr_add1 = '1' THEN |
|
106 | ELSIF raddr_add1 = '1' THEN | |
106 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); |
|
107 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
107 | END IF; |
|
108 | END IF; | |
108 | END IF; |
|
109 | END IF; | |
109 | END PROCESS; |
|
110 | END PROCESS; | |
110 | RADDR <= counter; |
|
111 | RADDR <= counter; | |
111 |
|
112 | |||
112 | ----------------------------------------------------------------------------- |
|
113 | ----------------------------------------------------------------------------- | |
113 | -- WADDR |
|
114 | -- WADDR | |
114 | ----------------------------------------------------------------------------- |
|
115 | ----------------------------------------------------------------------------- | |
115 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE |
|
116 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE | |
116 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE |
|
117 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE | |
117 | STD_LOGIC_VECTOR(UNSIGNED(counter)); |
|
118 | STD_LOGIC_VECTOR(UNSIGNED(counter)); | |
118 |
|
119 | |||
119 |
|
120 | |||
120 | END ar_RAM_CTRLR_v2; |
|
121 | END ar_RAM_CTRLR_v2; |
@@ -1,9 +1,9 | |||||
|
1 | lpp_fft.vhd | |||
1 | APB_FFT.vhd |
|
2 | APB_FFT.vhd | |
2 | APB_FFT_half.vhd |
|
3 | APB_FFT_half.vhd | |
3 | Driver_FFT.vhd |
|
4 | Driver_FFT.vhd | |
4 | FFT.vhd |
|
5 | FFT.vhd | |
5 | FFTamont.vhd |
|
6 | FFTamont.vhd | |
6 | FFTaval.vhd |
|
7 | FFTaval.vhd | |
7 | Flag_Extremum.vhd |
|
8 | Flag_Extremum.vhd | |
8 | Linker_FFT.vhd |
|
9 | Linker_FFT.vhd | |
9 | lpp_fft.vhd |
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@@ -1,198 +1,199 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
6 |
|
6 | |||
7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | PACKAGE lpp_top_lfr_pkg IS |
|
15 | PACKAGE lpp_top_lfr_pkg IS | |
16 |
|
16 | |||
17 | COMPONENT lpp_top_acq |
|
17 | COMPONENT lpp_top_acq | |
18 | GENERIC( |
|
18 | GENERIC( | |
19 | tech : INTEGER := 0 |
|
19 | tech : INTEGER := 0 | |
20 | ); |
|
20 | ); | |
21 | PORT ( |
|
21 | PORT ( | |
22 | -- ADS7886 |
|
22 | -- ADS7886 | |
23 | cnv_run : IN STD_LOGIC; |
|
23 | cnv_run : IN STD_LOGIC; | |
24 | cnv : OUT STD_LOGIC; |
|
24 | cnv : OUT STD_LOGIC; | |
25 | sck : OUT STD_LOGIC; |
|
25 | sck : OUT STD_LOGIC; | |
26 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
26 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
27 | -- |
|
27 | -- | |
28 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
28 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
29 | cnv_rstn : IN STD_LOGIC; |
|
29 | cnv_rstn : IN STD_LOGIC; | |
30 | -- |
|
30 | -- | |
31 | clk : IN STD_LOGIC; -- 25 MHz |
|
31 | clk : IN STD_LOGIC; -- 25 MHz | |
32 | rstn : IN STD_LOGIC; |
|
32 | rstn : IN STD_LOGIC; | |
33 | -- |
|
33 | -- | |
34 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
35 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
35 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
36 | -- |
|
36 | -- | |
37 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
38 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
38 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
39 | -- |
|
39 | -- | |
40 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
40 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
41 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
41 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
42 | -- |
|
42 | -- | |
43 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
43 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
44 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
|
44 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
45 | ); |
|
45 | ); | |
46 | END COMPONENT; |
|
46 | END COMPONENT; | |
47 |
|
47 | |||
48 | COMPONENT lpp_top_apbreg |
|
48 | COMPONENT lpp_top_apbreg | |
49 | GENERIC ( |
|
49 | GENERIC ( | |
50 | nb_burst_available_size : INTEGER; |
|
50 | nb_burst_available_size : INTEGER; | |
51 | nb_snapshot_param_size : INTEGER; |
|
51 | nb_snapshot_param_size : INTEGER; | |
52 | delta_snapshot_size : INTEGER; |
|
52 | delta_snapshot_size : INTEGER; | |
53 | delta_f2_f0_size : INTEGER; |
|
53 | delta_f2_f0_size : INTEGER; | |
54 | delta_f2_f1_size : INTEGER; |
|
54 | delta_f2_f1_size : INTEGER; | |
55 | pindex : INTEGER; |
|
55 | pindex : INTEGER; | |
56 | paddr : INTEGER; |
|
56 | paddr : INTEGER; | |
57 | pmask : INTEGER; |
|
57 | pmask : INTEGER; | |
58 | pirq : INTEGER); |
|
58 | pirq : INTEGER); | |
59 | PORT ( |
|
59 | PORT ( | |
60 | HCLK : IN STD_ULOGIC; |
|
60 | HCLK : IN STD_ULOGIC; | |
61 | HRESETn : IN STD_ULOGIC; |
|
61 | HRESETn : IN STD_ULOGIC; | |
62 | apbi : IN apb_slv_in_type; |
|
62 | apbi : IN apb_slv_in_type; | |
63 | apbo : OUT apb_slv_out_type; |
|
63 | apbo : OUT apb_slv_out_type; | |
64 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
64 | ready_matrix_f0_0 : IN STD_LOGIC; | |
65 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
66 | ready_matrix_f1 : IN STD_LOGIC; |
|
66 | ready_matrix_f1 : IN STD_LOGIC; | |
67 | ready_matrix_f2 : IN STD_LOGIC; |
|
67 | ready_matrix_f2 : IN STD_LOGIC; | |
68 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
69 | error_bad_component_error : IN STD_LOGIC; |
|
69 | error_bad_component_error : IN STD_LOGIC; | |
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
71 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
72 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
72 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
73 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
73 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
74 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
74 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
75 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
75 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
76 | status_error_bad_component_error : OUT STD_LOGIC; |
|
76 | status_error_bad_component_error : OUT STD_LOGIC; | |
77 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
77 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
78 | config_active_interruption_onError : OUT STD_LOGIC; |
|
78 | config_active_interruption_onError : OUT STD_LOGIC; | |
79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
83 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
83 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
84 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
84 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
85 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
85 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
86 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
86 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
87 | data_shaping_BW : OUT STD_LOGIC; |
|
87 | data_shaping_BW : OUT STD_LOGIC; | |
88 | data_shaping_SP0 : OUT STD_LOGIC; |
|
88 | data_shaping_SP0 : OUT STD_LOGIC; | |
89 | data_shaping_SP1 : OUT STD_LOGIC; |
|
89 | data_shaping_SP1 : OUT STD_LOGIC; | |
90 | data_shaping_R0 : OUT STD_LOGIC; |
|
90 | data_shaping_R0 : OUT STD_LOGIC; | |
91 | data_shaping_R1 : OUT STD_LOGIC; |
|
91 | data_shaping_R1 : OUT STD_LOGIC; | |
92 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
92 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
93 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
93 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
94 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
94 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
95 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
95 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
96 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
96 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
97 | enable_f0 : OUT STD_LOGIC; |
|
97 | enable_f0 : OUT STD_LOGIC; | |
98 | enable_f1 : OUT STD_LOGIC; |
|
98 | enable_f1 : OUT STD_LOGIC; | |
99 | enable_f2 : OUT STD_LOGIC; |
|
99 | enable_f2 : OUT STD_LOGIC; | |
100 | enable_f3 : OUT STD_LOGIC; |
|
100 | enable_f3 : OUT STD_LOGIC; | |
101 | burst_f0 : OUT STD_LOGIC; |
|
101 | burst_f0 : OUT STD_LOGIC; | |
102 | burst_f1 : OUT STD_LOGIC; |
|
102 | burst_f1 : OUT STD_LOGIC; | |
103 | burst_f2 : OUT STD_LOGIC; |
|
103 | burst_f2 : OUT STD_LOGIC; | |
104 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
104 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
105 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
106 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
107 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
107 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
108 | END COMPONENT; |
|
108 | END COMPONENT; | |
109 |
|
109 | |||
110 | COMPONENT lpp_top_lfr_wf_picker |
|
110 | COMPONENT lpp_top_lfr_wf_picker | |
111 | GENERIC ( |
|
111 | GENERIC ( | |
112 | hindex : INTEGER; |
|
112 | hindex : INTEGER; | |
113 | pindex : INTEGER; |
|
113 | pindex : INTEGER; | |
114 | paddr : INTEGER; |
|
114 | paddr : INTEGER; | |
115 | pmask : INTEGER; |
|
115 | pmask : INTEGER; | |
116 | pirq : INTEGER; |
|
116 | pirq : INTEGER; | |
117 | tech : INTEGER; |
|
117 | tech : INTEGER; | |
118 | nb_burst_available_size : INTEGER; |
|
118 | nb_burst_available_size : INTEGER; | |
119 | nb_snapshot_param_size : INTEGER; |
|
119 | nb_snapshot_param_size : INTEGER; | |
120 | delta_snapshot_size : INTEGER; |
|
120 | delta_snapshot_size : INTEGER; | |
121 | delta_f2_f0_size : INTEGER; |
|
121 | delta_f2_f0_size : INTEGER; | |
122 | delta_f2_f1_size : INTEGER); |
|
122 | delta_f2_f1_size : INTEGER); | |
123 | PORT ( |
|
123 | PORT ( | |
124 | cnv_run : IN STD_LOGIC; |
|
124 | cnv_run : IN STD_LOGIC; | |
125 | cnv : OUT STD_LOGIC; |
|
125 | cnv : OUT STD_LOGIC; | |
126 | sck : OUT STD_LOGIC; |
|
126 | sck : OUT STD_LOGIC; | |
127 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
127 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
128 | cnv_clk : IN STD_LOGIC; |
|
128 | cnv_clk : IN STD_LOGIC; | |
129 | cnv_rstn : IN STD_LOGIC; |
|
129 | cnv_rstn : IN STD_LOGIC; | |
130 | HCLK : IN STD_ULOGIC; |
|
130 | HCLK : IN STD_ULOGIC; | |
131 | HRESETn : IN STD_ULOGIC; |
|
131 | HRESETn : IN STD_ULOGIC; | |
132 | apbi : IN apb_slv_in_type; |
|
132 | apbi : IN apb_slv_in_type; | |
133 | apbo : OUT apb_slv_out_type; |
|
133 | apbo : OUT apb_slv_out_type; | |
134 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
134 | AHB_Master_In : IN AHB_Mst_In_Type; | |
135 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
135 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
136 | coarse_time_0 : IN STD_LOGIC; |
|
136 | coarse_time_0 : IN STD_LOGIC; | |
137 | data_shaping_BW : OUT STD_LOGIC); |
|
137 | data_shaping_BW : OUT STD_LOGIC); | |
138 | END COMPONENT; |
|
138 | END COMPONENT; | |
139 |
|
139 | |||
140 |
|
140 | |||
141 | COMPONENT lpp_top_lfr_wf_picker_ip |
|
141 | COMPONENT lpp_top_lfr_wf_picker_ip | |
142 | GENERIC ( |
|
142 | GENERIC ( | |
143 | hindex : INTEGER; |
|
143 | hindex : INTEGER; | |
144 | nb_burst_available_size : INTEGER; |
|
144 | nb_burst_available_size : INTEGER; | |
145 | nb_snapshot_param_size : INTEGER; |
|
145 | nb_snapshot_param_size : INTEGER; | |
146 | delta_snapshot_size : INTEGER; |
|
146 | delta_snapshot_size : INTEGER; | |
147 | delta_f2_f0_size : INTEGER; |
|
147 | delta_f2_f0_size : INTEGER; | |
148 | delta_f2_f1_size : INTEGER; |
|
148 | delta_f2_f1_size : INTEGER; | |
149 |
tech : INTEGER |
|
149 | tech : INTEGER; | |
|
150 | Mem_use : INTEGER); | |||
150 | PORT ( |
|
151 | PORT ( | |
151 | cnv_run : IN STD_LOGIC; |
|
152 | cnv_run : IN STD_LOGIC; | |
152 | cnv : OUT STD_LOGIC; |
|
153 | cnv : OUT STD_LOGIC; | |
153 | sck : OUT STD_LOGIC; |
|
154 | sck : OUT STD_LOGIC; | |
154 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
155 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
155 | cnv_clk : IN STD_LOGIC; |
|
156 | cnv_clk : IN STD_LOGIC; | |
156 | cnv_rstn : IN STD_LOGIC; |
|
157 | cnv_rstn : IN STD_LOGIC; | |
157 | clk : IN STD_LOGIC; |
|
158 | clk : IN STD_LOGIC; | |
158 | rstn : IN STD_LOGIC; |
|
159 | rstn : IN STD_LOGIC; | |
159 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
160 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
160 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
161 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
161 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
162 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
162 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
163 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
163 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
164 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
164 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
165 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
165 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
166 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
166 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
167 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
167 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
168 | AHB_Master_In : IN AHB_Mst_In_Type; | |
168 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
169 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
169 | coarse_time_0 : IN STD_LOGIC; |
|
170 | coarse_time_0 : IN STD_LOGIC; | |
170 | data_shaping_SP0 : IN STD_LOGIC; |
|
171 | data_shaping_SP0 : IN STD_LOGIC; | |
171 | data_shaping_SP1 : IN STD_LOGIC; |
|
172 | data_shaping_SP1 : IN STD_LOGIC; | |
172 | data_shaping_R0 : IN STD_LOGIC; |
|
173 | data_shaping_R0 : IN STD_LOGIC; | |
173 | data_shaping_R1 : IN STD_LOGIC; |
|
174 | data_shaping_R1 : IN STD_LOGIC; | |
174 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
175 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
175 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
176 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
176 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
177 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
177 | enable_f0 : IN STD_LOGIC; |
|
178 | enable_f0 : IN STD_LOGIC; | |
178 | enable_f1 : IN STD_LOGIC; |
|
179 | enable_f1 : IN STD_LOGIC; | |
179 | enable_f2 : IN STD_LOGIC; |
|
180 | enable_f2 : IN STD_LOGIC; | |
180 | enable_f3 : IN STD_LOGIC; |
|
181 | enable_f3 : IN STD_LOGIC; | |
181 | burst_f0 : IN STD_LOGIC; |
|
182 | burst_f0 : IN STD_LOGIC; | |
182 | burst_f1 : IN STD_LOGIC; |
|
183 | burst_f1 : IN STD_LOGIC; | |
183 | burst_f2 : IN STD_LOGIC; |
|
184 | burst_f2 : IN STD_LOGIC; | |
184 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
185 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
185 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
186 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
186 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
187 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
187 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
188 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
188 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
189 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
189 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
190 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
190 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
191 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
192 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
193 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
194 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
194 | END COMPONENT; |
|
195 | END COMPONENT; | |
195 |
|
196 | |||
196 |
|
197 | |||
197 |
|
198 | |||
198 | END lpp_top_lfr_pkg; |
|
199 | END lpp_top_lfr_pkg; |
@@ -1,243 +1,245 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
11 | USE lpp.lpp_top_lfr_pkg.ALL; | |
12 |
|
12 | |||
13 | LIBRARY techmap; |
|
13 | LIBRARY techmap; | |
14 | USE techmap.gencomp.ALL; |
|
14 | USE techmap.gencomp.ALL; | |
15 |
|
15 | |||
16 | LIBRARY grlib; |
|
16 | LIBRARY grlib; | |
17 | USE grlib.amba.ALL; |
|
17 | USE grlib.amba.ALL; | |
18 | USE grlib.stdlib.ALL; |
|
18 | USE grlib.stdlib.ALL; | |
19 | USE grlib.devices.ALL; |
|
19 | USE grlib.devices.ALL; | |
20 | USE GRLIB.DMA2AHB_Package.ALL; |
|
20 | USE GRLIB.DMA2AHB_Package.ALL; | |
21 |
|
21 | |||
22 | ENTITY lpp_top_lfr_wf_picker IS |
|
22 | ENTITY lpp_top_lfr_wf_picker IS | |
23 | GENERIC ( |
|
23 | GENERIC ( | |
24 | hindex : INTEGER := 2; |
|
24 | hindex : INTEGER := 2; | |
25 | pindex : INTEGER := 4; |
|
25 | pindex : INTEGER := 4; | |
26 | paddr : INTEGER := 4; |
|
26 | paddr : INTEGER := 4; | |
27 | pmask : INTEGER := 16#fff#; |
|
27 | pmask : INTEGER := 16#fff#; | |
28 | pirq : INTEGER := 0; |
|
28 | pirq : INTEGER := 0; | |
29 | tech : INTEGER := 0; |
|
29 | tech : INTEGER := 0; | |
30 | nb_burst_available_size : INTEGER := 11; |
|
30 | nb_burst_available_size : INTEGER := 11; | |
31 | nb_snapshot_param_size : INTEGER := 11; |
|
31 | nb_snapshot_param_size : INTEGER := 11; | |
32 | delta_snapshot_size : INTEGER := 16; |
|
32 | delta_snapshot_size : INTEGER := 16; | |
33 | delta_f2_f0_size : INTEGER := 10; |
|
33 | delta_f2_f0_size : INTEGER := 10; | |
34 | delta_f2_f1_size : INTEGER := 10 |
|
34 | delta_f2_f1_size : INTEGER := 10 | |
35 | ); |
|
35 | ); | |
36 | PORT ( |
|
36 | PORT ( | |
37 | -- ADS7886 |
|
37 | -- ADS7886 | |
38 | cnv_run : IN STD_LOGIC; |
|
38 | cnv_run : IN STD_LOGIC; | |
39 | cnv : OUT STD_LOGIC; |
|
39 | cnv : OUT STD_LOGIC; | |
40 | sck : OUT STD_LOGIC; |
|
40 | sck : OUT STD_LOGIC; | |
41 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
41 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
42 | -- |
|
42 | -- | |
43 | cnv_clk : IN STD_LOGIC; |
|
43 | cnv_clk : IN STD_LOGIC; | |
44 | cnv_rstn : IN STD_LOGIC; |
|
44 | cnv_rstn : IN STD_LOGIC; | |
45 |
|
45 | |||
46 | -- AMBA AHB system signals |
|
46 | -- AMBA AHB system signals | |
47 | HCLK : IN STD_ULOGIC; |
|
47 | HCLK : IN STD_ULOGIC; | |
48 | HRESETn : IN STD_ULOGIC; |
|
48 | HRESETn : IN STD_ULOGIC; | |
49 |
|
49 | |||
50 | -- AMBA APB Slave Interface |
|
50 | -- AMBA APB Slave Interface | |
51 | apbi : IN apb_slv_in_type; |
|
51 | apbi : IN apb_slv_in_type; | |
52 | apbo : OUT apb_slv_out_type; |
|
52 | apbo : OUT apb_slv_out_type; | |
53 |
|
53 | |||
54 | -- AMBA AHB Master Interface |
|
54 | -- AMBA AHB Master Interface | |
55 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
55 | AHB_Master_In : IN AHB_Mst_In_Type; | |
56 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
56 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
57 |
|
57 | |||
58 | -- |
|
58 | -- | |
59 | coarse_time_0 : IN STD_LOGIC; |
|
59 | coarse_time_0 : IN STD_LOGIC; | |
60 |
|
60 | |||
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC |
|
62 | data_shaping_BW : OUT STD_LOGIC | |
63 | ); |
|
63 | ); | |
64 | END lpp_top_lfr_wf_picker; |
|
64 | END lpp_top_lfr_wf_picker; | |
65 |
|
65 | |||
66 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS |
|
66 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS | |
67 |
|
67 | |||
68 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
68 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
69 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
69 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
70 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
70 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
71 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
71 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
72 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
72 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
73 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
73 | SIGNAL error_bad_component_error : STD_LOGIC; | |
74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
75 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
75 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
76 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
76 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
79 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
79 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
80 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
80 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
82 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
82 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
83 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
84 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 |
|
87 | |||
88 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
88 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
89 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
89 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
90 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
90 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
91 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
91 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
92 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
92 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
93 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
93 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
94 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
94 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
95 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
95 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
96 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
96 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
97 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
97 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
98 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
98 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
99 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
99 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
100 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
100 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
101 | SIGNAL enable_f0 : STD_LOGIC; |
|
101 | SIGNAL enable_f0 : STD_LOGIC; | |
102 | SIGNAL enable_f1 : STD_LOGIC; |
|
102 | SIGNAL enable_f1 : STD_LOGIC; | |
103 | SIGNAL enable_f2 : STD_LOGIC; |
|
103 | SIGNAL enable_f2 : STD_LOGIC; | |
104 | SIGNAL enable_f3 : STD_LOGIC; |
|
104 | SIGNAL enable_f3 : STD_LOGIC; | |
105 | SIGNAL burst_f0 : STD_LOGIC; |
|
105 | SIGNAL burst_f0 : STD_LOGIC; | |
106 | SIGNAL burst_f1 : STD_LOGIC; |
|
106 | SIGNAL burst_f1 : STD_LOGIC; | |
107 | SIGNAL burst_f2 : STD_LOGIC; |
|
107 | SIGNAL burst_f2 : STD_LOGIC; | |
108 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
109 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
109 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
110 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
110 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
111 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
111 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
112 |
|
112 | |||
113 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
113 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
114 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
114 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
115 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
115 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
116 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
116 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
117 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
117 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
118 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
118 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
120 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
120 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
121 |
|
121 | |||
122 |
|
122 | |||
123 | BEGIN |
|
123 | BEGIN | |
124 |
|
124 | |||
125 | lpp_top_apbreg_1: lpp_top_apbreg |
|
125 | lpp_top_apbreg_1: lpp_top_apbreg | |
126 | GENERIC MAP ( |
|
126 | GENERIC MAP ( | |
127 | nb_burst_available_size => nb_burst_available_size, |
|
127 | nb_burst_available_size => nb_burst_available_size, | |
128 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
128 | nb_snapshot_param_size => nb_snapshot_param_size, | |
129 | delta_snapshot_size => delta_snapshot_size, |
|
129 | delta_snapshot_size => delta_snapshot_size, | |
130 | delta_f2_f0_size => delta_f2_f0_size, |
|
130 | delta_f2_f0_size => delta_f2_f0_size, | |
131 | delta_f2_f1_size => delta_f2_f1_size, |
|
131 | delta_f2_f1_size => delta_f2_f1_size, | |
132 | pindex => pindex, |
|
132 | pindex => pindex, | |
133 | paddr => paddr, |
|
133 | paddr => paddr, | |
134 | pmask => pmask, |
|
134 | pmask => pmask, | |
135 | pirq => pirq) |
|
135 | pirq => pirq) | |
136 | PORT MAP ( |
|
136 | PORT MAP ( | |
137 | HCLK => HCLK, |
|
137 | HCLK => HCLK, | |
138 | HRESETn => HRESETn, |
|
138 | HRESETn => HRESETn, | |
139 | apbi => apbi, |
|
139 | apbi => apbi, | |
140 | apbo => apbo, |
|
140 | apbo => apbo, | |
141 |
|
141 | |||
142 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
142 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
143 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
143 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
144 | ready_matrix_f1 => ready_matrix_f1, |
|
144 | ready_matrix_f1 => ready_matrix_f1, | |
145 | ready_matrix_f2 => ready_matrix_f2, |
|
145 | ready_matrix_f2 => ready_matrix_f2, | |
146 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
146 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
147 | error_bad_component_error => error_bad_component_error, |
|
147 | error_bad_component_error => error_bad_component_error, | |
148 | debug_reg => debug_reg, |
|
148 | debug_reg => debug_reg, | |
149 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
149 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
150 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
150 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
151 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
151 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
152 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
152 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
153 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
153 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
154 | status_error_bad_component_error => status_error_bad_component_error, |
|
154 | status_error_bad_component_error => status_error_bad_component_error, | |
155 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
155 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
156 | config_active_interruption_onError => config_active_interruption_onError, |
|
156 | config_active_interruption_onError => config_active_interruption_onError, | |
157 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
157 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
158 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
158 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
159 | addr_matrix_f1 => addr_matrix_f1, |
|
159 | addr_matrix_f1 => addr_matrix_f1, | |
160 | addr_matrix_f2 => addr_matrix_f2, |
|
160 | addr_matrix_f2 => addr_matrix_f2, | |
161 |
|
161 | |||
162 | status_full => status_full, |
|
162 | status_full => status_full, | |
163 | status_full_ack => status_full_ack, |
|
163 | status_full_ack => status_full_ack, | |
164 | status_full_err => status_full_err, |
|
164 | status_full_err => status_full_err, | |
165 | status_new_err => status_new_err, |
|
165 | status_new_err => status_new_err, | |
166 | data_shaping_BW => data_shaping_BW, |
|
166 | data_shaping_BW => data_shaping_BW, | |
167 | data_shaping_SP0 => data_shaping_SP0, |
|
167 | data_shaping_SP0 => data_shaping_SP0, | |
168 | data_shaping_SP1 => data_shaping_SP1, |
|
168 | data_shaping_SP1 => data_shaping_SP1, | |
169 | data_shaping_R0 => data_shaping_R0, |
|
169 | data_shaping_R0 => data_shaping_R0, | |
170 | data_shaping_R1 => data_shaping_R1, |
|
170 | data_shaping_R1 => data_shaping_R1, | |
171 | delta_snapshot => delta_snapshot, |
|
171 | delta_snapshot => delta_snapshot, | |
172 | delta_f2_f1 => delta_f2_f1, |
|
172 | delta_f2_f1 => delta_f2_f1, | |
173 | delta_f2_f0 => delta_f2_f0, |
|
173 | delta_f2_f0 => delta_f2_f0, | |
174 | nb_burst_available => nb_burst_available, |
|
174 | nb_burst_available => nb_burst_available, | |
175 | nb_snapshot_param => nb_snapshot_param, |
|
175 | nb_snapshot_param => nb_snapshot_param, | |
176 | enable_f0 => enable_f0, |
|
176 | enable_f0 => enable_f0, | |
177 | enable_f1 => enable_f1, |
|
177 | enable_f1 => enable_f1, | |
178 | enable_f2 => enable_f2, |
|
178 | enable_f2 => enable_f2, | |
179 | enable_f3 => enable_f3, |
|
179 | enable_f3 => enable_f3, | |
180 | burst_f0 => burst_f0, |
|
180 | burst_f0 => burst_f0, | |
181 | burst_f1 => burst_f1, |
|
181 | burst_f1 => burst_f1, | |
182 | burst_f2 => burst_f2, |
|
182 | burst_f2 => burst_f2, | |
183 | addr_data_f0 => addr_data_f0, |
|
183 | addr_data_f0 => addr_data_f0, | |
184 | addr_data_f1 => addr_data_f1, |
|
184 | addr_data_f1 => addr_data_f1, | |
185 | addr_data_f2 => addr_data_f2, |
|
185 | addr_data_f2 => addr_data_f2, | |
186 | addr_data_f3 => addr_data_f3); |
|
186 | addr_data_f3 => addr_data_f3); | |
187 |
|
187 | |||
188 | lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip |
|
188 | lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip | |
189 | GENERIC MAP ( |
|
189 | GENERIC MAP ( | |
190 | hindex => hindex, |
|
190 | hindex => hindex, | |
191 | nb_burst_available_size => nb_burst_available_size, |
|
191 | nb_burst_available_size => nb_burst_available_size, | |
192 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
192 | nb_snapshot_param_size => nb_snapshot_param_size, | |
193 | delta_snapshot_size => delta_snapshot_size, |
|
193 | delta_snapshot_size => delta_snapshot_size, | |
194 | delta_f2_f0_size => delta_f2_f0_size, |
|
194 | delta_f2_f0_size => delta_f2_f0_size, | |
195 | delta_f2_f1_size => delta_f2_f1_size, |
|
195 | delta_f2_f1_size => delta_f2_f1_size, | |
196 |
tech => tech |
|
196 | tech => tech, | |
|
197 | Mem_use => use_RAM | |||
|
198 | ) | |||
197 | PORT MAP ( |
|
199 | PORT MAP ( | |
198 | cnv_run => cnv_run, |
|
200 | cnv_run => cnv_run, | |
199 | cnv => cnv, |
|
201 | cnv => cnv, | |
200 | sck => sck, |
|
202 | sck => sck, | |
201 | sdo => sdo, |
|
203 | sdo => sdo, | |
202 | cnv_clk => cnv_clk, |
|
204 | cnv_clk => cnv_clk, | |
203 | cnv_rstn => cnv_rstn, |
|
205 | cnv_rstn => cnv_rstn, | |
204 |
|
206 | |||
205 | clk => HCLK, |
|
207 | clk => HCLK, | |
206 | rstn => HRESETn, |
|
208 | rstn => HRESETn, | |
207 |
|
209 | |||
208 | sample_f0_wen => sample_f0_wen, |
|
210 | sample_f0_wen => sample_f0_wen, | |
209 | sample_f0_wdata => sample_f0_wdata, |
|
211 | sample_f0_wdata => sample_f0_wdata, | |
210 | sample_f1_wen => sample_f1_wen, |
|
212 | sample_f1_wen => sample_f1_wen, | |
211 | sample_f1_wdata => sample_f1_wdata, |
|
213 | sample_f1_wdata => sample_f1_wdata, | |
212 | sample_f2_wen => sample_f2_wen, |
|
214 | sample_f2_wen => sample_f2_wen, | |
213 | sample_f2_wdata => sample_f2_wdata, |
|
215 | sample_f2_wdata => sample_f2_wdata, | |
214 | sample_f3_wen => sample_f3_wen, |
|
216 | sample_f3_wen => sample_f3_wen, | |
215 | sample_f3_wdata => sample_f3_wdata, |
|
217 | sample_f3_wdata => sample_f3_wdata, | |
216 | AHB_Master_In => AHB_Master_In, |
|
218 | AHB_Master_In => AHB_Master_In, | |
217 | AHB_Master_Out => AHB_Master_Out, |
|
219 | AHB_Master_Out => AHB_Master_Out, | |
218 | coarse_time_0 => coarse_time_0, |
|
220 | coarse_time_0 => coarse_time_0, | |
219 | data_shaping_SP0 => data_shaping_SP0, |
|
221 | data_shaping_SP0 => data_shaping_SP0, | |
220 | data_shaping_SP1 => data_shaping_SP1, |
|
222 | data_shaping_SP1 => data_shaping_SP1, | |
221 | data_shaping_R0 => data_shaping_R0, |
|
223 | data_shaping_R0 => data_shaping_R0, | |
222 | data_shaping_R1 => data_shaping_R1, |
|
224 | data_shaping_R1 => data_shaping_R1, | |
223 | delta_snapshot => delta_snapshot, |
|
225 | delta_snapshot => delta_snapshot, | |
224 | delta_f2_f1 => delta_f2_f1, |
|
226 | delta_f2_f1 => delta_f2_f1, | |
225 | delta_f2_f0 => delta_f2_f0, |
|
227 | delta_f2_f0 => delta_f2_f0, | |
226 | enable_f0 => enable_f0, |
|
228 | enable_f0 => enable_f0, | |
227 | enable_f1 => enable_f1, |
|
229 | enable_f1 => enable_f1, | |
228 | enable_f2 => enable_f2, |
|
230 | enable_f2 => enable_f2, | |
229 | enable_f3 => enable_f3, |
|
231 | enable_f3 => enable_f3, | |
230 | burst_f0 => burst_f0, |
|
232 | burst_f0 => burst_f0, | |
231 | burst_f1 => burst_f1, |
|
233 | burst_f1 => burst_f1, | |
232 | burst_f2 => burst_f2, |
|
234 | burst_f2 => burst_f2, | |
233 | nb_burst_available => nb_burst_available, |
|
235 | nb_burst_available => nb_burst_available, | |
234 | nb_snapshot_param => nb_snapshot_param, |
|
236 | nb_snapshot_param => nb_snapshot_param, | |
235 | status_full => status_full, |
|
237 | status_full => status_full, | |
236 | status_full_ack => status_full_ack, |
|
238 | status_full_ack => status_full_ack, | |
237 | status_full_err => status_full_err, |
|
239 | status_full_err => status_full_err, | |
238 | status_new_err => status_new_err, |
|
240 | status_new_err => status_new_err, | |
239 | addr_data_f0 => addr_data_f0, |
|
241 | addr_data_f0 => addr_data_f0, | |
240 | addr_data_f1 => addr_data_f1, |
|
242 | addr_data_f1 => addr_data_f1, | |
241 | addr_data_f2 => addr_data_f2, |
|
243 | addr_data_f2 => addr_data_f2, | |
242 | addr_data_f3 => addr_data_f3); |
|
244 | addr_data_f3 => addr_data_f3); | |
243 | END tb; |
|
245 | END tb; |
@@ -1,502 +1,505 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
11 |
|
11 | |||
12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
14 |
|
14 | |||
15 | LIBRARY grlib; |
|
15 | LIBRARY grlib; | |
16 | USE grlib.amba.ALL; |
|
16 | USE grlib.amba.ALL; | |
17 | USE grlib.stdlib.ALL; |
|
17 | USE grlib.stdlib.ALL; | |
18 | USE grlib.devices.ALL; |
|
18 | USE grlib.devices.ALL; | |
19 | USE GRLIB.DMA2AHB_Package.ALL; |
|
19 | USE GRLIB.DMA2AHB_Package.ALL; | |
20 |
|
20 | |||
21 | ENTITY lpp_top_lfr_wf_picker_ip IS |
|
21 | ENTITY lpp_top_lfr_wf_picker_ip IS | |
22 | GENERIC( |
|
22 | GENERIC( | |
23 | hindex : INTEGER := 2; |
|
23 | hindex : INTEGER := 2; | |
24 | nb_burst_available_size : INTEGER := 11; |
|
24 | nb_burst_available_size : INTEGER := 11; | |
25 | nb_snapshot_param_size : INTEGER := 11; |
|
25 | nb_snapshot_param_size : INTEGER := 11; | |
26 | delta_snapshot_size : INTEGER := 16; |
|
26 | delta_snapshot_size : INTEGER := 16; | |
27 | delta_f2_f0_size : INTEGER := 10; |
|
27 | delta_f2_f0_size : INTEGER := 10; | |
28 | delta_f2_f1_size : INTEGER := 10; |
|
28 | delta_f2_f1_size : INTEGER := 10; | |
29 | tech : INTEGER := 0 |
|
29 | tech : INTEGER := 0; | |
|
30 | Mem_use : INTEGER := use_RAM | |||
30 | ); |
|
31 | ); | |
31 | PORT ( |
|
32 | PORT ( | |
32 | -- ADS7886 |
|
33 | -- ADS7886 | |
33 | cnv_run : IN STD_LOGIC; |
|
34 | cnv_run : IN STD_LOGIC; | |
34 | cnv : OUT STD_LOGIC; |
|
35 | cnv : OUT STD_LOGIC; | |
35 | sck : OUT STD_LOGIC; |
|
36 | sck : OUT STD_LOGIC; | |
36 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
37 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
37 | -- |
|
38 | -- | |
38 | cnv_clk : IN STD_LOGIC; |
|
39 | cnv_clk : IN STD_LOGIC; | |
39 | cnv_rstn : IN STD_LOGIC; |
|
40 | cnv_rstn : IN STD_LOGIC; | |
40 | -- |
|
41 | -- | |
41 | clk : IN STD_LOGIC; |
|
42 | clk : IN STD_LOGIC; | |
42 | rstn : IN STD_LOGIC; |
|
43 | rstn : IN STD_LOGIC; | |
43 | -- |
|
44 | -- | |
44 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
45 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
45 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
46 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
46 | -- |
|
47 | -- | |
47 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
48 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
48 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
49 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
49 | -- |
|
50 | -- | |
50 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
51 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
51 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
52 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
52 | -- |
|
53 | -- | |
53 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
54 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); | |
54 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
55 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
55 |
|
56 | |||
56 | -- AMBA AHB Master Interface |
|
57 | -- AMBA AHB Master Interface | |
57 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
58 | AHB_Master_In : IN AHB_Mst_In_Type; | |
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
59 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
59 |
|
60 | |||
60 | coarse_time_0 : IN STD_LOGIC; |
|
61 | coarse_time_0 : IN STD_LOGIC; | |
61 |
|
62 | |||
62 | --config |
|
63 | --config | |
63 | data_shaping_SP0 : IN STD_LOGIC; |
|
64 | data_shaping_SP0 : IN STD_LOGIC; | |
64 | data_shaping_SP1 : IN STD_LOGIC; |
|
65 | data_shaping_SP1 : IN STD_LOGIC; | |
65 | data_shaping_R0 : IN STD_LOGIC; |
|
66 | data_shaping_R0 : IN STD_LOGIC; | |
66 | data_shaping_R1 : IN STD_LOGIC; |
|
67 | data_shaping_R1 : IN STD_LOGIC; | |
67 |
|
68 | |||
68 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
69 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
69 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
70 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
70 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
71 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
71 |
|
72 | |||
72 | enable_f0 : IN STD_LOGIC; |
|
73 | enable_f0 : IN STD_LOGIC; | |
73 | enable_f1 : IN STD_LOGIC; |
|
74 | enable_f1 : IN STD_LOGIC; | |
74 | enable_f2 : IN STD_LOGIC; |
|
75 | enable_f2 : IN STD_LOGIC; | |
75 | enable_f3 : IN STD_LOGIC; |
|
76 | enable_f3 : IN STD_LOGIC; | |
76 |
|
77 | |||
77 | burst_f0 : IN STD_LOGIC; |
|
78 | burst_f0 : IN STD_LOGIC; | |
78 | burst_f1 : IN STD_LOGIC; |
|
79 | burst_f1 : IN STD_LOGIC; | |
79 | burst_f2 : IN STD_LOGIC; |
|
80 | burst_f2 : IN STD_LOGIC; | |
80 |
|
81 | |||
81 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
82 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
82 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
83 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
83 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
84 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
84 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
85 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
85 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
86 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
86 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
|
87 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
87 |
|
88 | |||
88 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
89 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
92 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
92 | ); |
|
93 | ); | |
93 | END lpp_top_lfr_wf_picker_ip; |
|
94 | END lpp_top_lfr_wf_picker_ip; | |
94 |
|
95 | |||
95 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS |
|
96 | ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS | |
96 |
|
97 | |||
97 | COMPONENT Downsampling |
|
98 | COMPONENT Downsampling | |
98 | GENERIC ( |
|
99 | GENERIC ( | |
99 | ChanelCount : INTEGER; |
|
100 | ChanelCount : INTEGER; | |
100 | SampleSize : INTEGER; |
|
101 | SampleSize : INTEGER; | |
101 | DivideParam : INTEGER); |
|
102 | DivideParam : INTEGER); | |
102 | PORT ( |
|
103 | PORT ( | |
103 | clk : IN STD_LOGIC; |
|
104 | clk : IN STD_LOGIC; | |
104 | rstn : IN STD_LOGIC; |
|
105 | rstn : IN STD_LOGIC; | |
105 | sample_in_val : IN STD_LOGIC; |
|
106 | sample_in_val : IN STD_LOGIC; | |
106 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
107 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
107 | sample_out_val : OUT STD_LOGIC; |
|
108 | sample_out_val : OUT STD_LOGIC; | |
108 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
109 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
109 | END COMPONENT; |
|
110 | END COMPONENT; | |
110 |
|
111 | |||
111 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
112 | CONSTANT ChanelCount : INTEGER := 8; |
|
113 | CONSTANT ChanelCount : INTEGER := 8; | |
113 | CONSTANT ncycle_cnv_high : INTEGER := 79; |
|
114 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
114 | CONSTANT ncycle_cnv : INTEGER := 500; |
|
115 | CONSTANT ncycle_cnv : INTEGER := 500; | |
115 |
|
116 | |||
116 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
117 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); |
|
118 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
118 | SIGNAL sample_val : STD_LOGIC; |
|
119 | SIGNAL sample_val : STD_LOGIC; | |
119 | SIGNAL sample_val_delay : STD_LOGIC; |
|
120 | SIGNAL sample_val_delay : STD_LOGIC; | |
120 | ----------------------------------------------------------------------------- |
|
121 | ----------------------------------------------------------------------------- | |
121 | CONSTANT Coef_SZ : INTEGER := 9; |
|
122 | CONSTANT Coef_SZ : INTEGER := 9; | |
122 | CONSTANT CoefCntPerCel : INTEGER := 6; |
|
123 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
123 | CONSTANT CoefPerCel : INTEGER := 5; |
|
124 | CONSTANT CoefPerCel : INTEGER := 5; | |
124 | CONSTANT Cels_count : INTEGER := 5; |
|
125 | CONSTANT Cels_count : INTEGER := 5; | |
125 |
|
126 | |||
126 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); |
|
127 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |
127 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
128 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
128 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
129 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
129 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
130 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
130 | -- |
|
131 | -- | |
131 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
132 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
132 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
133 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
133 | ----------------------------------------------------------------------------- |
|
134 | ----------------------------------------------------------------------------- | |
134 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; |
|
135 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; | |
135 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
136 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
136 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
137 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
137 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
138 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
138 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
139 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
139 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
140 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
140 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); |
|
141 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |
141 | ----------------------------------------------------------------------------- |
|
142 | ----------------------------------------------------------------------------- | |
142 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; |
|
143 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; | |
143 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
144 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
144 | ----------------------------------------------------------------------------- |
|
145 | ----------------------------------------------------------------------------- | |
145 | SIGNAL sample_f0_val : STD_LOGIC; |
|
146 | SIGNAL sample_f0_val : STD_LOGIC; | |
146 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
147 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
147 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
148 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
148 | -- |
|
149 | -- | |
149 | SIGNAL sample_f1_val : STD_LOGIC; |
|
150 | SIGNAL sample_f1_val : STD_LOGIC; | |
150 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); |
|
151 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |
151 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
152 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
152 | -- |
|
153 | -- | |
153 | SIGNAL sample_f2_val : STD_LOGIC; |
|
154 | SIGNAL sample_f2_val : STD_LOGIC; | |
154 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
155 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
155 | -- |
|
156 | -- | |
156 | SIGNAL sample_f3_val : STD_LOGIC; |
|
157 | SIGNAL sample_f3_val : STD_LOGIC; | |
157 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); |
|
158 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |
158 |
|
159 | |||
159 | ----------------------------------------------------------------------------- |
|
160 | ----------------------------------------------------------------------------- | |
160 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
161 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
161 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
162 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
162 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
163 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
163 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); |
|
164 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |
164 | ----------------------------------------------------------------------------- |
|
165 | ----------------------------------------------------------------------------- | |
165 |
|
166 | |||
166 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
167 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
167 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
168 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
168 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
169 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
169 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
170 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
170 | BEGIN |
|
171 | BEGIN | |
171 |
|
172 | |||
172 | -- component instantiation |
|
173 | -- component instantiation | |
173 | ----------------------------------------------------------------------------- |
|
174 | ----------------------------------------------------------------------------- | |
174 | DIGITAL_acquisition : AD7688_drvr |
|
175 | DIGITAL_acquisition : AD7688_drvr | |
175 | GENERIC MAP ( |
|
176 | GENERIC MAP ( | |
176 | ChanelCount => ChanelCount, |
|
177 | ChanelCount => ChanelCount, | |
177 | ncycle_cnv_high => ncycle_cnv_high, |
|
178 | ncycle_cnv_high => ncycle_cnv_high, | |
178 | ncycle_cnv => ncycle_cnv) |
|
179 | ncycle_cnv => ncycle_cnv) | |
179 | PORT MAP ( |
|
180 | PORT MAP ( | |
180 | cnv_clk => cnv_clk, -- |
|
181 | cnv_clk => cnv_clk, -- | |
181 | cnv_rstn => cnv_rstn, -- |
|
182 | cnv_rstn => cnv_rstn, -- | |
182 | cnv_run => cnv_run, -- |
|
183 | cnv_run => cnv_run, -- | |
183 | cnv => cnv, -- |
|
184 | cnv => cnv, -- | |
184 | clk => clk, -- |
|
185 | clk => clk, -- | |
185 | rstn => rstn, -- |
|
186 | rstn => rstn, -- | |
186 | sck => sck, -- |
|
187 | sck => sck, -- | |
187 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
|
188 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
188 | sample => sample, |
|
189 | sample => sample, | |
189 | sample_val => sample_val); |
|
190 | sample_val => sample_val); | |
190 |
|
191 | |||
191 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
192 |
|
193 | |||
193 | PROCESS (clk, rstn) |
|
194 | PROCESS (clk, rstn) | |
194 | BEGIN -- PROCESS |
|
195 | BEGIN -- PROCESS | |
195 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
196 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
196 | sample_val_delay <= '0'; |
|
197 | sample_val_delay <= '0'; | |
197 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
198 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
198 | sample_val_delay <= sample_val; |
|
199 | sample_val_delay <= sample_val; | |
199 | END IF; |
|
200 | END IF; | |
200 | END PROCESS; |
|
201 | END PROCESS; | |
201 |
|
202 | |||
202 | ----------------------------------------------------------------------------- |
|
203 | ----------------------------------------------------------------------------- | |
203 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
204 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
204 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
205 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
205 | sample_filter_in(i, j) <= sample(i)(j); |
|
206 | sample_filter_in(i, j) <= sample(i)(j); | |
206 | END GENERATE; |
|
207 | END GENERATE; | |
207 |
|
208 | |||
208 | sample_filter_in(i, 16) <= sample(i)(15); |
|
209 | sample_filter_in(i, 16) <= sample(i)(15); | |
209 | sample_filter_in(i, 17) <= sample(i)(15); |
|
210 | sample_filter_in(i, 17) <= sample(i)(15); | |
210 | END GENERATE; |
|
211 | END GENERATE; | |
211 |
|
212 | |||
212 | coefs_v2 <= CoefsInitValCst_v2; |
|
213 | coefs_v2 <= CoefsInitValCst_v2; | |
213 |
|
214 | |||
214 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
215 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
215 | GENERIC MAP ( |
|
216 | GENERIC MAP ( | |
216 | tech => 0, |
|
217 | tech => 0, | |
217 |
Mem_use => use |
|
218 | Mem_use => Mem_use, -- use_RAM | |
218 | Sample_SZ => 18, |
|
219 | Sample_SZ => 18, | |
219 | Coef_SZ => Coef_SZ, |
|
220 | Coef_SZ => Coef_SZ, | |
220 | Coef_Nb => 25, |
|
221 | Coef_Nb => 25, | |
221 | Coef_sel_SZ => 5, |
|
222 | Coef_sel_SZ => 5, | |
222 | Cels_count => Cels_count, |
|
223 | Cels_count => Cels_count, | |
223 | ChanelsCount => ChanelCount) |
|
224 | ChanelsCount => ChanelCount) | |
224 | PORT MAP ( |
|
225 | PORT MAP ( | |
225 | rstn => rstn, |
|
226 | rstn => rstn, | |
226 | clk => clk, |
|
227 | clk => clk, | |
227 | virg_pos => 7, |
|
228 | virg_pos => 7, | |
228 | coefs => coefs_v2, |
|
229 | coefs => coefs_v2, | |
229 | sample_in_val => sample_val_delay, |
|
230 | sample_in_val => sample_val_delay, | |
230 | sample_in => sample_filter_in, |
|
231 | sample_in => sample_filter_in, | |
231 | sample_out_val => sample_filter_v2_out_val, |
|
232 | sample_out_val => sample_filter_v2_out_val, | |
232 | sample_out => sample_filter_v2_out); |
|
233 | sample_out => sample_filter_v2_out); | |
233 |
|
234 | |||
234 | ----------------------------------------------------------------------------- |
|
235 | ----------------------------------------------------------------------------- | |
235 | -- DATA_SHAPING |
|
236 | -- DATA_SHAPING | |
236 | ----------------------------------------------------------------------------- |
|
237 | ----------------------------------------------------------------------------- | |
237 | all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE |
|
238 | all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE | |
238 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); |
|
239 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); | |
239 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); |
|
240 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); | |
240 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); |
|
241 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); | |
241 | END GENERATE all_data_shaping_in_loop; |
|
242 | END GENERATE all_data_shaping_in_loop; | |
242 |
|
243 | |||
243 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; |
|
244 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; | |
244 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; |
|
245 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; | |
245 |
|
246 | |||
246 | PROCESS (clk, rstn) |
|
247 | PROCESS (clk, rstn) | |
247 | BEGIN -- PROCESS |
|
248 | BEGIN -- PROCESS | |
248 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
249 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
249 | sample_data_shaping_out_val <= '0'; |
|
250 | sample_data_shaping_out_val <= '0'; | |
250 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
251 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
251 | sample_data_shaping_out_val <= sample_filter_v2_out_val; |
|
252 | sample_data_shaping_out_val <= sample_filter_v2_out_val; | |
252 | END IF; |
|
253 | END IF; | |
253 | END PROCESS; |
|
254 | END PROCESS; | |
254 |
|
255 | |||
255 | SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE |
|
256 | SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE | |
256 | PROCESS (clk, rstn) |
|
257 | PROCESS (clk, rstn) | |
257 | BEGIN |
|
258 | BEGIN | |
258 | IF rstn = '0' THEN |
|
259 | IF rstn = '0' THEN | |
259 | sample_data_shaping_out(0,j) <= '0'; |
|
260 | sample_data_shaping_out(0,j) <= '0'; | |
260 | sample_data_shaping_out(1,j) <= '0'; |
|
261 | sample_data_shaping_out(1,j) <= '0'; | |
261 | sample_data_shaping_out(2,j) <= '0'; |
|
262 | sample_data_shaping_out(2,j) <= '0'; | |
262 | sample_data_shaping_out(3,j) <= '0'; |
|
263 | sample_data_shaping_out(3,j) <= '0'; | |
263 | sample_data_shaping_out(4,j) <= '0'; |
|
264 | sample_data_shaping_out(4,j) <= '0'; | |
264 | sample_data_shaping_out(5,j) <= '0'; |
|
265 | sample_data_shaping_out(5,j) <= '0'; | |
265 | sample_data_shaping_out(6,j) <= '0'; |
|
266 | sample_data_shaping_out(6,j) <= '0'; | |
266 | sample_data_shaping_out(7,j) <= '0'; |
|
267 | sample_data_shaping_out(7,j) <= '0'; | |
267 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
268 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
268 | sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); |
|
269 | sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); | |
269 | IF data_shaping_SP0 = '1' THEN |
|
270 | IF data_shaping_SP0 = '1' THEN | |
270 | sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); |
|
271 | sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); | |
271 | ELSE |
|
272 | ELSE | |
272 | sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); |
|
273 | sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); | |
273 | END IF; |
|
274 | END IF; | |
274 | IF data_shaping_SP1 = '1' THEN |
|
275 | IF data_shaping_SP1 = '1' THEN | |
275 | sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); |
|
276 | sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); | |
276 | ELSE |
|
277 | ELSE | |
277 | sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); |
|
278 | sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); | |
278 | END IF; |
|
279 | END IF; | |
279 | sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); |
|
280 | sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); | |
280 | sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); |
|
281 | sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); | |
281 | sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); |
|
282 | sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); | |
282 | sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); |
|
283 | sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); | |
283 | END IF; |
|
284 | END IF; | |
284 | END PROCESS; |
|
285 | END PROCESS; | |
285 | END GENERATE; |
|
286 | END GENERATE; | |
286 |
|
287 | |||
287 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; |
|
288 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; | |
288 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE |
|
289 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE | |
289 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE |
|
290 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |
290 | sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); |
|
291 | sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); | |
291 | END GENERATE; |
|
292 | END GENERATE; | |
292 | END GENERATE; |
|
293 | END GENERATE; | |
293 | ----------------------------------------------------------------------------- |
|
294 | ----------------------------------------------------------------------------- | |
294 | -- F0 -- @24.576 kHz |
|
295 | -- F0 -- @24.576 kHz | |
295 | ----------------------------------------------------------------------------- |
|
296 | ----------------------------------------------------------------------------- | |
296 | Downsampling_f0 : Downsampling |
|
297 | Downsampling_f0 : Downsampling | |
297 | GENERIC MAP ( |
|
298 | GENERIC MAP ( | |
298 | ChanelCount => 8, |
|
299 | ChanelCount => 8, | |
299 | SampleSize => 16, |
|
300 | SampleSize => 16, | |
300 | DivideParam => 4) |
|
301 | DivideParam => 4) | |
301 | PORT MAP ( |
|
302 | PORT MAP ( | |
302 | clk => clk, |
|
303 | clk => clk, | |
303 | rstn => rstn, |
|
304 | rstn => rstn, | |
304 | sample_in_val => sample_filter_v2_out_val_s, |
|
305 | sample_in_val => sample_filter_v2_out_val_s, | |
305 | sample_in => sample_filter_v2_out_s, |
|
306 | sample_in => sample_filter_v2_out_s, | |
306 | sample_out_val => sample_f0_val, |
|
307 | sample_out_val => sample_f0_val, | |
307 | sample_out => sample_f0); |
|
308 | sample_out => sample_f0); | |
308 |
|
309 | |||
309 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
310 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
310 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V |
|
311 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V | |
311 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 |
|
312 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 | |
312 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 |
|
313 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 | |
313 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 |
|
314 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 | |
314 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 |
|
315 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 | |
315 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 |
|
316 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 | |
316 | END GENERATE all_bit_sample_f0; |
|
317 | END GENERATE all_bit_sample_f0; | |
317 |
|
318 | |||
318 | sample_f0_wen <= NOT(sample_f0_val) & |
|
319 | sample_f0_wen <= NOT(sample_f0_val) & | |
319 | NOT(sample_f0_val) & |
|
320 | NOT(sample_f0_val) & | |
320 | NOT(sample_f0_val) & |
|
321 | NOT(sample_f0_val) & | |
321 | NOT(sample_f0_val) & |
|
322 | NOT(sample_f0_val) & | |
322 | NOT(sample_f0_val) & |
|
323 | NOT(sample_f0_val) & | |
323 | NOT(sample_f0_val); |
|
324 | NOT(sample_f0_val); | |
324 |
|
325 | |||
325 | ----------------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------------- | |
326 | -- F1 -- @4096 Hz |
|
327 | -- F1 -- @4096 Hz | |
327 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- | |
328 | Downsampling_f1 : Downsampling |
|
329 | Downsampling_f1 : Downsampling | |
329 | GENERIC MAP ( |
|
330 | GENERIC MAP ( | |
330 | ChanelCount => 8, |
|
331 | ChanelCount => 8, | |
331 | SampleSize => 16, |
|
332 | SampleSize => 16, | |
332 | DivideParam => 6) |
|
333 | DivideParam => 6) | |
333 | PORT MAP ( |
|
334 | PORT MAP ( | |
334 | clk => clk, |
|
335 | clk => clk, | |
335 | rstn => rstn, |
|
336 | rstn => rstn, | |
336 | sample_in_val => sample_f0_val , |
|
337 | sample_in_val => sample_f0_val , | |
337 | sample_in => sample_f0, |
|
338 | sample_in => sample_f0, | |
338 | sample_out_val => sample_f1_val, |
|
339 | sample_out_val => sample_f1_val, | |
339 | sample_out => sample_f1); |
|
340 | sample_out => sample_f1); | |
340 |
|
341 | |||
341 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
342 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
342 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V |
|
343 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V | |
343 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 |
|
344 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 | |
344 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 |
|
345 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 | |
345 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 |
|
346 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 | |
346 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 |
|
347 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 | |
347 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 |
|
348 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 | |
348 | END GENERATE all_bit_sample_f1; |
|
349 | END GENERATE all_bit_sample_f1; | |
349 |
|
350 | |||
350 | sample_f1_wen <= NOT(sample_f1_val) & |
|
351 | sample_f1_wen <= NOT(sample_f1_val) & | |
351 | NOT(sample_f1_val) & |
|
352 | NOT(sample_f1_val) & | |
352 | NOT(sample_f1_val) & |
|
353 | NOT(sample_f1_val) & | |
353 | NOT(sample_f1_val) & |
|
354 | NOT(sample_f1_val) & | |
354 | NOT(sample_f1_val) & |
|
355 | NOT(sample_f1_val) & | |
355 | NOT(sample_f1_val); |
|
356 | NOT(sample_f1_val); | |
356 |
|
357 | |||
357 | ----------------------------------------------------------------------------- |
|
358 | ----------------------------------------------------------------------------- | |
358 | -- F2 -- @256 Hz |
|
359 | -- F2 -- @256 Hz | |
359 | ----------------------------------------------------------------------------- |
|
360 | ----------------------------------------------------------------------------- | |
360 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE |
|
361 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE | |
361 | sample_f0_s(0, I) <= sample_f0(0, I); -- V |
|
362 | sample_f0_s(0, I) <= sample_f0(0, I); -- V | |
362 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 |
|
363 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 | |
363 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 |
|
364 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 | |
364 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 |
|
365 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 | |
365 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 |
|
366 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 | |
366 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 |
|
367 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 | |
367 | END GENERATE all_bit_sample_f0_s; |
|
368 | END GENERATE all_bit_sample_f0_s; | |
368 |
|
369 | |||
369 | Downsampling_f2 : Downsampling |
|
370 | Downsampling_f2 : Downsampling | |
370 | GENERIC MAP ( |
|
371 | GENERIC MAP ( | |
371 | ChanelCount => 6, |
|
372 | ChanelCount => 6, | |
372 | SampleSize => 16, |
|
373 | SampleSize => 16, | |
373 | DivideParam => 96) |
|
374 | DivideParam => 96) | |
374 | PORT MAP ( |
|
375 | PORT MAP ( | |
375 | clk => clk, |
|
376 | clk => clk, | |
376 | rstn => rstn, |
|
377 | rstn => rstn, | |
377 | sample_in_val => sample_f0_val , |
|
378 | sample_in_val => sample_f0_val , | |
378 | sample_in => sample_f0_s, |
|
379 | sample_in => sample_f0_s, | |
379 | sample_out_val => sample_f2_val, |
|
380 | sample_out_val => sample_f2_val, | |
380 | sample_out => sample_f2); |
|
381 | sample_out => sample_f2); | |
381 |
|
382 | |||
382 | sample_f2_wen <= NOT(sample_f2_val) & |
|
383 | sample_f2_wen <= NOT(sample_f2_val) & | |
383 | NOT(sample_f2_val) & |
|
384 | NOT(sample_f2_val) & | |
384 | NOT(sample_f2_val) & |
|
385 | NOT(sample_f2_val) & | |
385 | NOT(sample_f2_val) & |
|
386 | NOT(sample_f2_val) & | |
386 | NOT(sample_f2_val) & |
|
387 | NOT(sample_f2_val) & | |
387 | NOT(sample_f2_val); |
|
388 | NOT(sample_f2_val); | |
388 |
|
389 | |||
389 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
390 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
390 | sample_f2_wdata_s(I) <= sample_f2(0, I); |
|
391 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |
391 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); |
|
392 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |
392 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); |
|
393 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |
393 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); |
|
394 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |
394 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); |
|
395 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |
395 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); |
|
396 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |
396 | END GENERATE all_bit_sample_f2; |
|
397 | END GENERATE all_bit_sample_f2; | |
397 |
|
398 | |||
398 | ----------------------------------------------------------------------------- |
|
399 | ----------------------------------------------------------------------------- | |
399 | -- F3 -- @16 Hz |
|
400 | -- F3 -- @16 Hz | |
400 | ----------------------------------------------------------------------------- |
|
401 | ----------------------------------------------------------------------------- | |
401 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE |
|
402 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE | |
402 | sample_f1_s(0, I) <= sample_f1(0, I); -- V |
|
403 | sample_f1_s(0, I) <= sample_f1(0, I); -- V | |
403 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 |
|
404 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 | |
404 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 |
|
405 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 | |
405 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 |
|
406 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 | |
406 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 |
|
407 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 | |
407 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 |
|
408 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 | |
408 | END GENERATE all_bit_sample_f1_s; |
|
409 | END GENERATE all_bit_sample_f1_s; | |
409 |
|
410 | |||
410 | Downsampling_f3 : Downsampling |
|
411 | Downsampling_f3 : Downsampling | |
411 | GENERIC MAP ( |
|
412 | GENERIC MAP ( | |
412 | ChanelCount => 6, |
|
413 | ChanelCount => 6, | |
413 | SampleSize => 16, |
|
414 | SampleSize => 16, | |
414 | DivideParam => 256) |
|
415 | DivideParam => 256) | |
415 | PORT MAP ( |
|
416 | PORT MAP ( | |
416 | clk => clk, |
|
417 | clk => clk, | |
417 | rstn => rstn, |
|
418 | rstn => rstn, | |
418 | sample_in_val => sample_f1_val , |
|
419 | sample_in_val => sample_f1_val , | |
419 | sample_in => sample_f1_s, |
|
420 | sample_in => sample_f1_s, | |
420 | sample_out_val => sample_f3_val, |
|
421 | sample_out_val => sample_f3_val, | |
421 | sample_out => sample_f3); |
|
422 | sample_out => sample_f3); | |
422 |
|
423 | |||
423 | sample_f3_wen <= (NOT sample_f3_val) & |
|
424 | sample_f3_wen <= (NOT sample_f3_val) & | |
424 | (NOT sample_f3_val) & |
|
425 | (NOT sample_f3_val) & | |
425 | (NOT sample_f3_val) & |
|
426 | (NOT sample_f3_val) & | |
426 | (NOT sample_f3_val) & |
|
427 | (NOT sample_f3_val) & | |
427 | (NOT sample_f3_val) & |
|
428 | (NOT sample_f3_val) & | |
428 | (NOT sample_f3_val); |
|
429 | (NOT sample_f3_val); | |
429 |
|
430 | |||
430 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
431 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
431 | sample_f3_wdata_s(I) <= sample_f3(0, I); |
|
432 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |
432 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); |
|
433 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |
433 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); |
|
434 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |
434 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); |
|
435 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |
435 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); |
|
436 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |
436 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); |
|
437 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |
437 | END GENERATE all_bit_sample_f3; |
|
438 | END GENERATE all_bit_sample_f3; | |
438 |
|
439 | |||
439 | lpp_waveform_1 : lpp_waveform |
|
440 | lpp_waveform_1 : lpp_waveform | |
440 | GENERIC MAP ( |
|
441 | GENERIC MAP ( | |
441 | hindex => hindex, |
|
442 | hindex => hindex, | |
442 | tech => tech, |
|
443 | tech => tech, | |
443 | data_size => 160, |
|
444 | data_size => 160, | |
444 | nb_burst_available_size => nb_burst_available_size, |
|
445 | nb_burst_available_size => nb_burst_available_size, | |
445 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
446 | nb_snapshot_param_size => nb_snapshot_param_size, | |
446 | delta_snapshot_size => delta_snapshot_size, |
|
447 | delta_snapshot_size => delta_snapshot_size, | |
447 | delta_f2_f0_size => delta_f2_f0_size, |
|
448 | delta_f2_f0_size => delta_f2_f0_size, | |
448 | delta_f2_f1_size => delta_f2_f1_size) |
|
449 | delta_f2_f1_size => delta_f2_f1_size) | |
449 | PORT MAP ( |
|
450 | PORT MAP ( | |
450 | clk => clk, |
|
451 | clk => clk, | |
451 | rstn => rstn, |
|
452 | rstn => rstn, | |
452 |
|
453 | |||
453 | AHB_Master_In => AHB_Master_In, |
|
454 | AHB_Master_In => AHB_Master_In, | |
454 | AHB_Master_Out => AHB_Master_Out, |
|
455 | AHB_Master_Out => AHB_Master_Out, | |
455 |
|
456 | |||
456 | coarse_time_0 => coarse_time_0, -- IN |
|
457 | coarse_time_0 => coarse_time_0, -- IN | |
457 | delta_snapshot => delta_snapshot, -- IN |
|
458 | delta_snapshot => delta_snapshot, -- IN | |
458 | delta_f2_f1 => delta_f2_f1, -- IN |
|
459 | delta_f2_f1 => delta_f2_f1, -- IN | |
459 | delta_f2_f0 => delta_f2_f0, -- IN |
|
460 | delta_f2_f0 => delta_f2_f0, -- IN | |
460 | enable_f0 => enable_f0, -- IN |
|
461 | enable_f0 => enable_f0, -- IN | |
461 | enable_f1 => enable_f1, -- IN |
|
462 | enable_f1 => enable_f1, -- IN | |
462 | enable_f2 => enable_f2, -- IN |
|
463 | enable_f2 => enable_f2, -- IN | |
463 | enable_f3 => enable_f3, -- IN |
|
464 | enable_f3 => enable_f3, -- IN | |
464 | burst_f0 => burst_f0, -- IN |
|
465 | burst_f0 => burst_f0, -- IN | |
465 | burst_f1 => burst_f1, -- IN |
|
466 | burst_f1 => burst_f1, -- IN | |
466 | burst_f2 => burst_f2, -- IN |
|
467 | burst_f2 => burst_f2, -- IN | |
467 | nb_burst_available => nb_burst_available, |
|
468 | nb_burst_available => nb_burst_available, | |
468 | nb_snapshot_param => nb_snapshot_param, |
|
469 | nb_snapshot_param => nb_snapshot_param, | |
469 | status_full => status_full, |
|
470 | status_full => status_full, | |
470 | status_full_ack => status_full_ack, -- IN |
|
471 | status_full_ack => status_full_ack, -- IN | |
471 | status_full_err => status_full_err, |
|
472 | status_full_err => status_full_err, | |
472 | status_new_err => status_new_err, |
|
473 | status_new_err => status_new_err, | |
473 |
|
474 | |||
474 | addr_data_f0 => addr_data_f0, -- IN |
|
475 | addr_data_f0 => addr_data_f0, -- IN | |
475 | addr_data_f1 => addr_data_f1, -- IN |
|
476 | addr_data_f1 => addr_data_f1, -- IN | |
476 | addr_data_f2 => addr_data_f2, -- IN |
|
477 | addr_data_f2 => addr_data_f2, -- IN | |
477 | addr_data_f3 => addr_data_f3, -- IN |
|
478 | addr_data_f3 => addr_data_f3, -- IN | |
478 |
|
479 | |||
479 | data_f0_in => data_f0_in_valid, |
|
480 | data_f0_in => data_f0_in_valid, | |
480 | data_f1_in => data_f1_in_valid, |
|
481 | data_f1_in => data_f1_in_valid, | |
481 | data_f2_in => data_f2_in_valid, |
|
482 | data_f2_in => data_f2_in_valid, | |
482 | data_f3_in => data_f3_in_valid, |
|
483 | data_f3_in => data_f3_in_valid, | |
|
484 | ||||
483 |
|
|
485 | data_f0_in_valid => sample_f0_val, | |
484 | data_f1_in_valid => sample_f1_val, |
|
486 | data_f1_in_valid => sample_f1_val, | |
485 | data_f2_in_valid => sample_f2_val, |
|
487 | data_f2_in_valid => sample_f2_val, | |
486 | data_f3_in_valid => sample_f3_val); |
|
488 | data_f3_in_valid => sample_f3_val); | |
487 |
|
489 | |||
488 | data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
|
490 | data_f0_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
489 | data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
|
491 | data_f1_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
490 | data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
|
492 | data_f2_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
491 | data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); |
|
493 | data_f3_in_valid((4*16)-1 DOWNTO 0) <= (others => '0'); | |
|
494 | ||||
492 |
|
|
495 | data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; | |
493 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; |
|
496 | data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; | |
494 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; |
|
497 | data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; | |
495 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; |
|
498 | data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; | |
496 |
|
499 | |||
497 | sample_f0_wdata <= sample_f0_wdata_s; |
|
500 | sample_f0_wdata <= sample_f0_wdata_s; | |
498 | sample_f1_wdata <= sample_f1_wdata_s; |
|
501 | sample_f1_wdata <= sample_f1_wdata_s; | |
499 | sample_f2_wdata <= sample_f2_wdata_s; |
|
502 | sample_f2_wdata <= sample_f2_wdata_s; | |
500 | sample_f3_wdata <= sample_f3_wdata_s; |
|
503 | sample_f3_wdata <= sample_f3_wdata_s; | |
501 |
|
504 | |||
502 | END tb; No newline at end of file |
|
505 | END tb; |
@@ -1,363 +1,384 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
27 | LIBRARY ieee; |
|
27 | LIBRARY ieee; | |
28 | USE ieee.std_logic_1164.ALL; |
|
28 | USE ieee.std_logic_1164.ALL; | |
29 | USE ieee.numeric_std.ALL; |
|
29 | USE ieee.numeric_std.ALL; | |
30 | LIBRARY grlib; |
|
30 | LIBRARY grlib; | |
31 | USE grlib.amba.ALL; |
|
31 | USE grlib.amba.ALL; | |
32 | USE grlib.stdlib.ALL; |
|
32 | USE grlib.stdlib.ALL; | |
33 | USE grlib.devices.ALL; |
|
33 | USE grlib.devices.ALL; | |
34 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |
35 | LIBRARY lpp; |
|
35 | LIBRARY lpp; | |
36 | USE lpp.lpp_amba.ALL; |
|
36 | USE lpp.lpp_amba.ALL; | |
37 | USE lpp.apb_devices_list.ALL; |
|
37 | USE lpp.apb_devices_list.ALL; | |
38 | USE lpp.lpp_memory.ALL; |
|
38 | USE lpp.lpp_memory.ALL; | |
39 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | USE lpp.lpp_dma_pkg.ALL; | |
40 | USE lpp.lpp_waveform_pkg.ALL; |
|
40 | USE lpp.lpp_waveform_pkg.ALL; | |
41 | LIBRARY techmap; |
|
41 | LIBRARY techmap; | |
42 | USE techmap.gencomp.ALL; |
|
42 | USE techmap.gencomp.ALL; | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | ENTITY lpp_waveform_dma IS |
|
45 | ENTITY lpp_waveform_dma IS | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | data_size : INTEGER := 160; |
|
47 | data_size : INTEGER := 160; | |
48 | tech : INTEGER := inferred; |
|
48 | tech : INTEGER := inferred; | |
49 | hindex : INTEGER := 2; |
|
49 | hindex : INTEGER := 2; | |
50 | nb_burst_available_size : INTEGER := 11 |
|
50 | nb_burst_available_size : INTEGER := 11 | |
51 | ); |
|
51 | ); | |
52 | PORT ( |
|
52 | PORT ( | |
53 | -- AMBA AHB system signals |
|
53 | -- AMBA AHB system signals | |
54 | HCLK : IN STD_ULOGIC; |
|
54 | HCLK : IN STD_ULOGIC; | |
55 | HRESETn : IN STD_ULOGIC; |
|
55 | HRESETn : IN STD_ULOGIC; | |
56 | -- AMBA AHB Master Interface |
|
56 | -- AMBA AHB Master Interface | |
57 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
57 | AHB_Master_In : IN AHB_Mst_In_Type; | |
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
58 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
59 | -- |
|
59 | -- | |
60 | data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo |
|
60 | data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |
61 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
61 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
62 | data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo |
|
62 | data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |
63 | data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo |
|
63 | data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo | |
64 | -- Reg |
|
64 | -- Reg | |
65 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
65 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |
66 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
66 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
67 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
67 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
68 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
68 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
69 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
|
69 | -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma | |
70 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
72 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
72 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
73 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
74 | ); |
|
74 | ); | |
75 | END; |
|
75 | END; | |
76 |
|
76 | |||
77 | ARCHITECTURE Behavioral OF lpp_waveform_dma IS |
|
77 | ARCHITECTURE Behavioral OF lpp_waveform_dma IS | |
78 | ----------------------------------------------------------------------------- |
|
78 | ----------------------------------------------------------------------------- | |
79 |
SIGNAL DMAIn |
|
79 | SIGNAL DMAIn : DMA_In_Type; | |
80 |
SIGNAL DMAOut |
|
80 | SIGNAL DMAOut : DMA_OUt_Type; | |
81 | ----------------------------------------------------------------------------- |
|
81 | ----------------------------------------------------------------------------- | |
82 |
TYPE |
|
82 | TYPE state_DMAWriteBurst IS (IDLE, | |
83 | SEND_TIME_0, WAIT_TIME_0, |
|
83 | SEND_TIME_0, WAIT_TIME_0, | |
84 | SEND_TIME_1, WAIT_TIME_1, |
|
84 | SEND_TIME_1, WAIT_TIME_1, | |
85 | SEND_5_TIME, |
|
85 | SEND_5_TIME, | |
86 | SEND_DATA, WAIT_DATA); |
|
86 | SEND_DATA, WAIT_DATA); | |
87 | SIGNAL state : state_DMAWriteBurst := IDLE; |
|
87 | SIGNAL state : state_DMAWriteBurst := IDLE; | |
88 | ----------------------------------------------------------------------------- |
|
88 | ----------------------------------------------------------------------------- | |
89 | -- CONTROL |
|
89 | -- CONTROL | |
90 | SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
90 | SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
91 | SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
91 | SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
92 | SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
92 | SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
93 | SIGNAL time_select : STD_LOGIC; |
|
93 | SIGNAL time_select : STD_LOGIC; | |
94 | SIGNAL time_write : STD_LOGIC; |
|
94 | SIGNAL time_write : STD_LOGIC; | |
95 | SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
95 | SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
96 | SIGNAL time_already_send_s : STD_LOGIC; |
|
96 | SIGNAL time_already_send_s : STD_LOGIC; | |
97 | ----------------------------------------------------------------------------- |
|
97 | ----------------------------------------------------------------------------- | |
98 | -- SEND TIME MODULE |
|
98 | -- SEND TIME MODULE | |
99 | SIGNAL time_dmai : DMA_In_Type; |
|
99 | SIGNAL time_dmai : DMA_In_Type; | |
100 | SIGNAL time_send : STD_LOGIC; |
|
100 | SIGNAL time_send : STD_LOGIC; | |
101 | SIGNAL time_send_ok : STD_LOGIC; |
|
101 | SIGNAL time_send_ok : STD_LOGIC; | |
102 | SIGNAL time_send_ko : STD_LOGIC; |
|
102 | SIGNAL time_send_ko : STD_LOGIC; | |
103 | SIGNAL time_fifo_ren : STD_LOGIC; |
|
103 | SIGNAL time_fifo_ren : STD_LOGIC; | |
104 | SIGNAL time_ren : STD_LOGIC; |
|
104 | SIGNAL time_ren : STD_LOGIC; | |
105 | ----------------------------------------------------------------------------- |
|
105 | ----------------------------------------------------------------------------- | |
106 | -- SEND DATA MODULE |
|
106 | -- SEND DATA MODULE | |
107 | SIGNAL data_dmai : DMA_In_Type; |
|
107 | SIGNAL data_dmai : DMA_In_Type; | |
108 | SIGNAL data_send : STD_LOGIC; |
|
108 | SIGNAL data_send : STD_LOGIC; | |
109 | SIGNAL data_send_ok : STD_LOGIC; |
|
109 | SIGNAL data_send_ok : STD_LOGIC; | |
110 | SIGNAL data_send_ko : STD_LOGIC; |
|
110 | SIGNAL data_send_ko : STD_LOGIC; | |
111 | SIGNAL data_fifo_ren : STD_LOGIC; |
|
111 | SIGNAL data_fifo_ren : STD_LOGIC; | |
112 | SIGNAL data_ren : STD_LOGIC; |
|
112 | SIGNAL data_ren : STD_LOGIC; | |
113 | ----------------------------------------------------------------------------- |
|
113 | ----------------------------------------------------------------------------- | |
114 | -- SELECT ADDRESS |
|
114 | -- SELECT ADDRESS | |
115 | SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
116 | SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
116 | SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
117 | SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
117 | SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
118 | SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
118 | SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
120 |
SIGNAL send_16_3_time : STD_LOGIC_VECTOR( |
|
120 | SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); | |
|
121 | SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); | |||
|
122 | ----------------------------------------------------------------------------- | |||
|
123 | SIGNAL send_16_3_time : STD_LOGIC; | |||
121 | SIGNAL count_send_time : INTEGER; |
|
124 | SIGNAL count_send_time : INTEGER; | |
122 | BEGIN |
|
125 | BEGIN | |
123 |
|
126 | |||
124 | ----------------------------------------------------------------------------- |
|
127 | ----------------------------------------------------------------------------- | |
125 | -- DMA to AHB interface |
|
128 | -- DMA to AHB interface | |
126 | DMA2AHB_1 : DMA2AHB |
|
129 | DMA2AHB_1 : DMA2AHB | |
127 | GENERIC MAP ( |
|
130 | GENERIC MAP ( | |
128 | hindex => hindex, |
|
131 | hindex => hindex, | |
129 | vendorid => VENDOR_LPP, |
|
132 | vendorid => VENDOR_LPP, | |
130 | deviceid => 0, |
|
133 | deviceid => 0, | |
131 | version => 0, |
|
134 | version => 0, | |
132 | syncrst => 1, |
|
135 | syncrst => 1, | |
133 | boundary => 1) -- FIX 11/01/2013 |
|
136 | boundary => 1) -- FIX 11/01/2013 | |
134 | PORT MAP ( |
|
137 | PORT MAP ( | |
135 | HCLK => HCLK, |
|
138 | HCLK => HCLK, | |
136 | HRESETn => HRESETn, |
|
139 | HRESETn => HRESETn, | |
137 | DMAIn => DMAIn, |
|
140 | DMAIn => DMAIn, | |
138 | DMAOut => DMAOut, |
|
141 | DMAOut => DMAOut, | |
139 | AHBIn => AHB_Master_In, |
|
142 | AHBIn => AHB_Master_In, | |
140 | AHBOut => AHB_Master_Out); |
|
143 | AHBOut => AHB_Master_Out); | |
141 | ----------------------------------------------------------------------------- |
|
144 | ----------------------------------------------------------------------------- | |
142 |
|
145 | |||
143 | ----------------------------------------------------------------------------- |
|
146 | ----------------------------------------------------------------------------- | |
144 | -- This module memorises when the Times info are write. When FSM send |
|
147 | -- This module memorises when the Times info are write. When FSM send | |
145 | -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. |
|
148 | -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. | |
146 | all_time_write: FOR I IN 3 DOWNTO 0 GENERATE |
|
149 | all_time_write : FOR I IN 3 DOWNTO 0 GENERATE | |
147 | PROCESS (HCLK, HRESETn) |
|
150 | PROCESS (HCLK, HRESETn) | |
148 | BEGIN -- PROCESS |
|
151 | BEGIN -- PROCESS | |
149 |
IF HRESETn = '0' THEN |
|
152 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
150 | time_already_send(I) <= '0'; |
|
153 | time_already_send(I) <= '0'; | |
151 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
154 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
152 | IF time_write = '1' AND UNSIGNED(sel_data) = I THEN |
|
155 | IF time_write = '1' AND UNSIGNED(sel_data) = I THEN | |
153 | time_already_send(I) <= '1'; |
|
156 | time_already_send(I) <= '1'; | |
154 | ELSIF status_full_ack(I) = '1' THEN |
|
157 | ELSIF status_full_ack(I) = '1' THEN | |
155 | time_already_send(I) <= '0'; |
|
158 | time_already_send(I) <= '0'; | |
156 | END IF; |
|
159 | END IF; | |
157 | END IF; |
|
160 | END IF; | |
158 | END PROCESS; |
|
161 | END PROCESS; | |
159 | END GENERATE all_time_write; |
|
162 | END GENERATE all_time_write; | |
160 |
|
163 | |||
|
164 | ||||
|
165 | ||||
161 | ----------------------------------------------------------------------------- |
|
166 | ----------------------------------------------------------------------------- | |
162 | sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE |
|
167 | sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE | |
163 | "01" WHEN data_ready(1) = '1' ELSE |
|
168 | "01" WHEN data_ready(1) = '1' ELSE | |
164 | "10" WHEN data_ready(2) = '1' ELSE |
|
169 | "10" WHEN data_ready(2) = '1' ELSE | |
165 | "11"; |
|
170 | "11"; | |
166 |
|
171 | |||
167 | time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE |
|
172 | time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE | |
168 | time_already_send(1) WHEN data_ready(1) = '1' ELSE |
|
173 | time_already_send(1) WHEN data_ready(1) = '1' ELSE | |
169 | time_already_send(2) WHEN data_ready(2) = '1' ELSE |
|
174 | time_already_send(2) WHEN data_ready(2) = '1' ELSE | |
170 | time_already_send(3); |
|
175 | time_already_send(3); | |
171 |
|
176 | |||
|
177 | ||||
|
178 | send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE | |||
|
179 | send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE | |||
|
180 | send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE | |||
|
181 | send_16_3_time_reg(9) ; | |||
|
182 | ||||
|
183 | all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE | |||
|
184 | send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <= | |||
|
185 | send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE | |||
|
186 | send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1); | |||
|
187 | END GENERATE all_send_16_3; | |||
|
188 | ||||
172 |
|
|
189 | -- DMA control | |
173 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
190 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
174 | BEGIN -- PROCESS DMAWriteBurst_p |
|
191 | BEGIN -- PROCESS DMAWriteBurst_p | |
175 | IF HRESETn = '0' THEN |
|
192 | IF HRESETn = '0' THEN | |
176 |
state |
|
193 | state <= IDLE; | |
177 |
|
194 | |||
178 | sel_data <= "00"; |
|
195 | sel_data <= "00"; | |
179 | update <= "00"; |
|
196 | update <= "00"; | |
180 | time_select <= '0'; |
|
197 | time_select <= '0'; | |
181 | time_fifo_ren <= '1'; |
|
198 | time_fifo_ren <= '1'; | |
182 | data_send <= '0'; |
|
199 | data_send <= '0'; | |
183 | time_send <= '0'; |
|
200 | time_send <= '0'; | |
184 | time_write <= '0'; |
|
201 | time_write <= '0'; | |
185 | send_16_3_time <= "001"; |
|
202 | --send_16_3_time <= "001"; | |
|
203 | send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001"; | |||
|
204 | send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001"; | |||
|
205 | send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001"; | |||
|
206 | send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001"; | |||
186 |
|
207 | |||
187 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
208 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
188 |
|
209 | |||
189 | CASE state IS |
|
210 | CASE state IS | |
190 | WHEN IDLE => |
|
211 | WHEN IDLE => | |
191 | count_send_time <= 0; |
|
212 | count_send_time <= 0; | |
192 | sel_data <= "00"; |
|
213 | sel_data <= "00"; | |
193 | update <= "00"; |
|
214 | update <= "00"; | |
194 | time_select <= '0'; |
|
215 | time_select <= '0'; | |
195 | time_fifo_ren <= '1'; |
|
216 | time_fifo_ren <= '1'; | |
196 | data_send <= '0'; |
|
217 | data_send <= '0'; | |
197 | time_send <= '0'; |
|
218 | time_send <= '0'; | |
198 | time_write <= '0'; |
|
219 | time_write <= '0'; | |
199 |
|
220 | |||
200 | IF data_ready = "0000" THEN |
|
221 | IF data_ready = "0000" THEN | |
201 |
state |
|
222 | state <= IDLE; | |
202 | ELSE |
|
223 | ELSE | |
203 | sel_data <= sel_data_s; |
|
224 | sel_data <= sel_data_s; | |
204 |
send_16_3_time <= send_16_3_time |
|
225 | send_16_3_time_reg <= send_16_3_time_reg_s; | |
205 |
IF send_16_3_time |
|
226 | IF send_16_3_time = '1' THEN | |
206 |
state |
|
227 | state <= SEND_TIME_0; | |
207 | ELSE |
|
228 | ELSE | |
208 |
state |
|
229 | state <= SEND_5_TIME; | |
209 | END IF; |
|
230 | END IF; | |
210 | END IF; |
|
231 | END IF; | |
211 |
|
232 | |||
212 | WHEN SEND_TIME_0 => |
|
233 | WHEN SEND_TIME_0 => | |
213 |
time_select |
|
234 | time_select <= '1'; | |
214 | IF time_already_send_s = '0' THEN |
|
235 | IF time_already_send_s = '0' THEN | |
215 | time_send <= '1'; |
|
236 | time_send <= '1'; | |
216 | state <= WAIT_TIME_0; |
|
237 | state <= WAIT_TIME_0; | |
217 | ELSE |
|
238 | ELSE | |
218 | time_send <= '0'; |
|
239 | time_send <= '0'; | |
219 | state <= SEND_TIME_1; |
|
240 | state <= SEND_TIME_1; | |
220 | END IF; |
|
241 | END IF; | |
221 |
|
|
242 | time_fifo_ren <= '0'; | |
222 |
|
243 | |||
223 | WHEN WAIT_TIME_0 => |
|
244 | WHEN WAIT_TIME_0 => | |
224 | time_fifo_ren <= '1'; |
|
245 | time_fifo_ren <= '1'; | |
225 | update <= "00"; |
|
246 | update <= "00"; | |
226 | time_send <= '0'; |
|
247 | time_send <= '0'; | |
227 | IF time_send_ok = '1' OR time_send_ko = '1' THEN |
|
248 | IF time_send_ok = '1' OR time_send_ko = '1' THEN | |
228 |
update |
|
249 | update <= "01"; | |
229 |
state |
|
250 | state <= SEND_TIME_1; | |
230 | END IF; |
|
251 | END IF; | |
231 |
|
252 | |||
232 | WHEN SEND_TIME_1 => |
|
253 | WHEN SEND_TIME_1 => | |
233 |
time_select |
|
254 | time_select <= '1'; | |
234 | IF time_already_send_s = '0' THEN |
|
255 | IF time_already_send_s = '0' THEN | |
235 | time_send <= '1'; |
|
256 | time_send <= '1'; | |
236 | state <= WAIT_TIME_1; |
|
257 | state <= WAIT_TIME_1; | |
237 | ELSE |
|
258 | ELSE | |
238 | time_send <= '0'; |
|
259 | time_send <= '0'; | |
239 | state <= SEND_5_TIME; |
|
260 | state <= SEND_5_TIME; | |
240 | END IF; |
|
261 | END IF; | |
241 | time_fifo_ren <= '0'; |
|
262 | time_fifo_ren <= '0'; | |
242 |
|
263 | |||
243 | WHEN WAIT_TIME_1 => |
|
264 | WHEN WAIT_TIME_1 => | |
244 | time_fifo_ren <= '1'; |
|
265 | time_fifo_ren <= '1'; | |
245 | update <= "00"; |
|
266 | update <= "00"; | |
246 | time_send <= '0'; |
|
267 | time_send <= '0'; | |
247 | IF time_send_ok = '1' OR time_send_ko = '1' THEN |
|
268 | IF time_send_ok = '1' OR time_send_ko = '1' THEN | |
248 |
time_write <= |
|
269 | time_write <= '1'; | |
249 | update <= "01"; |
|
270 | update <= "01"; | |
250 |
state <= SEND_5_TIME; |
|
271 | state <= SEND_5_TIME; | |
251 | END IF; |
|
272 | END IF; | |
252 |
|
273 | |||
253 | WHEN SEND_5_TIME => |
|
274 | WHEN SEND_5_TIME => | |
254 | update <= "00"; |
|
275 | update <= "00"; | |
255 | time_select <= '1'; |
|
276 | time_select <= '1'; | |
256 | time_fifo_ren <= '0'; |
|
277 | time_fifo_ren <= '0'; | |
257 | count_send_time <= count_send_time + 1; |
|
278 | count_send_time <= count_send_time + 1; | |
258 | IF count_send_time = 10 THEN |
|
279 | IF count_send_time = 10 THEN | |
259 |
state |
|
280 | state <= SEND_DATA; | |
260 |
END IF; |
|
281 | END IF; | |
261 |
|
282 | |||
262 | WHEN SEND_DATA => |
|
283 | WHEN SEND_DATA => | |
263 | time_fifo_ren <= '1'; |
|
284 | time_fifo_ren <= '1'; | |
264 | time_write <= '0'; |
|
285 | time_write <= '0'; | |
265 | time_send <= '0'; |
|
286 | time_send <= '0'; | |
266 |
|
287 | |||
267 |
time_select |
|
288 | time_select <= '0'; | |
268 |
data_send |
|
289 | data_send <= '1'; | |
269 |
update |
|
290 | update <= "00"; | |
270 |
state |
|
291 | state <= WAIT_DATA; | |
271 |
|
292 | |||
272 | WHEN WAIT_DATA => |
|
293 | WHEN WAIT_DATA => | |
273 |
data_send |
|
294 | data_send <= '0'; | |
274 |
|
295 | |||
275 | IF data_send_ok = '1' OR data_send_ko = '1' THEN |
|
296 | IF data_send_ok = '1' OR data_send_ko = '1' THEN | |
276 | state <= IDLE; |
|
297 | state <= IDLE; | |
277 | update <= "10"; |
|
298 | update <= "10"; | |
278 | END IF; |
|
299 | END IF; | |
279 |
|
300 | |||
280 | WHEN OTHERS => NULL; |
|
301 | WHEN OTHERS => NULL; | |
281 | END CASE; |
|
302 | END CASE; | |
282 |
|
303 | |||
283 | END IF; |
|
304 | END IF; | |
284 | END PROCESS DMAWriteFSM_p; |
|
305 | END PROCESS DMAWriteFSM_p; | |
285 | ----------------------------------------------------------------------------- |
|
306 | ----------------------------------------------------------------------------- | |
286 |
|
307 | |||
287 |
|
308 | |||
288 |
|
309 | |||
289 | ----------------------------------------------------------------------------- |
|
310 | ----------------------------------------------------------------------------- | |
290 | -- SEND 1 word by DMA |
|
311 | -- SEND 1 word by DMA | |
291 | ----------------------------------------------------------------------------- |
|
312 | ----------------------------------------------------------------------------- | |
292 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
|
313 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |
293 | PORT MAP ( |
|
314 | PORT MAP ( | |
294 | HCLK => HCLK, |
|
315 | HCLK => HCLK, | |
295 | HRESETn => HRESETn, |
|
316 | HRESETn => HRESETn, | |
296 | DMAIn => time_dmai, |
|
317 | DMAIn => time_dmai, | |
297 | DMAOut => DMAOut, |
|
318 | DMAOut => DMAOut, | |
298 |
|
319 | |||
299 | send => time_send, |
|
320 | send => time_send, | |
300 | address => data_address, |
|
321 | address => data_address, | |
301 | data => data, |
|
322 | data => data, | |
302 | send_ok => time_send_ok, |
|
323 | send_ok => time_send_ok, | |
303 | send_ko => time_send_ko |
|
324 | send_ko => time_send_ko | |
304 | ); |
|
325 | ); | |
305 |
|
326 | |||
306 | ----------------------------------------------------------------------------- |
|
327 | ----------------------------------------------------------------------------- | |
307 | -- SEND 16 word by DMA (in burst mode) |
|
328 | -- SEND 16 word by DMA (in burst mode) | |
308 | ----------------------------------------------------------------------------- |
|
329 | ----------------------------------------------------------------------------- | |
309 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
|
330 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
310 | PORT MAP ( |
|
331 | PORT MAP ( | |
311 | HCLK => HCLK, |
|
332 | HCLK => HCLK, | |
312 | HRESETn => HRESETn, |
|
333 | HRESETn => HRESETn, | |
313 | DMAIn => data_dmai, |
|
334 | DMAIn => data_dmai, | |
314 | DMAOut => DMAOut, |
|
335 | DMAOut => DMAOut, | |
315 |
|
336 | |||
316 | send => data_send, |
|
337 | send => data_send, | |
317 | address => data_address, |
|
338 | address => data_address, | |
318 | data => data, |
|
339 | data => data, | |
319 | ren => data_fifo_ren, |
|
340 | ren => data_fifo_ren, | |
320 | send_ok => data_send_ok, |
|
341 | send_ok => data_send_ok, | |
321 | send_ko => data_send_ko); |
|
342 | send_ko => data_send_ko); | |
322 |
|
343 | |||
323 | DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; |
|
344 | DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; | |
324 | data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; |
|
345 | data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; | |
325 | time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; |
|
346 | time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; | |
326 |
|
347 | |||
327 | all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE |
|
348 | all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE | |
328 | data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; |
|
349 | data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; | |
329 | data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; |
|
350 | data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; | |
330 | END GENERATE all_data_ren; |
|
351 | END GENERATE all_data_ren; | |
331 |
|
352 | |||
332 | ----------------------------------------------------------------------------- |
|
353 | ----------------------------------------------------------------------------- | |
333 | -- SELECT ADDRESS |
|
354 | -- SELECT ADDRESS | |
334 | addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; |
|
355 | addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; | |
335 |
|
356 | |||
336 | gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE |
|
357 | gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE | |
337 |
|
358 | |||
338 | update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; |
|
359 | update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; | |
339 |
|
360 | |||
340 | lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress |
|
361 | lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress | |
341 | GENERIC MAP ( |
|
362 | GENERIC MAP ( | |
342 | nb_burst_available_size => nb_burst_available_size) |
|
363 | nb_burst_available_size => nb_burst_available_size) | |
343 | PORT MAP ( |
|
364 | PORT MAP ( | |
344 | HCLK => HCLK, |
|
365 | HCLK => HCLK, | |
345 | HRESETn => HRESETn, |
|
366 | HRESETn => HRESETn, | |
346 | update => update_and_sel((2*I)+1 DOWNTO 2*I), |
|
367 | update => update_and_sel((2*I)+1 DOWNTO 2*I), | |
347 | nb_burst_available => nb_burst_available, |
|
368 | nb_burst_available => nb_burst_available, | |
348 | addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), |
|
369 | addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), | |
349 | addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), |
|
370 | addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), | |
350 | status_full => status_full(I), |
|
371 | status_full => status_full(I), | |
351 | status_full_ack => status_full_ack(I), |
|
372 | status_full_ack => status_full_ack(I), | |
352 | status_full_err => status_full_err(I)); |
|
373 | status_full_err => status_full_err(I)); | |
353 |
|
374 | |||
354 | END GENERATE gen_select_address; |
|
375 | END GENERATE gen_select_address; | |
355 |
|
376 | |||
356 | data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE |
|
377 | data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE | |
357 | addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE |
|
378 | addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE | |
358 | addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE |
|
379 | addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE | |
359 | addr_data_vector(32*3+31 DOWNTO 32*3); |
|
380 | addr_data_vector(32*3+31 DOWNTO 32*3); | |
360 | ----------------------------------------------------------------------------- |
|
381 | ----------------------------------------------------------------------------- | |
361 |
|
382 | |||
362 |
|
383 | |||
363 | END Behavioral; |
|
384 | END Behavioral; |
@@ -1,116 +1,116 | |||||
1 | LIBRARY IEEE; |
|
1 | LIBRARY IEEE; | |
2 | USE IEEE.STD_LOGIC_1164.ALL; |
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 | ENTITY lpp_waveform_snapshot_controler IS |
|
5 | ENTITY lpp_waveform_snapshot_controler IS | |
6 |
|
6 | |||
7 | GENERIC ( |
|
7 | GENERIC ( | |
8 | delta_snapshot_size : INTEGER := 16; |
|
8 | delta_snapshot_size : INTEGER := 16; | |
9 | delta_f2_f0_size : INTEGER := 10; |
|
9 | delta_f2_f0_size : INTEGER := 10; | |
10 | delta_f2_f1_size : INTEGER := 10); |
|
10 | delta_f2_f1_size : INTEGER := 10); | |
11 |
|
11 | |||
12 | PORT ( |
|
12 | PORT ( | |
13 | clk : IN STD_LOGIC; |
|
13 | clk : IN STD_LOGIC; | |
14 | rstn : IN STD_LOGIC; |
|
14 | rstn : IN STD_LOGIC; | |
15 | --config |
|
15 | --config | |
16 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
16 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |
17 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
17 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |
18 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
18 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |
19 |
|
19 | |||
20 | --input |
|
20 | --input | |
21 | coarse_time_0 : IN STD_LOGIC; |
|
21 | coarse_time_0 : IN STD_LOGIC; | |
22 | data_f0_in_valid : IN STD_LOGIC; |
|
22 | data_f0_in_valid : IN STD_LOGIC; | |
23 | data_f2_in_valid : IN STD_LOGIC; |
|
23 | data_f2_in_valid : IN STD_LOGIC; | |
24 | --output |
|
24 | --output | |
25 | start_snapshot_f0 : OUT STD_LOGIC; |
|
25 | start_snapshot_f0 : OUT STD_LOGIC; | |
26 | start_snapshot_f1 : OUT STD_LOGIC; |
|
26 | start_snapshot_f1 : OUT STD_LOGIC; | |
27 | start_snapshot_f2 : OUT STD_LOGIC |
|
27 | start_snapshot_f2 : OUT STD_LOGIC | |
28 | ); |
|
28 | ); | |
29 |
|
29 | |||
30 | END lpp_waveform_snapshot_controler; |
|
30 | END lpp_waveform_snapshot_controler; | |
31 |
|
31 | |||
32 | ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS |
|
32 | ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS | |
33 | SIGNAL counter_delta_snapshot : INTEGER; |
|
33 | SIGNAL counter_delta_snapshot : INTEGER; | |
34 | SIGNAL counter_delta_f0 : INTEGER; |
|
34 | SIGNAL counter_delta_f0 : INTEGER; | |
35 |
|
35 | |||
36 | SIGNAL coarse_time_0_r : STD_LOGIC; |
|
36 | SIGNAL coarse_time_0_r : STD_LOGIC; | |
37 | SIGNAL start_snapshot_f2_temp : STD_LOGIC; |
|
37 | SIGNAL start_snapshot_f2_temp : STD_LOGIC; | |
38 | SIGNAL start_snapshot_fothers_temp : STD_LOGIC; |
|
38 | SIGNAL start_snapshot_fothers_temp : STD_LOGIC; | |
39 | SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; |
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39 | SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; | |
40 | BEGIN -- beh |
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40 | BEGIN -- beh | |
41 |
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41 | |||
42 | PROCESS (clk, rstn) |
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42 | PROCESS (clk, rstn) | |
43 | BEGIN |
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43 | BEGIN | |
44 | IF rstn = '0' THEN |
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44 | IF rstn = '0' THEN | |
45 | start_snapshot_f0 <= '0'; |
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45 | start_snapshot_f0 <= '0'; | |
46 | start_snapshot_f1 <= '0'; |
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46 | start_snapshot_f1 <= '0'; | |
47 | start_snapshot_f2 <= '0'; |
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47 | start_snapshot_f2 <= '0'; | |
48 | counter_delta_snapshot <= 0; |
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48 | counter_delta_snapshot <= 0; | |
49 | counter_delta_f0 <= 0; |
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49 | counter_delta_f0 <= 0; | |
50 | coarse_time_0_r <= '0'; |
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50 | coarse_time_0_r <= '0'; | |
51 | start_snapshot_f2_temp <= '0'; |
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51 | start_snapshot_f2_temp <= '0'; | |
52 | start_snapshot_fothers_temp <= '0'; |
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52 | start_snapshot_fothers_temp <= '0'; | |
53 | start_snapshot_fothers_temp2 <= '0'; |
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53 | start_snapshot_fothers_temp2 <= '0'; | |
54 | ELSIF clk'EVENT AND clk = '1' THEN |
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54 | ELSIF clk'EVENT AND clk = '1' THEN | |
55 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN |
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55 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |
56 | start_snapshot_f2_temp <= '1'; |
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56 | start_snapshot_f2_temp <= '1'; | |
57 | ELSE |
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57 | ELSE | |
58 | start_snapshot_f2_temp <= '0'; |
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58 | start_snapshot_f2_temp <= '0'; | |
59 | END IF; |
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59 | END IF; | |
60 | ------------------------------------------------------------------------- |
|
60 | ------------------------------------------------------------------------- | |
61 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN |
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61 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN | |
62 | start_snapshot_f2 <= '1'; |
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62 | start_snapshot_f2 <= '1'; | |
63 | ELSE |
|
63 | ELSE | |
64 | start_snapshot_f2 <= '0'; |
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64 | start_snapshot_f2 <= '0'; | |
65 | END IF; |
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65 | END IF; | |
66 | ------------------------------------------------------------------------- |
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66 | ------------------------------------------------------------------------- | |
67 | coarse_time_0_r <= coarse_time_0; |
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67 | coarse_time_0_r <= coarse_time_0; | |
68 |
IF coarse_time_0 = NOT coarse_time_0_r |
|
68 | IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN | |
69 | IF counter_delta_snapshot = 0 THEN |
|
69 | IF counter_delta_snapshot = 0 THEN | |
70 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); |
|
70 | counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); | |
71 | ELSE |
|
71 | ELSE | |
72 | counter_delta_snapshot <= counter_delta_snapshot - 1; |
|
72 | counter_delta_snapshot <= counter_delta_snapshot - 1; | |
73 | END IF; |
|
73 | END IF; | |
74 | END IF; |
|
74 | END IF; | |
75 |
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75 | |||
76 |
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76 | |||
77 | ------------------------------------------------------------------------- |
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77 | ------------------------------------------------------------------------- | |
78 |
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78 | |||
79 |
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79 | |||
80 |
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80 | |||
81 | IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN |
|
81 | IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN | |
82 | start_snapshot_f1 <= '1'; |
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82 | start_snapshot_f1 <= '1'; | |
83 | ELSE |
|
83 | ELSE | |
84 | start_snapshot_f1 <= '0'; |
|
84 | start_snapshot_f1 <= '0'; | |
85 | END IF; |
|
85 | END IF; | |
86 |
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86 | |||
87 | IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN |
|
87 | IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN | |
88 | start_snapshot_f0 <= '1'; |
|
88 | start_snapshot_f0 <= '1'; | |
89 | ELSE |
|
89 | ELSE | |
90 | start_snapshot_f0 <= '0'; |
|
90 | start_snapshot_f0 <= '0'; | |
91 | END IF; |
|
91 | END IF; | |
92 |
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92 | |||
93 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) |
|
93 | IF counter_delta_snapshot = UNSIGNED(delta_snapshot) | |
94 | AND start_snapshot_f2_temp = '0' |
|
94 | AND start_snapshot_f2_temp = '0' | |
95 | THEN -- |
|
95 | THEN -- | |
96 | start_snapshot_fothers_temp <= '1'; |
|
96 | start_snapshot_fothers_temp <= '1'; | |
97 | ELSIF counter_delta_f0 > 0 THEN |
|
97 | ELSIF counter_delta_f0 > 0 THEN | |
98 | start_snapshot_fothers_temp <= '0'; |
|
98 | start_snapshot_fothers_temp <= '0'; | |
99 | END IF; |
|
99 | END IF; | |
100 |
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100 | |||
101 |
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101 | |||
102 | ------------------------------------------------------------------------- |
|
102 | ------------------------------------------------------------------------- | |
103 | IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN |
|
103 | IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN | |
104 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- |
|
104 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- | |
105 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN |
|
105 | --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN | |
106 | counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; |
|
106 | counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; | |
107 | ELSE |
|
107 | ELSE | |
108 | IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN |
|
108 | IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN | |
109 | counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; |
|
109 | counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; | |
110 | END IF; |
|
110 | END IF; | |
111 | END IF; |
|
111 | END IF; | |
112 | ------------------------------------------------------------------------- |
|
112 | ------------------------------------------------------------------------- | |
113 | END IF; |
|
113 | END IF; | |
114 | END PROCESS; |
|
114 | END PROCESS; | |
115 |
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115 | |||
116 | END beh; |
|
116 | END beh; |
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