@@ -21,7 +21,7 | |||||
21 | | ABOUT |
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21 | | ABOUT | |
22 | | ~~~~~ |
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22 | | ~~~~~ | |
23 |
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23 | |||
24 |
LPP's VHD_Lib is a VHDL library |
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24 | LPP's VHD_Lib is a VHDL library which is target independent and includes a set of scripts for integrating into | |
25 | gaisler's grlib and use its features. For setup read instalation section. |
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25 | gaisler's grlib and use its features. For setup read instalation section. | |
26 |
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26 | |||
27 |
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27 | |||
@@ -61,6 +61,4 All the programs used by the VHD_Lib are | |||||
61 | license. They all are free software and most of them are covered by the |
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61 | license. They all are free software and most of them are covered by the | |
62 | GNU General Public License. |
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62 | GNU General Public License. | |
63 |
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63 | |||
64 | The VHD_Lib itself, meaning all the scripts which are used in the building |
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65 | process, are covered by the GNU General Public License. |
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66 |
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64 |
@@ -36,7 +36,7 constant ClearDSPLY : std_logic_vector( | |||||
36 | constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; |
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36 | constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; | |
37 | constant RetHome : std_logic_vector(7 downto 0):= X"02"; |
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37 | constant RetHome : std_logic_vector(7 downto 0):= X"02"; | |
38 | constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; |
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38 | constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; | |
39 |
constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0 |
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39 | constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E"; | |
40 |
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40 | |||
41 | constant CursorON : std_logic_vector(7 downto 0):= X"0E"; |
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41 | constant CursorON : std_logic_vector(7 downto 0):= X"0E"; | |
42 | constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; |
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42 | constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; |
@@ -1,4 +1,4 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
@@ -35,16 +35,18 | |||||
35 | -- Additional Comments: |
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35 | -- Additional Comments: | |
36 | -- |
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36 | -- | |
37 | ---------------------------------------------------------------------------------- |
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37 | ---------------------------------------------------------------------------------- | |
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38 | ||||
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39 | ---TDODO => Clean Enable pulse FSM | |||
38 | library IEEE; |
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40 | library IEEE; | |
39 | use IEEE.STD_LOGIC_1164.ALL; |
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41 | use IEEE.STD_LOGIC_1164.ALL; | |
40 | use IEEE.NUMERIC_STD.all; |
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42 | use IEEE.NUMERIC_STD.all; | |
41 | library lpp; |
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43 | library lpp; | |
42 | use lpp.amba_lcd_16x2_ctrlr.all; |
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44 | use lpp.amba_lcd_16x2_ctrlr.all; | |
43 |
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45 | use lpp.lcd_16x2_cfg.all; | ||
44 |
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46 | |||
45 | entity LCD_16x2_DRIVER is |
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47 | entity LCD_16x2_DRIVER is | |
46 | generic( |
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48 | generic( | |
47 |
OSC_Freq_ |
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49 | OSC_Freq_KHz : integer:=50000 | |
48 | ); |
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50 | ); | |
49 | Port( |
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51 | Port( | |
50 | reset : in STD_LOGIC; |
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52 | reset : in STD_LOGIC; | |
@@ -57,11 +59,129 end LCD_16x2_DRIVER; | |||||
57 |
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59 | |||
58 | architecture Behavioral of LCD_16x2_DRIVER is |
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60 | architecture Behavioral of LCD_16x2_DRIVER is | |
59 |
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61 | |||
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62 | type stateT is (idle,Enable0,Enable1,Enable2,tempo); | |||
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63 | signal state : stateT; | |||
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64 | ||||
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65 | ||||
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66 | constant trigger_4us : integer := 5; | |||
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67 | constant trigger_100us : integer := 100; | |||
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68 | constant trigger_4ms : integer := 4200; | |||
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69 | constant trigger_20ms : integer := 20000; | |||
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70 | ||||
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71 | ||||
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72 | signal i : integer :=0; | |||
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73 | signal reset_i : std_logic := '0'; | |||
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74 | signal tempoTRIG : integer :=0; | |||
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75 | ||||
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76 | signal clk_1us : std_logic; | |||
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77 | signal clk_1us_reg : std_logic; | |||
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78 | ||||
60 | begin |
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79 | begin | |
61 |
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80 | |||
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81 | ||||
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82 | CLK0: LCD_CLK_GENERATOR | |||
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83 | generic map(OSC_Freq_KHz) | |||
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84 | Port map( clk,reset,clk_1us); | |||
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85 | ||||
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86 | ||||
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87 | ||||
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88 | process(clk_1us,reset_i) | |||
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89 | begin | |||
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90 | if reset_i = '0' then | |||
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91 | i <= 0; | |||
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92 | elsif clk_1us'event and clk_1us ='1' then | |||
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93 | i <= i+1; | |||
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94 | end if; | |||
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95 | end process; | |||
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96 | ||||
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97 | LCD_CTRL.LCD_RW <= '0'; | |||
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98 | ||||
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99 | process(clk,reset) | |||
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100 | begin | |||
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101 | if reset = '0' then | |||
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102 | state <= idle; | |||
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103 | LCD_CTRL.LCD_E <= '0'; | |||
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104 | SYNCH.DRVR_READY <= '0'; | |||
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105 | SYNCH.LCD_INITIALISED <= '0'; | |||
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106 | reset_i <= '0'; | |||
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107 | elsif clk'event and clk = '1' then | |||
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108 | case state is | |||
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109 | when idle => | |||
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110 | SYNCH.LCD_INITIALISED <= '1'; | |||
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111 | LCD_CTRL.LCD_E <= '0'; | |||
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112 | if DRIVER_CMD.Exec = '1' then | |||
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113 | state <= Enable0; | |||
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114 | reset_i <= '1'; | |||
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115 | SYNCH.DRVR_READY <= '0'; | |||
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116 | LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word; | |||
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117 | LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data; | |||
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118 | case DRIVER_CMD.Duration is | |||
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119 | when Duration_4us => | |||
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120 | tempoTRIG <= trigger_4us; | |||
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121 | when Duration_100us => | |||
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122 | tempoTRIG <= trigger_100us; | |||
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123 | when Duration_4ms => | |||
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124 | tempoTRIG <= trigger_4ms; | |||
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125 | when Duration_20ms => | |||
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126 | tempoTRIG <= trigger_20ms; | |||
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127 | when others => | |||
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128 | tempoTRIG <= trigger_20ms; | |||
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129 | end case; | |||
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130 | else | |||
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131 | SYNCH.DRVR_READY <= '1'; | |||
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132 | reset_i <= '0'; | |||
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133 | end if; | |||
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134 | when Enable0 => | |||
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135 | if i = 1 then | |||
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136 | reset_i <= '0'; | |||
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137 | LCD_CTRL.LCD_E <= '1'; | |||
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138 | state <= Enable1; | |||
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139 | else | |||
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140 | reset_i <= '1'; | |||
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141 | LCD_CTRL.LCD_E <= '0'; | |||
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142 | end if; | |||
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143 | when Enable1 => | |||
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144 | if i = 2 then | |||
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145 | reset_i <= '0'; | |||
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146 | LCD_CTRL.LCD_E <= '0'; | |||
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147 | state <= Enable2; | |||
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148 | else | |||
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149 | reset_i <= '1'; | |||
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150 | LCD_CTRL.LCD_E <= '1'; | |||
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151 | end if; | |||
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152 | when Enable2 => | |||
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153 | if i = 1 then | |||
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154 | reset_i <= '0'; | |||
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155 | LCD_CTRL.LCD_E <= '0'; | |||
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156 | state <= tempo; | |||
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157 | else | |||
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158 | reset_i <= '1'; | |||
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159 | LCD_CTRL.LCD_E <= '0'; | |||
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160 | end if; | |||
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161 | when tempo => | |||
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162 | if i = tempoTRIG then | |||
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163 | reset_i <= '0'; | |||
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164 | state <= idle; | |||
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165 | else | |||
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166 | reset_i <= '1'; | |||
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167 | end if; | |||
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168 | end case; | |||
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169 | end if; | |||
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170 | end process; | |||
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171 | ||||
62 | end Behavioral; |
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172 | end Behavioral; | |
63 |
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173 | |||
64 |
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174 | |||
65 |
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175 | |||
66 |
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176 | |||
67 |
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177 | |||
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178 | ||||
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179 | ||||
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180 | ||||
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181 | ||||
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182 | ||||
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183 | ||||
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184 | ||||
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185 | ||||
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186 | ||||
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187 |
@@ -153,12 +153,12 begin | |||||
153 | DRIVER_CMD.Duration <= Duration_100us; |
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153 | DRIVER_CMD.Duration <= Duration_100us; | |
154 | DRIVER_CMD.CMD_Data <= '1'; |
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154 | DRIVER_CMD.CMD_Data <= '1'; | |
155 | DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); |
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155 | DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); | |
156 | i <= i + 1; |
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157 | state <= Refresh0; |
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156 | state <= Refresh0; | |
158 | else |
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157 | else | |
159 | DRIVER_CMD.Exec <= '0'; |
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158 | DRIVER_CMD.Exec <= '0'; | |
160 | end if; |
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159 | end if; | |
161 | when Refresh0=> |
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160 | when Refresh0=> | |
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161 | i <= i + 1; | |||
162 | state <= Refresh1; |
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162 | state <= Refresh1; | |
163 | DRIVER_CMD.Exec <= '0'; |
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163 | DRIVER_CMD.Exec <= '0'; | |
164 | when Refresh1=> |
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164 | when Refresh1=> | |
@@ -205,7 +205,7 begin | |||||
205 | DRIVER_CMD.Exec <= '1'; |
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205 | DRIVER_CMD.Exec <= '1'; | |
206 | DRIVER_CMD.Duration <= Duration_4ms; |
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206 | DRIVER_CMD.Duration <= Duration_4ms; | |
207 | DRIVER_CMD.CMD_Data <= '0'; |
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207 | DRIVER_CMD.CMD_Data <= '0'; | |
208 |
DRIVER_CMD.Word <= |
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208 | DRIVER_CMD.Word <= RetHome; | |
209 | state <= Idle; |
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209 | state <= Idle; | |
210 | else |
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210 | else | |
211 | DRIVER_CMD.Exec <= '0'; |
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211 | DRIVER_CMD.Exec <= '0'; |
@@ -83,13 +83,12 LCD_CS2 <= '0'; | |||||
83 |
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83 | |||
84 | SF_CE0 <= '1'; |
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84 | SF_CE0 <= '1'; | |
85 |
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85 | |||
86 | rst <= not reset; |
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87 |
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86 | |||
88 |
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87 | |||
89 |
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88 | |||
90 | Driver0 : LCD_16x2_ENGINE |
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89 | Driver0 : LCD_16x2_ENGINE | |
91 | generic map(50000) |
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90 | generic map(50000) | |
92 | Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); |
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91 | Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL); | |
93 |
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92 | |||
94 | FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else |
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93 | FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else | |
95 | X"42" when Bp1 = '1' else |
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94 | X"42" when Bp1 = '1' else |
@@ -1,3 +1,4 | |||||
1 | ./dsp/iir_filter |
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2 | ./general_purpose |
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1 | ./general_purpose | |
3 | ./lpp_amba |
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2 | ./lpp_amba | |
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3 | ./dsp/iir_filter | |||
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4 | ./amba_lcd_16x2_ctrlr |
@@ -1,12 +1,12 | |||||
1 | APB_IIR_CEL.vhd |
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1 | APB_IIR_CEL.vhd | |
2 | FILTER.vhd |
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3 | FILTER_RAM_CTRLR.vhd |
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4 | FILTERcfg.vhd |
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2 | FILTERcfg.vhd | |
5 | FilterCTRLR.vhd |
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3 | FilterCTRLR.vhd | |
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4 | FILTER_RAM_CTRLR.vhd | |||
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5 | FILTER.vhd | |||
6 | IIR_CEL_CTRLR.vhd |
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6 | IIR_CEL_CTRLR.vhd | |
7 | IIR_CEL_FILTER.vhd |
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7 | IIR_CEL_FILTER.vhd | |
8 | RAM.vhd |
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8 | iir_filter.vhd | |
9 | RAM_CEL.vhd |
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9 | RAM_CEL.vhd | |
10 | RAM_CTRLR2.vhd |
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10 | RAM_CTRLR2.vhd | |
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11 | RAM.vhd | |||
11 | Top_Filtre_IIR.vhd |
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12 | Top_Filtre_IIR.vhd | |
12 | iir_filter.vhd |
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@@ -1,13 +1,13 | |||||
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1 | Adder.vhd | |||
1 | ADDRcntr.vhd |
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2 | ADDRcntr.vhd | |
2 | ALU.vhd |
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3 | ALU.vhd | |
3 | Adder.vhd |
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4 | general_purpose.vhd | |
4 | MAC.vhd |
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5 | MAC_CONTROLER.vhd |
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5 | MAC_CONTROLER.vhd | |
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6 | MAC_MUX2.vhd | |||
6 | MAC_MUX.vhd |
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7 | MAC_MUX.vhd | |
7 | MAC_MUX2.vhd |
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8 | MAC_REG.vhd |
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8 | MAC_REG.vhd | |
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9 | MAC.vhd | |||
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10 | Multiplier.vhd | |||
9 | MUX2.vhd |
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11 | MUX2.vhd | |
10 | Multiplier.vhd |
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11 | REG.vhd |
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12 | REG.vhd | |
12 | Shifter.vhd |
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13 | Shifter.vhd | |
13 | general_purpose.vhd |
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