HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r555:b0c415521d3c

update : suppression d'une erreur de min-delay au niveau du time managment

pellion -

r555:b0c415521d3c (MINI-LFR) WFP_MS-0-1-66 JC

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r555:b0c415521d3c

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                    pirq_ms                => 6,
                    pirq_wfp               => 14,
                    hindex                 => 2,
-                   top_lfr_version        => X"000141")  -- aa.bb.cc version
+                   top_lfr_version        => X"000142")  -- aa.bb.cc version
                  PORT MAP (
                    clk             => clk_25,
                    rstn            => LFR_rstn,

lib/lpp/lfr_management/coarse_time_counter.vhd +17 -3

                SIGNAL set_synchronized       : STD_LOGIC;
                SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
-               --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
+               --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
+               SIGNAL set_TCU_reg       :  STD_LOGIC;
              BEGIN  -- beh
                -----------------------------------------------------------------------------
                    clk       => clk,
                    rstn      => rstn,
                    MAX_VALUE => "111" & X"FFFFFFF" ,
-                   set       => set_TCU,
+                   set       => set_TCU_reg,
                    set_value => set_TCU_value(30 DOWNTO 0),
                    add1      => CT_add1,
                    counter   => coarse_time(30 DOWNTO 0));
                    coarse_time_31_reg <= '0';
                  ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                    coarse_time_31_reg <= coarse_time_31;
-                   IF set_TCU = '1' OR CT_add1 = '1' THEN
+                   IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
                      coarse_time_new_counter <= '1';
                    ELSE
                      coarse_time_new_counter <= '0';
                  END IF;
                END PROCESS;
+               -----------------------------------------------------------------------------
+               -- Just to try to limit the constraint
+               PROCESS (clk, rstn)
+               BEGIN  -- PROCESS
+                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                   set_TCU_reg <= '0';
+                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                   set_TCU_reg <= set_TCU;
+                 END IF;
+               END PROCESS;
+               -----------------------------------------------------------------------------
              END beh;
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd 0 -1

                SIGNAL sample_load    : STD_LOGIC;
                SIGNAL sample_valid   : STD_LOGIC;
                SIGNAL sample_valid_r : STD_LOGIC;
-               SIGNAL sample_valid_delay : STD_LOGIC;
                SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);

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