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update : suppression d'une erreur de min-delay au niveau du time managment
pellion -
r555:b0c415521d3c (MINI-LFR) WFP_MS-0-1-66 JC
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@@ -522,7 +522,7 BEGIN -- beh
522 pirq_ms => 6,
522 pirq_ms => 6,
523 pirq_wfp => 14,
523 pirq_wfp => 14,
524 hindex => 2,
524 hindex => 2,
525 top_lfr_version => X"000141") -- aa.bb.cc version
525 top_lfr_version => X"000142") -- aa.bb.cc version
526 PORT MAP (
526 PORT MAP (
527 clk => clk_25,
527 clk => clk_25,
528 rstn => LFR_rstn,
528 rstn => LFR_rstn,
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@@ -39,7 +39,9 ARCHITECTURE beh OF coarse_time_counter
39 SIGNAL set_synchronized : STD_LOGIC;
39 SIGNAL set_synchronized : STD_LOGIC;
40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
41
41
42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
43 SIGNAL set_TCU_reg : STD_LOGIC;
44
43 BEGIN -- beh
45 BEGIN -- beh
44
46
45 -----------------------------------------------------------------------------
47 -----------------------------------------------------------------------------
@@ -54,7 +56,7 BEGIN -- beh
54 clk => clk,
56 clk => clk,
55 rstn => rstn,
57 rstn => rstn,
56 MAX_VALUE => "111" & X"FFFFFFF" ,
58 MAX_VALUE => "111" & X"FFFFFFF" ,
57 set => set_TCU,
59 set => set_TCU_reg,
58 set_value => set_TCU_value(30 DOWNTO 0),
60 set_value => set_TCU_value(30 DOWNTO 0),
59 add1 => CT_add1,
61 add1 => CT_add1,
60 counter => coarse_time(30 DOWNTO 0));
62 counter => coarse_time(30 DOWNTO 0));
@@ -98,7 +100,7 BEGIN -- beh
98 coarse_time_31_reg <= '0';
100 coarse_time_31_reg <= '0';
99 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
101 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
100 coarse_time_31_reg <= coarse_time_31;
102 coarse_time_31_reg <= coarse_time_31;
101 IF set_TCU = '1' OR CT_add1 = '1' THEN
103 IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
102 coarse_time_new_counter <= '1';
104 coarse_time_new_counter <= '1';
103 ELSE
105 ELSE
104 coarse_time_new_counter <= '0';
106 coarse_time_new_counter <= '0';
@@ -106,4 +108,16 BEGIN -- beh
106 END IF;
108 END IF;
107 END PROCESS;
109 END PROCESS;
108
110
111 -----------------------------------------------------------------------------
112 -- Just to try to limit the constraint
113 PROCESS (clk, rstn)
114 BEGIN -- PROCESS
115 IF rstn = '0' THEN -- asynchronous reset (active low)
116 set_TCU_reg <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 set_TCU_reg <= set_TCU;
119 END IF;
120 END PROCESS;
121 -----------------------------------------------------------------------------
122
109 END beh; No newline at end of file
123 END beh;
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@@ -146,7 +146,6 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
146 SIGNAL sample_load : STD_LOGIC;
146 SIGNAL sample_load : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
149 SIGNAL sample_valid_delay : STD_LOGIC;
150 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
151
150
152
151
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