@@ -490,7 +490,7 BEGIN | |||||
490 | pirq_ms => 6, |
|
490 | pirq_ms => 6, | |
491 | pirq_wfp => 14, |
|
491 | pirq_wfp => 14, | |
492 | hindex => 2, |
|
492 | hindex => 2, | |
493 |
top_lfr_version => X"0000000 |
|
493 | top_lfr_version => X"00000005") | |
494 | PORT MAP ( |
|
494 | PORT MAP ( | |
495 | clk => clkm, |
|
495 | clk => clkm, | |
496 | rstn => rstn, |
|
496 | rstn => rstn, |
@@ -146,7 +146,7 BEGIN | |||||
146 |
|
146 | |||
147 | send => single_send, |
|
147 | send => single_send, | |
148 | address => address, |
|
148 | address => address, | |
149 | data => data, |
|
149 | data => data_2_halfword, | |
150 | ren => single_ren, |
|
150 | ren => single_ren, | |
151 |
|
151 | |||
152 | send_ok => single_send_ok, -- TODO |
|
152 | send_ok => single_send_ok, -- TODO |
@@ -59,7 +59,17 ENTITY lpp_lfr IS | |||||
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
|
63 | ||||
|
64 | --debug | |||
|
65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
66 | debug_f0_data_valid : OUT STD_LOGIC; | |||
|
67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
68 | debug_f1_data_valid : OUT STD_LOGIC; | |||
|
69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
70 | debug_f2_data_valid : OUT STD_LOGIC; | |||
|
71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
72 | debug_f3_data_valid : OUT STD_LOGIC | |||
63 |
|
|
73 | ); | |
64 | END lpp_lfr; |
|
74 | END lpp_lfr; | |
65 |
|
75 | |||
@@ -395,7 +405,17 BEGIN | |||||
395 | data_f3_data_out => data_f3_data_out, |
|
405 | data_f3_data_out => data_f3_data_out, | |
396 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
406 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
397 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
407 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
398 | data_f3_data_out_ren => data_f3_data_out_ren |
|
408 | data_f3_data_out_ren => data_f3_data_out_ren, | |
|
409 | ||||
|
410 | --debug | |||
|
411 | debug_f0_data => debug_f0_data, | |||
|
412 | debug_f0_data_valid => debug_f0_data_valid , | |||
|
413 | debug_f1_data => debug_f1_data , | |||
|
414 | debug_f1_data_valid => debug_f1_data_valid, | |||
|
415 | debug_f2_data => debug_f2_data , | |||
|
416 | debug_f2_data_valid => debug_f2_data_valid , | |||
|
417 | debug_f3_data => debug_f3_data , | |||
|
418 | debug_f3_data_valid => debug_f3_data_valid | |||
399 |
|
|
419 | ||
400 | ); |
|
420 | ); | |
401 |
|
421 |
@@ -309,9 +309,12 BEGIN -- beh | |||||
309 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
|
309 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
310 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
310 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |
311 | all_status: FOR I IN 3 DOWNTO 0 LOOP |
|
311 | all_status: FOR I IN 3 DOWNTO 0 LOOP | |
312 | reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
312 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
313 | reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
|
313 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
314 | reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; |
|
314 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
|
315 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |||
|
316 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |||
|
317 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |||
315 | END LOOP all_status; |
|
318 | END LOOP all_status; | |
316 |
|
319 | |||
317 | paddr := "000000"; |
|
320 | paddr := "000000"; |
@@ -99,7 +99,17 PACKAGE lpp_lfr_pkg IS | |||||
99 | ahbo : OUT AHB_Mst_Out_Type; |
|
99 | ahbo : OUT AHB_Mst_Out_Type; | |
100 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
100 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
101 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
101 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
102 |
data_shaping_BW : OUT STD_LOGIC |
|
102 | data_shaping_BW : OUT STD_LOGIC; | |
|
103 | ||||
|
104 | --debug | |||
|
105 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
106 | debug_f0_data_valid : OUT STD_LOGIC; | |||
|
107 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
108 | debug_f1_data_valid : OUT STD_LOGIC; | |||
|
109 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
110 | debug_f2_data_valid : OUT STD_LOGIC; | |||
|
111 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |||
|
112 | debug_f3_data_valid : OUT STD_LOGIC ); | |||
103 | END COMPONENT; |
|
113 | END COMPONENT; | |
104 |
|
114 | |||
105 | COMPONENT lpp_lfr_apbreg |
|
115 | COMPONENT lpp_lfr_apbreg |
@@ -127,9 +127,17 ENTITY lpp_waveform IS | |||||
127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
128 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
128 | data_f3_data_out_valid : OUT STD_LOGIC; | |
129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
130 | data_f3_data_out_ren : IN STD_LOGIC |
|
130 | data_f3_data_out_ren : IN STD_LOGIC; | |
131 |
|
131 | |||
132 |
|
132 | --debug | ||
|
133 | debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
134 | debug_f0_data_valid : OUT STD_LOGIC; | |||
|
135 | debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
136 | debug_f1_data_valid : OUT STD_LOGIC; | |||
|
137 | debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
138 | debug_f2_data_valid : OUT STD_LOGIC; | |||
|
139 | debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
140 | debug_f3_data_valid : OUT STD_LOGIC | |||
133 | ); |
|
141 | ); | |
134 |
|
142 | |||
135 | END lpp_waveform; |
|
143 | END lpp_waveform; | |
@@ -219,7 +227,7 BEGIN -- beh | |||||
219 | data_in_valid => data_f0_in_valid, |
|
227 | data_in_valid => data_f0_in_valid, | |
220 | data_out => data_f0_out, |
|
228 | data_out => data_f0_out, | |
221 | data_out_valid => data_f0_out_valid); |
|
229 | data_out_valid => data_f0_out_valid); | |
222 |
|
230 | |||
223 |
|
|
231 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; | |
224 |
|
232 | |||
225 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot |
|
233 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot | |
@@ -269,6 +277,18 BEGIN -- beh | |||||
269 | data_out => data_f3_out, |
|
277 | data_out => data_f3_out, | |
270 | data_out_valid => data_f3_out_valid); |
|
278 | data_out_valid => data_f3_out_valid); | |
271 |
|
279 | |||
|
280 | ----------------------------------------------------------------------------- | |||
|
281 | -- DEBUG | |||
|
282 | debug_f0_data_valid <= data_f0_out_valid; | |||
|
283 | debug_f0_data <= data_f0_out; | |||
|
284 | debug_f1_data_valid <= data_f1_out_valid; | |||
|
285 | debug_f1_data <= data_f1_out; | |||
|
286 | debug_f2_data_valid <= data_f2_out_valid; | |||
|
287 | debug_f2_data <= data_f2_out; | |||
|
288 | debug_f3_data_valid <= data_f3_out_valid; | |||
|
289 | debug_f3_data <= data_f3_out; | |||
|
290 | ----------------------------------------------------------------------------- | |||
|
291 | ||||
272 | PROCESS (clk, rstn) |
|
292 | PROCESS (clk, rstn) | |
273 | BEGIN -- PROCESS |
|
293 | BEGIN -- PROCESS | |
274 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
294 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
@@ -323,6 +343,7 BEGIN -- beh | |||||
323 |
|
343 | |||
324 | data_out => wdata, |
|
344 | data_out => wdata, | |
325 | data_out_wen => data_wen, |
|
345 | data_out_wen => data_wen, | |
|
346 | full_almost => full_almost, | |||
326 | full => full); |
|
347 | full => full); | |
327 |
|
348 | |||
328 | lpp_waveform_fifo_1 : lpp_waveform_fifo |
|
349 | lpp_waveform_fifo_1 : lpp_waveform_fifo |
@@ -51,6 +51,7 ENTITY lpp_waveform_fifo_arbiter IS | |||||
51 | --------------------------------------------------------------------------- |
|
51 | --------------------------------------------------------------------------- | |
52 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
52 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
53 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
53 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
54 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
54 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
55 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
55 |
|
56 | |||
56 | ); |
|
57 | ); | |
@@ -58,6 +59,9 END ENTITY; | |||||
58 |
|
59 | |||
59 |
|
60 | |||
60 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
|
61 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS | |
|
62 | TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST); | |||
|
63 | SIGNAL state : state_type_fifo_arbiter; | |||
|
64 | ||||
61 |
|
|
65 | ----------------------------------------------------------------------------- | |
62 | -- DATA MUX |
|
66 | -- DATA MUX | |
63 | ----------------------------------------------------------------------------- |
|
67 | ----------------------------------------------------------------------------- | |
@@ -77,6 +81,9 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||||
77 | ----------------------------------------------------------------------------- |
|
81 | ----------------------------------------------------------------------------- | |
78 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
82 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
79 | SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
83 | SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
84 | SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
85 | SIGNAL sel_reg : STD_LOGIC; | |||
|
86 | SIGNAL sel_ack : STD_LOGIC; | |||
80 | SIGNAL no_sel : STD_LOGIC; |
|
87 | SIGNAL no_sel : STD_LOGIC; | |
81 |
|
88 | |||
82 | ----------------------------------------------------------------------------- |
|
89 | ----------------------------------------------------------------------------- | |
@@ -86,13 +93,13 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||||
86 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
93 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
87 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
94 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
88 |
|
95 | |||
89 | SIGNAL shift_data_enable : STD_LOGIC; |
|
96 | --SIGNAL shift_data_enable : STD_LOGIC; | |
90 | SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
97 | --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
91 | SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
98 | --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
92 |
|
99 | |||
93 | SIGNAL shift_time_enable : STD_LOGIC; |
|
100 | --SIGNAL shift_time_enable : STD_LOGIC; | |
94 | SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
101 | --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
95 | SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
102 | --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
96 |
|
103 | |||
97 | BEGIN |
|
104 | BEGIN | |
98 |
|
105 | |||
@@ -101,62 +108,125 BEGIN | |||||
101 | ----------------------------------------------------------------------------- |
|
108 | ----------------------------------------------------------------------------- | |
102 | PROCESS (clk, rstn) |
|
109 | PROCESS (clk, rstn) | |
103 | BEGIN -- PROCESS |
|
110 | BEGIN -- PROCESS | |
104 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
111 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
105 | count_enable <= '0'; |
|
112 | count_enable <= '0'; | |
106 | shift_time_enable <= '0'; |
|
113 | data_in_ack <= (OTHERS => '0'); | |
107 | shift_data_enable <= '0'; |
|
114 | data_out_wen <= (OTHERS => '1'); | |
|
115 | sel_ack <= '0'; | |||
|
116 | state <= IDLE; | |||
|
117 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
118 | count_enable <= '0'; | |||
108 | data_in_ack <= (OTHERS => '0'); |
|
119 | data_in_ack <= (OTHERS => '0'); | |
109 | data_out_wen <= (OTHERS => '1'); |
|
120 | data_out_wen <= (OTHERS => '1'); | |
110 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
121 | sel_ack <= '0'; | |
111 |
IF run = '0' |
|
122 | IF run = '0' THEN | |
112 | count_enable <= '0'; |
|
123 | state <= IDLE; | |
113 | shift_time_enable <= '0'; |
|
|||
114 | shift_data_enable <= '0'; |
|
|||
115 | data_in_ack <= (OTHERS => '0'); |
|
|||
116 | data_out_wen <= (OTHERS => '1'); |
|
|||
117 | ELSE |
|
124 | ELSE | |
118 | --COUNT |
|
125 | CASE state IS | |
119 | IF shift_data_s = "10" THEN |
|
126 | WHEN IDLE => | |
120 |
|
|
127 | IF no_sel = '0' THEN | |
121 | ELSE |
|
128 | state <= TIME1; | |
122 | count_enable <= '0'; |
|
129 | END IF; | |
123 |
EN |
|
130 | WHEN TIME1 => | |
124 | --DATA |
|
131 | count_enable <= '1'; | |
125 | IF shift_time_s = "10" THEN |
|
132 | IF UNSIGNED(count) = 0 THEN | |
126 | shift_data_enable <= '1'; |
|
133 | state <= TIME2; | |
127 | ELSE |
|
134 | data_out_wen <= NOT sel; | |
128 | shift_data_enable <= '0'; |
|
135 | data_out <= data_sel(0); | |
129 | END IF; |
|
136 | ELSE | |
130 |
|
137 | state <= DATA1; | ||
131 | --TIME |
|
138 | END IF; | |
132 | IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR |
|
139 | WHEN TIME2 => | |
133 | shift_time_s = "00" OR |
|
140 | data_out_wen <= NOT sel; | |
134 | shift_time_s = "01" |
|
141 | data_out <= data_sel(1) ; | |
135 | THEN |
|
142 | state <= DATA1; | |
136 | shift_time_enable <= '1'; |
|
143 | WHEN DATA1 => | |
137 | ELSE |
|
144 | data_out_wen <= NOT sel; | |
138 | shift_time_enable <= '0'; |
|
145 | data_out <= data_sel(2); | |
139 | END IF; |
|
146 | state <= DATA2; | |
140 |
|
147 | WHEN DATA2 => | ||
141 | --ACK |
|
148 | data_out_wen <= NOT sel; | |
142 | IF shift_data_s = "10" THEN |
|
149 | data_out <= data_sel(3); | |
143 | data_in_ack <= sel; |
|
150 | state <= DATA3; | |
144 | ELSE |
|
151 | WHEN DATA3 => | |
145 |
|
|
152 | data_out_wen <= NOT sel; | |
146 | END IF; |
|
153 | data_out <= data_sel(4); | |
147 |
|
154 | state <= LAST; | ||
148 | --VALID OUT |
|
155 | data_in_ack <= sel; | |
149 | all_wen: FOR I IN 3 DOWNTO 0 LOOP |
|
156 | WHEN LAST => | |
150 | IF sel(I) = '1' AND count_enable = '0' THEN |
|
157 | state <= IDLE; | |
151 | data_out_wen(I) <= '0'; |
|
158 | sel_ack <= '1'; | |
152 |
|
|
159 | ||
153 | data_out_wen(I) <= '1'; |
|
160 | WHEN OTHERS => NULL; | |
154 |
|
|
161 | END CASE; | |
155 | END LOOP all_wen; |
|
|||
156 |
|
||||
157 | END IF; |
|
162 | END IF; | |
158 | END IF; |
|
163 | END IF; | |
159 | END PROCESS; |
|
164 | END PROCESS; | |
|
165 | ----------------------------------------------------------------------------- | |||
|
166 | ||||
|
167 | ||||
|
168 | --PROCESS (clk, rstn) | |||
|
169 | --BEGIN -- PROCESS | |||
|
170 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
171 | -- count_enable <= '0'; | |||
|
172 | -- shift_time_enable <= '0'; | |||
|
173 | -- shift_data_enable <= '0'; | |||
|
174 | -- data_in_ack <= (OTHERS => '0'); | |||
|
175 | -- data_out_wen <= (OTHERS => '1'); | |||
|
176 | -- sel_ack <= '0'; | |||
|
177 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
178 | -- IF run = '0' OR no_sel = '1' THEN | |||
|
179 | -- count_enable <= '0'; | |||
|
180 | -- shift_time_enable <= '0'; | |||
|
181 | -- shift_data_enable <= '0'; | |||
|
182 | -- data_in_ack <= (OTHERS => '0'); | |||
|
183 | -- data_out_wen <= (OTHERS => '1'); | |||
|
184 | -- sel_ack <= '0'; | |||
|
185 | -- ELSE | |||
|
186 | -- --COUNT | |||
|
187 | -- IF shift_data_s = "10" THEN | |||
|
188 | -- count_enable <= '1'; | |||
|
189 | -- ELSE | |||
|
190 | -- count_enable <= '0'; | |||
|
191 | -- END IF; | |||
|
192 | -- --DATA | |||
|
193 | -- IF shift_time_s = "10" THEN | |||
|
194 | -- shift_data_enable <= '1'; | |||
|
195 | -- ELSE | |||
|
196 | -- shift_data_enable <= '0'; | |||
|
197 | -- END IF; | |||
|
198 | ||||
|
199 | -- --TIME | |||
|
200 | -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR | |||
|
201 | -- shift_time_s = "00" OR | |||
|
202 | -- shift_time_s = "01" | |||
|
203 | -- THEN | |||
|
204 | -- shift_time_enable <= '1'; | |||
|
205 | -- ELSE | |||
|
206 | -- shift_time_enable <= '0'; | |||
|
207 | -- END IF; | |||
|
208 | ||||
|
209 | -- --ACK | |||
|
210 | -- IF shift_data_s = "10" THEN | |||
|
211 | -- data_in_ack <= sel; | |||
|
212 | -- sel_ack <= '1'; | |||
|
213 | -- ELSE | |||
|
214 | -- data_in_ack <= (OTHERS => '0'); | |||
|
215 | -- sel_ack <= '0'; | |||
|
216 | -- END IF; | |||
|
217 | ||||
|
218 | -- --VALID OUT | |||
|
219 | -- all_wen: FOR I IN 3 DOWNTO 0 LOOP | |||
|
220 | -- IF sel(I) = '1' AND count_enable = '0' THEN | |||
|
221 | -- data_out_wen(I) <= '0'; | |||
|
222 | -- ELSE | |||
|
223 | -- data_out_wen(I) <= '1'; | |||
|
224 | -- END IF; | |||
|
225 | -- END LOOP all_wen; | |||
|
226 | ||||
|
227 | -- END IF; | |||
|
228 | -- END IF; | |||
|
229 | --END PROCESS; | |||
160 |
|
230 | |||
161 | ----------------------------------------------------------------------------- |
|
231 | ----------------------------------------------------------------------------- | |
162 | -- DATA MUX |
|
232 | -- DATA MUX | |
@@ -196,18 +266,19 BEGIN | |||||
196 | data_2 WHEN sel(2) = '1' ELSE |
|
266 | data_2 WHEN sel(2) = '1' ELSE | |
197 | data_3; |
|
267 | data_3; | |
198 |
|
268 | |||
199 | data_out <= data_sel(0) WHEN shift_time = "00" ELSE |
|
269 | --data_out <= data_sel(0) WHEN shift_time = "00" ELSE | |
200 | data_sel(1) WHEN shift_time = "01" ELSE |
|
270 | -- data_sel(1) WHEN shift_time = "01" ELSE | |
201 | data_sel(2) WHEN shift_data = "00" ELSE |
|
271 | -- data_sel(2) WHEN shift_data = "00" ELSE | |
202 | data_sel(3) WHEN shift_data = "01" ELSE |
|
272 | -- data_sel(3) WHEN shift_data = "01" ELSE | |
203 | data_sel(4); |
|
273 | -- data_sel(4); | |
204 |
|
274 | |||
205 |
|
275 | |||
206 | ----------------------------------------------------------------------------- |
|
276 | ----------------------------------------------------------------------------- | |
207 | -- RR and SELECTION |
|
277 | -- RR and SELECTION | |
208 | ----------------------------------------------------------------------------- |
|
278 | ----------------------------------------------------------------------------- | |
209 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
|
279 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE | |
210 | valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); |
|
280 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); | |
|
281 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); | |||
211 | END GENERATE all_input_rr; |
|
282 | END GENERATE all_input_rr; | |
212 |
|
283 | |||
213 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
284 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
@@ -215,8 +286,34 BEGIN | |||||
215 | clk => clk, |
|
286 | clk => clk, | |
216 | rstn => rstn, |
|
287 | rstn => rstn, | |
217 | in_valid => valid_in_rr, |
|
288 | in_valid => valid_in_rr, | |
218 | out_grant => sel); |
|
289 | out_grant => sel_s); --sel_s); | |
219 |
|
290 | |||
|
291 | -- sel <= sel_s; | |||
|
292 | ||||
|
293 | PROCESS (clk, rstn) | |||
|
294 | BEGIN -- PROCESS | |||
|
295 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
296 | sel <= "0000"; | |||
|
297 | sel_reg <= '0'; | |||
|
298 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
299 | -- sel_reg | |||
|
300 | -- sel_ack | |||
|
301 | -- sel_s | |||
|
302 | -- sel = "0000 " | |||
|
303 | --sel <= sel_s; | |||
|
304 | IF sel_reg = '0' OR sel_ack = '1' | |||
|
305 | --OR shift_data_s = "10" | |||
|
306 | THEN | |||
|
307 | sel <= sel_s; | |||
|
308 | IF sel_s = "0000" THEN | |||
|
309 | sel_reg <= '0'; | |||
|
310 | ELSE | |||
|
311 | sel_reg <= '1'; | |||
|
312 | END IF; | |||
|
313 | END IF; | |||
|
314 | END IF; | |||
|
315 | END PROCESS; | |||
|
316 | ||||
220 |
|
|
317 | no_sel <= '1' WHEN sel = "0000" ELSE '0'; | |
221 |
|
318 | |||
222 | ----------------------------------------------------------------------------- |
|
319 | ----------------------------------------------------------------------------- | |
@@ -236,34 +333,34 BEGIN | |||||
236 | data => count, |
|
333 | data => count, | |
237 | data_s => count_s); |
|
334 | data_s => count_s); | |
238 |
|
335 | |||
239 | reg_shift_data_i: lpp_waveform_fifo_arbiter_reg |
|
336 | --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg | |
240 | GENERIC MAP ( |
|
337 | -- GENERIC MAP ( | |
241 | data_size => 2, |
|
338 | -- data_size => 2, | |
242 | data_nb => 4) |
|
339 | -- data_nb => 4) | |
243 | PORT MAP ( |
|
340 | -- PORT MAP ( | |
244 | clk => clk, |
|
341 | -- clk => clk, | |
245 | rstn => rstn, |
|
342 | -- rstn => rstn, | |
246 | run => run, |
|
343 | -- run => run, | |
247 | max_count => "10", -- 2 |
|
344 | -- max_count => "10", -- 2 | |
248 | enable => shift_data_enable, |
|
345 | -- enable => shift_data_enable, | |
249 | sel => sel, |
|
346 | -- sel => sel, | |
250 | data => shift_data, |
|
347 | -- data => shift_data, | |
251 | data_s => shift_data_s); |
|
348 | -- data_s => shift_data_s); | |
252 |
|
349 | |||
253 |
|
350 | |||
254 | reg_shift_time_i: lpp_waveform_fifo_arbiter_reg |
|
351 | --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg | |
255 | GENERIC MAP ( |
|
352 | -- GENERIC MAP ( | |
256 | data_size => 2, |
|
353 | -- data_size => 2, | |
257 | data_nb => 4) |
|
354 | -- data_nb => 4) | |
258 | PORT MAP ( |
|
355 | -- PORT MAP ( | |
259 | clk => clk, |
|
356 | -- clk => clk, | |
260 | rstn => rstn, |
|
357 | -- rstn => rstn, | |
261 | run => run, |
|
358 | -- run => run, | |
262 | max_count => "10", -- 2 |
|
359 | -- max_count => "10", -- 2 | |
263 | enable => shift_time_enable, |
|
360 | -- enable => shift_time_enable, | |
264 | sel => sel, |
|
361 | -- sel => sel, | |
265 | data => shift_time, |
|
362 | -- data => shift_time, | |
266 | data_s => shift_time_s); |
|
363 | -- data_s => shift_time_s); | |
267 |
|
364 | |||
268 |
|
365 | |||
269 |
|
366 |
@@ -36,12 +36,12 PACKAGE lpp_waveform_pkg IS | |||||
36 |
|
36 | |||
37 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
37 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); | |
38 |
|
38 | |||
39 | TYPE Data_Vector IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>) OF STD_LOGIC; |
|
39 | TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
40 |
|
40 | |||
41 | ----------------------------------------------------------------------------- |
|
41 | ----------------------------------------------------------------------------- | |
42 | -- SNAPSHOT |
|
42 | -- SNAPSHOT | |
43 | ----------------------------------------------------------------------------- |
|
43 | ----------------------------------------------------------------------------- | |
44 |
|
44 | |||
45 | COMPONENT lpp_waveform_snapshot |
|
45 | COMPONENT lpp_waveform_snapshot | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | data_size : INTEGER; |
|
47 | data_size : INTEGER; | |
@@ -102,13 +102,13 PACKAGE lpp_waveform_pkg IS | |||||
102 | ----------------------------------------------------------------------------- |
|
102 | ----------------------------------------------------------------------------- | |
103 | COMPONENT lpp_waveform |
|
103 | COMPONENT lpp_waveform | |
104 | GENERIC ( |
|
104 | GENERIC ( | |
105 |
tech |
|
105 | tech : INTEGER; | |
106 |
data_size |
|
106 | data_size : INTEGER; | |
107 | nb_data_by_buffer_size : INTEGER; |
|
107 | nb_data_by_buffer_size : INTEGER; | |
108 | nb_word_by_buffer_size : INTEGER; |
|
108 | nb_word_by_buffer_size : INTEGER; | |
109 |
nb_snapshot_param_size |
|
109 | nb_snapshot_param_size : INTEGER; | |
110 |
delta_vector_size |
|
110 | delta_vector_size : INTEGER; | |
111 |
delta_vector_size_f0_2 |
|
111 | delta_vector_size_f0_2 : INTEGER); | |
112 | PORT ( |
|
112 | PORT ( | |
113 | clk : IN STD_LOGIC; |
|
113 | clk : IN STD_LOGIC; | |
114 | rstn : IN STD_LOGIC; |
|
114 | rstn : IN STD_LOGIC; | |
@@ -126,8 +126,8 PACKAGE lpp_waveform_pkg IS | |||||
126 | burst_f0 : IN STD_LOGIC; |
|
126 | burst_f0 : IN STD_LOGIC; | |
127 | burst_f1 : IN STD_LOGIC; |
|
127 | burst_f1 : IN STD_LOGIC; | |
128 | burst_f2 : IN STD_LOGIC; |
|
128 | burst_f2 : IN STD_LOGIC; | |
129 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
129 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
131 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
131 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
132 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
132 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
133 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
133 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
@@ -166,7 +166,17 PACKAGE lpp_waveform_pkg IS | |||||
166 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
167 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
167 | data_f3_data_out_valid : OUT STD_LOGIC; | |
168 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
168 | data_f3_data_out_valid_burst : OUT STD_LOGIC; | |
169 |
data_f3_data_out_ren : IN STD_LOGIC |
|
169 | data_f3_data_out_ren : IN STD_LOGIC; | |
|
170 | ||||
|
171 | --debug | |||
|
172 | debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
173 | debug_f0_data_valid : OUT STD_LOGIC; | |||
|
174 | debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
175 | debug_f1_data_valid : OUT STD_LOGIC; | |||
|
176 | debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
177 | debug_f2_data_valid : OUT STD_LOGIC; | |||
|
178 | debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
|
179 | debug_f3_data_valid : OUT STD_LOGIC); | |||
170 | END COMPONENT; |
|
180 | END COMPONENT; | |
171 |
|
181 | |||
172 | COMPONENT lpp_waveform_dma_genvalid |
|
182 | COMPONENT lpp_waveform_dma_genvalid | |
@@ -197,8 +207,8 PACKAGE lpp_waveform_pkg IS | |||||
197 | wen : IN STD_LOGIC; |
|
207 | wen : IN STD_LOGIC; | |
198 | mem_re : OUT STD_LOGIC; |
|
208 | mem_re : OUT STD_LOGIC; | |
199 | mem_we : OUT STD_LOGIC; |
|
209 | mem_we : OUT STD_LOGIC; | |
200 |
mem_addr_ren : |
|
210 | mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); | |
201 |
mem_addr_wen : |
|
211 | mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); | |
202 | empty_almost : OUT STD_LOGIC; |
|
212 | empty_almost : OUT STD_LOGIC; | |
203 | empty : OUT STD_LOGIC; |
|
213 | empty : OUT STD_LOGIC; | |
204 | full_almost : OUT STD_LOGIC; |
|
214 | full_almost : OUT STD_LOGIC; | |
@@ -207,7 +217,7 PACKAGE lpp_waveform_pkg IS | |||||
207 |
|
217 | |||
208 | COMPONENT lpp_waveform_fifo_arbiter |
|
218 | COMPONENT lpp_waveform_fifo_arbiter | |
209 | GENERIC ( |
|
219 | GENERIC ( | |
210 |
tech |
|
220 | tech : INTEGER; | |
211 | nb_data_by_buffer_size : INTEGER); |
|
221 | nb_data_by_buffer_size : INTEGER); | |
212 | PORT ( |
|
222 | PORT ( | |
213 | clk : IN STD_LOGIC; |
|
223 | clk : IN STD_LOGIC; | |
@@ -220,6 +230,7 PACKAGE lpp_waveform_pkg IS | |||||
220 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
|
230 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); | |
221 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
231 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
222 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
232 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
233 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
223 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
234 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
224 | END COMPONENT; |
|
235 | END COMPONENT; | |
225 |
|
236 | |||
@@ -276,7 +287,7 PACKAGE lpp_waveform_pkg IS | |||||
276 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
287 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
277 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
288 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
278 | END COMPONENT; |
|
289 | END COMPONENT; | |
279 |
|
290 | |||
280 | ----------------------------------------------------------------------------- |
|
291 | ----------------------------------------------------------------------------- | |
281 | -- GEN ADDRESS |
|
292 | -- GEN ADDRESS | |
282 | ----------------------------------------------------------------------------- |
|
293 | ----------------------------------------------------------------------------- | |
@@ -311,7 +322,7 PACKAGE lpp_waveform_pkg IS | |||||
311 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
322 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
312 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
323 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
313 | END COMPONENT; |
|
324 | END COMPONENT; | |
314 |
|
325 | |||
315 | ----------------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------------- | |
316 | -- lpp_waveform_fifo_arbiter_reg |
|
327 | -- lpp_waveform_fifo_arbiter_reg | |
317 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- |
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