# HG changeset patch # User pellion # Date 2013-11-19 08:27:23 # Node ID af3a90f3ec47b27bb56cf2c603238cc7bd9d180e # Parent 201a69540ab81a91132e20f4934384c70b7e3364 WaveFormPicker :Correction du registre Status et de l'arbitre en entree de la FIFO diff --git a/designs/LFR-em-WaveFormPicker/leon3mp.vhd b/designs/LFR-em-WaveFormPicker/leon3mp.vhd --- a/designs/LFR-em-WaveFormPicker/leon3mp.vhd +++ b/designs/LFR-em-WaveFormPicker/leon3mp.vhd @@ -490,7 +490,7 @@ BEGIN pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00000003") + top_lfr_version => X"00000005") PORT MAP ( clk => clkm, rstn => rstn, diff --git a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd --- a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd @@ -146,7 +146,7 @@ BEGIN send => single_send, address => address, - data => data, + data => data_2_halfword, ren => single_ren, send_ok => single_send_ok, -- TODO diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -59,7 +59,17 @@ ENTITY lpp_lfr IS coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo -- - data_shaping_BW : OUT STD_LOGIC + data_shaping_BW : OUT STD_LOGIC; + + --debug + debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC ); END lpp_lfr; @@ -395,7 +405,17 @@ BEGIN data_f3_data_out => data_f3_data_out, data_f3_data_out_valid => data_f3_data_out_valid_s, data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, - data_f3_data_out_ren => data_f3_data_out_ren + data_f3_data_out_ren => data_f3_data_out_ren, + + --debug + debug_f0_data => debug_f0_data, + debug_f0_data_valid => debug_f0_data_valid , + debug_f1_data => debug_f1_data , + debug_f1_data_valid => debug_f1_data_valid, + debug_f2_data => debug_f2_data , + debug_f2_data_valid => debug_f2_data_valid , + debug_f3_data => debug_f3_data , + debug_f3_data_valid => debug_f3_data_valid ); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -309,9 +309,12 @@ BEGIN -- beh reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; all_status: FOR I IN 3 DOWNTO 0 LOOP - reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; - reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; - reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; + --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; + --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; + --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; + reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; + reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; + reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; END LOOP all_status; paddr := "000000"; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -99,7 +99,17 @@ PACKAGE lpp_lfr_pkg IS ahbo : OUT AHB_Mst_Out_Type; coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC); + data_shaping_BW : OUT STD_LOGIC; + + --debug + debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC ); END COMPONENT; COMPONENT lpp_lfr_apbreg diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -127,9 +127,17 @@ ENTITY lpp_waveform IS data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_data_out_valid : OUT STD_LOGIC; data_f3_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_ren : IN STD_LOGIC + data_f3_data_out_ren : IN STD_LOGIC; - + --debug + debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC ); END lpp_waveform; @@ -219,7 +227,7 @@ BEGIN -- beh data_in_valid => data_f0_in_valid, data_out => data_f0_out, data_out_valid => data_f0_out_valid); - + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1; lpp_waveform_snapshot_f1 : lpp_waveform_snapshot @@ -269,6 +277,18 @@ BEGIN -- beh data_out => data_f3_out, data_out_valid => data_f3_out_valid); + ----------------------------------------------------------------------------- + -- DEBUG + debug_f0_data_valid <= data_f0_out_valid; + debug_f0_data <= data_f0_out; + debug_f1_data_valid <= data_f1_out_valid; + debug_f1_data <= data_f1_out; + debug_f2_data_valid <= data_f2_out_valid; + debug_f2_data <= data_f2_out; + debug_f3_data_valid <= data_f3_out_valid; + debug_f3_data <= data_f3_out; + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) @@ -323,6 +343,7 @@ BEGIN -- beh data_out => wdata, data_out_wen => data_wen, + full_almost => full_almost, full => full); lpp_waveform_fifo_1 : lpp_waveform_fifo diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -51,6 +51,7 @@ ENTITY lpp_waveform_fifo_arbiter IS --------------------------------------------------------------------------- data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); @@ -58,6 +59,9 @@ END ENTITY; ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS + TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST); + SIGNAL state : state_type_fifo_arbiter; + ----------------------------------------------------------------------------- -- DATA MUX ----------------------------------------------------------------------------- @@ -77,6 +81,9 @@ ARCHITECTURE ar_lpp_waveform_fifo_arbite ----------------------------------------------------------------------------- SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sel_reg : STD_LOGIC; + SIGNAL sel_ack : STD_LOGIC; SIGNAL no_sel : STD_LOGIC; ----------------------------------------------------------------------------- @@ -86,13 +93,13 @@ ARCHITECTURE ar_lpp_waveform_fifo_arbite SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - SIGNAL shift_data_enable : STD_LOGIC; - SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + --SIGNAL shift_data_enable : STD_LOGIC; + --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); + --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL shift_time_enable : STD_LOGIC; - SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + --SIGNAL shift_time_enable : STD_LOGIC; + --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); + --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN @@ -101,62 +108,125 @@ BEGIN ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) + IF rstn = '0' THEN -- asynchronous reset (active low) count_enable <= '0'; - shift_time_enable <= '0'; - shift_data_enable <= '0'; + data_in_ack <= (OTHERS => '0'); + data_out_wen <= (OTHERS => '1'); + sel_ack <= '0'; + state <= IDLE; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + count_enable <= '0'; data_in_ack <= (OTHERS => '0'); data_out_wen <= (OTHERS => '1'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF run = '0' OR no_sel = '1' THEN - count_enable <= '0'; - shift_time_enable <= '0'; - shift_data_enable <= '0'; - data_in_ack <= (OTHERS => '0'); - data_out_wen <= (OTHERS => '1'); + sel_ack <= '0'; + IF run = '0' THEN + state <= IDLE; ELSE - --COUNT - IF shift_data_s = "10" THEN - count_enable <= '1'; - ELSE - count_enable <= '0'; - END IF; - --DATA - IF shift_time_s = "10" THEN - shift_data_enable <= '1'; - ELSE - shift_data_enable <= '0'; - END IF; - - --TIME - IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR - shift_time_s = "00" OR - shift_time_s = "01" - THEN - shift_time_enable <= '1'; - ELSE - shift_time_enable <= '0'; - END IF; - - --ACK - IF shift_data_s = "10" THEN - data_in_ack <= sel; - ELSE - data_in_ack <= (OTHERS => '0'); - END IF; - - --VALID OUT - all_wen: FOR I IN 3 DOWNTO 0 LOOP - IF sel(I) = '1' AND count_enable = '0' THEN - data_out_wen(I) <= '0'; - ELSE - data_out_wen(I) <= '1'; - END IF; - END LOOP all_wen; - + CASE state IS + WHEN IDLE => + IF no_sel = '0' THEN + state <= TIME1; + END IF; + WHEN TIME1 => + count_enable <= '1'; + IF UNSIGNED(count) = 0 THEN + state <= TIME2; + data_out_wen <= NOT sel; + data_out <= data_sel(0); + ELSE + state <= DATA1; + END IF; + WHEN TIME2 => + data_out_wen <= NOT sel; + data_out <= data_sel(1) ; + state <= DATA1; + WHEN DATA1 => + data_out_wen <= NOT sel; + data_out <= data_sel(2); + state <= DATA2; + WHEN DATA2 => + data_out_wen <= NOT sel; + data_out <= data_sel(3); + state <= DATA3; + WHEN DATA3 => + data_out_wen <= NOT sel; + data_out <= data_sel(4); + state <= LAST; + data_in_ack <= sel; + WHEN LAST => + state <= IDLE; + sel_ack <= '1'; + + WHEN OTHERS => NULL; + END CASE; END IF; END IF; END PROCESS; + ----------------------------------------------------------------------------- + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- count_enable <= '0'; + -- shift_time_enable <= '0'; + -- shift_data_enable <= '0'; + -- data_in_ack <= (OTHERS => '0'); + -- data_out_wen <= (OTHERS => '1'); + -- sel_ack <= '0'; + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- IF run = '0' OR no_sel = '1' THEN + -- count_enable <= '0'; + -- shift_time_enable <= '0'; + -- shift_data_enable <= '0'; + -- data_in_ack <= (OTHERS => '0'); + -- data_out_wen <= (OTHERS => '1'); + -- sel_ack <= '0'; + -- ELSE + -- --COUNT + -- IF shift_data_s = "10" THEN + -- count_enable <= '1'; + -- ELSE + -- count_enable <= '0'; + -- END IF; + -- --DATA + -- IF shift_time_s = "10" THEN + -- shift_data_enable <= '1'; + -- ELSE + -- shift_data_enable <= '0'; + -- END IF; + + -- --TIME + -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR + -- shift_time_s = "00" OR + -- shift_time_s = "01" + -- THEN + -- shift_time_enable <= '1'; + -- ELSE + -- shift_time_enable <= '0'; + -- END IF; + + -- --ACK + -- IF shift_data_s = "10" THEN + -- data_in_ack <= sel; + -- sel_ack <= '1'; + -- ELSE + -- data_in_ack <= (OTHERS => '0'); + -- sel_ack <= '0'; + -- END IF; + + -- --VALID OUT + -- all_wen: FOR I IN 3 DOWNTO 0 LOOP + -- IF sel(I) = '1' AND count_enable = '0' THEN + -- data_out_wen(I) <= '0'; + -- ELSE + -- data_out_wen(I) <= '1'; + -- END IF; + -- END LOOP all_wen; + + -- END IF; + -- END IF; + --END PROCESS; ----------------------------------------------------------------------------- -- DATA MUX @@ -196,18 +266,19 @@ BEGIN data_2 WHEN sel(2) = '1' ELSE data_3; - data_out <= data_sel(0) WHEN shift_time = "00" ELSE - data_sel(1) WHEN shift_time = "01" ELSE - data_sel(2) WHEN shift_data = "00" ELSE - data_sel(3) WHEN shift_data = "01" ELSE - data_sel(4); + --data_out <= data_sel(0) WHEN shift_time = "00" ELSE + -- data_sel(1) WHEN shift_time = "01" ELSE + -- data_sel(2) WHEN shift_data = "00" ELSE + -- data_sel(3) WHEN shift_data = "01" ELSE + -- data_sel(4); ----------------------------------------------------------------------------- -- RR and SELECTION ----------------------------------------------------------------------------- all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE - valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); +-- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); + valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); END GENERATE all_input_rr; RR_Arbiter_4_1 : RR_Arbiter_4 @@ -215,8 +286,34 @@ BEGIN clk => clk, rstn => rstn, in_valid => valid_in_rr, - out_grant => sel); + out_grant => sel_s); --sel_s); +-- sel <= sel_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sel <= "0000"; + sel_reg <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- sel_reg + -- sel_ack + -- sel_s + -- sel = "0000 " + --sel <= sel_s; + IF sel_reg = '0' OR sel_ack = '1' + --OR shift_data_s = "10" + THEN + sel <= sel_s; + IF sel_s = "0000" THEN + sel_reg <= '0'; + ELSE + sel_reg <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + no_sel <= '1' WHEN sel = "0000" ELSE '0'; ----------------------------------------------------------------------------- @@ -236,34 +333,34 @@ BEGIN data => count, data_s => count_s); - reg_shift_data_i: lpp_waveform_fifo_arbiter_reg - GENERIC MAP ( - data_size => 2, - data_nb => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - max_count => "10", -- 2 - enable => shift_data_enable, - sel => sel, - data => shift_data, - data_s => shift_data_s); + --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg + -- GENERIC MAP ( + -- data_size => 2, + -- data_nb => 4) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- max_count => "10", -- 2 + -- enable => shift_data_enable, + -- sel => sel, + -- data => shift_data, + -- data_s => shift_data_s); - reg_shift_time_i: lpp_waveform_fifo_arbiter_reg - GENERIC MAP ( - data_size => 2, - data_nb => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - run => run, - max_count => "10", -- 2 - enable => shift_time_enable, - sel => sel, - data => shift_time, - data_s => shift_time_s); + --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg + -- GENERIC MAP ( + -- data_size => 2, + -- data_nb => 4) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- max_count => "10", -- 2 + -- enable => shift_time_enable, + -- sel => sel, + -- data => shift_time, + -- data_s => shift_time_s); diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -36,12 +36,12 @@ PACKAGE lpp_waveform_pkg IS TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); - TYPE Data_Vector IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>) OF STD_LOGIC; + TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; ----------------------------------------------------------------------------- -- SNAPSHOT ----------------------------------------------------------------------------- - + COMPONENT lpp_waveform_snapshot GENERIC ( data_size : INTEGER; @@ -102,13 +102,13 @@ PACKAGE lpp_waveform_pkg IS ----------------------------------------------------------------------------- COMPONENT lpp_waveform GENERIC ( - tech : INTEGER; - data_size : INTEGER; + tech : INTEGER; + data_size : INTEGER; nb_data_by_buffer_size : INTEGER; nb_word_by_buffer_size : INTEGER; - nb_snapshot_param_size : INTEGER; - delta_vector_size : INTEGER; - delta_vector_size_f0_2 : INTEGER); + nb_snapshot_param_size : INTEGER; + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -126,8 +126,8 @@ PACKAGE lpp_waveform_pkg IS burst_f0 : IN STD_LOGIC; burst_f1 : IN STD_LOGIC; burst_f2 : IN STD_LOGIC; - nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -166,7 +166,17 @@ PACKAGE lpp_waveform_pkg IS data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_data_out_valid : OUT STD_LOGIC; data_f3_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_ren : IN STD_LOGIC); + data_f3_data_out_ren : IN STD_LOGIC; + + --debug + debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC); END COMPONENT; COMPONENT lpp_waveform_dma_genvalid @@ -197,8 +207,8 @@ PACKAGE lpp_waveform_pkg IS wen : IN STD_LOGIC; mem_re : OUT STD_LOGIC; mem_we : OUT STD_LOGIC; - mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); - mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); empty_almost : OUT STD_LOGIC; empty : OUT STD_LOGIC; full_almost : OUT STD_LOGIC; @@ -207,7 +217,7 @@ PACKAGE lpp_waveform_pkg IS COMPONENT lpp_waveform_fifo_arbiter GENERIC ( - tech : INTEGER; + tech : INTEGER; nb_data_by_buffer_size : INTEGER); PORT ( clk : IN STD_LOGIC; @@ -220,6 +230,7 @@ PACKAGE lpp_waveform_pkg IS time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; @@ -276,7 +287,7 @@ PACKAGE lpp_waveform_pkg IS data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; - + ----------------------------------------------------------------------------- -- GEN ADDRESS ----------------------------------------------------------------------------- @@ -311,7 +322,7 @@ PACKAGE lpp_waveform_pkg IS data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; - + ----------------------------------------------------------------------------- -- lpp_waveform_fifo_arbiter_reg -----------------------------------------------------------------------------