@@ -490,7 +490,7 BEGIN | |||
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490 | 490 | pirq_ms => 6, |
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491 | 491 | pirq_wfp => 14, |
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492 | 492 | hindex => 2, |
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493 |
top_lfr_version => X"0000000 |
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493 | top_lfr_version => X"00000005") | |
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494 | 494 | PORT MAP ( |
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495 | 495 | clk => clkm, |
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496 | 496 | rstn => rstn, |
@@ -146,7 +146,7 BEGIN | |||
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146 | 146 | |
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147 | 147 | send => single_send, |
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148 | 148 | address => address, |
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149 | data => data, | |
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149 | data => data_2_halfword, | |
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150 | 150 | ren => single_ren, |
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151 | 151 | |
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152 | 152 | send_ok => single_send_ok, -- TODO |
@@ -59,7 +59,17 ENTITY lpp_lfr IS | |||
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59 | 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
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60 | 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
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61 | 61 | -- |
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62 | data_shaping_BW : OUT STD_LOGIC | |
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62 | data_shaping_BW : OUT STD_LOGIC; | |
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63 | ||
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64 | --debug | |
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65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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66 | debug_f0_data_valid : OUT STD_LOGIC; | |
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67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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68 | debug_f1_data_valid : OUT STD_LOGIC; | |
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69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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70 | debug_f2_data_valid : OUT STD_LOGIC; | |
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71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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72 | debug_f3_data_valid : OUT STD_LOGIC | |
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63 | 73 |
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64 | 74 | END lpp_lfr; |
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65 | 75 | |
@@ -395,7 +405,17 BEGIN | |||
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395 | 405 | data_f3_data_out => data_f3_data_out, |
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396 | 406 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
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397 | 407 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
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398 | data_f3_data_out_ren => data_f3_data_out_ren | |
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408 | data_f3_data_out_ren => data_f3_data_out_ren, | |
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409 | ||
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410 | --debug | |
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411 | debug_f0_data => debug_f0_data, | |
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412 | debug_f0_data_valid => debug_f0_data_valid , | |
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413 | debug_f1_data => debug_f1_data , | |
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414 | debug_f1_data_valid => debug_f1_data_valid, | |
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415 | debug_f2_data => debug_f2_data , | |
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416 | debug_f2_data_valid => debug_f2_data_valid , | |
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417 | debug_f3_data => debug_f3_data , | |
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418 | debug_f3_data_valid => debug_f3_data_valid | |
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399 | 419 |
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400 | 420 | ); |
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401 | 421 |
@@ -309,9 +309,12 BEGIN -- beh | |||
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309 | 309 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
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310 | 310 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
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311 | 311 | all_status: FOR I IN 3 DOWNTO 0 LOOP |
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312 | reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
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313 | reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
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314 | reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
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312 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; | |
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313 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; | |
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314 | --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; | |
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315 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; | |
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316 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; | |
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317 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ; | |
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315 | 318 | END LOOP all_status; |
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316 | 319 | |
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317 | 320 | paddr := "000000"; |
@@ -99,7 +99,17 PACKAGE lpp_lfr_pkg IS | |||
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99 | 99 | ahbo : OUT AHB_Mst_Out_Type; |
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100 | 100 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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101 | 101 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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102 |
data_shaping_BW : OUT STD_LOGIC |
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102 | data_shaping_BW : OUT STD_LOGIC; | |
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103 | ||
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104 | --debug | |
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105 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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106 | debug_f0_data_valid : OUT STD_LOGIC; | |
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107 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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108 | debug_f1_data_valid : OUT STD_LOGIC; | |
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109 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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110 | debug_f2_data_valid : OUT STD_LOGIC; | |
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111 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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112 | debug_f3_data_valid : OUT STD_LOGIC ); | |
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103 | 113 | END COMPONENT; |
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104 | 114 | |
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105 | 115 | COMPONENT lpp_lfr_apbreg |
@@ -127,9 +127,17 ENTITY lpp_waveform IS | |||
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127 | 127 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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128 | 128 | data_f3_data_out_valid : OUT STD_LOGIC; |
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129 | 129 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
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130 | data_f3_data_out_ren : IN STD_LOGIC | |
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130 | data_f3_data_out_ren : IN STD_LOGIC; | |
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131 | 131 | |
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132 | ||
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132 | --debug | |
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133 | debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
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134 | debug_f0_data_valid : OUT STD_LOGIC; | |
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135 | debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
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136 | debug_f1_data_valid : OUT STD_LOGIC; | |
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137 | debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
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138 | debug_f2_data_valid : OUT STD_LOGIC; | |
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139 | debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
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140 | debug_f3_data_valid : OUT STD_LOGIC | |
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133 | 141 | ); |
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134 | 142 | |
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135 | 143 | END lpp_waveform; |
@@ -219,7 +227,7 BEGIN -- beh | |||
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219 | 227 | data_in_valid => data_f0_in_valid, |
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220 | 228 | data_out => data_f0_out, |
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221 | 229 | data_out_valid => data_f0_out_valid); |
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222 | ||
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230 | ||
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223 | 231 |
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224 | 232 | |
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225 | 233 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot |
@@ -269,6 +277,18 BEGIN -- beh | |||
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269 | 277 | data_out => data_f3_out, |
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270 | 278 | data_out_valid => data_f3_out_valid); |
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271 | 279 | |
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280 | ----------------------------------------------------------------------------- | |
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281 | -- DEBUG | |
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282 | debug_f0_data_valid <= data_f0_out_valid; | |
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283 | debug_f0_data <= data_f0_out; | |
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284 | debug_f1_data_valid <= data_f1_out_valid; | |
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285 | debug_f1_data <= data_f1_out; | |
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286 | debug_f2_data_valid <= data_f2_out_valid; | |
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287 | debug_f2_data <= data_f2_out; | |
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288 | debug_f3_data_valid <= data_f3_out_valid; | |
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289 | debug_f3_data <= data_f3_out; | |
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290 | ----------------------------------------------------------------------------- | |
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291 | ||
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272 | 292 | PROCESS (clk, rstn) |
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273 | 293 | BEGIN -- PROCESS |
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274 | 294 | IF rstn = '0' THEN -- asynchronous reset (active low) |
@@ -323,6 +343,7 BEGIN -- beh | |||
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323 | 343 | |
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324 | 344 | data_out => wdata, |
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325 | 345 | data_out_wen => data_wen, |
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346 | full_almost => full_almost, | |
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326 | 347 | full => full); |
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327 | 348 | |
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328 | 349 | lpp_waveform_fifo_1 : lpp_waveform_fifo |
@@ -51,6 +51,7 ENTITY lpp_waveform_fifo_arbiter IS | |||
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51 | 51 | --------------------------------------------------------------------------- |
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52 | 52 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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53 | 53 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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54 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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54 | 55 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
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55 | 56 | |
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56 | 57 | ); |
@@ -58,6 +59,9 END ENTITY; | |||
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58 | 59 | |
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59 | 60 | |
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60 | 61 | ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS |
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62 | TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST); | |
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63 | SIGNAL state : state_type_fifo_arbiter; | |
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64 | ||
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61 | 65 |
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62 | 66 | -- DATA MUX |
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63 | 67 | ----------------------------------------------------------------------------- |
@@ -77,6 +81,9 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||
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77 | 81 | ----------------------------------------------------------------------------- |
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78 | 82 | SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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79 | 83 | SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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84 | SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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85 | SIGNAL sel_reg : STD_LOGIC; | |
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86 | SIGNAL sel_ack : STD_LOGIC; | |
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80 | 87 | SIGNAL no_sel : STD_LOGIC; |
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81 | 88 | |
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82 | 89 | ----------------------------------------------------------------------------- |
@@ -86,13 +93,13 ARCHITECTURE ar_lpp_waveform_fifo_arbite | |||
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86 | 93 | SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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87 | 94 | SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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88 | 95 | |
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89 | SIGNAL shift_data_enable : STD_LOGIC; | |
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90 | SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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91 | SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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96 | --SIGNAL shift_data_enable : STD_LOGIC; | |
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97 | --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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98 | --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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92 | 99 | |
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93 | SIGNAL shift_time_enable : STD_LOGIC; | |
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94 | SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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95 | SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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100 | --SIGNAL shift_time_enable : STD_LOGIC; | |
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101 | --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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102 | --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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96 | 103 | |
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97 | 104 | BEGIN |
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98 | 105 | |
@@ -101,62 +108,125 BEGIN | |||
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101 | 108 | ----------------------------------------------------------------------------- |
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102 | 109 | PROCESS (clk, rstn) |
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103 | 110 | BEGIN -- PROCESS |
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104 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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111 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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105 | 112 | count_enable <= '0'; |
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106 | shift_time_enable <= '0'; | |
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107 | shift_data_enable <= '0'; | |
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113 | data_in_ack <= (OTHERS => '0'); | |
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114 | data_out_wen <= (OTHERS => '1'); | |
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115 | sel_ack <= '0'; | |
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116 | state <= IDLE; | |
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117 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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118 | count_enable <= '0'; | |
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108 | 119 | data_in_ack <= (OTHERS => '0'); |
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109 | 120 | data_out_wen <= (OTHERS => '1'); |
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110 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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111 |
IF run = '0' |
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112 | count_enable <= '0'; | |
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113 | shift_time_enable <= '0'; | |
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114 | shift_data_enable <= '0'; | |
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115 | data_in_ack <= (OTHERS => '0'); | |
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116 | data_out_wen <= (OTHERS => '1'); | |
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121 | sel_ack <= '0'; | |
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122 | IF run = '0' THEN | |
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123 | state <= IDLE; | |
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117 | 124 | ELSE |
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118 | --COUNT | |
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119 | IF shift_data_s = "10" THEN | |
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120 |
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121 | ELSE | |
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122 | count_enable <= '0'; | |
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123 |
EN |
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124 | --DATA | |
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125 | IF shift_time_s = "10" THEN | |
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126 | shift_data_enable <= '1'; | |
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127 | ELSE | |
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128 | shift_data_enable <= '0'; | |
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129 | END IF; | |
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130 | ||
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131 | --TIME | |
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132 | IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR | |
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133 | shift_time_s = "00" OR | |
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134 | shift_time_s = "01" | |
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135 | THEN | |
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136 | shift_time_enable <= '1'; | |
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137 | ELSE | |
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138 | shift_time_enable <= '0'; | |
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139 | END IF; | |
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140 | ||
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141 | --ACK | |
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142 | IF shift_data_s = "10" THEN | |
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143 | data_in_ack <= sel; | |
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144 | ELSE | |
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145 |
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146 | END IF; | |
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147 | ||
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148 | --VALID OUT | |
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149 | all_wen: FOR I IN 3 DOWNTO 0 LOOP | |
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150 | IF sel(I) = '1' AND count_enable = '0' THEN | |
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151 | data_out_wen(I) <= '0'; | |
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152 |
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153 | data_out_wen(I) <= '1'; | |
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154 |
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155 | END LOOP all_wen; | |
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156 | ||
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125 | CASE state IS | |
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126 | WHEN IDLE => | |
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127 | IF no_sel = '0' THEN | |
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128 | state <= TIME1; | |
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129 | END IF; | |
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130 | WHEN TIME1 => | |
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131 | count_enable <= '1'; | |
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132 | IF UNSIGNED(count) = 0 THEN | |
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133 | state <= TIME2; | |
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134 | data_out_wen <= NOT sel; | |
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135 | data_out <= data_sel(0); | |
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136 | ELSE | |
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137 | state <= DATA1; | |
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138 | END IF; | |
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139 | WHEN TIME2 => | |
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140 | data_out_wen <= NOT sel; | |
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141 | data_out <= data_sel(1) ; | |
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142 | state <= DATA1; | |
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143 | WHEN DATA1 => | |
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144 | data_out_wen <= NOT sel; | |
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145 | data_out <= data_sel(2); | |
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146 | state <= DATA2; | |
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147 | WHEN DATA2 => | |
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148 | data_out_wen <= NOT sel; | |
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149 | data_out <= data_sel(3); | |
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150 | state <= DATA3; | |
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151 | WHEN DATA3 => | |
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152 | data_out_wen <= NOT sel; | |
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153 | data_out <= data_sel(4); | |
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154 | state <= LAST; | |
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155 | data_in_ack <= sel; | |
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156 | WHEN LAST => | |
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157 | state <= IDLE; | |
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158 | sel_ack <= '1'; | |
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159 | ||
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160 | WHEN OTHERS => NULL; | |
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161 | END CASE; | |
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157 | 162 | END IF; |
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158 | 163 | END IF; |
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159 | 164 | END PROCESS; |
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165 | ----------------------------------------------------------------------------- | |
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166 | ||
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167 | ||
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168 | --PROCESS (clk, rstn) | |
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169 | --BEGIN -- PROCESS | |
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170 | -- IF rstn = '0' THEN -- asynchronous reset (active low) | |
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171 | -- count_enable <= '0'; | |
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172 | -- shift_time_enable <= '0'; | |
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173 | -- shift_data_enable <= '0'; | |
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174 | -- data_in_ack <= (OTHERS => '0'); | |
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175 | -- data_out_wen <= (OTHERS => '1'); | |
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176 | -- sel_ack <= '0'; | |
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177 | -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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178 | -- IF run = '0' OR no_sel = '1' THEN | |
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179 | -- count_enable <= '0'; | |
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180 | -- shift_time_enable <= '0'; | |
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181 | -- shift_data_enable <= '0'; | |
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182 | -- data_in_ack <= (OTHERS => '0'); | |
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183 | -- data_out_wen <= (OTHERS => '1'); | |
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184 | -- sel_ack <= '0'; | |
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185 | -- ELSE | |
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186 | -- --COUNT | |
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187 | -- IF shift_data_s = "10" THEN | |
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188 | -- count_enable <= '1'; | |
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189 | -- ELSE | |
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190 | -- count_enable <= '0'; | |
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191 | -- END IF; | |
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192 | -- --DATA | |
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193 | -- IF shift_time_s = "10" THEN | |
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194 | -- shift_data_enable <= '1'; | |
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195 | -- ELSE | |
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196 | -- shift_data_enable <= '0'; | |
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197 | -- END IF; | |
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198 | ||
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199 | -- --TIME | |
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200 | -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR | |
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201 | -- shift_time_s = "00" OR | |
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202 | -- shift_time_s = "01" | |
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203 | -- THEN | |
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204 | -- shift_time_enable <= '1'; | |
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205 | -- ELSE | |
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206 | -- shift_time_enable <= '0'; | |
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207 | -- END IF; | |
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208 | ||
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209 | -- --ACK | |
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210 | -- IF shift_data_s = "10" THEN | |
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211 | -- data_in_ack <= sel; | |
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212 | -- sel_ack <= '1'; | |
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213 | -- ELSE | |
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214 | -- data_in_ack <= (OTHERS => '0'); | |
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215 | -- sel_ack <= '0'; | |
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216 | -- END IF; | |
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217 | ||
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218 | -- --VALID OUT | |
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219 | -- all_wen: FOR I IN 3 DOWNTO 0 LOOP | |
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220 | -- IF sel(I) = '1' AND count_enable = '0' THEN | |
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221 | -- data_out_wen(I) <= '0'; | |
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222 | -- ELSE | |
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223 | -- data_out_wen(I) <= '1'; | |
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224 | -- END IF; | |
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225 | -- END LOOP all_wen; | |
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226 | ||
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227 | -- END IF; | |
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228 | -- END IF; | |
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229 | --END PROCESS; | |
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160 | 230 | |
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161 | 231 | ----------------------------------------------------------------------------- |
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162 | 232 | -- DATA MUX |
@@ -196,18 +266,19 BEGIN | |||
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196 | 266 | data_2 WHEN sel(2) = '1' ELSE |
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197 | 267 | data_3; |
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198 | 268 | |
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199 | data_out <= data_sel(0) WHEN shift_time = "00" ELSE | |
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200 | data_sel(1) WHEN shift_time = "01" ELSE | |
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201 | data_sel(2) WHEN shift_data = "00" ELSE | |
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202 | data_sel(3) WHEN shift_data = "01" ELSE | |
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203 | data_sel(4); | |
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269 | --data_out <= data_sel(0) WHEN shift_time = "00" ELSE | |
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270 | -- data_sel(1) WHEN shift_time = "01" ELSE | |
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271 | -- data_sel(2) WHEN shift_data = "00" ELSE | |
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272 | -- data_sel(3) WHEN shift_data = "01" ELSE | |
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273 | -- data_sel(4); | |
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204 | 274 | |
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205 | 275 | |
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206 | 276 | ----------------------------------------------------------------------------- |
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207 | 277 | -- RR and SELECTION |
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208 | 278 | ----------------------------------------------------------------------------- |
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209 | 279 | all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE |
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210 | valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); | |
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280 | -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); | |
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281 | valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); | |
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211 | 282 | END GENERATE all_input_rr; |
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212 | 283 | |
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213 | 284 | RR_Arbiter_4_1 : RR_Arbiter_4 |
@@ -215,8 +286,34 BEGIN | |||
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215 | 286 | clk => clk, |
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216 | 287 | rstn => rstn, |
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217 | 288 | in_valid => valid_in_rr, |
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218 | out_grant => sel); | |
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289 | out_grant => sel_s); --sel_s); | |
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219 | 290 | |
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291 | -- sel <= sel_s; | |
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292 | ||
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293 | PROCESS (clk, rstn) | |
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294 | BEGIN -- PROCESS | |
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295 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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296 | sel <= "0000"; | |
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297 | sel_reg <= '0'; | |
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298 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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299 | -- sel_reg | |
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300 | -- sel_ack | |
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301 | -- sel_s | |
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302 | -- sel = "0000 " | |
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303 | --sel <= sel_s; | |
|
304 | IF sel_reg = '0' OR sel_ack = '1' | |
|
305 | --OR shift_data_s = "10" | |
|
306 | THEN | |
|
307 | sel <= sel_s; | |
|
308 | IF sel_s = "0000" THEN | |
|
309 | sel_reg <= '0'; | |
|
310 | ELSE | |
|
311 | sel_reg <= '1'; | |
|
312 | END IF; | |
|
313 | END IF; | |
|
314 | END IF; | |
|
315 | END PROCESS; | |
|
316 | ||
|
220 | 317 |
|
|
221 | 318 | |
|
222 | 319 | ----------------------------------------------------------------------------- |
@@ -236,34 +333,34 BEGIN | |||
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236 | 333 | data => count, |
|
237 | 334 | data_s => count_s); |
|
238 | 335 | |
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239 | reg_shift_data_i: lpp_waveform_fifo_arbiter_reg | |
|
240 | GENERIC MAP ( | |
|
241 | data_size => 2, | |
|
242 | data_nb => 4) | |
|
243 | PORT MAP ( | |
|
244 | clk => clk, | |
|
245 | rstn => rstn, | |
|
246 | run => run, | |
|
247 | max_count => "10", -- 2 | |
|
248 | enable => shift_data_enable, | |
|
249 | sel => sel, | |
|
250 | data => shift_data, | |
|
251 | data_s => shift_data_s); | |
|
336 | --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg | |
|
337 | -- GENERIC MAP ( | |
|
338 | -- data_size => 2, | |
|
339 | -- data_nb => 4) | |
|
340 | -- PORT MAP ( | |
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341 | -- clk => clk, | |
|
342 | -- rstn => rstn, | |
|
343 | -- run => run, | |
|
344 | -- max_count => "10", -- 2 | |
|
345 | -- enable => shift_data_enable, | |
|
346 | -- sel => sel, | |
|
347 | -- data => shift_data, | |
|
348 | -- data_s => shift_data_s); | |
|
252 | 349 | |
|
253 | 350 | |
|
254 | reg_shift_time_i: lpp_waveform_fifo_arbiter_reg | |
|
255 | GENERIC MAP ( | |
|
256 | data_size => 2, | |
|
257 | data_nb => 4) | |
|
258 | PORT MAP ( | |
|
259 | clk => clk, | |
|
260 | rstn => rstn, | |
|
261 | run => run, | |
|
262 | max_count => "10", -- 2 | |
|
263 | enable => shift_time_enable, | |
|
264 | sel => sel, | |
|
265 | data => shift_time, | |
|
266 | data_s => shift_time_s); | |
|
351 | --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg | |
|
352 | -- GENERIC MAP ( | |
|
353 | -- data_size => 2, | |
|
354 | -- data_nb => 4) | |
|
355 | -- PORT MAP ( | |
|
356 | -- clk => clk, | |
|
357 | -- rstn => rstn, | |
|
358 | -- run => run, | |
|
359 | -- max_count => "10", -- 2 | |
|
360 | -- enable => shift_time_enable, | |
|
361 | -- sel => sel, | |
|
362 | -- data => shift_time, | |
|
363 | -- data_s => shift_time_s); | |
|
267 | 364 | |
|
268 | 365 | |
|
269 | 366 |
@@ -36,12 +36,12 PACKAGE lpp_waveform_pkg IS | |||
|
36 | 36 | |
|
37 | 37 | TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); |
|
38 | 38 | |
|
39 | TYPE Data_Vector IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>) OF STD_LOGIC; | |
|
39 | TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
|
40 | 40 | |
|
41 | 41 | ----------------------------------------------------------------------------- |
|
42 | 42 | -- SNAPSHOT |
|
43 | 43 | ----------------------------------------------------------------------------- |
|
44 | ||
|
44 | ||
|
45 | 45 | COMPONENT lpp_waveform_snapshot |
|
46 | 46 | GENERIC ( |
|
47 | 47 | data_size : INTEGER; |
@@ -102,13 +102,13 PACKAGE lpp_waveform_pkg IS | |||
|
102 | 102 | ----------------------------------------------------------------------------- |
|
103 | 103 | COMPONENT lpp_waveform |
|
104 | 104 | GENERIC ( |
|
105 |
tech |
|
|
106 |
data_size |
|
|
105 | tech : INTEGER; | |
|
106 | data_size : INTEGER; | |
|
107 | 107 | nb_data_by_buffer_size : INTEGER; |
|
108 | 108 | nb_word_by_buffer_size : INTEGER; |
|
109 |
nb_snapshot_param_size |
|
|
110 |
delta_vector_size |
|
|
111 |
delta_vector_size_f0_2 |
|
|
109 | nb_snapshot_param_size : INTEGER; | |
|
110 | delta_vector_size : INTEGER; | |
|
111 | delta_vector_size_f0_2 : INTEGER); | |
|
112 | 112 | PORT ( |
|
113 | 113 | clk : IN STD_LOGIC; |
|
114 | 114 | rstn : IN STD_LOGIC; |
@@ -126,8 +126,8 PACKAGE lpp_waveform_pkg IS | |||
|
126 | 126 | burst_f0 : IN STD_LOGIC; |
|
127 | 127 | burst_f1 : IN STD_LOGIC; |
|
128 | 128 | burst_f2 : IN STD_LOGIC; |
|
129 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
129 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
130 | nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
131 | 131 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
132 | 132 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
133 | 133 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -166,7 +166,17 PACKAGE lpp_waveform_pkg IS | |||
|
166 | 166 | data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | 167 | data_f3_data_out_valid : OUT STD_LOGIC; |
|
168 | 168 | data_f3_data_out_valid_burst : OUT STD_LOGIC; |
|
169 |
data_f3_data_out_ren : IN STD_LOGIC |
|
|
169 | data_f3_data_out_ren : IN STD_LOGIC; | |
|
170 | ||
|
171 | --debug | |
|
172 | debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
173 | debug_f0_data_valid : OUT STD_LOGIC; | |
|
174 | debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
175 | debug_f1_data_valid : OUT STD_LOGIC; | |
|
176 | debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
177 | debug_f2_data_valid : OUT STD_LOGIC; | |
|
178 | debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
|
179 | debug_f3_data_valid : OUT STD_LOGIC); | |
|
170 | 180 | END COMPONENT; |
|
171 | 181 | |
|
172 | 182 | COMPONENT lpp_waveform_dma_genvalid |
@@ -197,8 +207,8 PACKAGE lpp_waveform_pkg IS | |||
|
197 | 207 | wen : IN STD_LOGIC; |
|
198 | 208 | mem_re : OUT STD_LOGIC; |
|
199 | 209 | mem_we : OUT STD_LOGIC; |
|
200 |
mem_addr_ren : |
|
|
201 |
mem_addr_wen : |
|
|
210 | mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); | |
|
211 | mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); | |
|
202 | 212 | empty_almost : OUT STD_LOGIC; |
|
203 | 213 | empty : OUT STD_LOGIC; |
|
204 | 214 | full_almost : OUT STD_LOGIC; |
@@ -207,7 +217,7 PACKAGE lpp_waveform_pkg IS | |||
|
207 | 217 | |
|
208 | 218 | COMPONENT lpp_waveform_fifo_arbiter |
|
209 | 219 | GENERIC ( |
|
210 |
tech |
|
|
220 | tech : INTEGER; | |
|
211 | 221 | nb_data_by_buffer_size : INTEGER); |
|
212 | 222 | PORT ( |
|
213 | 223 | clk : IN STD_LOGIC; |
@@ -220,6 +230,7 PACKAGE lpp_waveform_pkg IS | |||
|
220 | 230 | time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
|
221 | 231 | data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
222 | 232 | data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
223 | 234 | full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
224 | 235 | END COMPONENT; |
|
225 | 236 | |
@@ -276,7 +287,7 PACKAGE lpp_waveform_pkg IS | |||
|
276 | 287 | data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
277 | 288 | wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
278 | 289 | END COMPONENT; |
|
279 | ||
|
290 | ||
|
280 | 291 | ----------------------------------------------------------------------------- |
|
281 | 292 | -- GEN ADDRESS |
|
282 | 293 | ----------------------------------------------------------------------------- |
@@ -311,7 +322,7 PACKAGE lpp_waveform_pkg IS | |||
|
311 | 322 | data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
312 | 323 | data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
313 | 324 | END COMPONENT; |
|
314 | ||
|
325 | ||
|
315 | 326 | ----------------------------------------------------------------------------- |
|
316 | 327 | -- lpp_waveform_fifo_arbiter_reg |
|
317 | 328 | ----------------------------------------------------------------------------- |
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