@@ -428,7 +428,7 BEGIN -- beh | |||
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428 | 428 | pirq_ms => 6, |
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429 | 429 | pirq_wfp => 14, |
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430 | 430 | hindex => 2, |
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431 |
top_lfr_version => X"00011 |
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431 | top_lfr_version => X"00011E") -- aa.bb.cc version | |
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432 | 432 | PORT MAP ( |
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433 | 433 | clk => clk_25, |
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434 | 434 | rstn => reset, |
@@ -58,12 +58,13 BEGIN | |||
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58 | 58 | ----------------------------------------------------------------------------- |
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59 | 59 | -- SEL_SAMPLE |
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60 | 60 | ----------------------------------------------------------------------------- |
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61 | sample_temp(0) <= sample_vector(0) WHEN sel_sample(0) = '0' ELSE sample_vector(1); | |
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62 |
sample_temp( |
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63 |
sample_temp( |
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64 |
sample_temp( |
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65 |
sample |
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66 | ||
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61 | all_bit: FOR I IN 15 DOWNTO 0 GENERATE | |
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62 | sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I); | |
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63 | sample_temp(1,I) <= data_in(3,I) WHEN sel_sample(0) = '0' ELSE data_in(4,I); | |
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64 | sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I); | |
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65 | sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I); | |
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66 | sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I); | |
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67 | END GENERATE all_bit; | |
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67 | 68 | |
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68 | 69 | END beh; |
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69 | 70 |
@@ -23,6 +23,8 | |||
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23 | 23 | |
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24 | 24 | LIBRARY ieee; |
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25 | 25 | USE ieee.std_logic_1164.ALL; |
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26 | USE ieee.numeric_std.ALL; | |
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27 | ||
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26 | 28 | |
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27 | 29 | LIBRARY lpp; |
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28 | 30 | USE lpp.cic_pkg.ALL; |
@@ -47,6 +49,7 ENTITY cic_lfr_control IS | |||
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47 | 49 | r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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48 | 50 | r_addr_add1 : OUT STD_LOGIC; |
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49 | 51 | -- |
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52 | w_en : OUT STD_LOGIC; | |
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50 | 53 | w_addr_init : OUT STD_LOGIC; |
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51 | 54 | w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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52 | 55 | w_addr_add1 : OUT STD_LOGIC |
@@ -56,13 +59,41 END cic_lfr_control; | |||
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56 | 59 | |
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57 | 60 | ARCHITECTURE beh OF cic_lfr_control IS |
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58 | 61 | |
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59 |
TYPE STATE_CIC_LFR_TYPE IS (IDLE, |
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62 | TYPE STATE_CIC_LFR_TYPE IS (IDLE, | |
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63 | ||
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64 | INT_0_d0, INT_1_d0, INT_2_d0, | |
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65 | INT_0_d1, INT_1_d1, INT_2_d1, | |
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66 | INT_0_d2, INT_1_d2, INT_2_d2, | |
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67 | ||
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68 | WAIT_INT_to_COMB_16, | |
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69 | ||
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70 | COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0, | |
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71 | COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1, | |
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72 | ||
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73 | COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0, | |
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74 | COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1, | |
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75 | COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2, | |
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76 | ||
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77 | READ_INT_2_d0, | |
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78 | READ_INT_2_d1 | |
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79 | ); | |
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60 | 80 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; |
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61 | 81 | |
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62 | 82 | SIGNAL nb_data_receipt : INTEGER; |
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83 | SIGNAL current_channel : INTEGER; | |
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84 | ||
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85 | TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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63 | 86 | |
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87 | SIGNAL base_addr_INT : ARRAY_OF_ADDR; | |
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88 | CONSTANT base_addr_delta : INTEGER := 40; | |
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64 | 89 | BEGIN |
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65 | 90 | |
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91 | all_channel: FOR I IN 5 DOWNTO 0 GENERATE | |
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92 | all_bit: FOR J IN 7 DOWNTO 0 GENERATE | |
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93 | base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0'; | |
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94 | END GENERATE all_bit; | |
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95 | END GENERATE all_channel; | |
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96 | ||
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66 | 97 | PROCESS (clk, rstn) |
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67 | 98 | BEGIN -- PROCESS |
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68 | 99 | IF rstn = '0' THEN -- asynchronous reset (active low) |
@@ -80,12 +111,25 BEGIN | |||
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80 | 111 | r_addr_base <= (OTHERS => '0'); |
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81 | 112 | r_addr_add1 <= '0'; |
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82 | 113 | -- |
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114 | w_en <= '1'; | |
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83 | 115 | w_addr_init <= '0'; |
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84 | 116 | w_addr_base <= (OTHERS => '0'); |
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85 | 117 | w_addr_add1 <= '0'; |
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86 | 118 | -- |
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87 | 119 | nb_data_receipt <= 0; |
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88 | 120 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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121 | data_out_16_valid <= '0'; | |
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122 | data_out_256_valid <= '0'; | |
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123 | op_valid <= '0'; | |
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124 | op_ADD_SUBn <= '0'; | |
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125 | r_addr_init <= '0'; | |
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126 | r_addr_base <= (OTHERS => '0'); | |
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127 | r_addr_add1 <= '0'; | |
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128 | w_en <= '1'; | |
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129 | w_addr_init <= '0'; | |
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130 | w_addr_base <= (OTHERS => '0'); | |
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131 | w_addr_add1 <= '0'; | |
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132 | ||
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89 | 133 | IF run = '0' THEN |
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90 | 134 | STATE_CIC_LFR <= IDLE; |
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91 | 135 | -- |
@@ -101,11 +145,13 BEGIN | |||
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101 | 145 | r_addr_base <= (OTHERS => '0'); |
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102 | 146 | r_addr_add1 <= '0'; |
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103 | 147 | -- |
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148 | w_en <= '1'; | |
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104 | 149 | w_addr_init <= '0'; |
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105 | 150 | w_addr_base <= (OTHERS => '0'); |
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106 | 151 | w_addr_add1 <= '0'; |
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107 | 152 | -- |
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108 | 153 | nb_data_receipt <= 0; |
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154 | current_channel <= 0; | |
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109 | 155 | ELSE |
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110 | 156 | CASE STATE_CIC_LFR IS |
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111 | 157 | WHEN IDLE => |
@@ -121,14 +167,93 BEGIN | |||
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121 | 167 | r_addr_base <= (OTHERS => '0'); |
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122 | 168 | r_addr_add1 <= '0'; |
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123 | 169 | -- |
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170 | w_en <= '1'; | |
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124 | 171 | w_addr_init <= '0'; |
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125 | 172 | w_addr_base <= (OTHERS => '0'); |
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126 | 173 | w_addr_add1 <= '0'; |
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174 | -- | |
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127 | 175 | IF data_in_valid = '1' THEN |
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128 |
nb_data_receipt <= |
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129 | STATE_CIC_LFR <= INT_0; | |
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176 | nb_data_receipt <= nb_data_receipt+1; | |
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177 | current_channel <= 0; | |
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178 | STATE_CIC_LFR <= INT_0_d0; | |
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130 | 179 | END IF; |
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131 | WHEN INT_0 => | |
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180 | ||
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181 | ------------------------------------------------------------------- | |
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182 | WHEN INT_0_d0 => | |
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183 | sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)); | |
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184 | STATE_CIC_LFR <= INT_0_d1; | |
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185 | r_addr_init <= '1'; | |
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186 | r_addr_base <= base_addr_INT(current_channel); | |
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187 | ||
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188 | ||
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189 | WHEN INT_0_d1 => | |
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190 | STATE_CIC_LFR <= INT_0_d2; | |
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191 | r_addr_add1 <= '1'; | |
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192 | ||
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193 | WHEN INT_0_d2 => | |
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194 | STATE_CIC_LFR <= INT_1_d0; | |
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195 | r_addr_add1 <= '1'; | |
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196 | op_ADD_SUBn <= '1'; | |
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197 | op_valid <= '1'; | |
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198 | ||
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199 | WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1; | |
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200 | WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2; | |
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201 | WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0; | |
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202 | ||
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203 | WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1; | |
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204 | WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2; | |
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205 | WHEN INT_2_d2 => | |
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206 | IF nb_data_receipt = 256 THEN | |
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207 | STATE_CIC_LFR <= COMB_0_256_d0; | |
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208 | ELSIF (nb_data_receipt mod 16) = 0 THEN | |
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209 | STATE_CIC_LFR <= WAIT_INT_to_COMB_16; | |
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210 | ELSE | |
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211 | IF current_channel = 5 THEN | |
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212 | STATE_CIC_LFR <= IDLE; | |
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213 | ELSE | |
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214 | current_channel <= current_channel +1; | |
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215 | STATE_CIC_LFR <= INT_0_d0; | |
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216 | END IF; | |
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217 | END IF; | |
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218 | ||
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219 | ------------------------------------------------------------------- | |
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220 | WHEN WAIT_INT_to_COMB_16 => | |
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221 | STATE_CIC_LFR <= COMB_0_16_d0; | |
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222 | ||
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223 | WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1; | |
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224 | WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0; | |
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225 | ||
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226 | WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1; | |
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227 | WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0; | |
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228 | ||
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229 | WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1; | |
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230 | WHEN COMB_2_16_d1 => | |
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231 | IF current_channel = 5 THEN | |
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232 | STATE_CIC_LFR <= IDLE; | |
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233 | IF nb_data_receipt = 256 THEN | |
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234 | nb_data_receipt <= 0; | |
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235 | END IF; | |
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236 | ELSE | |
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237 | current_channel <= current_channel +1; | |
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238 | STATE_CIC_LFR <= INT_0_d0; | |
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239 | END IF; | |
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240 | ||
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241 | ------------------------------------------------------------------- | |
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242 | WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1; | |
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243 | WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2; | |
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244 | WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0; | |
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245 | ||
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246 | WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1; | |
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247 | WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2; | |
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248 | WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0; | |
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249 | ||
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250 | WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1; | |
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251 | WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2; | |
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252 | WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0; | |
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253 | ||
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254 | ------------------------------------------------------------------- | |
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255 | WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1; | |
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256 | WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0; | |
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132 | 257 | |
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133 | 258 | WHEN OTHERS => NULL; |
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134 | 259 | END CASE; |
@@ -86,4 +86,26 PACKAGE cic_pkg IS | |||
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86 | 86 | END COMPONENT; |
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87 | 87 | ----------------------------------------------------------------------------- |
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88 | 88 | |
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89 | ||
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90 | ----------------------------------------------------------------------------- | |
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91 | COMPONENT cic_lfr_control | |
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92 | PORT ( | |
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93 | clk : IN STD_LOGIC; | |
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94 | rstn : IN STD_LOGIC; | |
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95 | run : IN STD_LOGIC; | |
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96 | data_in_valid : IN STD_LOGIC; | |
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97 | data_out_16_valid : OUT STD_LOGIC; | |
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98 | data_out_256_valid : OUT STD_LOGIC; | |
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99 | sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
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100 | op_valid : OUT STD_LOGIC; | |
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101 | op_ADD_SUBn : OUT STD_LOGIC; | |
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102 | r_addr_init : OUT STD_LOGIC; | |
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103 | r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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104 | r_addr_add1 : OUT STD_LOGIC; | |
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105 | w_en : OUT STD_LOGIC; | |
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106 | w_addr_init : OUT STD_LOGIC; | |
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107 | w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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108 | w_addr_add1 : OUT STD_LOGIC); | |
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109 | END COMPONENT; | |
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110 | ----------------------------------------------------------------------------- | |
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89 | 111 | END cic_pkg; |
@@ -4,3 +4,4 cic_integrator.vhd | |||
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4 | 4 | cic_downsampler.vhd |
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5 | 5 | cic_comb.vhd |
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6 | 6 | cic_lfr.vhd |
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7 | cic_lfr_control.vhd |
@@ -524,25 +524,25 BEGIN -- beh | |||
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524 | 524 | --34 |
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525 | 525 | WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
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526 | 526 | --35 |
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527 |
WHEN "101000" => prdata(1 |
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528 |
WHEN "101001" => prdata( |
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529 |
WHEN "101010" => prdata(1 |
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530 |
WHEN "101011" => prdata( |
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527 | WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0); | |
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528 | WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16); | |
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529 | WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1); | |
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530 | WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32); | |
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531 | 531 | |
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532 |
WHEN "101100" => prdata(1 |
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533 |
WHEN "101101" => prdata( |
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534 |
WHEN "101110" => prdata(1 |
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535 |
WHEN "101111" => prdata( |
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532 | WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2); | |
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533 | WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32); | |
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534 | WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3); | |
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535 | WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32); | |
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536 | 536 | |
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537 |
WHEN "110000" => prdata(1 |
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538 |
WHEN "110001" => prdata( |
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539 |
WHEN "110010" => prdata(1 |
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540 |
WHEN "110011" => prdata( |
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537 | WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4); | |
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538 | WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32); | |
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539 | WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5); | |
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540 | WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32); | |
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541 | 541 | |
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542 |
WHEN "110100" => prdata(1 |
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543 |
WHEN "110101" => prdata( |
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544 |
WHEN "110110" => prdata(1 |
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545 |
WHEN "110111" => prdata( |
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542 | WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6); | |
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543 | WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32); | |
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544 | WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); | |
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545 | WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); | |
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546 | 546 | |
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547 | 547 | WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; |
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548 | 548 | |
@@ -773,4 +773,4 BEGIN -- beh | |||
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773 | 773 | END GENERATE all_wfp_pointer; |
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774 | 774 | ----------------------------------------------------------------------------- |
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775 | 775 | |
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776 |
END beh; |
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776 | END beh; No newline at end of file |
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