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MINI_LFR-WFP_MS-0.1.30.pdb :...
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r449:af027809897d (MINI-LFR) WFP_MS-0-1-30 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 -- nb_word_by_buffer_size => 30,
421 -- nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"00011D") -- aa.bb.cc version
431 top_lfr_version => X"00011E") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig);
444 data_shaping_BW => bias_fail_sw_sig);
445
445
446 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
447 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
447 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
448 END GENERATE all_sample;
448 END GENERATE all_sample;
449
449
450
450
451
451
452 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
452 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
453 GENERIC MAP(
453 GENERIC MAP(
454 ChannelCount => 8,
454 ChannelCount => 8,
455 SampleNbBits => 14,
455 SampleNbBits => 14,
456 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
456 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
457 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
457 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
458 PORT MAP (
458 PORT MAP (
459 -- CONV
459 -- CONV
460 cnv_clk => clk_24,
460 cnv_clk => clk_24,
461 cnv_rstn => reset,
461 cnv_rstn => reset,
462 cnv => ADC_nCS_sig,
462 cnv => ADC_nCS_sig,
463 -- DATA
463 -- DATA
464 clk => clk_25,
464 clk => clk_25,
465 rstn => reset,
465 rstn => reset,
466 sck => ADC_CLK_sig,
466 sck => ADC_CLK_sig,
467 sdo => ADC_SDO_sig,
467 sdo => ADC_SDO_sig,
468 -- SAMPLE
468 -- SAMPLE
469 sample => sample,
469 sample => sample,
470 sample_val => sample_val);
470 sample_val => sample_val);
471
471
472 --IO10 <= ADC_SDO_sig(5);
472 --IO10 <= ADC_SDO_sig(5);
473 --IO9 <= ADC_SDO_sig(4);
473 --IO9 <= ADC_SDO_sig(4);
474 --IO8 <= ADC_SDO_sig(3);
474 --IO8 <= ADC_SDO_sig(3);
475
475
476 ADC_nCS <= ADC_nCS_sig;
476 ADC_nCS <= ADC_nCS_sig;
477 ADC_CLK <= ADC_CLK_sig;
477 ADC_CLK <= ADC_CLK_sig;
478 ADC_SDO_sig <= ADC_SDO;
478 ADC_SDO_sig <= ADC_SDO;
479
479
480 ----------------------------------------------------------------------
480 ----------------------------------------------------------------------
481 --- GPIO -----------------------------------------------------------
481 --- GPIO -----------------------------------------------------------
482 ----------------------------------------------------------------------
482 ----------------------------------------------------------------------
483
483
484 grgpio0 : grgpio
484 grgpio0 : grgpio
485 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
485 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
486 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
486 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
487
487
488 --pio_pad_0 : iopad
488 --pio_pad_0 : iopad
489 -- GENERIC MAP (tech => CFG_PADTECH)
489 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
490 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
491 --pio_pad_1 : iopad
491 --pio_pad_1 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
493 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
494 --pio_pad_2 : iopad
494 --pio_pad_2 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
496 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
497 --pio_pad_3 : iopad
497 --pio_pad_3 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
499 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
500 --pio_pad_4 : iopad
500 --pio_pad_4 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
502 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
503 --pio_pad_5 : iopad
503 --pio_pad_5 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
505 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
506 --pio_pad_6 : iopad
506 --pio_pad_6 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
508 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
509 --pio_pad_7 : iopad
509 --pio_pad_7 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
511 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
512
512
513 PROCESS (clk_25, reset)
513 PROCESS (clk_25, reset)
514 BEGIN -- PROCESS
514 BEGIN -- PROCESS
515 IF reset = '0' THEN -- asynchronous reset (active low)
515 IF reset = '0' THEN -- asynchronous reset (active low)
516 IO0 <= '0';
516 IO0 <= '0';
517 IO1 <= '0';
517 IO1 <= '0';
518 IO2 <= '0';
518 IO2 <= '0';
519 IO3 <= '0';
519 IO3 <= '0';
520 IO4 <= '0';
520 IO4 <= '0';
521 IO5 <= '0';
521 IO5 <= '0';
522 IO6 <= '0';
522 IO6 <= '0';
523 IO7 <= '0';
523 IO7 <= '0';
524 IO8 <= '0';
524 IO8 <= '0';
525 IO9 <= '0';
525 IO9 <= '0';
526 IO10 <= '0';
526 IO10 <= '0';
527 IO11 <= '0';
527 IO11 <= '0';
528 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
528 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
529 CASE gpioo.dout(2 DOWNTO 0) IS
529 CASE gpioo.dout(2 DOWNTO 0) IS
530 WHEN "011" =>
530 WHEN "011" =>
531 IO0 <= observation_reg(0 );
531 IO0 <= observation_reg(0 );
532 IO1 <= observation_reg(1 );
532 IO1 <= observation_reg(1 );
533 IO2 <= observation_reg(2 );
533 IO2 <= observation_reg(2 );
534 IO3 <= observation_reg(3 );
534 IO3 <= observation_reg(3 );
535 IO4 <= observation_reg(4 );
535 IO4 <= observation_reg(4 );
536 IO5 <= observation_reg(5 );
536 IO5 <= observation_reg(5 );
537 IO6 <= observation_reg(6 );
537 IO6 <= observation_reg(6 );
538 IO7 <= observation_reg(7 );
538 IO7 <= observation_reg(7 );
539 IO8 <= observation_reg(8 );
539 IO8 <= observation_reg(8 );
540 IO9 <= observation_reg(9 );
540 IO9 <= observation_reg(9 );
541 IO10 <= observation_reg(10);
541 IO10 <= observation_reg(10);
542 IO11 <= observation_reg(11);
542 IO11 <= observation_reg(11);
543 WHEN "001" =>
543 WHEN "001" =>
544 IO0 <= observation_reg(0 + 12);
544 IO0 <= observation_reg(0 + 12);
545 IO1 <= observation_reg(1 + 12);
545 IO1 <= observation_reg(1 + 12);
546 IO2 <= observation_reg(2 + 12);
546 IO2 <= observation_reg(2 + 12);
547 IO3 <= observation_reg(3 + 12);
547 IO3 <= observation_reg(3 + 12);
548 IO4 <= observation_reg(4 + 12);
548 IO4 <= observation_reg(4 + 12);
549 IO5 <= observation_reg(5 + 12);
549 IO5 <= observation_reg(5 + 12);
550 IO6 <= observation_reg(6 + 12);
550 IO6 <= observation_reg(6 + 12);
551 IO7 <= observation_reg(7 + 12);
551 IO7 <= observation_reg(7 + 12);
552 IO8 <= observation_reg(8 + 12);
552 IO8 <= observation_reg(8 + 12);
553 IO9 <= observation_reg(9 + 12);
553 IO9 <= observation_reg(9 + 12);
554 IO10 <= observation_reg(10 + 12);
554 IO10 <= observation_reg(10 + 12);
555 IO11 <= observation_reg(11 + 12);
555 IO11 <= observation_reg(11 + 12);
556 WHEN "010" =>
556 WHEN "010" =>
557 IO0 <= observation_reg(0 + 12 + 12);
557 IO0 <= observation_reg(0 + 12 + 12);
558 IO1 <= observation_reg(1 + 12 + 12);
558 IO1 <= observation_reg(1 + 12 + 12);
559 IO2 <= observation_reg(2 + 12 + 12);
559 IO2 <= observation_reg(2 + 12 + 12);
560 IO3 <= observation_reg(3 + 12 + 12);
560 IO3 <= observation_reg(3 + 12 + 12);
561 IO4 <= observation_reg(4 + 12 + 12);
561 IO4 <= observation_reg(4 + 12 + 12);
562 IO5 <= observation_reg(5 + 12 + 12);
562 IO5 <= observation_reg(5 + 12 + 12);
563 IO6 <= observation_reg(6 + 12 + 12);
563 IO6 <= observation_reg(6 + 12 + 12);
564 IO7 <= observation_reg(7 + 12 + 12);
564 IO7 <= observation_reg(7 + 12 + 12);
565 IO8 <= '0';
565 IO8 <= '0';
566 IO9 <= '0';
566 IO9 <= '0';
567 IO10 <= '0';
567 IO10 <= '0';
568 IO11 <= '0';
568 IO11 <= '0';
569 WHEN "000" =>
569 WHEN "000" =>
570 IO0 <= observation_vector_0(0 );
570 IO0 <= observation_vector_0(0 );
571 IO1 <= observation_vector_0(1 );
571 IO1 <= observation_vector_0(1 );
572 IO2 <= observation_vector_0(2 );
572 IO2 <= observation_vector_0(2 );
573 IO3 <= observation_vector_0(3 );
573 IO3 <= observation_vector_0(3 );
574 IO4 <= observation_vector_0(4 );
574 IO4 <= observation_vector_0(4 );
575 IO5 <= observation_vector_0(5 );
575 IO5 <= observation_vector_0(5 );
576 IO6 <= observation_vector_0(6 );
576 IO6 <= observation_vector_0(6 );
577 IO7 <= observation_vector_0(7 );
577 IO7 <= observation_vector_0(7 );
578 IO8 <= observation_vector_0(8 );
578 IO8 <= observation_vector_0(8 );
579 IO9 <= observation_vector_0(9 );
579 IO9 <= observation_vector_0(9 );
580 IO10 <= observation_vector_0(10);
580 IO10 <= observation_vector_0(10);
581 IO11 <= observation_vector_0(11);
581 IO11 <= observation_vector_0(11);
582 WHEN "100" =>
582 WHEN "100" =>
583 IO0 <= observation_vector_1(0 );
583 IO0 <= observation_vector_1(0 );
584 IO1 <= observation_vector_1(1 );
584 IO1 <= observation_vector_1(1 );
585 IO2 <= observation_vector_1(2 );
585 IO2 <= observation_vector_1(2 );
586 IO3 <= observation_vector_1(3 );
586 IO3 <= observation_vector_1(3 );
587 IO4 <= observation_vector_1(4 );
587 IO4 <= observation_vector_1(4 );
588 IO5 <= observation_vector_1(5 );
588 IO5 <= observation_vector_1(5 );
589 IO6 <= observation_vector_1(6 );
589 IO6 <= observation_vector_1(6 );
590 IO7 <= observation_vector_1(7 );
590 IO7 <= observation_vector_1(7 );
591 IO8 <= observation_vector_1(8 );
591 IO8 <= observation_vector_1(8 );
592 IO9 <= observation_vector_1(9 );
592 IO9 <= observation_vector_1(9 );
593 IO10 <= observation_vector_1(10);
593 IO10 <= observation_vector_1(10);
594 IO11 <= observation_vector_1(11);
594 IO11 <= observation_vector_1(11);
595 WHEN OTHERS => NULL;
595 WHEN OTHERS => NULL;
596 END CASE;
596 END CASE;
597
597
598 END IF;
598 END IF;
599 END PROCESS;
599 END PROCESS;
600
600
601 END beh;
601 END beh;
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@@ -1,69 +1,70
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26
26
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.cic_pkg.ALL;
28 USE lpp.cic_pkg.ALL;
29 USE lpp.data_type_pkg.ALL;
29 USE lpp.data_type_pkg.ALL;
30
30
31 ENTITY cic_lfr IS
31 ENTITY cic_lfr IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
34 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
35 );
35 );
36 PORT (
36 PORT (
37 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40
40
41 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
41 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
42 data_in_valid : IN STD_LOGIC;
43
43
44 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
44 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
45 data_out_16_valid : OUT STD_LOGIC;
45 data_out_16_valid : OUT STD_LOGIC;
46 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
46 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
47 data_out_256_valid : OUT STD_LOGIC
47 data_out_256_valid : OUT STD_LOGIC
48 );
48 );
49
49
50 END cic_lfr;
50 END cic_lfr;
51
51
52 ARCHITECTURE beh OF cic_lfr IS
52 ARCHITECTURE beh OF cic_lfr IS
53 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
53 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
54 SIGNAL sample_temp : sample_vector(3 DOWNTO 0,15 DOWNTO 0);
54 SIGNAL sample_temp : sample_vector(3 DOWNTO 0,15 DOWNTO 0);
55 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
55 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
56 BEGIN
56 BEGIN
57
57
58 -----------------------------------------------------------------------------
58 -----------------------------------------------------------------------------
59 -- SEL_SAMPLE
59 -- SEL_SAMPLE
60 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
61 sample_temp(0) <= sample_vector(0) WHEN sel_sample(0) = '0' ELSE sample_vector(1);
61 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
62 sample_temp(1) <= sample_vector(3) WHEN sel_sample(0) = '0' ELSE sample_vector(4);
62 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
63 sample_temp(2) <= sample_temp(0) WHEN sel_sample(1) = '0' ELSE sample_vector(2);
63 sample_temp(1,I) <= data_in(3,I) WHEN sel_sample(0) = '0' ELSE data_in(4,I);
64 sample_temp(3) <= sample_temp(1) WHEN sel_sample(1) = '0' ELSE sample_vector(5);
64 sample_temp(2,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE data_in(2,I);
65 sample <= sample_temp(2) WHEN sel_sample(2) = '0' ELSE sample_temp(3);
65 sample_temp(3,I) <= sample_temp(1,I) WHEN sel_sample(1) = '0' ELSE data_in(5,I);
66
66 sample(I) <= sample_temp(2,I) WHEN sel_sample(2) = '0' ELSE sample_temp(3,I);
67 END GENERATE all_bit;
67
68
68 END beh;
69 END beh;
69
70
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@@ -1,140 +1,265
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27
26
28
27 LIBRARY lpp;
29 LIBRARY lpp;
28 USE lpp.cic_pkg.ALL;
30 USE lpp.cic_pkg.ALL;
29 USE lpp.data_type_pkg.ALL;
31 USE lpp.data_type_pkg.ALL;
30
32
31 ENTITY cic_lfr_control IS
33 ENTITY cic_lfr_control IS
32 PORT (
34 PORT (
33 clk : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
37 run : IN STD_LOGIC;
36 --
38 --
37 data_in_valid : IN STD_LOGIC;
39 data_in_valid : IN STD_LOGIC;
38 data_out_16_valid : OUT STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
39 data_out_256_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
40 -- dataflow
42 -- dataflow
41 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 --
44 --
43 op_valid : OUT STD_LOGIC;
45 op_valid : OUT STD_LOGIC;
44 op_ADD_SUBn : OUT STD_LOGIC;
46 op_ADD_SUBn : OUT STD_LOGIC;
45 --
47 --
46 r_addr_init : OUT STD_LOGIC;
48 r_addr_init : OUT STD_LOGIC;
47 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
49 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
48 r_addr_add1 : OUT STD_LOGIC;
50 r_addr_add1 : OUT STD_LOGIC;
49 --
51 --
52 w_en : OUT STD_LOGIC;
50 w_addr_init : OUT STD_LOGIC;
53 w_addr_init : OUT STD_LOGIC;
51 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
54 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
52 w_addr_add1 : OUT STD_LOGIC
55 w_addr_add1 : OUT STD_LOGIC
53 );
56 );
54
57
55 END cic_lfr_control;
58 END cic_lfr_control;
56
59
57 ARCHITECTURE beh OF cic_lfr_control IS
60 ARCHITECTURE beh OF cic_lfr_control IS
58
61
59 TYPE STATE_CIC_LFR_TYPE IS (IDLE,INT_0, INT_1, INT_2);
62 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
63
64 INT_0_d0, INT_1_d0, INT_2_d0,
65 INT_0_d1, INT_1_d1, INT_2_d1,
66 INT_0_d2, INT_1_d2, INT_2_d2,
67
68 WAIT_INT_to_COMB_16,
69
70 COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
71 COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
72
73 COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
74 COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
76
77 READ_INT_2_d0,
78 READ_INT_2_d1
79 );
60 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
80 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
61
81
62 SIGNAL nb_data_receipt : INTEGER;
82 SIGNAL nb_data_receipt : INTEGER;
83 SIGNAL current_channel : INTEGER;
84
85 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
63
86
87 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
88 CONSTANT base_addr_delta : INTEGER := 40;
64 BEGIN
89 BEGIN
65
90
91 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
92 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
93 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
94 END GENERATE all_bit;
95 END GENERATE all_channel;
96
66 PROCESS (clk, rstn)
97 PROCESS (clk, rstn)
67 BEGIN -- PROCESS
98 BEGIN -- PROCESS
68 IF rstn = '0' THEN -- asynchronous reset (active low)
99 IF rstn = '0' THEN -- asynchronous reset (active low)
69 STATE_CIC_LFR <= IDLE;
100 STATE_CIC_LFR <= IDLE;
70 --
101 --
71 data_out_16_valid <= '0';
102 data_out_16_valid <= '0';
72 data_out_256_valid <= '0';
103 data_out_256_valid <= '0';
73 --
104 --
74 sel_sample <= (OTHERS => '0');
105 sel_sample <= (OTHERS => '0');
75 --
106 --
76 op_valid <= '0';
107 op_valid <= '0';
77 op_ADD_SUBn <= '0';
108 op_ADD_SUBn <= '0';
78 --
109 --
79 r_addr_init <= '0';
110 r_addr_init <= '0';
80 r_addr_base <= (OTHERS => '0');
111 r_addr_base <= (OTHERS => '0');
81 r_addr_add1 <= '0';
112 r_addr_add1 <= '0';
82 --
113 --
114 w_en <= '1';
83 w_addr_init <= '0';
115 w_addr_init <= '0';
84 w_addr_base <= (OTHERS => '0');
116 w_addr_base <= (OTHERS => '0');
85 w_addr_add1 <= '0';
117 w_addr_add1 <= '0';
86 --
118 --
87 nb_data_receipt <= 0;
119 nb_data_receipt <= 0;
88 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
120 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
121 data_out_16_valid <= '0';
122 data_out_256_valid <= '0';
123 op_valid <= '0';
124 op_ADD_SUBn <= '0';
125 r_addr_init <= '0';
126 r_addr_base <= (OTHERS => '0');
127 r_addr_add1 <= '0';
128 w_en <= '1';
129 w_addr_init <= '0';
130 w_addr_base <= (OTHERS => '0');
131 w_addr_add1 <= '0';
132
89 IF run = '0' THEN
133 IF run = '0' THEN
90 STATE_CIC_LFR <= IDLE;
134 STATE_CIC_LFR <= IDLE;
91 --
135 --
92 data_out_16_valid <= '0';
136 data_out_16_valid <= '0';
93 data_out_256_valid <= '0';
137 data_out_256_valid <= '0';
94 --
138 --
95 sel_sample <= (OTHERS => '0');
139 sel_sample <= (OTHERS => '0');
96 --
140 --
97 op_valid <= '0';
141 op_valid <= '0';
98 op_ADD_SUBn <= '0';
142 op_ADD_SUBn <= '0';
99 --
143 --
100 r_addr_init <= '0';
144 r_addr_init <= '0';
101 r_addr_base <= (OTHERS => '0');
145 r_addr_base <= (OTHERS => '0');
102 r_addr_add1 <= '0';
146 r_addr_add1 <= '0';
103 --
147 --
148 w_en <= '1';
104 w_addr_init <= '0';
149 w_addr_init <= '0';
105 w_addr_base <= (OTHERS => '0');
150 w_addr_base <= (OTHERS => '0');
106 w_addr_add1 <= '0';
151 w_addr_add1 <= '0';
107 --
152 --
108 nb_data_receipt <= 0;
153 nb_data_receipt <= 0;
154 current_channel <= 0;
109 ELSE
155 ELSE
110 CASE STATE_CIC_LFR IS
156 CASE STATE_CIC_LFR IS
111 WHEN IDLE =>
157 WHEN IDLE =>
112 data_out_16_valid <= '0';
158 data_out_16_valid <= '0';
113 data_out_256_valid <= '0';
159 data_out_256_valid <= '0';
114 --
160 --
115 sel_sample <= (OTHERS => '0');
161 sel_sample <= (OTHERS => '0');
116 --
162 --
117 op_valid <= '0';
163 op_valid <= '0';
118 op_ADD_SUBn <= '0';
164 op_ADD_SUBn <= '0';
119 --
165 --
120 r_addr_init <= '0';
166 r_addr_init <= '0';
121 r_addr_base <= (OTHERS => '0');
167 r_addr_base <= (OTHERS => '0');
122 r_addr_add1 <= '0';
168 r_addr_add1 <= '0';
123 --
169 --
170 w_en <= '1';
124 w_addr_init <= '0';
171 w_addr_init <= '0';
125 w_addr_base <= (OTHERS => '0');
172 w_addr_base <= (OTHERS => '0');
126 w_addr_add1 <= '0';
173 w_addr_add1 <= '0';
174 --
127 IF data_in_valid = '1' THEN
175 IF data_in_valid = '1' THEN
128 nb_data_receipt <= 0;
176 nb_data_receipt <= nb_data_receipt+1;
129 STATE_CIC_LFR <= INT_0;
177 current_channel <= 0;
178 STATE_CIC_LFR <= INT_0_d0;
130 END IF;
179 END IF;
131 WHEN INT_0 =>
180
181 -------------------------------------------------------------------
182 WHEN INT_0_d0 =>
183 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
184 STATE_CIC_LFR <= INT_0_d1;
185 r_addr_init <= '1';
186 r_addr_base <= base_addr_INT(current_channel);
187
188
189 WHEN INT_0_d1 =>
190 STATE_CIC_LFR <= INT_0_d2;
191 r_addr_add1 <= '1';
192
193 WHEN INT_0_d2 =>
194 STATE_CIC_LFR <= INT_1_d0;
195 r_addr_add1 <= '1';
196 op_ADD_SUBn <= '1';
197 op_valid <= '1';
198
199 WHEN INT_1_d0 => STATE_CIC_LFR <= INT_1_d1;
200 WHEN INT_1_d1 => STATE_CIC_LFR <= INT_1_d2;
201 WHEN INT_1_d2 => STATE_CIC_LFR <= INT_2_d0;
202
203 WHEN INT_2_d0 => STATE_CIC_LFR <= INT_2_d1;
204 WHEN INT_2_d1 => STATE_CIC_LFR <= INT_2_d2;
205 WHEN INT_2_d2 =>
206 IF nb_data_receipt = 256 THEN
207 STATE_CIC_LFR <= COMB_0_256_d0;
208 ELSIF (nb_data_receipt mod 16) = 0 THEN
209 STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
210 ELSE
211 IF current_channel = 5 THEN
212 STATE_CIC_LFR <= IDLE;
213 ELSE
214 current_channel <= current_channel +1;
215 STATE_CIC_LFR <= INT_0_d0;
216 END IF;
217 END IF;
218
219 -------------------------------------------------------------------
220 WHEN WAIT_INT_to_COMB_16 =>
221 STATE_CIC_LFR <= COMB_0_16_d0;
222
223 WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
224 WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
225
226 WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
227 WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
228
229 WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
230 WHEN COMB_2_16_d1 =>
231 IF current_channel = 5 THEN
232 STATE_CIC_LFR <= IDLE;
233 IF nb_data_receipt = 256 THEN
234 nb_data_receipt <= 0;
235 END IF;
236 ELSE
237 current_channel <= current_channel +1;
238 STATE_CIC_LFR <= INT_0_d0;
239 END IF;
240
241 -------------------------------------------------------------------
242 WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
243 WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
244 WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
245
246 WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
247 WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
248 WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
249
250 WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
251 WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
252 WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
253
254 -------------------------------------------------------------------
255 WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
256 WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
132
257
133 WHEN OTHERS => NULL;
258 WHEN OTHERS => NULL;
134 END CASE;
259 END CASE;
135 END IF;
260 END IF;
136 END IF;
261 END IF;
137 END PROCESS;
262 END PROCESS;
138
263
139 END beh;
264 END beh;
140
265
Show file before | Show file after | Hide comments
@@ -1,89 +1,111
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26
26
27 PACKAGE cic_pkg IS
27 PACKAGE cic_pkg IS
28
28
29 -----------------------------------------------------------------------------
29 -----------------------------------------------------------------------------
30 COMPONENT cic
30 COMPONENT cic
31 GENERIC (
31 GENERIC (
32 D_delay_number : INTEGER;
32 D_delay_number : INTEGER;
33 S_stage_number : INTEGER;
33 S_stage_number : INTEGER;
34 R_downsampling_decimation_factor : INTEGER;
34 R_downsampling_decimation_factor : INTEGER;
35 b_data_size : INTEGER;
35 b_data_size : INTEGER;
36 b_grow : INTEGER);
36 b_grow : INTEGER);
37 PORT (
37 PORT (
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 run : IN STD_LOGIC;
40 run : IN STD_LOGIC;
41 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
41 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
42 data_in_valid : IN STD_LOGIC;
43 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
43 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
44 data_out_valid : OUT STD_LOGIC);
44 data_out_valid : OUT STD_LOGIC);
45 END COMPONENT;
45 END COMPONENT;
46 -----------------------------------------------------------------------------
46 -----------------------------------------------------------------------------
47 COMPONENT cic_integrator
47 COMPONENT cic_integrator
48 GENERIC (
48 GENERIC (
49 b_data_size : INTEGER);
49 b_data_size : INTEGER);
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 run : IN STD_LOGIC;
53 run : IN STD_LOGIC;
54 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
54 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
55 data_in_valid : IN STD_LOGIC;
55 data_in_valid : IN STD_LOGIC;
56 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
56 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
57 data_out_valid : OUT STD_LOGIC);
57 data_out_valid : OUT STD_LOGIC);
58 END COMPONENT;
58 END COMPONENT;
59
59
60 COMPONENT cic_downsampler
60 COMPONENT cic_downsampler
61 GENERIC (
61 GENERIC (
62 R_downsampling_decimation_factor : INTEGER;
62 R_downsampling_decimation_factor : INTEGER;
63 b_data_size : INTEGER);
63 b_data_size : INTEGER);
64 PORT (
64 PORT (
65 clk : IN STD_LOGIC;
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 run : IN STD_LOGIC;
67 run : IN STD_LOGIC;
68 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
68 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
69 data_in_valid : IN STD_LOGIC;
69 data_in_valid : IN STD_LOGIC;
70 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
70 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
71 data_out_valid : OUT STD_LOGIC);
71 data_out_valid : OUT STD_LOGIC);
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT cic_comb
74 COMPONENT cic_comb
75 GENERIC (
75 GENERIC (
76 b_data_size : INTEGER;
76 b_data_size : INTEGER;
77 D_delay_number : INTEGER);
77 D_delay_number : INTEGER);
78 PORT (
78 PORT (
79 clk : IN STD_LOGIC;
79 clk : IN STD_LOGIC;
80 rstn : IN STD_LOGIC;
80 rstn : IN STD_LOGIC;
81 run : IN STD_LOGIC;
81 run : IN STD_LOGIC;
82 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
82 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
83 data_in_valid : IN STD_LOGIC;
83 data_in_valid : IN STD_LOGIC;
84 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
84 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
85 data_out_valid : OUT STD_LOGIC);
85 data_out_valid : OUT STD_LOGIC);
86 END COMPONENT;
86 END COMPONENT;
87 -----------------------------------------------------------------------------
87 -----------------------------------------------------------------------------
88
88
89
90 -----------------------------------------------------------------------------
91 COMPONENT cic_lfr_control
92 PORT (
93 clk : IN STD_LOGIC;
94 rstn : IN STD_LOGIC;
95 run : IN STD_LOGIC;
96 data_in_valid : IN STD_LOGIC;
97 data_out_16_valid : OUT STD_LOGIC;
98 data_out_256_valid : OUT STD_LOGIC;
99 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
100 op_valid : OUT STD_LOGIC;
101 op_ADD_SUBn : OUT STD_LOGIC;
102 r_addr_init : OUT STD_LOGIC;
103 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
104 r_addr_add1 : OUT STD_LOGIC;
105 w_en : OUT STD_LOGIC;
106 w_addr_init : OUT STD_LOGIC;
107 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
108 w_addr_add1 : OUT STD_LOGIC);
109 END COMPONENT;
110 -----------------------------------------------------------------------------
89 END cic_pkg;
111 END cic_pkg;
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@@ -1,6 +1,7
1 cic_pkg.vhd
1 cic_pkg.vhd
2 cic.vhd
2 cic.vhd
3 cic_integrator.vhd
3 cic_integrator.vhd
4 cic_downsampler.vhd
4 cic_downsampler.vhd
5 cic_comb.vhd
5 cic_comb.vhd
6 cic_lfr.vhd
6 cic_lfr.vhd
7 cic_lfr_control.vhd
Show file before | Show file after | Hide comments
@@ -1,776 +1,776
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
36 USE techmap.gencomp.ALL;
37
37
38 ENTITY lpp_lfr_apbreg IS
38 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
39 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
40 nb_data_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
43 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
44 delta_vector_size_f0_2 : INTEGER := 3;
45
45
46 pindex : INTEGER := 4;
46 pindex : INTEGER := 4;
47 paddr : INTEGER := 4;
47 paddr : INTEGER := 4;
48 pmask : INTEGER := 16#fff#;
48 pmask : INTEGER := 16#fff#;
49 pirq_ms : INTEGER := 0;
49 pirq_ms : INTEGER := 0;
50 pirq_wfp : INTEGER := 1;
50 pirq_wfp : INTEGER := 1;
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 -- Spectral Matrix Reg
62 -- Spectral Matrix Reg
63 run_ms : OUT STD_LOGIC;
63 run_ms : OUT STD_LOGIC;
64 -- IN
64 -- IN
65 ready_matrix_f0 : IN STD_LOGIC;
65 ready_matrix_f0 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68
68
69 -- error_bad_component_error : IN STD_LOGIC;
69 -- error_bad_component_error : IN STD_LOGIC;
70 error_buffer_full : IN STD_LOGIC; -- TODO
70 error_buffer_full : IN STD_LOGIC; -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72
72
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- OUT
75 -- OUT
76 status_ready_matrix_f0 : OUT STD_LOGIC;
76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
79
79
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90
90
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94
94
95 ---------------------------------------------------------------------------
95 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
97 -- WaveForm picker Reg
97 -- WaveForm picker Reg
98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102
102
103 -- OUT
103 -- OUT
104 data_shaping_BW : OUT STD_LOGIC;
104 data_shaping_BW : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
110
110
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
119
119
120 enable_f0 : OUT STD_LOGIC;
120 enable_f0 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
124
124
125 burst_f0 : OUT STD_LOGIC;
125 burst_f0 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
128
128
129 run : OUT STD_LOGIC;
129 run : OUT STD_LOGIC;
130
130
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
132
132
133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
139
139
140 );
140 );
141
141
142 END lpp_lfr_apbreg;
142 END lpp_lfr_apbreg;
143
143
144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
145
145
146 CONSTANT REVISION : INTEGER := 1;
146 CONSTANT REVISION : INTEGER := 1;
147
147
148 CONSTANT pconfig : apb_config_type := (
148 CONSTANT pconfig : apb_config_type := (
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
150 1 => apb_iobar(paddr, pmask));
150 1 => apb_iobar(paddr, pmask));
151
151
152 TYPE lpp_SpectralMatrix_regs IS RECORD
152 TYPE lpp_SpectralMatrix_regs IS RECORD
153 config_active_interruption_onNewMatrix : STD_LOGIC;
153 config_active_interruption_onNewMatrix : STD_LOGIC;
154 config_active_interruption_onError : STD_LOGIC;
154 config_active_interruption_onError : STD_LOGIC;
155 config_ms_run : STD_LOGIC;
155 config_ms_run : STD_LOGIC;
156 status_ready_matrix_f0_0 : STD_LOGIC;
156 status_ready_matrix_f0_0 : STD_LOGIC;
157 status_ready_matrix_f1_0 : STD_LOGIC;
157 status_ready_matrix_f1_0 : STD_LOGIC;
158 status_ready_matrix_f2_0 : STD_LOGIC;
158 status_ready_matrix_f2_0 : STD_LOGIC;
159 status_ready_matrix_f0_1 : STD_LOGIC;
159 status_ready_matrix_f0_1 : STD_LOGIC;
160 status_ready_matrix_f1_1 : STD_LOGIC;
160 status_ready_matrix_f1_1 : STD_LOGIC;
161 status_ready_matrix_f2_1 : STD_LOGIC;
161 status_ready_matrix_f2_1 : STD_LOGIC;
162 -- status_error_bad_component_error : STD_LOGIC;
162 -- status_error_bad_component_error : STD_LOGIC;
163 status_error_buffer_full : STD_LOGIC;
163 status_error_buffer_full : STD_LOGIC;
164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
165
165
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172
172
173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
174
174
175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
181 END RECORD;
181 END RECORD;
182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
183
183
184 TYPE lpp_WaveformPicker_regs IS RECORD
184 TYPE lpp_WaveformPicker_regs IS RECORD
185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 data_shaping_BW : STD_LOGIC;
188 data_shaping_BW : STD_LOGIC;
189 data_shaping_SP0 : STD_LOGIC;
189 data_shaping_SP0 : STD_LOGIC;
190 data_shaping_SP1 : STD_LOGIC;
190 data_shaping_SP1 : STD_LOGIC;
191 data_shaping_R0 : STD_LOGIC;
191 data_shaping_R0 : STD_LOGIC;
192 data_shaping_R1 : STD_LOGIC;
192 data_shaping_R1 : STD_LOGIC;
193 data_shaping_R2 : STD_LOGIC;
193 data_shaping_R2 : STD_LOGIC;
194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
202 enable_f0 : STD_LOGIC;
202 enable_f0 : STD_LOGIC;
203 enable_f1 : STD_LOGIC;
203 enable_f1 : STD_LOGIC;
204 enable_f2 : STD_LOGIC;
204 enable_f2 : STD_LOGIC;
205 enable_f3 : STD_LOGIC;
205 enable_f3 : STD_LOGIC;
206 burst_f0 : STD_LOGIC;
206 burst_f0 : STD_LOGIC;
207 burst_f1 : STD_LOGIC;
207 burst_f1 : STD_LOGIC;
208 burst_f2 : STD_LOGIC;
208 burst_f2 : STD_LOGIC;
209 run : STD_LOGIC;
209 run : STD_LOGIC;
210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
216 END RECORD;
216 END RECORD;
217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
218
218
219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
220
220
221 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
222 -- IRQ
222 -- IRQ
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
229 SIGNAL ored_irq_wfp : STD_LOGIC;
229 SIGNAL ored_irq_wfp : STD_LOGIC;
230
230
231 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
232 --
232 --
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237
237
238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241
241
242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245
245
246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249
249
250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253
253
254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 SIGNAL apbo_irq_ms : STD_LOGIC;
257 SIGNAL apbo_irq_ms : STD_LOGIC;
258 SIGNAL apbo_irq_wfp : STD_LOGIC;
258 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
261
261
262 BEGIN -- beh
262 BEGIN -- beh
263
263
264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
267
267
268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
270
270
271
271
272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
275
275
276
276
277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
280 data_shaping_R0 <= reg_wp.data_shaping_R0;
280 data_shaping_R0 <= reg_wp.data_shaping_R0;
281 data_shaping_R1 <= reg_wp.data_shaping_R1;
281 data_shaping_R1 <= reg_wp.data_shaping_R1;
282 data_shaping_R2 <= reg_wp.data_shaping_R2;
282 data_shaping_R2 <= reg_wp.data_shaping_R2;
283
283
284 delta_snapshot <= reg_wp.delta_snapshot;
284 delta_snapshot <= reg_wp.delta_snapshot;
285 delta_f0 <= reg_wp.delta_f0;
285 delta_f0 <= reg_wp.delta_f0;
286 delta_f0_2 <= reg_wp.delta_f0_2;
286 delta_f0_2 <= reg_wp.delta_f0_2;
287 delta_f1 <= reg_wp.delta_f1;
287 delta_f1 <= reg_wp.delta_f1;
288 delta_f2 <= reg_wp.delta_f2;
288 delta_f2 <= reg_wp.delta_f2;
289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
291
291
292 enable_f0 <= reg_wp.enable_f0;
292 enable_f0 <= reg_wp.enable_f0;
293 enable_f1 <= reg_wp.enable_f1;
293 enable_f1 <= reg_wp.enable_f1;
294 enable_f2 <= reg_wp.enable_f2;
294 enable_f2 <= reg_wp.enable_f2;
295 enable_f3 <= reg_wp.enable_f3;
295 enable_f3 <= reg_wp.enable_f3;
296
296
297 burst_f0 <= reg_wp.burst_f0;
297 burst_f0 <= reg_wp.burst_f0;
298 burst_f1 <= reg_wp.burst_f1;
298 burst_f1 <= reg_wp.burst_f1;
299 burst_f2 <= reg_wp.burst_f2;
299 burst_f2 <= reg_wp.burst_f2;
300
300
301 run <= reg_wp.run;
301 run <= reg_wp.run;
302
302
303 --addr_data_f0 <= reg_wp.addr_data_f0;
303 --addr_data_f0 <= reg_wp.addr_data_f0;
304 --addr_data_f1 <= reg_wp.addr_data_f1;
304 --addr_data_f1 <= reg_wp.addr_data_f1;
305 --addr_data_f2 <= reg_wp.addr_data_f2;
305 --addr_data_f2 <= reg_wp.addr_data_f2;
306 --addr_data_f3 <= reg_wp.addr_data_f3;
306 --addr_data_f3 <= reg_wp.addr_data_f3;
307
307
308 start_date <= reg_wp.start_date;
308 start_date <= reg_wp.start_date;
309
309
310 length_matrix_f0 <= reg_sp.length_matrix;
310 length_matrix_f0 <= reg_sp.length_matrix;
311 length_matrix_f1 <= reg_sp.length_matrix;
311 length_matrix_f1 <= reg_sp.length_matrix;
312 length_matrix_f2 <= reg_sp.length_matrix;
312 length_matrix_f2 <= reg_sp.length_matrix;
313 wfp_length_buffer <= reg_wp.length_buffer;
313 wfp_length_buffer <= reg_wp.length_buffer;
314
314
315
315
316 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
316 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
317 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
317 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
318 BEGIN -- PROCESS lpp_dma_top
318 BEGIN -- PROCESS lpp_dma_top
319 IF HRESETn = '0' THEN -- asynchronous reset (active low)
319 IF HRESETn = '0' THEN -- asynchronous reset (active low)
320 reg_sp.config_active_interruption_onNewMatrix <= '0';
320 reg_sp.config_active_interruption_onNewMatrix <= '0';
321 reg_sp.config_active_interruption_onError <= '0';
321 reg_sp.config_active_interruption_onError <= '0';
322 reg_sp.config_ms_run <= '0';
322 reg_sp.config_ms_run <= '0';
323 reg_sp.status_ready_matrix_f0_0 <= '0';
323 reg_sp.status_ready_matrix_f0_0 <= '0';
324 reg_sp.status_ready_matrix_f1_0 <= '0';
324 reg_sp.status_ready_matrix_f1_0 <= '0';
325 reg_sp.status_ready_matrix_f2_0 <= '0';
325 reg_sp.status_ready_matrix_f2_0 <= '0';
326 reg_sp.status_ready_matrix_f0_1 <= '0';
326 reg_sp.status_ready_matrix_f0_1 <= '0';
327 reg_sp.status_ready_matrix_f1_1 <= '0';
327 reg_sp.status_ready_matrix_f1_1 <= '0';
328 reg_sp.status_ready_matrix_f2_1 <= '0';
328 reg_sp.status_ready_matrix_f2_1 <= '0';
329 reg_sp.status_error_buffer_full <= '0';
329 reg_sp.status_error_buffer_full <= '0';
330 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
330 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
331
331
332 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
332 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
333 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
333 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
334 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
334 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
335
335
336 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
336 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
337 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
337 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
338 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
338 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
339
339
340 reg_sp.length_matrix <= (OTHERS => '0');
340 reg_sp.length_matrix <= (OTHERS => '0');
341
341
342 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
342 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
343 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
343 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
344 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
344 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
345
345
346 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
346 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
347 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
347 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
348 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
348 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
349
349
350 prdata <= (OTHERS => '0');
350 prdata <= (OTHERS => '0');
351
351
352
352
353 apbo_irq_ms <= '0';
353 apbo_irq_ms <= '0';
354 apbo_irq_wfp <= '0';
354 apbo_irq_wfp <= '0';
355
355
356
356
357 -- status_full_ack <= (OTHERS => '0');
357 -- status_full_ack <= (OTHERS => '0');
358
358
359 reg_wp.data_shaping_BW <= '0';
359 reg_wp.data_shaping_BW <= '0';
360 reg_wp.data_shaping_SP0 <= '0';
360 reg_wp.data_shaping_SP0 <= '0';
361 reg_wp.data_shaping_SP1 <= '0';
361 reg_wp.data_shaping_SP1 <= '0';
362 reg_wp.data_shaping_R0 <= '0';
362 reg_wp.data_shaping_R0 <= '0';
363 reg_wp.data_shaping_R1 <= '0';
363 reg_wp.data_shaping_R1 <= '0';
364 reg_wp.data_shaping_R2 <= '0';
364 reg_wp.data_shaping_R2 <= '0';
365 reg_wp.enable_f0 <= '0';
365 reg_wp.enable_f0 <= '0';
366 reg_wp.enable_f1 <= '0';
366 reg_wp.enable_f1 <= '0';
367 reg_wp.enable_f2 <= '0';
367 reg_wp.enable_f2 <= '0';
368 reg_wp.enable_f3 <= '0';
368 reg_wp.enable_f3 <= '0';
369 reg_wp.burst_f0 <= '0';
369 reg_wp.burst_f0 <= '0';
370 reg_wp.burst_f1 <= '0';
370 reg_wp.burst_f1 <= '0';
371 reg_wp.burst_f2 <= '0';
371 reg_wp.burst_f2 <= '0';
372 reg_wp.run <= '0';
372 reg_wp.run <= '0';
373 -- reg_wp.status_full <= (OTHERS => '0');
373 -- reg_wp.status_full <= (OTHERS => '0');
374 -- reg_wp.status_full_err <= (OTHERS => '0');
374 -- reg_wp.status_full_err <= (OTHERS => '0');
375 reg_wp.status_new_err <= (OTHERS => '0');
375 reg_wp.status_new_err <= (OTHERS => '0');
376 reg_wp.error_buffer_full <= (OTHERS => '0');
376 reg_wp.error_buffer_full <= (OTHERS => '0');
377 reg_wp.delta_snapshot <= (OTHERS => '0');
377 reg_wp.delta_snapshot <= (OTHERS => '0');
378 reg_wp.delta_f0 <= (OTHERS => '0');
378 reg_wp.delta_f0 <= (OTHERS => '0');
379 reg_wp.delta_f0_2 <= (OTHERS => '0');
379 reg_wp.delta_f0_2 <= (OTHERS => '0');
380 reg_wp.delta_f1 <= (OTHERS => '0');
380 reg_wp.delta_f1 <= (OTHERS => '0');
381 reg_wp.delta_f2 <= (OTHERS => '0');
381 reg_wp.delta_f2 <= (OTHERS => '0');
382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
384 reg_wp.start_date <= (OTHERS => '0');
384 reg_wp.start_date <= (OTHERS => '0');
385
385
386 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
386 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
387 reg_wp.length_buffer <= (OTHERS => '0');
387 reg_wp.length_buffer <= (OTHERS => '0');
388 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
388 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
389
389
390 -- status_full_ack <= (OTHERS => '0');
390 -- status_full_ack <= (OTHERS => '0');
391
391
392 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
392 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
393 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
393 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
394 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
394 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
395
395
396 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
396 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
397 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
397 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
398 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
398 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
399
399
400 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
400 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
401 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
401 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
402 END LOOP all_status_ready_buffer_bit;
402 END LOOP all_status_ready_buffer_bit;
403
403
404
404
405 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
405 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
406 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
406 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
407 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
407 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
408 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
408 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
409
409
410
410
411
411
412 all_status : FOR I IN 3 DOWNTO 0 LOOP
412 all_status : FOR I IN 3 DOWNTO 0 LOOP
413 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
413 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
414 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
414 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
415 END LOOP all_status;
415 END LOOP all_status;
416
416
417 paddr := "000000";
417 paddr := "000000";
418 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
418 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
419 prdata <= (OTHERS => '0');
419 prdata <= (OTHERS => '0');
420 IF apbi.psel(pindex) = '1' THEN
420 IF apbi.psel(pindex) = '1' THEN
421 -- APB DMA READ --
421 -- APB DMA READ --
422 CASE paddr(7 DOWNTO 2) IS
422 CASE paddr(7 DOWNTO 2) IS
423 --0
423 --0
424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
425 prdata(1) <= reg_sp.config_active_interruption_onError;
425 prdata(1) <= reg_sp.config_active_interruption_onError;
426 prdata(2) <= reg_sp.config_ms_run;
426 prdata(2) <= reg_sp.config_ms_run;
427 --1
427 --1
428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
435 prdata(7) <= reg_sp.status_error_buffer_full;
435 prdata(7) <= reg_sp.status_error_buffer_full;
436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
439 --2
439 --2
440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
441 --3
441 --3
442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
443 --4
443 --4
444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
445 --5
445 --5
446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
447 --6
447 --6
448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
449 --7
449 --7
450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
451 --8
451 --8
452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
453 --9
453 --9
454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
455 --10
455 --10
456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
457 --11
457 --11
458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
459 --12
459 --12
460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
461 --13
461 --13
462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
463 --14
463 --14
464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
465 --15
465 --15
466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
467 --16
467 --16
468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
469 --17
469 --17
470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 --18
471 --18
472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
473 --19
473 --19
474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
475 --20
475 --20
476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
477 ---------------------------------------------------------------------
477 ---------------------------------------------------------------------
478 --20
478 --20
479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
480 prdata(1) <= reg_wp.data_shaping_SP0;
480 prdata(1) <= reg_wp.data_shaping_SP0;
481 prdata(2) <= reg_wp.data_shaping_SP1;
481 prdata(2) <= reg_wp.data_shaping_SP1;
482 prdata(3) <= reg_wp.data_shaping_R0;
482 prdata(3) <= reg_wp.data_shaping_R0;
483 prdata(4) <= reg_wp.data_shaping_R1;
483 prdata(4) <= reg_wp.data_shaping_R1;
484 prdata(5) <= reg_wp.data_shaping_R2;
484 prdata(5) <= reg_wp.data_shaping_R2;
485 --21
485 --21
486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
487 prdata(1) <= reg_wp.enable_f1;
487 prdata(1) <= reg_wp.enable_f1;
488 prdata(2) <= reg_wp.enable_f2;
488 prdata(2) <= reg_wp.enable_f2;
489 prdata(3) <= reg_wp.enable_f3;
489 prdata(3) <= reg_wp.enable_f3;
490 prdata(4) <= reg_wp.burst_f0;
490 prdata(4) <= reg_wp.burst_f0;
491 prdata(5) <= reg_wp.burst_f1;
491 prdata(5) <= reg_wp.burst_f1;
492 prdata(6) <= reg_wp.burst_f2;
492 prdata(6) <= reg_wp.burst_f2;
493 prdata(7) <= reg_wp.run;
493 prdata(7) <= reg_wp.run;
494 --22
494 --22
495 --ON GOING \/
495 --ON GOING \/
496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
504 --ON GOING /\
504 --ON GOING /\
505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
510 --27
510 --27
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
512 --28
512 --28
513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
514 --29
514 --29
515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
516 --30
516 --30
517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
518 --31
518 --31
519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
520 --32
520 --32
521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
522 --33
522 --33
523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
524 --34
524 --34
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
526 --35
526 --35
527 WHEN "101000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
528 WHEN "101001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
529 WHEN "101010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+15 DOWNTO 48*1);
529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
530 WHEN "101011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1+47 DOWNTO 48*1+16);
530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
531
531
532 WHEN "101100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+15 DOWNTO 48*2);
532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
533 WHEN "101101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2+47 DOWNTO 48*2+16);
533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
534 WHEN "101110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+15 DOWNTO 48*3);
534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
535 WHEN "101111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3+47 DOWNTO 48*3+16);
535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
536
536
537 WHEN "110000" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+15 DOWNTO 48*4);
537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
538 WHEN "110001" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4+47 DOWNTO 48*4+16);
538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
539 WHEN "110010" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+15 DOWNTO 48*5);
539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
540 WHEN "110011" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5+47 DOWNTO 48*5+16);
540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
541
541
542 WHEN "110100" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+15 DOWNTO 48*6);
542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
543 WHEN "110101" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6+47 DOWNTO 48*6+16);
543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
544 WHEN "110110" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+15 DOWNTO 48*7);
544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
545 WHEN "110111" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7+47 DOWNTO 48*7+16);
545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
546
546
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
548
548
549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
550 ----------------------------------------------------
550 ----------------------------------------------------
551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
552 WHEN OTHERS => NULL;
552 WHEN OTHERS => NULL;
553
553
554 END CASE;
554 END CASE;
555 IF (apbi.pwrite AND apbi.penable) = '1' THEN
555 IF (apbi.pwrite AND apbi.penable) = '1' THEN
556 -- APB DMA WRITE --
556 -- APB DMA WRITE --
557 CASE paddr(7 DOWNTO 2) IS
557 CASE paddr(7 DOWNTO 2) IS
558 --
558 --
559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
561 reg_sp.config_ms_run <= apbi.pwdata(2);
561 reg_sp.config_ms_run <= apbi.pwdata(2);
562
562
563 WHEN "000001" =>
563 WHEN "000001" =>
564 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
564 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
565 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
565 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
566 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
566 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
567 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
567 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
568 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
568 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
569 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
569 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
570 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
570 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
571 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
571 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
572 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
572 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
573 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
573 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
574 --2
574 --2
575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
581 --8 to 19
581 --8 to 19
582 --20
582 --20
583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
584 --20
584 --20
585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
592 reg_wp.enable_f1 <= apbi.pwdata(1);
592 reg_wp.enable_f1 <= apbi.pwdata(1);
593 reg_wp.enable_f2 <= apbi.pwdata(2);
593 reg_wp.enable_f2 <= apbi.pwdata(2);
594 reg_wp.enable_f3 <= apbi.pwdata(3);
594 reg_wp.enable_f3 <= apbi.pwdata(3);
595 reg_wp.burst_f0 <= apbi.pwdata(4);
595 reg_wp.burst_f0 <= apbi.pwdata(4);
596 reg_wp.burst_f1 <= apbi.pwdata(5);
596 reg_wp.burst_f1 <= apbi.pwdata(5);
597 reg_wp.burst_f2 <= apbi.pwdata(6);
597 reg_wp.burst_f2 <= apbi.pwdata(6);
598 reg_wp.run <= apbi.pwdata(7);
598 reg_wp.run <= apbi.pwdata(7);
599 --22
599 --22
600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
608 --26
608 --26
609 WHEN "011111" =>
609 WHEN "011111" =>
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
615 END LOOP all_reg_wp_status_bit;
615 END LOOP all_reg_wp_status_bit;
616
616
617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
625
625
626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
627
627
628
628
629
629
630
630
631
631
632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
633 --
633 --
634 WHEN OTHERS => NULL;
634 WHEN OTHERS => NULL;
635 END CASE;
635 END CASE;
636 END IF;
636 END IF;
637 END IF;
637 END IF;
638 --apbo.pirq(pirq_ms) <=
638 --apbo.pirq(pirq_ms) <=
639 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
639 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
640 ready_matrix_f1 OR
640 ready_matrix_f1 OR
641 ready_matrix_f2)
641 ready_matrix_f2)
642 )
642 )
643 OR
643 OR
644 (reg_sp.config_active_interruption_onError AND (
644 (reg_sp.config_active_interruption_onError AND (
645 -- error_bad_component_error OR
645 -- error_bad_component_error OR
646 error_buffer_full
646 error_buffer_full
647 OR error_input_fifo_write(0)
647 OR error_input_fifo_write(0)
648 OR error_input_fifo_write(1)
648 OR error_input_fifo_write(1)
649 OR error_input_fifo_write(2))
649 OR error_input_fifo_write(2))
650 ));
650 ));
651 -- apbo.pirq(pirq_wfp)
651 -- apbo.pirq(pirq_wfp)
652 apbo_irq_wfp<= ored_irq_wfp;
652 apbo_irq_wfp<= ored_irq_wfp;
653
653
654 END IF;
654 END IF;
655 END PROCESS lpp_lfr_apbreg;
655 END PROCESS lpp_lfr_apbreg;
656
656
657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
659
659
660 apbo.pindex <= pindex;
660 apbo.pindex <= pindex;
661 apbo.pconfig <= pconfig;
661 apbo.pconfig <= pconfig;
662 apbo.prdata <= prdata;
662 apbo.prdata <= prdata;
663
663
664 -----------------------------------------------------------------------------
664 -----------------------------------------------------------------------------
665 -- IRQ
665 -- IRQ
666 -----------------------------------------------------------------------------
666 -----------------------------------------------------------------------------
667 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
667 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
668
668
669 PROCESS (HCLK, HRESETn)
669 PROCESS (HCLK, HRESETn)
670 BEGIN -- PROCESS
670 BEGIN -- PROCESS
671 IF HRESETn = '0' THEN -- asynchronous reset (active low)
671 IF HRESETn = '0' THEN -- asynchronous reset (active low)
672 irq_wfp_reg <= (OTHERS => '0');
672 irq_wfp_reg <= (OTHERS => '0');
673 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
673 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
674 irq_wfp_reg <= irq_wfp_reg_s;
674 irq_wfp_reg <= irq_wfp_reg_s;
675 END IF;
675 END IF;
676 END PROCESS;
676 END PROCESS;
677
677
678 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
678 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
679 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
679 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
680 END GENERATE all_irq_wfp;
680 END GENERATE all_irq_wfp;
681
681
682 irq_wfp_ZERO <= (OTHERS => '0');
682 irq_wfp_ZERO <= (OTHERS => '0');
683 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
683 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
684
684
685 run_ms <= reg_sp.config_ms_run;
685 run_ms <= reg_sp.config_ms_run;
686
686
687 -----------------------------------------------------------------------------
687 -----------------------------------------------------------------------------
688 --
688 --
689 -----------------------------------------------------------------------------
689 -----------------------------------------------------------------------------
690 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
690 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
691 PORT MAP (
691 PORT MAP (
692 clk => HCLK,
692 clk => HCLK,
693 rstn => HRESETn,
693 rstn => HRESETn,
694
694
695 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
695 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
696 reg0_ready_matrix => reg0_ready_matrix_f0,
696 reg0_ready_matrix => reg0_ready_matrix_f0,
697 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
697 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
698 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
698 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
699
699
700 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
700 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
701 reg1_ready_matrix => reg1_ready_matrix_f0,
701 reg1_ready_matrix => reg1_ready_matrix_f0,
702 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
702 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
703 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
703 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
704
704
705 ready_matrix => ready_matrix_f0,
705 ready_matrix => ready_matrix_f0,
706 status_ready_matrix => status_ready_matrix_f0,
706 status_ready_matrix => status_ready_matrix_f0,
707 addr_matrix => addr_matrix_f0,
707 addr_matrix => addr_matrix_f0,
708 matrix_time => matrix_time_f0);
708 matrix_time => matrix_time_f0);
709
709
710 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
710 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
711 PORT MAP (
711 PORT MAP (
712 clk => HCLK,
712 clk => HCLK,
713 rstn => HRESETn,
713 rstn => HRESETn,
714
714
715 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
715 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
716 reg0_ready_matrix => reg0_ready_matrix_f1,
716 reg0_ready_matrix => reg0_ready_matrix_f1,
717 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
717 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
718 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
718 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
719
719
720 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
720 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
721 reg1_ready_matrix => reg1_ready_matrix_f1,
721 reg1_ready_matrix => reg1_ready_matrix_f1,
722 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
722 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
723 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
723 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
724
724
725 ready_matrix => ready_matrix_f1,
725 ready_matrix => ready_matrix_f1,
726 status_ready_matrix => status_ready_matrix_f1,
726 status_ready_matrix => status_ready_matrix_f1,
727 addr_matrix => addr_matrix_f1,
727 addr_matrix => addr_matrix_f1,
728 matrix_time => matrix_time_f1);
728 matrix_time => matrix_time_f1);
729
729
730 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
730 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
731 PORT MAP (
731 PORT MAP (
732 clk => HCLK,
732 clk => HCLK,
733 rstn => HRESETn,
733 rstn => HRESETn,
734
734
735 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
735 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
736 reg0_ready_matrix => reg0_ready_matrix_f2,
736 reg0_ready_matrix => reg0_ready_matrix_f2,
737 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
737 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
738 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
738 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
739
739
740 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
740 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
741 reg1_ready_matrix => reg1_ready_matrix_f2,
741 reg1_ready_matrix => reg1_ready_matrix_f2,
742 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
742 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
743 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
743 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
744
744
745 ready_matrix => ready_matrix_f2,
745 ready_matrix => ready_matrix_f2,
746 status_ready_matrix => status_ready_matrix_f2,
746 status_ready_matrix => status_ready_matrix_f2,
747 addr_matrix => addr_matrix_f2,
747 addr_matrix => addr_matrix_f2,
748 matrix_time => matrix_time_f2);
748 matrix_time => matrix_time_f2);
749
749
750 -----------------------------------------------------------------------------
750 -----------------------------------------------------------------------------
751 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
751 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
752 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
752 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
753 PORT MAP (
753 PORT MAP (
754 clk => HCLK,
754 clk => HCLK,
755 rstn => HRESETn,
755 rstn => HRESETn,
756
756
757 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
757 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
758 reg0_ready_matrix => reg_ready_buffer_f(2*I),
758 reg0_ready_matrix => reg_ready_buffer_f(2*I),
759 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
759 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
760 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
760 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
761
761
762 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
762 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
763 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
763 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
764 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
764 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
765 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
765 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
766
766
767 ready_matrix => wfp_ready_buffer(I),
767 ready_matrix => wfp_ready_buffer(I),
768 status_ready_matrix => wfp_status_buffer_ready(I),
768 status_ready_matrix => wfp_status_buffer_ready(I),
769 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
769 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
770 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
770 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
771 );
771 );
772
772
773 END GENERATE all_wfp_pointer;
773 END GENERATE all_wfp_pointer;
774 -----------------------------------------------------------------------------
774 -----------------------------------------------------------------------------
775
775
776 END beh;
776 END beh; No newline at end of file
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