HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r196:ac9b8685732d

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r196:ac9b8685732d

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boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc +5 0

             set_io	clk49_152MHz	-pinname	D5	-fixed	yes	-DIRECTION	Inout
             set_io	clk50MHz	-pinname	B3	-fixed	yes	-DIRECTION	Inout
             set_io	reset		-pinname	N18	-fixed	yes	-DIRECTION	Inout
             set_io	{address[0]}	-pinname	H16	-fixed	yes	-DIRECTION	Inout
             set_io	{address[1]}	-pinname	J15	-fixed	yes	-DIRECTION	Inout
             set_io	{address[2]}	-pinname	B18	-fixed	yes	-DIRECTION	Inout
             set_io	{address[3]}	-pinname	C17	-fixed	yes	-DIRECTION	Inout
             set_io	{address[4]}	-pinname	C18	-fixed	yes	-DIRECTION	Inout
             set_io	{address[5]}	-pinname	U2	-fixed	yes	-DIRECTION	Inout
             set_io	{address[6]}	-pinname	U3	-fixed	yes	-DIRECTION	Inout
             set_io	{address[7]}	-pinname	R5	-fixed	yes	-DIRECTION	Inout
             set_io	{address[8]}	-pinname	N11	-fixed	yes	-DIRECTION	Inout
             set_io	{address[9]}	-pinname	R13	-fixed	yes	-DIRECTION	Inout
             set_io	{address[10]}	-pinname	V13	-fixed	yes	-DIRECTION	Inout
             set_io	{address[11]}	-pinname	U13	-fixed	yes	-DIRECTION	Inout
             set_io	{address[12]}	-pinname	V15	-fixed	yes	-DIRECTION	Inout
             set_io	{address[13]}	-pinname	V16	-fixed	yes	-DIRECTION	Inout
             set_io	{address[14]}	-pinname	V17	-fixed	yes	-DIRECTION	Inout
             set_io	{address[15]}	-pinname	N1	-fixed	yes	-DIRECTION	Inout
             set_io	{address[16]}	-pinname	R3	-fixed	yes	-DIRECTION	Inout
             set_io	{address[17]}	-pinname	P4	-fixed	yes	-DIRECTION	Inout
             set_io	{address[18]}	-pinname	N3	-fixed	yes	-DIRECTION	Inout
             set_io	{address[19]}	-pinname	M7	-fixed	yes	-DIRECTION	Inout
             set_io	{data[0]}	-pinname	P17	-fixed	yes	-DIRECTION	Inout
             set_io	{data[1]}	-pinname	R18	-fixed	yes	-DIRECTION	Inout
             set_io	{data[2]}	-pinname	T18	-fixed	yes	-DIRECTION	Inout
             set_io	{data[3]}	-pinname	J13	-fixed	yes	-DIRECTION	Inout
             set_io	{data[4]}	-pinname	T13	-fixed	yes	-DIRECTION	Inout
             set_io	{data[5]}	-pinname	T12	-fixed	yes	-DIRECTION	Inout
             set_io	{data[6]}	-pinname	R12	-fixed	yes	-DIRECTION	Inout
             set_io	{data[7]}	-pinname	T11	-fixed	yes	-DIRECTION	Inout
             set_io	{data[8]}	-pinname	N2	-fixed	yes	-DIRECTION	Inout
             set_io	{data[9]}	-pinname	P1	-fixed	yes	-DIRECTION	Inout
             set_io	{data[10]}	-pinname	R1	-fixed	yes	-DIRECTION	Inout
             set_io	{data[11]}	-pinname	T1	-fixed	yes	-DIRECTION	Inout
             set_io	{data[12]}	-pinname	M4	-fixed	yes	-DIRECTION	Inout
             set_io	{data[13]}	-pinname	K1	-fixed	yes	-DIRECTION	Inout
             set_io	{data[14]}	-pinname	J1	-fixed	yes	-DIRECTION	Inout
             set_io	{data[15]}	-pinname	H1	-fixed	yes	-DIRECTION	Inout
             set_io	{data[16]}	-pinname	H15	-fixed	yes	-DIRECTION	Inout
             set_io	{data[17]}	-pinname	G15	-fixed	yes	-DIRECTION	Inout
             set_io	{data[18]}	-pinname	H13	-fixed	yes	-DIRECTION	Inout
             set_io	{data[19]}	-pinname	G12	-fixed	yes	-DIRECTION	Inout
             set_io	{data[20]}	-pinname	V14	-fixed	yes	-DIRECTION	Inout
             set_io	{data[21]}	-pinname	N9	-fixed	yes	-DIRECTION	Inout
             set_io	{data[22]}	-pinname	M13	-fixed	yes	-DIRECTION	Inout
             set_io	{data[23]}	-pinname	M15	-fixed	yes	-DIRECTION	Inout
             set_io	{data[24]}	-pinname	J17	-fixed	yes	-DIRECTION	Inout
             set_io	{data[25]}	-pinname	K15	-fixed	yes	-DIRECTION	Inout
             set_io	{data[26]}	-pinname	J14	-fixed	yes	-DIRECTION	Inout
             set_io	{data[27]}	-pinname	U18	-fixed	yes	-DIRECTION	Inout
             set_io	{data[28]}	-pinname	H18	-fixed	yes	-DIRECTION	Inout
             set_io	{data[29]}	-pinname	J18	-fixed	yes	-DIRECTION	Inout
             set_io	{data[30]}	-pinname	G17	-fixed	yes	-DIRECTION	Inout
             set_io	{data[31]}	-pinname	F18	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_BE0	-pinname	U12	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_BE1	-pinname	K18	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_BE2	-pinname	K12	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_BE3	-pinname	F17	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_WE	-pinname	D18	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_CE	-pinname	M6	-fixed	yes	-DIRECTION	Inout
             set_io	nSRAM_OE	-pinname	N12	-fixed	yes	-DIRECTION	Inout
             set_io	spw1_din	-pinname	D6	-fixed	yes	-DIRECTION	Inout
             set_io	spw1_sin	-pinname	C6	-fixed	yes	-DIRECTION	Inout
             set_io	spw1_dout	-pinname	C16	-fixed	yes	-DIRECTION	Inout
             set_io	spw1_sout	-pinname	C4	-fixed	yes	-DIRECTION	Inout
+            set_io	spw2_din	-pinname	E6	-fixed	yes	-DIRECTION	Inout
+            set_io	spw2_sin	-pinname	C15	-fixed	yes	-DIRECTION	Inout
+            set_io	spw2_dout	-pinname	B7	-fixed	yes	-DIRECTION	Inout
+            set_io	spw2_sout	-pinname	D7	-fixed	yes	-DIRECTION	Inout
             set_io	{led[0]}	-pinname	K17	-fixed	yes	-DIRECTION	Inout
             set_io	{led[1]}	-pinname	L18	-fixed	yes	-DIRECTION	Inout
             set_io	{led[2]}	-pinname	M17	-fixed	yes	-DIRECTION	Inout
             set_io	ahbtxd	-pinname	J12	-fixed	yes	-DIRECTION	Inout
             #set_io	TAG2	-pinname	K13	-fixed	yes	-DIRECTION	Inout
             set_io	ahbrxd	-pinname	L16	-fixed	yes	-DIRECTION	Inout
             #set_io	TAG4	-pinname	L15	-fixed	yes	-DIRECTION	Inout
             set_io	urxd1	-pinname	M16	-fixed	yes	-DIRECTION	Inout
             set_io	utxd1	-pinname	L13	-fixed	yes	-DIRECTION	Inout
             set_io	errorn	-pinname	P6	-fixed	yes	-DIRECTION	Inout
             #set_io	TAG8	-pinname	R6	-fixed	yes	-DIRECTION	Inout
             #set_io	TAG9	-pinname	T4	-fixed	yes	-DIRECTION	Inout
             set_io bias_fail_sw -pinname A3 -fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[0]}	-pinname	A13	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[1]}	-pinname	A14	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[2]}	-pinname	A10	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[3]}	-pinname	B10	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[4]}	-pinname	B13	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[5]}	-pinname	D13	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[6]}	-pinname	A11	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_OEB_bar_CH[7]}	-pinname	B12	-fixed	yes	-DIRECTION	Inout
             set_io	ADC_smpclk	-pinname	A15	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[0]}	-pinname	A16	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[1]}	-pinname	B16	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[2]}	-pinname	A17	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[3]}	-pinname	C12	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[4]}	-pinname	B17	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[5]}	-pinname	C13	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[6]}	-pinname	D15	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[7]}	-pinname	E15	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[8]}	-pinname	D16	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[9]}	-pinname	F16	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[10]}	-pinname	F15	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[11]}	-pinname	G16	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[12]}	-pinname	F13	-fixed	yes	-DIRECTION	Inout
             set_io	{ADC_data[13]}	-pinname	G13	-fixed	yes	-DIRECTION	Inout

lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +3 -2

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_top_lfr_pkg IS
               COMPONENT lpp_top_acq
               GENERIC(
                 tech : INTEGER := 0
                 );
               PORT (
                 -- ADS7886
                 cnv_run         : IN  STD_LOGIC;
                 cnv             : OUT STD_LOGIC;
                 sck             : OUT STD_LOGIC;
                 sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 --
                 cnv_clk         : IN  STD_LOGIC;    -- 49 MHz
                 cnv_rstn        : IN  STD_LOGIC;
                 --
                 clk             : IN  STD_LOGIC;    -- 25 MHz
                 rstn            : IN  STD_LOGIC;
                 --
                 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f3_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
                 );
               END COMPONENT;
               COMPONENT lpp_top_apbreg
                 GENERIC (
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq                    : INTEGER);
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   apbi                                   : IN  apb_slv_in_type;
                   apbo                                   : OUT apb_slv_out_type;
                   ready_matrix_f0_0                      : IN  STD_LOGIC;
                   ready_matrix_f0_1                      : IN  STD_LOGIC;
                   ready_matrix_f1                        : IN  STD_LOGIC;
                   ready_matrix_f2                        : IN  STD_LOGIC;
                   error_anticipating_empty_fifo          : IN  STD_LOGIC;
                   error_bad_component_error              : IN  STD_LOGIC;
                   debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : OUT STD_LOGIC;
                   status_ready_matrix_f0_1               : OUT STD_LOGIC;
                   status_ready_matrix_f1                 : OUT STD_LOGIC;
                   status_ready_matrix_f2                 : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo   : OUT STD_LOGIC;
                   status_error_bad_component_error       : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err                         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW                        : OUT STD_LOGIC;
                   data_shaping_SP0                       : OUT STD_LOGIC;
                   data_shaping_SP1                       : OUT STD_LOGIC;
                   data_shaping_R0                        : OUT STD_LOGIC;
                   data_shaping_R1                        : OUT STD_LOGIC;
                   delta_snapshot                         : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                   delta_f2_f1                            : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                   delta_f2_f0                            : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                   nb_burst_available                     : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                   nb_snapshot_param                      : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0                              : OUT STD_LOGIC;
                   enable_f1                              : OUT STD_LOGIC;
                   enable_f2                              : OUT STD_LOGIC;
                   enable_f3                              : OUT STD_LOGIC;
                   burst_f0                               : OUT STD_LOGIC;
                   burst_f1                               : OUT STD_LOGIC;
                   burst_f2                               : OUT STD_LOGIC;
                   addr_data_f0                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_top_lfr_wf_picker
                 GENERIC (
                   hindex                  : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq                    : INTEGER;
                   tech                    : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   ENABLE_FILTER           : STD_LOGIC);
                 PORT (
                   cnv_run         : IN  STD_LOGIC;
                   cnv             : OUT STD_LOGIC;
                   sck             : OUT STD_LOGIC;
                   sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                   cnv_clk         : IN  STD_LOGIC;
                   cnv_rstn        : IN  STD_LOGIC;
                   HCLK            : IN  STD_ULOGIC;
                   HRESETn         : IN  STD_ULOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   AHB_Master_In   : IN  AHB_Mst_In_Type;
                   AHB_Master_Out  : OUT AHB_Mst_Out_Type;
                   coarse_time_0   : IN  STD_LOGIC;
                   data_shaping_BW : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_top_lfr_wf_picker_ip
                 GENERIC (
                   hindex                  : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   tech                    : INTEGER;
                   Mem_use                 : INTEGER);
                 PORT (
                 sample               : IN Samples(7 DOWNTO 0);
                 sample_val           : IN STD_LOGIC;
                   cnv_clk            : IN  STD_LOGIC;
                   cnv_rstn           : IN  STD_LOGIC;
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   sample_f0_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f0_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f1_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f2_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f3_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   AHB_Master_In      : IN  AHB_Mst_In_Type;
                   AHB_Master_Out     : OUT AHB_Mst_Out_Type;
                   coarse_time_0      : IN  STD_LOGIC;
                   data_shaping_SP0   : IN  STD_LOGIC;
                   data_shaping_SP1   : IN  STD_LOGIC;
                   data_shaping_R0    : IN  STD_LOGIC;
                   data_shaping_R1    : IN  STD_LOGIC;
                   delta_snapshot     : IN  STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                   delta_f2_f1        : IN  STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                   delta_f2_f0        : IN  STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                   enable_f0          : IN  STD_LOGIC;
                   enable_f1          : IN  STD_LOGIC;
                   enable_f2          : IN  STD_LOGIC;
                   enable_f3          : IN  STD_LOGIC;
                   burst_f0           : IN  STD_LOGIC;
                   burst_f1           : IN  STD_LOGIC;
                   burst_f2           : IN  STD_LOGIC;
                   nb_burst_available : IN  STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                   nb_snapshot_param  : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_full        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   addr_data_f0       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
                 GENERIC (
                   hindex                  : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   tech                    : INTEGER);
                 PORT (
                   sample             : IN  Samples(7 DOWNTO 0);
                   sample_val         : IN  STD_LOGIC;
                   cnv_clk            : IN  STD_LOGIC;
                   cnv_rstn           : IN  STD_LOGIC;
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   sample_f0_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f0_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f1_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f2_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
                   sample_f3_wdata    : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   AHB_Master_In      : IN  AHB_Mst_In_Type;
                   AHB_Master_Out     : OUT AHB_Mst_Out_Type;
                   coarse_time_0      : IN  STD_LOGIC;
                   data_shaping_SP0   : IN  STD_LOGIC;
                   data_shaping_SP1   : IN  STD_LOGIC;
                   data_shaping_R0    : IN  STD_LOGIC;
                   data_shaping_R1    : IN  STD_LOGIC;
                   delta_snapshot     : IN  STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
                   delta_f2_f1        : IN  STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
                   delta_f2_f0        : IN  STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
                   enable_f0          : IN  STD_LOGIC;
                   enable_f1          : IN  STD_LOGIC;
                   enable_f2          : IN  STD_LOGIC;
                   enable_f3          : IN  STD_LOGIC;
                   burst_f0           : IN  STD_LOGIC;
                   burst_f1           : IN  STD_LOGIC;
                   burst_f2           : IN  STD_LOGIC;
                   nb_burst_available : IN  STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
                   nb_snapshot_param  : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_full        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_new_err     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   addr_data_f0       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT top_wf_picker
                 GENERIC (
                   hindex                  : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq                    : INTEGER;
                   tech                    : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   ENABLE_FILTER           : STD_LOGIC);
                 PORT (
                   cnv_clk         : IN  STD_LOGIC;
                   cnv_rstn        : IN  STD_LOGIC;
-                  sample          : IN  Samples14v(7 DOWNTO 0);
+                  sample_B          : IN  Samples14v(2 DOWNTO 0);
+                  sample_E          : IN  Samples14v(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   HCLK            : IN  STD_ULOGIC;
                   HRESETn         : IN  STD_ULOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   AHB_Master_In   : IN  AHB_Mst_In_Type;
                   AHB_Master_Out  : OUT AHB_Mst_Out_Type;
                   coarse_time_0   : IN  STD_LOGIC;
                   data_shaping_BW : OUT STD_LOGIC);
               END COMPONENT;
-            END lpp_top_lfr_pkg;
  No newline at end of file
+            END lpp_top_lfr_pkg;

lib/lpp/lpp_top_lfr/top_wf_picker.vhd +8 -2

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY top_wf_picker IS
               GENERIC (
                 hindex                  : INTEGER   := 2;
                 pindex                  : INTEGER   := 15;
                 paddr                   : INTEGER   := 15;
                 pmask                   : INTEGER   := 16#fff#;
                 pirq                    : INTEGER   := 15;
                 tech                    : INTEGER   := 0;
                 nb_burst_available_size : INTEGER   := 11;
                 nb_snapshot_param_size  : INTEGER   := 11;
                 delta_snapshot_size     : INTEGER   := 16;
                 delta_f2_f0_size        : INTEGER   := 10;
                 delta_f2_f1_size        : INTEGER   := 10;
                 ENABLE_FILTER           : STD_LOGIC := '1'
                 );
               PORT (
                 cnv_clk  : IN  STD_LOGIC;
                 cnv_rstn : IN  STD_LOGIC;
                 --
-                sample     : IN Samples14v(7 DOWNTO 0);
+                sample_B   : IN Samples14v(2 DOWNTO 0);
+                sample_E   : IN Samples14v(4 DOWNTO 0);
                 sample_val : IN STD_LOGIC;
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
                 -- AMBA APB Slave Interface
                 apbi : IN  apb_slv_in_type;
                 apbo : OUT apb_slv_out_type;
                 -- AMBA AHB Master Interface
                 AHB_Master_In  : IN  AHB_Mst_In_Type;
                 AHB_Master_Out : OUT AHB_Mst_Out_Type;
                 --
                 coarse_time_0 : IN STD_LOGIC;
                 --
                 data_shaping_BW : OUT STD_LOGIC
                 );
             END top_wf_picker;
             ARCHITECTURE tb OF top_wf_picker IS
               SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
               SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
               SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
               SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
               SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_full        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack    : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err    : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL data_shaping_SP0   : STD_LOGIC;
               SIGNAL data_shaping_SP1   : STD_LOGIC;
               SIGNAL data_shaping_R0    : STD_LOGIC;
               SIGNAL data_shaping_R1    : STD_LOGIC;
               SIGNAL delta_snapshot     : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
               SIGNAL delta_f2_f1        : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
               SIGNAL delta_f2_f0        : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
               SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param  : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0          : STD_LOGIC;
               SIGNAL enable_f1          : STD_LOGIC;
               SIGNAL enable_f2          : STD_LOGIC;
               SIGNAL enable_f3          : STD_LOGIC;
               SIGNAL burst_f0           : STD_LOGIC;
               SIGNAL burst_f1           : STD_LOGIC;
               SIGNAL burst_f2           : STD_LOGIC;
               SIGNAL addr_data_f0       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f1       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f2       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f3       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL sample_f0_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               CONSTANT ChanelCount     : INTEGER := 8;
               CONSTANT ncycle_cnv_high : INTEGER := 40;
               CONSTANT ncycle_cnv      : INTEGER := 250;
-              SIGNAL   sample_s          : Samples(ChanelCount-1 DOWNTO 0);
+              SIGNAL  sample_s          : Samples(ChanelCount-1 DOWNTO 0);
+              SIGNAL  sample            :  Samples14v(7 DOWNTO 0);
             BEGIN
+              sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+              sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
               ready_matrix_f0_0             <= '0';
               ready_matrix_f0_1             <= '0';
               ready_matrix_f1               <= '0';
               ready_matrix_f2               <= '0';
               error_anticipating_empty_fifo <= '0';
               error_bad_component_error     <= '0';
               debug_reg                     <= (OTHERS => '0');
               lpp_top_apbreg_1 : lpp_top_apbreg
                 GENERIC MAP (
                   nb_burst_available_size => nb_burst_available_size,
                   nb_snapshot_param_size  => nb_snapshot_param_size,
                   delta_snapshot_size     => delta_snapshot_size,
                   delta_f2_f0_size        => delta_f2_f0_size,
                   delta_f2_f1_size        => delta_f2_f1_size,
                   pindex                  => pindex,
                   paddr                   => paddr,
                   pmask                   => pmask,
                   pirq                    => pirq)
                 PORT MAP (
                   HCLK    => HCLK,
                   HRESETn => HRESETn,
                   apbi    => apbi,
                   apbo    => apbo,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0_0                       => addr_matrix_f0_0,
                   addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
                   status_full        => status_full,
                   status_full_ack    => status_full_ack,
                   status_full_err    => status_full_err,
                   status_new_err     => status_new_err,
                   data_shaping_BW    => data_shaping_BW,
                   data_shaping_SP0   => data_shaping_SP0,
                   data_shaping_SP1   => data_shaping_SP1,
                   data_shaping_R0    => data_shaping_R0,
                   data_shaping_R1    => data_shaping_R1,
                   delta_snapshot     => delta_snapshot,
                   delta_f2_f1        => delta_f2_f1,
                   delta_f2_f0        => delta_f2_f0,
                   nb_burst_available => nb_burst_available,
                   nb_snapshot_param  => nb_snapshot_param,
                   enable_f0          => enable_f0,
                   enable_f1          => enable_f1,
                   enable_f2          => enable_f2,
                   enable_f3          => enable_f3,
                   burst_f0           => burst_f0,
                   burst_f1           => burst_f1,
                   burst_f2           => burst_f2,
                   addr_data_f0       => addr_data_f0,
                   addr_data_f1       => addr_data_f1,
                   addr_data_f2       => addr_data_f2,
                   addr_data_f3       => addr_data_f3);
               --DIGITAL_acquisition : AD7688_drvr_sync
               --  GENERIC MAP (
               --    ChanelCount     => ChanelCount,
               --    ncycle_cnv_high => ncycle_cnv_high,
               --    ncycle_cnv      => ncycle_cnv)
               --  PORT MAP (
               --    cnv_clk    => cnv_clk,                      --
               --    cnv_rstn   => cnv_rstn,                     --
               --    cnv_run    => cnv_run,                      --
               --    cnv        => cnv,                          --
               --    sck        => sck,                          --
               --    sdo        => sdo(ChanelCount-1 DOWNTO 0),  --
               --    sample     => sample,
               --    sample_val => sample_val);
               all_channel: FOR i IN 7 DOWNTO 0 GENERATE
                 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
               END GENERATE all_channel;
               wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
                 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
                   GENERIC MAP (
                     hindex                  => hindex,
                     nb_burst_available_size => nb_burst_available_size,
                     nb_snapshot_param_size  => nb_snapshot_param_size,
                     delta_snapshot_size     => delta_snapshot_size,
                     delta_f2_f0_size        => delta_f2_f0_size,
                     delta_f2_f1_size        => delta_f2_f1_size,
                     tech                    => tech,
                     Mem_use                 => use_RAM
                     )
                   PORT MAP (
                     sample     => sample_s,
                     sample_val => sample_val,
                     cnv_clk  => HCLK,--cnv_clk,
                     cnv_rstn => HRESETn,--cnv_rstn,
                     clk  => HCLK,
                     rstn => HRESETn,
                     sample_f0_wen      => sample_f0_wen,
                     sample_f0_wdata    => sample_f0_wdata,
                     sample_f1_wen      => sample_f1_wen,
                     sample_f1_wdata    => sample_f1_wdata,
                     sample_f2_wen      => sample_f2_wen,
                     sample_f2_wdata    => sample_f2_wdata,
                     sample_f3_wen      => sample_f3_wen,
                     sample_f3_wdata    => sample_f3_wdata,
                     AHB_Master_In      => AHB_Master_In,
                     AHB_Master_Out     => AHB_Master_Out,
                     coarse_time_0      => coarse_time_0,
                     data_shaping_SP0   => data_shaping_SP0,
                     data_shaping_SP1   => data_shaping_SP1,
                     data_shaping_R0    => data_shaping_R0,
                     data_shaping_R1    => data_shaping_R1,
                     delta_snapshot     => delta_snapshot,
                     delta_f2_f1        => delta_f2_f1,
                     delta_f2_f0        => delta_f2_f0,
                     enable_f0          => enable_f0,
                     enable_f1          => enable_f1,
                     enable_f2          => enable_f2,
                     enable_f3          => enable_f3,
                     burst_f0           => burst_f0,
                     burst_f1           => burst_f1,
                     burst_f2           => burst_f2,
                     nb_burst_available => nb_burst_available,
                     nb_snapshot_param  => nb_snapshot_param,
                     status_full        => status_full,
                     status_full_ack    => status_full_ack,
                     status_full_err    => status_full_err,
                     status_new_err     => status_new_err,
                     addr_data_f0       => addr_data_f0,
                     addr_data_f1       => addr_data_f1,
                     addr_data_f2       => addr_data_f2,
                     addr_data_f3       => addr_data_f3);
               END GENERATE wf_picker_with_filter;
               wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
                 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
                   GENERIC MAP (
                     hindex                  => hindex,
                     nb_burst_available_size => nb_burst_available_size,
                     nb_snapshot_param_size  => nb_snapshot_param_size,
                     delta_snapshot_size     => delta_snapshot_size,
                     delta_f2_f0_size        => delta_f2_f0_size,
                     delta_f2_f1_size        => delta_f2_f1_size,
                     tech                    => tech
                     )
                   PORT MAP (
                     sample     => sample_s,
                     sample_val => sample_val,
                     cnv_clk  => cnv_clk,
                     cnv_rstn => cnv_rstn,
                     clk  => HCLK,
                     rstn => HRESETn,
                     sample_f0_wen      => sample_f0_wen,
                     sample_f0_wdata    => sample_f0_wdata,
                     sample_f1_wen      => sample_f1_wen,
                     sample_f1_wdata    => sample_f1_wdata,
                     sample_f2_wen      => sample_f2_wen,
                     sample_f2_wdata    => sample_f2_wdata,
                     sample_f3_wen      => sample_f3_wen,
                     sample_f3_wdata    => sample_f3_wdata,
                     AHB_Master_In      => AHB_Master_In,
                     AHB_Master_Out     => AHB_Master_Out,
                     coarse_time_0      => coarse_time_0,
                     data_shaping_SP0   => data_shaping_SP0,
                     data_shaping_SP1   => data_shaping_SP1,
                     data_shaping_R0    => data_shaping_R0,
                     data_shaping_R1    => data_shaping_R1,
                     delta_snapshot     => delta_snapshot,
                     delta_f2_f1        => delta_f2_f1,
                     delta_f2_f0        => delta_f2_f0,
                     enable_f0          => enable_f0,
                     enable_f1          => enable_f1,
                     enable_f2          => enable_f2,
                     enable_f3          => enable_f3,
                     burst_f0           => burst_f0,
                     burst_f1           => burst_f1,
                     burst_f2           => burst_f2,
                     nb_burst_available => nb_burst_available,
                     nb_snapshot_param  => nb_snapshot_param,
                     status_full        => status_full,
                     status_full_ack    => status_full_ack,
                     status_full_err    => status_full_err,
                     status_new_err     => status_new_err,
                     addr_data_f0       => addr_data_f0,
                     addr_data_f1       => addr_data_f1,
                     addr_data_f2       => addr_data_f2,
                     addr_data_f3       => addr_data_f3);
               END GENERATE wf_picker_without_filter;
             END tb;

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