diff --git a/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc b/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc --- a/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc +++ b/boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc @@ -69,6 +69,11 @@ set_io spw1_sin -pinname C6 -fixed yes - set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -263,7 +263,8 @@ PACKAGE lpp_top_lfr_pkg IS PORT ( cnv_clk : IN STD_LOGIC; cnv_rstn : IN STD_LOGIC; - sample : IN Samples14v(7 DOWNTO 0); + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); sample_val : IN STD_LOGIC; HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; @@ -275,4 +276,4 @@ PACKAGE lpp_top_lfr_pkg IS data_shaping_BW : OUT STD_LOGIC); END COMPONENT; -END lpp_top_lfr_pkg; \ No newline at end of file +END lpp_top_lfr_pkg; diff --git a/lib/lpp/lpp_top_lfr/top_wf_picker.vhd b/lib/lpp/lpp_top_lfr/top_wf_picker.vhd --- a/lib/lpp/lpp_top_lfr/top_wf_picker.vhd +++ b/lib/lpp/lpp_top_lfr/top_wf_picker.vhd @@ -38,7 +38,8 @@ ENTITY top_wf_picker IS cnv_clk : IN STD_LOGIC; cnv_rstn : IN STD_LOGIC; -- - sample : IN Samples14v(7 DOWNTO 0); + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); sample_val : IN STD_LOGIC; -- AMBA AHB system signals @@ -121,10 +122,15 @@ ARCHITECTURE tb OF top_wf_picker IS CONSTANT ncycle_cnv_high : INTEGER := 40; CONSTANT ncycle_cnv : INTEGER := 250; - SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample : Samples14v(7 DOWNTO 0); BEGIN + sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); + sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); + + ready_matrix_f0_0 <= '0'; ready_matrix_f0_1 <= '0'; ready_matrix_f1 <= '0';