HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r196:ac9b8685732d

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pellion -

r196:ac9b8685732d JC

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r196:ac9b8685732d

boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc +5 0

              set_io	spw1_dout	-pinname	C16	-fixed	yes	-DIRECTION	Inout
              set_io	spw1_sout	-pinname	C4	-fixed	yes	-DIRECTION	Inout
+             set_io	spw2_din	-pinname	E6	-fixed	yes	-DIRECTION	Inout
+             set_io	spw2_sin	-pinname	C15	-fixed	yes	-DIRECTION	Inout
+             set_io	spw2_dout	-pinname	B7	-fixed	yes	-DIRECTION	Inout
+             set_io	spw2_sout	-pinname	D7	-fixed	yes	-DIRECTION	Inout
              set_io	{led[0]}	-pinname	K17	-fixed	yes	-DIRECTION	Inout
              set_io	{led[1]}	-pinname	L18	-fixed	yes	-DIRECTION	Inout
              set_io	{led[2]}	-pinname	M17	-fixed	yes	-DIRECTION	Inout

lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +3 -2

                  PORT (
                    cnv_clk         : IN  STD_LOGIC;
                    cnv_rstn        : IN  STD_LOGIC;
-                   sample          : IN  Samples14v(7 DOWNTO 0);
+                   sample_B          : IN  Samples14v(2 DOWNTO 0);
+                   sample_E          : IN  Samples14v(4 DOWNTO 0);
                    sample_val      : IN  STD_LOGIC;
                    HCLK            : IN  STD_ULOGIC;
                    HRESETn         : IN  STD_ULOGIC;
                    data_shaping_BW : OUT STD_LOGIC);
                END COMPONENT;
-             END lpp_top_lfr_pkg;
  No newline at end of file
+             END lpp_top_lfr_pkg;

lib/lpp/lpp_top_lfr/top_wf_picker.vhd +8 -2

                  cnv_clk  : IN  STD_LOGIC;
                  cnv_rstn : IN  STD_LOGIC;
                  --
-                 sample     : IN Samples14v(7 DOWNTO 0);
+                 sample_B   : IN Samples14v(2 DOWNTO 0);
+                 sample_E   : IN Samples14v(4 DOWNTO 0);
                  sample_val : IN STD_LOGIC;
                  -- AMBA AHB system signals
                CONSTANT ncycle_cnv_high : INTEGER := 40;
                CONSTANT ncycle_cnv      : INTEGER := 250;
-               SIGNAL   sample_s          : Samples(ChanelCount-1 DOWNTO 0);
+               SIGNAL  sample_s          : Samples(ChanelCount-1 DOWNTO 0);
+               SIGNAL  sample            :  Samples14v(7 DOWNTO 0);
              BEGIN
+               sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+               sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-               ready_matrix_f0_0             <= '0';
                ready_matrix_f0_1             <= '0';
                ready_matrix_f1               <= '0';

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