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Update DMA data (big endian)
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r368:aaed3c518959 (MINI-LFR) WFP_MS-0-1-13 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176
176
177 BEGIN -- beh
177 BEGIN -- beh
178
178
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180 -- CLK
180 -- CLK
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182
182
183 PROCESS(clk_50)
183 PROCESS(clk_50)
184 BEGIN
184 BEGIN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
186 clk_50_s <= NOT clk_50_s;
186 clk_50_s <= NOT clk_50_s;
187 END IF;
187 END IF;
188 END PROCESS;
188 END PROCESS;
189
189
190 PROCESS(clk_50_s)
190 PROCESS(clk_50_s)
191 BEGIN
191 BEGIN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
193 clk_25 <= NOT clk_25;
193 clk_25 <= NOT clk_25;
194 END IF;
194 END IF;
195 END PROCESS;
195 END PROCESS;
196
196
197 PROCESS(clk_49)
197 PROCESS(clk_49)
198 BEGIN
198 BEGIN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
200 clk_24 <= NOT clk_24;
200 clk_24 <= NOT clk_24;
201 END IF;
201 END IF;
202 END PROCESS;
202 END PROCESS;
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205
205
206 PROCESS (clk_25, reset)
206 PROCESS (clk_25, reset)
207 BEGIN -- PROCESS
207 BEGIN -- PROCESS
208 IF reset = '0' THEN -- asynchronous reset (active low)
208 IF reset = '0' THEN -- asynchronous reset (active low)
209 LED0 <= '0';
209 LED0 <= '0';
210 LED1 <= '0';
210 LED1 <= '0';
211 LED2 <= '0';
211 LED2 <= '0';
212 --IO1 <= '0';
212 --IO1 <= '0';
213 --IO2 <= '1';
213 --IO2 <= '1';
214 --IO3 <= '0';
214 --IO3 <= '0';
215 --IO4 <= '0';
215 --IO4 <= '0';
216 --IO5 <= '0';
216 --IO5 <= '0';
217 --IO6 <= '0';
217 --IO6 <= '0';
218 --IO7 <= '0';
218 --IO7 <= '0';
219 --IO8 <= '0';
219 --IO8 <= '0';
220 --IO9 <= '0';
220 --IO9 <= '0';
221 --IO10 <= '0';
221 --IO10 <= '0';
222 --IO11 <= '0';
222 --IO11 <= '0';
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
224 LED0 <= '0';
224 LED0 <= '0';
225 LED1 <= '1';
225 LED1 <= '1';
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
227 --IO1 <= '1';
227 --IO1 <= '1';
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
229 --IO3 <= ADC_SDO(0);
229 --IO3 <= ADC_SDO(0);
230 --IO4 <= ADC_SDO(1);
230 --IO4 <= ADC_SDO(1);
231 --IO5 <= ADC_SDO(2);
231 --IO5 <= ADC_SDO(2);
232 --IO6 <= ADC_SDO(3);
232 --IO6 <= ADC_SDO(3);
233 --IO7 <= ADC_SDO(4);
233 --IO7 <= ADC_SDO(4);
234 --IO8 <= ADC_SDO(5);
234 --IO8 <= ADC_SDO(5);
235 --IO9 <= ADC_SDO(6);
235 --IO9 <= ADC_SDO(6);
236 --IO10 <= ADC_SDO(7);
236 --IO10 <= ADC_SDO(7);
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
238 END IF;
238 END IF;
239 END PROCESS;
239 END PROCESS;
240
240
241 PROCESS (clk_24, reset)
241 PROCESS (clk_24, reset)
242 BEGIN -- PROCESS
242 BEGIN -- PROCESS
243 IF reset = '0' THEN -- asynchronous reset (active low)
243 IF reset = '0' THEN -- asynchronous reset (active low)
244 I00_s <= '0';
244 I00_s <= '0';
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
246 I00_s <= NOT I00_s ;
246 I00_s <= NOT I00_s ;
247 END IF;
247 END IF;
248 END PROCESS;
248 END PROCESS;
249 -- IO0 <= I00_s;
249 -- IO0 <= I00_s;
250
250
251 --UARTs
251 --UARTs
252 nCTS1 <= '1';
252 nCTS1 <= '1';
253 nCTS2 <= '1';
253 nCTS2 <= '1';
254 nDCD2 <= '1';
254 nDCD2 <= '1';
255
255
256 --EXT CONNECTOR
256 --EXT CONNECTOR
257
257
258 --SPACE WIRE
258 --SPACE WIRE
259
259
260 leon3_soc_1 : leon3_soc
260 leon3_soc_1 : leon3_soc
261 GENERIC MAP (
261 GENERIC MAP (
262 fabtech => apa3e,
262 fabtech => apa3e,
263 memtech => apa3e,
263 memtech => apa3e,
264 padtech => inferred,
264 padtech => inferred,
265 clktech => inferred,
265 clktech => inferred,
266 disas => 0,
266 disas => 0,
267 dbguart => 0,
267 dbguart => 0,
268 pclow => 2,
268 pclow => 2,
269 clk_freq => 25000,
269 clk_freq => 25000,
270 NB_CPU => 1,
270 NB_CPU => 1,
271 ENABLE_FPU => 1,
271 ENABLE_FPU => 1,
272 FPU_NETLIST => 0,
272 FPU_NETLIST => 0,
273 ENABLE_DSU => 1,
273 ENABLE_DSU => 1,
274 ENABLE_AHB_UART => 1,
274 ENABLE_AHB_UART => 1,
275 ENABLE_APB_UART => 1,
275 ENABLE_APB_UART => 1,
276 ENABLE_IRQMP => 1,
276 ENABLE_IRQMP => 1,
277 ENABLE_GPT => 1,
277 ENABLE_GPT => 1,
278 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_MASTER => NB_AHB_MASTER,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
280 NB_APB_SLAVE => NB_APB_SLAVE)
280 NB_APB_SLAVE => NB_APB_SLAVE)
281 PORT MAP (
281 PORT MAP (
282 clk => clk_25,
282 clk => clk_25,
283 reset => reset,
283 reset => reset,
284 errorn => errorn,
284 errorn => errorn,
285 ahbrxd => TXD1,
285 ahbrxd => TXD1,
286 ahbtxd => RXD1,
286 ahbtxd => RXD1,
287 urxd1 => TXD2,
287 urxd1 => TXD2,
288 utxd1 => RXD2,
288 utxd1 => RXD2,
289 address => SRAM_A,
289 address => SRAM_A,
290 data => SRAM_DQ,
290 data => SRAM_DQ,
291 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE0 => SRAM_nBE(0),
292 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE1 => SRAM_nBE(1),
293 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE2 => SRAM_nBE(2),
294 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_BE3 => SRAM_nBE(3),
295 nSRAM_WE => SRAM_nWE,
295 nSRAM_WE => SRAM_nWE,
296 nSRAM_CE => SRAM_CE,
296 nSRAM_CE => SRAM_CE,
297 nSRAM_OE => SRAM_nOE,
297 nSRAM_OE => SRAM_nOE,
298
298
299 apbi_ext => apbi_ext,
299 apbi_ext => apbi_ext,
300 apbo_ext => apbo_ext,
300 apbo_ext => apbo_ext,
301 ahbi_s_ext => ahbi_s_ext,
301 ahbi_s_ext => ahbi_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
303 ahbi_m_ext => ahbi_m_ext,
303 ahbi_m_ext => ahbi_m_ext,
304 ahbo_m_ext => ahbo_m_ext);
304 ahbo_m_ext => ahbo_m_ext);
305
305
306 -------------------------------------------------------------------------------
306 -------------------------------------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 apb_lfr_time_management_1 : apb_lfr_time_management
309 apb_lfr_time_management_1 : apb_lfr_time_management
310 GENERIC MAP (
310 GENERIC MAP (
311 pindex => 6,
311 pindex => 6,
312 paddr => 6,
312 paddr => 6,
313 pmask => 16#fff#,
313 pmask => 16#fff#,
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
316 PORT MAP (
316 PORT MAP (
317 clk25MHz => clk_25,
317 clk25MHz => clk_25,
318 clk24_576MHz => clk_24, -- 49.152MHz/2
318 clk24_576MHz => clk_24, -- 49.152MHz/2
319 resetn => reset,
319 resetn => reset,
320 grspw_tick => swno.tickout,
320 grspw_tick => swno.tickout,
321 apbi => apbi_ext,
321 apbi => apbi_ext,
322 apbo => apbo_ext(6),
322 apbo => apbo_ext(6),
323 coarse_time => coarse_time,
323 coarse_time => coarse_time,
324 fine_time => fine_time);
324 fine_time => fine_time);
325
325
326 -----------------------------------------------------------------------
326 -----------------------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329
329
330 SPW_EN <= '1';
330 SPW_EN <= '1';
331
331
332 spw_clk <= clk_50_s;
332 spw_clk <= clk_50_s;
333 spw_rxtxclk <= spw_clk;
333 spw_rxtxclk <= spw_clk;
334 spw_rxclkn <= NOT spw_rxtxclk;
334 spw_rxclkn <= NOT spw_rxtxclk;
335
335
336 -- PADS for SPW1
336 -- PADS for SPW1
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_SIN, stmp(0));
340 PORT MAP (SPW_NOM_SIN, stmp(0));
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
345 -- PADS FOR SPW2
345 -- PADS FOR SPW2
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 PORT MAP (SPW_RED_SIN, dtmp(1));
347 PORT MAP (SPW_RED_SIN, dtmp(1));
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_DIN, stmp(1));
349 PORT MAP (SPW_RED_DIN, stmp(1));
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
354
354
355 -- GRSPW PHY
355 -- GRSPW PHY
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
358 spw_phy0 : grspw_phy
358 spw_phy0 : grspw_phy
359 GENERIC MAP(
359 GENERIC MAP(
360 tech => apa3e,
360 tech => apa3e,
361 rxclkbuftype => 1,
361 rxclkbuftype => 1,
362 scantest => 0)
362 scantest => 0)
363 PORT MAP(
363 PORT MAP(
364 rxrst => swno.rxrst,
364 rxrst => swno.rxrst,
365 di => dtmp(j),
365 di => dtmp(j),
366 si => stmp(j),
366 si => stmp(j),
367 rxclko => spw_rxclk(j),
367 rxclko => spw_rxclk(j),
368 do => swni.d(j),
368 do => swni.d(j),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
371 END GENERATE spw_inputloop;
371 END GENERATE spw_inputloop;
372
372
373 -- SPW core
373 -- SPW core
374 sw0 : grspwm GENERIC MAP(
374 sw0 : grspwm GENERIC MAP(
375 tech => apa3e,
375 tech => apa3e,
376 hindex => 1,
376 hindex => 1,
377 pindex => 5,
377 pindex => 5,
378 paddr => 5,
378 paddr => 5,
379 pirq => 11,
379 pirq => 11,
380 sysfreq => 25000, -- CPU_FREQ
380 sysfreq => 25000, -- CPU_FREQ
381 rmap => 1,
381 rmap => 1,
382 rmapcrc => 1,
382 rmapcrc => 1,
383 fifosize1 => 16,
383 fifosize1 => 16,
384 fifosize2 => 16,
384 fifosize2 => 16,
385 rxclkbuftype => 1,
385 rxclkbuftype => 1,
386 rxunaligned => 0,
386 rxunaligned => 0,
387 rmapbufs => 4,
387 rmapbufs => 4,
388 ft => 0,
388 ft => 0,
389 netlist => 0,
389 netlist => 0,
390 ports => 2,
390 ports => 2,
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
392 memtech => apa3e,
392 memtech => apa3e,
393 destkey => 2,
393 destkey => 2,
394 spwcore => 1
394 spwcore => 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
398 )
398 )
399 PORT MAP(reset, clk_25, spw_rxclk(0),
399 PORT MAP(reset, clk_25, spw_rxclk(0),
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
402 swni, swno);
402 swni, swno);
403
403
404 swni.tickin <= '0';
404 swni.tickin <= '0';
405 swni.rmapen <= '1';
405 swni.rmapen <= '1';
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
407 swni.tickinraw <= '0';
407 swni.tickinraw <= '0';
408 swni.timein <= (OTHERS => '0');
408 swni.timein <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
411
411
412 -------------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 lpp_lfr_1 : lpp_lfr
415 lpp_lfr_1 : lpp_lfr
416 GENERIC MAP (
416 GENERIC MAP (
417 Mem_use => use_RAM,
417 Mem_use => use_RAM,
418 nb_data_by_buffer_size => 32,
418 nb_data_by_buffer_size => 32,
419 nb_word_by_buffer_size => 30,
419 nb_word_by_buffer_size => 30,
420 nb_snapshot_param_size => 32,
420 nb_snapshot_param_size => 32,
421 delta_vector_size => 32,
421 delta_vector_size => 32,
422 delta_vector_size_f0_2 => 7, -- log2(96)
422 delta_vector_size_f0_2 => 7, -- log2(96)
423 pindex => 15,
423 pindex => 15,
424 paddr => 15,
424 paddr => 15,
425 pmask => 16#fff#,
425 pmask => 16#fff#,
426 pirq_ms => 6,
426 pirq_ms => 6,
427 pirq_wfp => 14,
427 pirq_wfp => 14,
428 hindex => 2,
428 hindex => 2,
429 top_lfr_version => X"00010C") -- aa.bb.cc version
429 top_lfr_version => X"00010D") -- aa.bb.cc version
430 PORT MAP (
430 PORT MAP (
431 clk => clk_25,
431 clk => clk_25,
432 rstn => reset,
432 rstn => reset,
433 sample_B => sample_s(2 DOWNTO 0),
433 sample_B => sample_s(2 DOWNTO 0),
434 sample_E => sample_s(7 DOWNTO 3),
434 sample_E => sample_s(7 DOWNTO 3),
435 sample_val => sample_val,
435 sample_val => sample_val,
436 apbi => apbi_ext,
436 apbi => apbi_ext,
437 apbo => apbo_ext(15),
437 apbo => apbo_ext(15),
438 ahbi => ahbi_m_ext,
438 ahbi => ahbi_m_ext,
439 ahbo => ahbo_m_ext(2),
439 ahbo => ahbo_m_ext(2),
440 coarse_time => coarse_time,
440 coarse_time => coarse_time,
441 fine_time => fine_time,
441 fine_time => fine_time,
442 data_shaping_BW => bias_fail_sw_sig,
442 data_shaping_BW => bias_fail_sw_sig,
443 observation_reg => observation_reg);
443 observation_reg => observation_reg);
444
444
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
446 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
447 END GENERATE all_sample;
447 END GENERATE all_sample;
448
448
449
449
450
450
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
452 GENERIC MAP(
452 GENERIC MAP(
453 ChannelCount => 8,
453 ChannelCount => 8,
454 SampleNbBits => 14,
454 SampleNbBits => 14,
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
457 PORT MAP (
457 PORT MAP (
458 -- CONV
458 -- CONV
459 cnv_clk => clk_24,
459 cnv_clk => clk_24,
460 cnv_rstn => reset,
460 cnv_rstn => reset,
461 cnv => ADC_nCS_sig,
461 cnv => ADC_nCS_sig,
462 -- DATA
462 -- DATA
463 clk => clk_25,
463 clk => clk_25,
464 rstn => reset,
464 rstn => reset,
465 sck => ADC_CLK_sig,
465 sck => ADC_CLK_sig,
466 sdo => ADC_SDO_sig,
466 sdo => ADC_SDO_sig,
467 -- SAMPLE
467 -- SAMPLE
468 sample => sample,
468 sample => sample,
469 sample_val => sample_val);
469 sample_val => sample_val);
470
470
471 --IO10 <= ADC_SDO_sig(5);
471 --IO10 <= ADC_SDO_sig(5);
472 --IO9 <= ADC_SDO_sig(4);
472 --IO9 <= ADC_SDO_sig(4);
473 --IO8 <= ADC_SDO_sig(3);
473 --IO8 <= ADC_SDO_sig(3);
474
474
475 ADC_nCS <= ADC_nCS_sig;
475 ADC_nCS <= ADC_nCS_sig;
476 ADC_CLK <= ADC_CLK_sig;
476 ADC_CLK <= ADC_CLK_sig;
477 ADC_SDO_sig <= ADC_SDO;
477 ADC_SDO_sig <= ADC_SDO;
478
478
479 ----------------------------------------------------------------------
479 ----------------------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
481 ----------------------------------------------------------------------
481 ----------------------------------------------------------------------
482
482
483 grgpio0 : grgpio
483 grgpio0 : grgpio
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
486
486
487 --pio_pad_0 : iopad
487 --pio_pad_0 : iopad
488 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- GENERIC MAP (tech => CFG_PADTECH)
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
490 --pio_pad_1 : iopad
490 --pio_pad_1 : iopad
491 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
493 --pio_pad_2 : iopad
493 --pio_pad_2 : iopad
494 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
496 --pio_pad_3 : iopad
496 --pio_pad_3 : iopad
497 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
499 --pio_pad_4 : iopad
499 --pio_pad_4 : iopad
500 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
502 --pio_pad_5 : iopad
502 --pio_pad_5 : iopad
503 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
505 --pio_pad_6 : iopad
505 --pio_pad_6 : iopad
506 -- GENERIC MAP (tech => CFG_PADTECH)
506 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
508 --pio_pad_7 : iopad
508 --pio_pad_7 : iopad
509 -- GENERIC MAP (tech => CFG_PADTECH)
509 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
511
511
512 PROCESS (clk_25, reset)
512 PROCESS (clk_25, reset)
513 BEGIN -- PROCESS
513 BEGIN -- PROCESS
514 IF reset = '0' THEN -- asynchronous reset (active low)
514 IF reset = '0' THEN -- asynchronous reset (active low)
515 IO0 <= '0';
515 IO0 <= '0';
516 IO1 <= '0';
516 IO1 <= '0';
517 IO2 <= '0';
517 IO2 <= '0';
518 IO3 <= '0';
518 IO3 <= '0';
519 IO4 <= '0';
519 IO4 <= '0';
520 IO5 <= '0';
520 IO5 <= '0';
521 IO6 <= '0';
521 IO6 <= '0';
522 IO7 <= '0';
522 IO7 <= '0';
523 IO8 <= '0';
523 IO8 <= '0';
524 IO9 <= '0';
524 IO9 <= '0';
525 IO10 <= '0';
525 IO10 <= '0';
526 IO11 <= '0';
526 IO11 <= '0';
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
528 CASE gpioo.dout(1 DOWNTO 0) IS
528 CASE gpioo.dout(1 DOWNTO 0) IS
529 WHEN "00" =>
529 WHEN "00" =>
530 IO0 <= observation_reg(0 );
530 IO0 <= observation_reg(0 );
531 IO1 <= observation_reg(1 );
531 IO1 <= observation_reg(1 );
532 IO2 <= observation_reg(2 );
532 IO2 <= observation_reg(2 );
533 IO3 <= observation_reg(3 );
533 IO3 <= observation_reg(3 );
534 IO4 <= observation_reg(4 );
534 IO4 <= observation_reg(4 );
535 IO5 <= observation_reg(5 );
535 IO5 <= observation_reg(5 );
536 IO6 <= observation_reg(6 );
536 IO6 <= observation_reg(6 );
537 IO7 <= observation_reg(7 );
537 IO7 <= observation_reg(7 );
538 IO8 <= observation_reg(8 );
538 IO8 <= observation_reg(8 );
539 IO9 <= observation_reg(9 );
539 IO9 <= observation_reg(9 );
540 IO10 <= observation_reg(10);
540 IO10 <= observation_reg(10);
541 IO11 <= observation_reg(11);
541 IO11 <= observation_reg(11);
542 WHEN "01" =>
542 WHEN "01" =>
543 IO0 <= observation_reg(0 + 12);
543 IO0 <= observation_reg(0 + 12);
544 IO1 <= observation_reg(1 + 12);
544 IO1 <= observation_reg(1 + 12);
545 IO2 <= observation_reg(2 + 12);
545 IO2 <= observation_reg(2 + 12);
546 IO3 <= observation_reg(3 + 12);
546 IO3 <= observation_reg(3 + 12);
547 IO4 <= observation_reg(4 + 12);
547 IO4 <= observation_reg(4 + 12);
548 IO5 <= observation_reg(5 + 12);
548 IO5 <= observation_reg(5 + 12);
549 IO6 <= observation_reg(6 + 12);
549 IO6 <= observation_reg(6 + 12);
550 IO7 <= observation_reg(7 + 12);
550 IO7 <= observation_reg(7 + 12);
551 IO8 <= observation_reg(8 + 12);
551 IO8 <= observation_reg(8 + 12);
552 IO9 <= observation_reg(9 + 12);
552 IO9 <= observation_reg(9 + 12);
553 IO10 <= observation_reg(10 + 12);
553 IO10 <= observation_reg(10 + 12);
554 IO11 <= observation_reg(11 + 12);
554 IO11 <= observation_reg(11 + 12);
555 WHEN "10" =>
555 WHEN "10" =>
556 IO0 <= observation_reg(0 + 12 + 12);
556 IO0 <= observation_reg(0 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
564 IO8 <= '0';
564 IO8 <= '0';
565 IO9 <= '0';
565 IO9 <= '0';
566 IO10 <= '0';
566 IO10 <= '0';
567 IO11 <= '0';
567 IO11 <= '0';
568 WHEN "11" =>
568 WHEN "11" =>
569 IO0 <= '0';
569 IO0 <= '0';
570 IO1 <= '0';
570 IO1 <= '0';
571 IO2 <= '0';
571 IO2 <= '0';
572 IO3 <= '0';
572 IO3 <= '0';
573 IO4 <= '0';
573 IO4 <= '0';
574 IO5 <= '0';
574 IO5 <= '0';
575 IO6 <= '0';
575 IO6 <= '0';
576 IO7 <= '0';
576 IO7 <= '0';
577 IO8 <= '0';
577 IO8 <= '0';
578 IO9 <= '0';
578 IO9 <= '0';
579 IO10 <= '0';
579 IO10 <= '0';
580 IO11 <= '0';
580 IO11 <= '0';
581 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
582 END CASE;
582 END CASE;
583
583
584 END IF;
584 END IF;
585 END PROCESS;
585 END PROCESS;
586
586
587 END beh;
587 END beh;
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@@ -1,205 +1,206
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_singleOrBurst IS
45 ENTITY lpp_dma_singleOrBurst IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
48 hindex : INTEGER := 2
49 );
49 );
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
54 --
55 run : IN STD_LOGIC;
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 send : IN STD_LOGIC;
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 --
66 --
67 debug_dmaout_okay : OUT STD_LOGIC
67 debug_dmaout_okay : OUT STD_LOGIC
68
68
69 );
69 );
70 END;
70 END;
71
71
72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
73 -----------------------------------------------------------------------------
73 -----------------------------------------------------------------------------
74 SIGNAL DMAIn : DMA_In_Type;
74 SIGNAL DMAIn : DMA_In_Type;
75 SIGNAL DMAOut : DMA_OUt_Type;
75 SIGNAL DMAOut : DMA_OUt_Type;
76 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
78 -- CONTROL
78 -- CONTROL
79 SIGNAL single_send : STD_LOGIC;
79 SIGNAL single_send : STD_LOGIC;
80 SIGNAL burst_send : STD_LOGIC;
80 SIGNAL burst_send : STD_LOGIC;
81
81
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 -- SEND SINGLE MODULE
83 -- SEND SINGLE MODULE
84 SIGNAL single_dmai : DMA_In_Type;
84 SIGNAL single_dmai : DMA_In_Type;
85
85
86 SIGNAL single_send_ok : STD_LOGIC;
86 SIGNAL single_send_ok : STD_LOGIC;
87 SIGNAL single_send_ko : STD_LOGIC;
87 SIGNAL single_send_ko : STD_LOGIC;
88 SIGNAL single_ren : STD_LOGIC;
88 SIGNAL single_ren : STD_LOGIC;
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 -- SEND SINGLE MODULE
90 -- SEND SINGLE MODULE
91 SIGNAL burst_dmai : DMA_In_Type;
91 SIGNAL burst_dmai : DMA_In_Type;
92
92
93 SIGNAL burst_send_ok : STD_LOGIC;
93 SIGNAL burst_send_ok : STD_LOGIC;
94 SIGNAL burst_send_ko : STD_LOGIC;
94 SIGNAL burst_send_ko : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
99 -- \/ -- 20/02/2014 -- JC Pellion
99 -- \/ -- 20/02/2014 -- JC Pellion
100 SIGNAL send_reg : STD_LOGIC;
100 SIGNAL send_reg : STD_LOGIC;
101 SIGNAL send_s : STD_LOGIC;
101 SIGNAL send_s : STD_LOGIC;
102 -- /\ --
102 -- /\ --
103
103
104
104
105 BEGIN
105 BEGIN
106
106
107 debug_dmaout_okay <= DMAOut.OKAY;
107 debug_dmaout_okay <= DMAOut.OKAY;
108
108
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -- DMA to AHB interface
111 -- DMA to AHB interface
112 DMA2AHB_1 : DMA2AHB
112 DMA2AHB_1 : DMA2AHB
113 GENERIC MAP (
113 GENERIC MAP (
114 hindex => hindex,
114 hindex => hindex,
115 vendorid => VENDOR_LPP,
115 vendorid => VENDOR_LPP,
116 deviceid => 10,
116 deviceid => 10,
117 version => 0,
117 version => 0,
118 syncrst => 1,
118 syncrst => 1,
119 boundary => 1) -- FIX 11/01/2013
119 boundary => 1) -- FIX 11/01/2013
120 PORT MAP (
120 PORT MAP (
121 HCLK => HCLK,
121 HCLK => HCLK,
122 HRESETn => HRESETn,
122 HRESETn => HRESETn,
123 DMAIn => DMAIn,
123 DMAIn => DMAIn,
124 DMAOut => DMAOut,
124 DMAOut => DMAOut,
125
125
126 AHBIn => AHB_Master_In,
126 AHBIn => AHB_Master_In,
127 AHBOut => AHB_Master_Out);
127 AHBOut => AHB_Master_Out);
128 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
129
129
130 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
131 -- \/ -- 20/02/2014 -- JC Pellion
131 -- \/ -- 20/02/2014 -- JC Pellion
132 PROCESS (HCLK, HRESETn)
132 PROCESS (HCLK, HRESETn)
133 BEGIN
133 BEGIN
134 IF HRESETn = '0' THEN
134 IF HRESETn = '0' THEN
135 send_reg <= '0';
135 send_reg <= '0';
136 ELSIF HCLK'event AND HCLK = '1' THEN
136 ELSIF HCLK'event AND HCLK = '1' THEN
137 send_reg <= send;
137 send_reg <= send;
138 END IF;
138 END IF;
139 END PROCESS;
139 END PROCESS;
140 send_s <= send_reg;
140 send_s <= send_reg;
141
141
142 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
142 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
143 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
143 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
144 -- /\ --
144 -- /\ --
145
145
146 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
146 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
147
147
148 -- TODO : verifier
148 -- TODO : verifier
149 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
149 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
150 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
150 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
151 -- burst_send_ok OR burst_send_ko;
151 -- burst_send_ok OR burst_send_ko;
152
152
153 --ren <= burst_ren WHEN valid_burst = '1' ELSE
153 --ren <= burst_ren WHEN valid_burst = '1' ELSE
154 -- NOT single_send_ok;
154 -- NOT single_send_ok;
155 --ren <= burst_ren AND single_ren;
155 --ren <= burst_ren AND single_ren;
156
156
157 -- \/ JC - 20/01/2014 \/
157 -- \/ JC - 20/01/2014 \/
158 ren <= burst_ren WHEN valid_burst = '1' ELSE
158 ren <= burst_ren WHEN valid_burst = '1' ELSE
159 single_ren;
159 single_ren;
160
160
161
161
162 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
162 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
163 -- '1';
163 -- '1';
164 -- /\ JC - 20/01/2014 /\
164 -- /\ JC - 20/01/2014 /\
165
165
166 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
167 -- SEND 1 word by DMA
167 -- SEND 1 word by DMA
168 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
169 lpp_dma_send_1word_1 : lpp_dma_send_1word
169 lpp_dma_send_1word_1 : lpp_dma_send_1word
170 PORT MAP (
170 PORT MAP (
171 HCLK => HCLK,
171 HCLK => HCLK,
172 HRESETn => HRESETn,
172 HRESETn => HRESETn,
173 DMAIn => single_dmai,
173 DMAIn => single_dmai,
174 DMAOut => DMAOut,
174 DMAOut => DMAOut,
175
175
176 send => single_send,
176 send => single_send,
177 address => address,
177 address => address,
178 data => data_2_halfword,
178 data => data_2_halfword,
179 ren => single_ren,
179 ren => single_ren,
180
180
181 send_ok => single_send_ok, -- TODO
181 send_ok => single_send_ok, -- TODO
182 send_ko => single_send_ko -- TODO
182 send_ko => single_send_ko -- TODO
183 );
183 );
184
184
185 -----------------------------------------------------------------------------
185 -----------------------------------------------------------------------------
186 -- SEND 16 word by DMA (in burst mode)
186 -- SEND 16 word by DMA (in burst mode)
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
188 --data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
189 data_2_halfword(31 DOWNTO 0) <= data(31 DOWNTO 0);
189
190
190 lpp_dma_send_16word_1 : lpp_dma_send_16word
191 lpp_dma_send_16word_1 : lpp_dma_send_16word
191 PORT MAP (
192 PORT MAP (
192 HCLK => HCLK,
193 HCLK => HCLK,
193 HRESETn => HRESETn,
194 HRESETn => HRESETn,
194 DMAIn => burst_dmai,
195 DMAIn => burst_dmai,
195 DMAOut => DMAOut,
196 DMAOut => DMAOut,
196
197
197 send => burst_send,
198 send => burst_send,
198 address => address,
199 address => address,
199 data => data_2_halfword,
200 data => data_2_halfword,
200 ren => burst_ren,
201 ren => burst_ren,
201
202
202 send_ok => burst_send_ok,
203 send_ok => burst_send_ok,
203 send_ko => burst_send_ko);
204 send_ko => burst_send_ko);
204
205
205 END Behavioral;
206 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,295 +1,295
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 LIBRARY techmap;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
38 USE techmap.gencomp.ALL;
39
39
40
40
41 ENTITY lpp_lfr_ms_fsmdma IS
41 ENTITY lpp_lfr_ms_fsmdma IS
42 PORT (
42 PORT (
43 -- AMBA AHB system signals
43 -- AMBA AHB system signals
44 HCLK : IN STD_ULOGIC;
44 HCLK : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
46
46
47 ---------------------------------------------------------------------------
47 ---------------------------------------------------------------------------
48 -- FIFO - IN
48 -- FIFO - IN
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
53 fifo_empty : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55
55
56 ---------------------------------------------------------------------------
56 ---------------------------------------------------------------------------
57 -- DMA - OUT
57 -- DMA - OUT
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_valid : OUT STD_LOGIC;
60 dma_valid : OUT STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
62 dma_ren : IN STD_LOGIC;
62 dma_ren : IN STD_LOGIC;
63 dma_done : IN STD_LOGIC;
63 dma_done : IN STD_LOGIC;
64
64
65 ---------------------------------------------------------------------------
65 ---------------------------------------------------------------------------
66 -- Reg out
66 -- Reg out
67 ready_matrix_f0 : OUT STD_LOGIC;
67 ready_matrix_f0 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
70
70
71 error_bad_component_error : OUT STD_LOGIC;
71 error_bad_component_error : OUT STD_LOGIC;
72 error_buffer_full : OUT STD_LOGIC;
72 error_buffer_full : OUT STD_LOGIC;
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- Reg In
75 -- Reg In
76 status_ready_matrix_f0 : IN STD_LOGIC;
76 status_ready_matrix_f0 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85
85
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
89
89
90 );
90 );
91 END;
91 END;
92
92
93 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
93 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
94 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
95 TYPE state_DMAWriteBurst IS (IDLE,
95 TYPE state_DMAWriteBurst IS (IDLE,
96 CHECK_COMPONENT_TYPE,
96 CHECK_COMPONENT_TYPE,
97 WRITE_COARSE_TIME,
97 WRITE_COARSE_TIME,
98 WRITE_FINE_TIME,
98 WRITE_FINE_TIME,
99 TRASH_FIFO,
99 TRASH_FIFO,
100 SEND_DATA,
100 SEND_DATA,
101 WAIT_DATA_ACK
101 WAIT_DATA_ACK
102 );
102 );
103 SIGNAL state : state_DMAWriteBurst;
103 SIGNAL state : state_DMAWriteBurst;
104
104
105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SIGNAL header_check_ok : STD_LOGIC;
108 SIGNAL header_check_ok : STD_LOGIC;
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
113
114 SIGNAL component_send : STD_LOGIC;
114 SIGNAL component_send : STD_LOGIC;
115 SIGNAL component_send_ok : STD_LOGIC;
115 SIGNAL component_send_ok : STD_LOGIC;
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 SIGNAL fifo_ren_trash : STD_LOGIC;
117 SIGNAL fifo_ren_trash : STD_LOGIC;
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 SIGNAL log_empty_fifo : STD_LOGIC;
122 SIGNAL log_empty_fifo : STD_LOGIC;
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
124
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
126 BEGIN
126 BEGIN
127
127
128 debug_reg <= debug_reg_s;
128 debug_reg <= debug_reg_s;
129
129
130
130
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
134 '0';
134 '0';
135
135
136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
138 '1' WHEN component_type = component_type_pre + "0001" ELSE
138 '1' WHEN component_type = component_type_pre + "0001" ELSE
139 '0';
139 '0';
140
140
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
144 (OTHERS => '0');
144 (OTHERS => '0');
145
145
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
147 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
148 -- DMA control
148 -- DMA control
149 -----------------------------------------------------------------------------
149 -----------------------------------------------------------------------------
150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
151 BEGIN
151 BEGIN
152 IF HRESETn = '0' THEN
152 IF HRESETn = '0' THEN
153 matrix_type <= (OTHERS => '0');
153 matrix_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
155 state <= IDLE;
155 state <= IDLE;
156 ready_matrix_f0 <= '0';
156 ready_matrix_f0 <= '0';
157 ready_matrix_f1 <= '0';
157 ready_matrix_f1 <= '0';
158 ready_matrix_f2 <= '0';
158 ready_matrix_f2 <= '0';
159 error_bad_component_error <= '0';
159 error_bad_component_error <= '0';
160 error_buffer_full <= '0'; -- TODO
160 error_buffer_full <= '0'; -- TODO
161 component_type_pre <= "0000";
161 component_type_pre <= "0000";
162 fifo_ren_trash <= '1';
162 fifo_ren_trash <= '1';
163 component_send <= '0';
163 component_send <= '0';
164 address <= (OTHERS => '0');
164 address <= (OTHERS => '0');
165
165
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
171
171
172 log_empty_fifo <= '0';
172 log_empty_fifo <= '0';
173
173
174 matrix_time_f0 <= (OTHERS => '0');
174 matrix_time_f0 <= (OTHERS => '0');
175 matrix_time_f1 <= (OTHERS => '0');
175 matrix_time_f1 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
177
177
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
179 --
179 --
180 debug_reg_s(3) <= status_ready_matrix_f0;
180 debug_reg_s(3) <= status_ready_matrix_f0;
181 debug_reg_s(4) <= status_ready_matrix_f0;
181 debug_reg_s(4) <= status_ready_matrix_f1;
182 debug_reg_s(5) <= status_ready_matrix_f0;
182 debug_reg_s(5) <= status_ready_matrix_f2;
183 debug_reg_s(6) <= '0';
183 debug_reg_s(6) <= '0';
184 debug_reg_s(7) <= '0';
184 debug_reg_s(7) <= '0';
185 debug_reg_s(8) <= '0';
185 debug_reg_s(8) <= '0';
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
187 debug_reg_s(14 DOWNTO 11) <= component_type;
187 debug_reg_s(14 DOWNTO 11) <= component_type;
188
188
189 --
189 --
190
190
191
191
192
192
193 ready_matrix_f0 <= '0';
193 ready_matrix_f0 <= '0';
194 ready_matrix_f1 <= '0';
194 ready_matrix_f1 <= '0';
195 ready_matrix_f2 <= '0';
195 ready_matrix_f2 <= '0';
196 error_bad_component_error <= '0';
196 error_bad_component_error <= '0';
197 error_buffer_full <= '0';
197 error_buffer_full <= '0';
198
198
199 CASE state IS
199 CASE state IS
200 WHEN IDLE =>
200 WHEN IDLE =>
201 debug_reg_s(2 DOWNTO 0) <= "000";
201 debug_reg_s(2 DOWNTO 0) <= "000";
202 IF fifo_empty = '0' THEN
202 IF fifo_empty = '0' THEN
203 state <= CHECK_COMPONENT_TYPE;
203 state <= CHECK_COMPONENT_TYPE;
204 matrix_type <= fifo_matrix_type;
204 matrix_type <= fifo_matrix_type;
205 component_type <= fifo_matrix_component;
205 component_type <= fifo_matrix_component;
206 component_type_pre <= component_type;
206 component_type_pre <= component_type;
207 END IF;
207 END IF;
208
208
209 log_empty_fifo <= '0';
209 log_empty_fifo <= '0';
210
210
211 WHEN CHECK_COMPONENT_TYPE =>
211 WHEN CHECK_COMPONENT_TYPE =>
212 debug_reg_s(2 DOWNTO 0) <= "001";
212 debug_reg_s(2 DOWNTO 0) <= "001";
213
213
214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
215 IF component_type = "0000" THEN
215 IF component_type = "0000" THEN
216 address <= address_matrix;
216 address <= address_matrix;
217 CASE matrix_type IS
217 CASE matrix_type IS
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
221 WHEN OTHERS => NULL;
221 WHEN OTHERS => NULL;
222 END CASE;
222 END CASE;
223 component_send <= '1';
223 component_send <= '1';
224 END IF;
224 END IF;
225 state <= SEND_DATA;
225 state <= SEND_DATA;
226 --
226 --
227 ELSE
227 ELSE
228 error_bad_component_error <= NOT header_check_ok;
228 error_bad_component_error <= NOT header_check_ok;
229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
230 component_type_pre <= "0000";
230 component_type_pre <= "0000";
231 state <= TRASH_FIFO;
231 state <= TRASH_FIFO;
232 END IF;
232 END IF;
233
233
234 WHEN TRASH_FIFO =>
234 WHEN TRASH_FIFO =>
235 debug_reg_s(2 DOWNTO 0) <= "100";
235 debug_reg_s(2 DOWNTO 0) <= "100";
236
236
237 error_bad_component_error <= '0';
237 error_bad_component_error <= '0';
238 IF fifo_empty = '1' THEN
238 IF fifo_empty = '1' THEN
239 state <= IDLE;
239 state <= IDLE;
240 fifo_ren_trash <= '1';
240 fifo_ren_trash <= '1';
241 ELSE
241 ELSE
242 fifo_ren_trash <= '0';
242 fifo_ren_trash <= '0';
243 END IF;
243 END IF;
244
244
245 WHEN SEND_DATA =>
245 WHEN SEND_DATA =>
246 debug_reg_s(2 DOWNTO 0) <= "010";
246 debug_reg_s(2 DOWNTO 0) <= "010";
247
247
248 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
248 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
249 state <= IDLE;
249 state <= IDLE;
250 IF component_type = "1110" THEN
250 IF component_type = "1110" THEN
251 CASE matrix_type IS
251 CASE matrix_type IS
252 WHEN "00" =>
252 WHEN "00" =>
253 ready_matrix_f0 <= '1';
253 ready_matrix_f0 <= '1';
254 debug_reg_s(6) <= '1';
254 debug_reg_s(6) <= '1';
255 WHEN "01" =>
255 WHEN "01" =>
256 ready_matrix_f1 <= '1';
256 ready_matrix_f1 <= '1';
257 debug_reg_s(7) <= '1';
257 debug_reg_s(7) <= '1';
258 WHEN "10" =>
258 WHEN "10" =>
259 ready_matrix_f2 <= '1';
259 ready_matrix_f2 <= '1';
260 debug_reg_s(8) <= '1';
260 debug_reg_s(8) <= '1';
261 WHEN OTHERS => NULL;
261 WHEN OTHERS => NULL;
262 END CASE;
262 END CASE;
263 END IF;
263 END IF;
264 ELSE
264 ELSE
265 component_send <= '1';
265 component_send <= '1';
266 address <= address;
266 address <= address;
267 state <= WAIT_DATA_ACK;
267 state <= WAIT_DATA_ACK;
268 END IF;
268 END IF;
269
269
270 WHEN WAIT_DATA_ACK =>
270 WHEN WAIT_DATA_ACK =>
271 log_empty_fifo <= fifo_empty OR log_empty_fifo;
271 log_empty_fifo <= fifo_empty OR log_empty_fifo;
272
272
273 debug_reg_s(2 DOWNTO 0) <= "011";
273 debug_reg_s(2 DOWNTO 0) <= "011";
274
274
275 component_send <= '0';
275 component_send <= '0';
276 IF component_send_ok = '1' THEN
276 IF component_send_ok = '1' THEN
277 address <= address + 64;
277 address <= address + 64;
278 state <= SEND_DATA;
278 state <= SEND_DATA;
279 END IF;
279 END IF;
280
280
281 WHEN OTHERS => NULL;
281 WHEN OTHERS => NULL;
282 END CASE;
282 END CASE;
283
283
284 END IF;
284 END IF;
285 END PROCESS DMAWriteFSM_p;
285 END PROCESS DMAWriteFSM_p;
286
286
287 dma_valid_burst <= component_send;
287 dma_valid_burst <= component_send;
288 dma_valid <= '0';
288 dma_valid <= '0';
289 dma_data <= fifo_data;
289 dma_data <= fifo_data;
290 dma_addr <= address;
290 dma_addr <= address;
291 fifo_ren <= dma_ren AND fifo_ren_trash;
291 fifo_ren <= dma_ren AND fifo_ren_trash;
292
292
293 component_send_ok <= dma_done;
293 component_send_ok <= dma_done;
294
294
295 END Behavioral;
295 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,525 +1,558
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
40
40
41 GENERIC (
41 GENERIC (
42 tech : INTEGER := inferred;
42 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
43 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
44 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
47 delta_vector_size : INTEGER := 20;
47 delta_vector_size : INTEGER := 20;
48 delta_vector_size_f0_2 : INTEGER := 3);
48 delta_vector_size_f0_2 : INTEGER := 3);
49
49
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53
53
54 ---- AMBA AHB Master Interface
54 ---- AMBA AHB Master Interface
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57
57
58 --config
58 --config
59 reg_run : IN STD_LOGIC;
59 reg_run : IN STD_LOGIC;
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
66
67 enable_f0 : IN STD_LOGIC;
67 enable_f0 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
71
71
72 burst_f0 : IN STD_LOGIC;
72 burst_f0 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
75
75
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 -- INPUT
84 -- INPUT
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
87
88 --f0
88 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
90 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
92 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
94 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
96 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
98 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
100 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
102 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104
104
105 ---------------------------------------------------------------------------
105 ---------------------------------------------------------------------------
106 -- OUTPUT
106 -- OUTPUT
107 --f0
107 --f0
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
110 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
113 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
116 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
119 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
122 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
125 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
128 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
131
131
132 ---------------------------------------------------------------------------
132 ---------------------------------------------------------------------------
133 --
133 --
134 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
134 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
135
135
136
136
137 ----debug SNAPSHOT OUT
137 ----debug SNAPSHOT OUT
138 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 --debug_f0_data_valid : OUT STD_LOGIC;
139 --debug_f0_data_valid : OUT STD_LOGIC;
140 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 --debug_f1_data_valid : OUT STD_LOGIC;
141 --debug_f1_data_valid : OUT STD_LOGIC;
142 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 --debug_f2_data_valid : OUT STD_LOGIC;
143 --debug_f2_data_valid : OUT STD_LOGIC;
144 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 --debug_f3_data_valid : OUT STD_LOGIC;
145 --debug_f3_data_valid : OUT STD_LOGIC;
146
146
147 ----debug FIFO IN
147 ----debug FIFO IN
148 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
149 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
150 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
151 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
152 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
153 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
154 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
154 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
155 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
156
156
157 );
157 );
158
158
159 END lpp_waveform;
159 END lpp_waveform;
160
160
161 ARCHITECTURE beh OF lpp_waveform IS
161 ARCHITECTURE beh OF lpp_waveform IS
162 SIGNAL start_snapshot_f0 : STD_LOGIC;
162 SIGNAL start_snapshot_f0 : STD_LOGIC;
163 SIGNAL start_snapshot_f1 : STD_LOGIC;
163 SIGNAL start_snapshot_f1 : STD_LOGIC;
164 SIGNAL start_snapshot_f2 : STD_LOGIC;
164 SIGNAL start_snapshot_f2 : STD_LOGIC;
165
165
166 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
166 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
167 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
167 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
168 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
168 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170
170
171 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175
171 SIGNAL data_f0_out_valid : STD_LOGIC;
176 SIGNAL data_f0_out_valid : STD_LOGIC;
172 SIGNAL data_f1_out_valid : STD_LOGIC;
177 SIGNAL data_f1_out_valid : STD_LOGIC;
173 SIGNAL data_f2_out_valid : STD_LOGIC;
178 SIGNAL data_f2_out_valid : STD_LOGIC;
174 SIGNAL data_f3_out_valid : STD_LOGIC;
179 SIGNAL data_f3_out_valid : STD_LOGIC;
175 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
180 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
176 --
181 --
177 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
191 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 --
195 --
191 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
196 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
197 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 --
200 --
196 SIGNAL run : STD_LOGIC;
201 SIGNAL run : STD_LOGIC;
197 --
202 --
198 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
203 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
199 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
204 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
200 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
205 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
201 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
206 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
202 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
207 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
203 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
208 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 --
210 --
206
211
207 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
212 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
208 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
211
216
212 --
217 --
213
218
214 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
220 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
216
221
217 BEGIN -- beh
222 BEGIN -- beh
218
223
219 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
220 -- DEBUG
225 -- DEBUG
221 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
222 PROCESS (clk, rstn)
227 PROCESS (clk, rstn)
223 BEGIN -- PROCESS
228 BEGIN -- PROCESS
224 IF rstn = '0' THEN -- asynchronous reset (active low)
229 IF rstn = '0' THEN -- asynchronous reset (active low)
225 observation_reg <= (OTHERS => '0');
230 observation_reg <= (OTHERS => '0');
226 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
231 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
227 observation_reg <= observation_reg_s;
232 observation_reg <= observation_reg_s;
228 END IF;
233 END IF;
229 END PROCESS;
234 END PROCESS;
230 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
235 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
231 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
236 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
232 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
237 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
233 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
238 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
234 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
239 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
235 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
240 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
236 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
237
242
238 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
243 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
239 GENERIC MAP (
244 GENERIC MAP (
240 delta_vector_size => delta_vector_size,
245 delta_vector_size => delta_vector_size,
241 delta_vector_size_f0_2 => delta_vector_size_f0_2
246 delta_vector_size_f0_2 => delta_vector_size_f0_2
242 )
247 )
243 PORT MAP (
248 PORT MAP (
244 clk => clk,
249 clk => clk,
245 rstn => rstn,
250 rstn => rstn,
246 reg_run => reg_run,
251 reg_run => reg_run,
247 reg_start_date => reg_start_date,
252 reg_start_date => reg_start_date,
248 reg_delta_snapshot => reg_delta_snapshot,
253 reg_delta_snapshot => reg_delta_snapshot,
249 reg_delta_f0 => reg_delta_f0,
254 reg_delta_f0 => reg_delta_f0,
250 reg_delta_f0_2 => reg_delta_f0_2,
255 reg_delta_f0_2 => reg_delta_f0_2,
251 reg_delta_f1 => reg_delta_f1,
256 reg_delta_f1 => reg_delta_f1,
252 reg_delta_f2 => reg_delta_f2,
257 reg_delta_f2 => reg_delta_f2,
253 coarse_time => coarse_time(30 DOWNTO 0),
258 coarse_time => coarse_time(30 DOWNTO 0),
254 data_f0_valid => data_f0_in_valid,
259 data_f0_valid => data_f0_in_valid,
255 data_f2_valid => data_f2_in_valid,
260 data_f2_valid => data_f2_in_valid,
256 start_snapshot_f0 => start_snapshot_f0,
261 start_snapshot_f0 => start_snapshot_f0,
257 start_snapshot_f1 => start_snapshot_f1,
262 start_snapshot_f1 => start_snapshot_f1,
258 start_snapshot_f2 => start_snapshot_f2,
263 start_snapshot_f2 => start_snapshot_f2,
259 wfp_on => run);
264 wfp_on => run);
260
265
261 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
266 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
262 GENERIC MAP (
267 GENERIC MAP (
263 data_size => data_size,
268 data_size => data_size,
264 nb_snapshot_param_size => nb_snapshot_param_size)
269 nb_snapshot_param_size => nb_snapshot_param_size)
265 PORT MAP (
270 PORT MAP (
266 clk => clk,
271 clk => clk,
267 rstn => rstn,
272 rstn => rstn,
268 run => run,
273 run => run,
269 enable => enable_f0,
274 enable => enable_f0,
270 burst_enable => burst_f0,
275 burst_enable => burst_f0,
271 nb_snapshot_param => nb_snapshot_param,
276 nb_snapshot_param => nb_snapshot_param,
272 start_snapshot => start_snapshot_f0,
277 start_snapshot => start_snapshot_f0,
273 data_in => data_f0_in,
278 data_in => data_f0_in,
274 data_in_valid => data_f0_in_valid,
279 data_in_valid => data_f0_in_valid,
275 data_out => data_f0_out,
280 data_out => data_f0_out,
276 data_out_valid => data_f0_out_valid);
281 data_out_valid => data_f0_out_valid);
277
282
278 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
283 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
279
284
280 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
285 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
281 GENERIC MAP (
286 GENERIC MAP (
282 data_size => data_size,
287 data_size => data_size,
283 nb_snapshot_param_size => nb_snapshot_param_size+1)
288 nb_snapshot_param_size => nb_snapshot_param_size+1)
284 PORT MAP (
289 PORT MAP (
285 clk => clk,
290 clk => clk,
286 rstn => rstn,
291 rstn => rstn,
287 run => run,
292 run => run,
288 enable => enable_f1,
293 enable => enable_f1,
289 burst_enable => burst_f1,
294 burst_enable => burst_f1,
290 nb_snapshot_param => nb_snapshot_param_more_one,
295 nb_snapshot_param => nb_snapshot_param_more_one,
291 start_snapshot => start_snapshot_f1,
296 start_snapshot => start_snapshot_f1,
292 data_in => data_f1_in,
297 data_in => data_f1_in,
293 data_in_valid => data_f1_in_valid,
298 data_in_valid => data_f1_in_valid,
294 data_out => data_f1_out,
299 data_out => data_f1_out,
295 data_out_valid => data_f1_out_valid);
300 data_out_valid => data_f1_out_valid);
296
301
297 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
302 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
298 GENERIC MAP (
303 GENERIC MAP (
299 data_size => data_size,
304 data_size => data_size,
300 nb_snapshot_param_size => nb_snapshot_param_size+1)
305 nb_snapshot_param_size => nb_snapshot_param_size+1)
301 PORT MAP (
306 PORT MAP (
302 clk => clk,
307 clk => clk,
303 rstn => rstn,
308 rstn => rstn,
304 run => run,
309 run => run,
305 enable => enable_f2,
310 enable => enable_f2,
306 burst_enable => burst_f2,
311 burst_enable => burst_f2,
307 nb_snapshot_param => nb_snapshot_param_more_one,
312 nb_snapshot_param => nb_snapshot_param_more_one,
308 start_snapshot => start_snapshot_f2,
313 start_snapshot => start_snapshot_f2,
309 data_in => data_f2_in,
314 data_in => data_f2_in,
310 data_in_valid => data_f2_in_valid,
315 data_in_valid => data_f2_in_valid,
311 data_out => data_f2_out,
316 data_out => data_f2_out,
312 data_out_valid => data_f2_out_valid);
317 data_out_valid => data_f2_out_valid);
313
318
314 lpp_waveform_burst_f3 : lpp_waveform_burst
319 lpp_waveform_burst_f3 : lpp_waveform_burst
315 GENERIC MAP (
320 GENERIC MAP (
316 data_size => data_size)
321 data_size => data_size)
317 PORT MAP (
322 PORT MAP (
318 clk => clk,
323 clk => clk,
319 rstn => rstn,
324 rstn => rstn,
320 run => run,
325 run => run,
321 enable => enable_f3,
326 enable => enable_f3,
322 data_in => data_f3_in,
327 data_in => data_f3_in,
323 data_in_valid => data_f3_in_valid,
328 data_in_valid => data_f3_in_valid,
324 data_out => data_f3_out,
329 data_out => data_f3_out,
325 data_out_valid => data_f3_out_valid);
330 data_out_valid => data_f3_out_valid);
326
331
327 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
328 -- DEBUG -- SNAPSHOT OUT
333 -- DEBUG -- SNAPSHOT OUT
329 --debug_f0_data_valid <= data_f0_out_valid;
334 --debug_f0_data_valid <= data_f0_out_valid;
330 --debug_f0_data <= data_f0_out;
335 --debug_f0_data <= data_f0_out;
331 --debug_f1_data_valid <= data_f1_out_valid;
336 --debug_f1_data_valid <= data_f1_out_valid;
332 --debug_f1_data <= data_f1_out;
337 --debug_f1_data <= data_f1_out;
333 --debug_f2_data_valid <= data_f2_out_valid;
338 --debug_f2_data_valid <= data_f2_out_valid;
334 --debug_f2_data <= data_f2_out;
339 --debug_f2_data <= data_f2_out;
335 --debug_f3_data_valid <= data_f3_out_valid;
340 --debug_f3_data_valid <= data_f3_out_valid;
336 --debug_f3_data <= data_f3_out;
341 --debug_f3_data <= data_f3_out;
337 -----------------------------------------------------------------------------
342 -----------------------------------------------------------------------------
338
343
339 PROCESS (clk, rstn)
344 PROCESS (clk, rstn)
340 BEGIN -- PROCESS
345 BEGIN -- PROCESS
341 IF rstn = '0' THEN -- asynchronous reset (active low)
346 IF rstn = '0' THEN -- asynchronous reset (active low)
342 time_reg1 <= (OTHERS => '0');
347 time_reg1 <= (OTHERS => '0');
343 time_reg2 <= (OTHERS => '0');
348 time_reg2 <= (OTHERS => '0');
344 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
345 time_reg1 <= fine_time & coarse_time;
350 time_reg1 <= fine_time & coarse_time;
346 time_reg2 <= time_reg1;
351 time_reg2 <= time_reg1;
347 END IF;
352 END IF;
348 END PROCESS;
353 END PROCESS;
349
354
350 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
355 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
351 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
356 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
352 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
357 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
353 PORT MAP (
358 PORT MAP (
354 HCLK => clk,
359 HCLK => clk,
355 HRESETn => rstn,
360 HRESETn => rstn,
356 run => run,
361 run => run,
357 valid_in => valid_in(I),
362 valid_in => valid_in(I),
358 ack_in => valid_ack(I),
363 ack_in => valid_ack(I),
359 time_in => time_reg2, -- Todo
364 time_in => time_reg2, -- Todo
360 valid_out => valid_out(I),
365 valid_out => valid_out(I),
361 time_out => time_out(I), -- Todo
366 time_out => time_out(I), -- Todo
362 error => status_new_err(I));
367 error => status_new_err(I));
363 END GENERATE all_input_valid;
368 END GENERATE all_input_valid;
364
369
370 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
371 data_f0_out((16*6)-1 DOWNTO 16*5) &
372 data_f0_out((16*3)-1 DOWNTO 16*2) &
373 data_f0_out((16*4)-1 DOWNTO 16*3) &
374 data_f0_out((16*1)-1 DOWNTO 16*0) &
375 data_f0_out((16*2)-1 DOWNTO 16*1) ;
376
377 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
378 data_f1_out((16*6)-1 DOWNTO 16*5) &
379 data_f1_out((16*3)-1 DOWNTO 16*2) &
380 data_f1_out((16*4)-1 DOWNTO 16*3) &
381 data_f1_out((16*1)-1 DOWNTO 16*0) &
382 data_f1_out((16*2)-1 DOWNTO 16*1) ;
383
384 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
385 data_f2_out((16*6)-1 DOWNTO 16*5) &
386 data_f2_out((16*3)-1 DOWNTO 16*2) &
387 data_f2_out((16*4)-1 DOWNTO 16*3) &
388 data_f2_out((16*1)-1 DOWNTO 16*0) &
389 data_f2_out((16*2)-1 DOWNTO 16*1) ;
390
391 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
392 data_f3_out((16*6)-1 DOWNTO 16*5) &
393 data_f3_out((16*3)-1 DOWNTO 16*2) &
394 data_f3_out((16*4)-1 DOWNTO 16*3) &
395 data_f3_out((16*1)-1 DOWNTO 16*0) &
396 data_f3_out((16*2)-1 DOWNTO 16*1) ;
397
365 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
398 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
366 data_out(0, I) <= data_f0_out(I);
399 data_out(0, I) <= data_f0_out_swap(I);
367 data_out(1, I) <= data_f1_out(I);
400 data_out(1, I) <= data_f1_out_swap(I);
368 data_out(2, I) <= data_f2_out(I);
401 data_out(2, I) <= data_f2_out_swap(I);
369 data_out(3, I) <= data_f3_out(I);
402 data_out(3, I) <= data_f3_out_swap(I);
370 END GENERATE all_bit_of_data_out;
403 END GENERATE all_bit_of_data_out;
371
404
372 -----------------------------------------------------------------------------
405 -----------------------------------------------------------------------------
373 -- TODO : debug
406 -- TODO : debug
374 -----------------------------------------------------------------------------
407 -----------------------------------------------------------------------------
375 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
408 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
376 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
409 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
377 time_out_2(J, I) <= time_out(J)(I);
410 time_out_2(J, I) <= time_out(J)(I);
378 END GENERATE all_sample_of_time_out;
411 END GENERATE all_sample_of_time_out;
379 END GENERATE all_bit_of_time_out;
412 END GENERATE all_bit_of_time_out;
380
413
381 -- DEBUG --
414 -- DEBUG --
382 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
415 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
383 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
416 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
384 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
417 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
385 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
418 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
386
419
387 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
420 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
388 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
421 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
389 -- time_out_2(J, I) <= time_out_debug(J)(I);
422 -- time_out_2(J, I) <= time_out_debug(J)(I);
390 -- END GENERATE all_sample_of_time_out;
423 -- END GENERATE all_sample_of_time_out;
391 --END GENERATE all_bit_of_time_out;
424 --END GENERATE all_bit_of_time_out;
392 -- DEBUG --
425 -- DEBUG --
393
426
394 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
427 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
395 GENERIC MAP (tech => tech,
428 GENERIC MAP (tech => tech,
396 nb_data_by_buffer_size => nb_data_by_buffer_size)
429 nb_data_by_buffer_size => nb_data_by_buffer_size)
397 PORT MAP (
430 PORT MAP (
398 clk => clk,
431 clk => clk,
399 rstn => rstn,
432 rstn => rstn,
400 run => run,
433 run => run,
401 nb_data_by_buffer => nb_data_by_buffer,
434 nb_data_by_buffer => nb_data_by_buffer,
402 data_in_valid => valid_out,
435 data_in_valid => valid_out,
403 data_in_ack => valid_ack,
436 data_in_ack => valid_ack,
404 data_in => data_out,
437 data_in => data_out,
405 time_in => time_out_2,
438 time_in => time_out_2,
406
439
407 data_out => wdata,
440 data_out => wdata,
408 data_out_wen => data_wen,
441 data_out_wen => data_wen,
409 full_almost => full_almost,
442 full_almost => full_almost,
410 full => full);
443 full => full);
411
444
412 -----------------------------------------------------------------------------
445 -----------------------------------------------------------------------------
413 -- DEBUG -- SNAPSHOT IN
446 -- DEBUG -- SNAPSHOT IN
414 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
447 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
415 --debug_f0_data_fifo_in <= wdata;
448 --debug_f0_data_fifo_in <= wdata;
416 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
449 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
417 --debug_f1_data_fifo_in <= wdata;
450 --debug_f1_data_fifo_in <= wdata;
418 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
451 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
419 --debug_f2_data_fifo_in <= wdata;
452 --debug_f2_data_fifo_in <= wdata;
420 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
453 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
421 --debug_f3_data_fifo_in <= wdata;s
454 --debug_f3_data_fifo_in <= wdata;s
422 -----------------------------------------------------------------------------
455 -----------------------------------------------------------------------------
423
456
424 lpp_waveform_fifo_1 : lpp_waveform_fifo
457 lpp_waveform_fifo_1 : lpp_waveform_fifo
425 GENERIC MAP (tech => tech)
458 GENERIC MAP (tech => tech)
426 PORT MAP (
459 PORT MAP (
427 clk => clk,
460 clk => clk,
428 rstn => rstn,
461 rstn => rstn,
429 run => run,
462 run => run,
430
463
431 empty => s_empty,
464 empty => s_empty,
432 empty_almost => s_empty_almost,
465 empty_almost => s_empty_almost,
433 data_ren => s_data_ren,
466 data_ren => s_data_ren,
434 rdata => s_rdata,
467 rdata => s_rdata,
435
468
436
469
437 full_almost => full_almost,
470 full_almost => full_almost,
438 full => full,
471 full => full,
439 data_wen => data_wen,
472 data_wen => data_wen,
440 wdata => wdata);
473 wdata => wdata);
441
474
442 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
475 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
443 GENERIC MAP (tech => tech)
476 GENERIC MAP (tech => tech)
444 PORT MAP (
477 PORT MAP (
445 clk => clk,
478 clk => clk,
446 rstn => rstn,
479 rstn => rstn,
447 run => run,
480 run => run,
448 o_empty_almost => empty_almost,
481 o_empty_almost => empty_almost,
449 o_empty => empty,
482 o_empty => empty,
450
483
451 o_data_ren => data_ren,
484 o_data_ren => data_ren,
452 o_rdata_0 => data_f0_data_out,
485 o_rdata_0 => data_f0_data_out,
453 o_rdata_1 => data_f1_data_out,
486 o_rdata_1 => data_f1_data_out,
454 o_rdata_2 => data_f2_data_out,
487 o_rdata_2 => data_f2_data_out,
455 o_rdata_3 => data_f3_data_out,
488 o_rdata_3 => data_f3_data_out,
456
489
457 i_empty_almost => s_empty_almost,
490 i_empty_almost => s_empty_almost,
458 i_empty => s_empty,
491 i_empty => s_empty,
459 i_data_ren => s_data_ren,
492 i_data_ren => s_data_ren,
460 i_rdata => s_rdata);
493 i_rdata => s_rdata);
461
494
462
495
463 --data_f0_data_out <= rdata;
496 --data_f0_data_out <= rdata;
464 --data_f1_data_out <= rdata;
497 --data_f1_data_out <= rdata;
465 --data_f2_data_out <= rdata;
498 --data_f2_data_out <= rdata;
466 --data_f3_data_out <= rdata;
499 --data_f3_data_out <= rdata;
467
500
468 data_ren <= data_f3_data_out_ren &
501 data_ren <= data_f3_data_out_ren &
469 data_f2_data_out_ren &
502 data_f2_data_out_ren &
470 data_f1_data_out_ren &
503 data_f1_data_out_ren &
471 data_f0_data_out_ren;
504 data_f0_data_out_ren;
472
505
473 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
506 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
474 GENERIC MAP (
507 GENERIC MAP (
475 nb_data_by_buffer_size => nb_word_by_buffer_size)
508 nb_data_by_buffer_size => nb_word_by_buffer_size)
476 PORT MAP (
509 PORT MAP (
477 clk => clk,
510 clk => clk,
478 rstn => rstn,
511 rstn => rstn,
479 run => run,
512 run => run,
480
513
481 -------------------------------------------------------------------------
514 -------------------------------------------------------------------------
482 -- CONFIG
515 -- CONFIG
483 -------------------------------------------------------------------------
516 -------------------------------------------------------------------------
484 nb_data_by_buffer => nb_word_by_buffer,
517 nb_data_by_buffer => nb_word_by_buffer,
485
518
486 addr_data_f0 => addr_data_f0,
519 addr_data_f0 => addr_data_f0,
487 addr_data_f1 => addr_data_f1,
520 addr_data_f1 => addr_data_f1,
488 addr_data_f2 => addr_data_f2,
521 addr_data_f2 => addr_data_f2,
489 addr_data_f3 => addr_data_f3,
522 addr_data_f3 => addr_data_f3,
490 -------------------------------------------------------------------------
523 -------------------------------------------------------------------------
491 -- CTRL
524 -- CTRL
492 -------------------------------------------------------------------------
525 -------------------------------------------------------------------------
493 -- IN
526 -- IN
494 empty => empty,
527 empty => empty,
495 empty_almost => empty_almost,
528 empty_almost => empty_almost,
496 data_ren => data_ren,
529 data_ren => data_ren,
497
530
498 -------------------------------------------------------------------------
531 -------------------------------------------------------------------------
499 -- STATUS
532 -- STATUS
500 -------------------------------------------------------------------------
533 -------------------------------------------------------------------------
501 status_full => status_full_s,
534 status_full => status_full_s,
502 status_full_ack => status_full_ack,
535 status_full_ack => status_full_ack,
503 status_full_err => status_full_err,
536 status_full_err => status_full_err,
504
537
505 -------------------------------------------------------------------------
538 -------------------------------------------------------------------------
506 -- ADDR DATA OUT
539 -- ADDR DATA OUT
507 -------------------------------------------------------------------------
540 -------------------------------------------------------------------------
508 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
541 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
509 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
542 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
510 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
543 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
511 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
544 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
512
545
513 data_f0_data_out_valid => data_f0_data_out_valid,
546 data_f0_data_out_valid => data_f0_data_out_valid,
514 data_f1_data_out_valid => data_f1_data_out_valid,
547 data_f1_data_out_valid => data_f1_data_out_valid,
515 data_f2_data_out_valid => data_f2_data_out_valid,
548 data_f2_data_out_valid => data_f2_data_out_valid,
516 data_f3_data_out_valid => data_f3_data_out_valid,
549 data_f3_data_out_valid => data_f3_data_out_valid,
517
550
518 data_f0_addr_out => data_f0_addr_out,
551 data_f0_addr_out => data_f0_addr_out,
519 data_f1_addr_out => data_f1_addr_out,
552 data_f1_addr_out => data_f1_addr_out,
520 data_f2_addr_out => data_f2_addr_out,
553 data_f2_addr_out => data_f2_addr_out,
521 data_f3_addr_out => data_f3_addr_out
554 data_f3_addr_out => data_f3_addr_out
522 );
555 );
523 status_full <= status_full_s;
556 status_full <= status_full_s;
524
557
525 END beh;
558 END beh;
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