# HG changeset patch
# User pellion
# Date 2014-05-23 12:28:24
# Node ID aaed3c51895940118b5d91521f383f33754394b4
# Parent  9af6d7bda61c1a689649813025a83848b912cd75

Update DMA data (big endian)

diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
--- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
+++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
@@ -426,7 +426,7 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"00010C")  -- aa.bb.cc version
+      top_lfr_version        => X"00010D")  -- aa.bb.cc version
     PORT MAP (
       clk             => clk_25,
       rstn            => reset,
diff --git a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd
--- a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd
+++ b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd
@@ -185,7 +185,8 @@ BEGIN
   -----------------------------------------------------------------------------
   -- SEND 16 word by DMA (in burst mode)
   -----------------------------------------------------------------------------
-  data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
+  --data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
+  data_2_halfword(31 DOWNTO 0) <= data(31 DOWNTO 0);
   
   lpp_dma_send_16word_1 : lpp_dma_send_16word
     PORT MAP (
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
@@ -178,8 +178,8 @@ BEGIN
     ELSIF HCLK'EVENT AND HCLK = '1' THEN
       --
       debug_reg_s(3)  <= status_ready_matrix_f0;
-      debug_reg_s(4)  <= status_ready_matrix_f0;
-      debug_reg_s(5)  <= status_ready_matrix_f0;
+      debug_reg_s(4)  <= status_ready_matrix_f1;
+      debug_reg_s(5)  <= status_ready_matrix_f2;
       debug_reg_s(6)  <= '0';
       debug_reg_s(7)  <= '0';
       debug_reg_s(8)  <= '0';
diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd
--- a/lib/lpp/lpp_waveform/lpp_waveform.vhd
+++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd
@@ -168,6 +168,11 @@ ARCHITECTURE beh OF lpp_waveform IS
   SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
   SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
 
+  SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+  SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+  SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+  SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
+
   SIGNAL data_f0_out_valid          : STD_LOGIC;
   SIGNAL data_f1_out_valid          : STD_LOGIC;
   SIGNAL data_f2_out_valid          : STD_LOGIC;
@@ -362,13 +367,41 @@ BEGIN  -- beh
         error     => status_new_err(I));
   END GENERATE all_input_valid;
 
+  data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &  
+                      data_f0_out((16*6)-1 DOWNTO 16*5) &
+                      data_f0_out((16*3)-1 DOWNTO 16*2) &
+                      data_f0_out((16*4)-1 DOWNTO 16*3) &
+                      data_f0_out((16*1)-1 DOWNTO 16*0) &
+                      data_f0_out((16*2)-1 DOWNTO 16*1) ;  
+
+  data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &  
+                      data_f1_out((16*6)-1 DOWNTO 16*5) &
+                      data_f1_out((16*3)-1 DOWNTO 16*2) &
+                      data_f1_out((16*4)-1 DOWNTO 16*3) &
+                      data_f1_out((16*1)-1 DOWNTO 16*0) &
+                      data_f1_out((16*2)-1 DOWNTO 16*1) ;   
+
+  data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &  
+                      data_f2_out((16*6)-1 DOWNTO 16*5) &
+                      data_f2_out((16*3)-1 DOWNTO 16*2) &
+                      data_f2_out((16*4)-1 DOWNTO 16*3) &
+                      data_f2_out((16*1)-1 DOWNTO 16*0) &
+                      data_f2_out((16*2)-1 DOWNTO 16*1) ;   
+
+  data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &  
+                      data_f3_out((16*6)-1 DOWNTO 16*5) &
+                      data_f3_out((16*3)-1 DOWNTO 16*2) &
+                      data_f3_out((16*4)-1 DOWNTO 16*3) &
+                      data_f3_out((16*1)-1 DOWNTO 16*0) &
+                      data_f3_out((16*2)-1 DOWNTO 16*1) ;  
+  
   all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
-    data_out(0, I) <= data_f0_out(I);
-    data_out(1, I) <= data_f1_out(I);
-    data_out(2, I) <= data_f2_out(I);
-    data_out(3, I) <= data_f3_out(I);
+    data_out(0, I) <= data_f0_out_swap(I);
+    data_out(1, I) <= data_f1_out_swap(I);
+    data_out(2, I) <= data_f2_out_swap(I);
+    data_out(3, I) <= data_f3_out_swap(I);
   END GENERATE all_bit_of_data_out;
-
+  
   -----------------------------------------------------------------------------
   -- TODO : debug
   -----------------------------------------------------------------------------