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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fft.all;
32 32 use lpp.lpp_memory.all;
33 33 use work.fft_components.all;
34 34
35 35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
36 36
37 37 entity APB_FFT is
38 38 generic (
39 39 pindex : integer := 0;
40 40 paddr : integer := 0;
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 43 abits : integer := 8;
44 44 Data_sz : integer := 32;
45 45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 48 clk : in std_logic; --! Horloge du composant
49 49 rst : in std_logic; --! Reset general du composant
50 50 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
51 51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 52 );
53 53 end APB_FFT;
54 54
55 55
56 56 architecture ar_APB_FFT of APB_FFT is
57 57
58 58 signal ReadEnable : std_logic;
59 59 signal WriteEnable : std_logic;
60 60 signal FlagEmpty : std_logic;
61 61 signal FlagFull : std_logic;
62 62 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
63 63 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
64 64 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
65 65 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
66 66 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 67 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 68 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
69 69 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
70 70
71 71 signal start : std_logic;
72 72 signal load : std_logic;
73 73 signal rdy : std_logic;
74 signal zero : std_logic;
75 74
76 75 begin
77 76
78 77 APB : ApbDriver
79 78 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
80 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,zero,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
79 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
81 80
82 81
83 82 Extremum : Flag_Extremum
84 83 port map(clk,rst,load,rdy,FlagFull,FlagEmpty);
85 84
86 85
87 86 DEVICE : CoreFFT
88 87 generic map(
89 88 LOGPTS => gLOGPTS,
90 89 LOGLOGPTS => gLOGLOGPTS,
91 90 WSIZE => gWSIZE,
92 91 TWIDTH => gTWIDTH,
93 92 DWIDTH => gDWIDTH,
94 93 TDWIDTH => gTDWIDTH,
95 94 RND_MODE => gRND_MODE,
96 95 SCALE_MODE => gSCALE_MODE,
97 96 PTS => gPTS,
98 97 HALFPTS => gHALFPTS,
99 98 inBuf_RWDLY => gInBuf_RWDLY)
100 99 port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
101 100
102 101 start <= not rst;
103 zero <= '0';
104 102
105 103 DataIn_re <= DataIn(31 downto 16);
106 104 DataIn_im <= DataIn(15 downto 0);
107 105 DataOut <= DataOut_re & DataOut_im;
108 106
109 107 end ar_APB_FFT; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 31
32 32 package lpp_cna is
33 33
34 34 component APB_CNA is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8);
41 41 port (
42 42 clk : in std_logic;
43 43 rst : in std_logic;
44 44 apbi : in apb_slv_in_type;
45 45 apbo : out apb_slv_out_type;
46 46 SYNC : out std_logic;
47 47 SCLK : out std_logic;
48 48 DATA : out std_logic
49 49 );
50 50 end component;
51 51
52 52
53 53 component CNA_TabloC is
54 54 port(
55 55 clock : in std_logic;
56 56 rst : in std_logic;
57 flag_nw : in std_logic;
58 bp : in std_logic;
57 enable : in std_logic;
59 58 Data_C : in std_logic_vector(15 downto 0);
60 59 SYNC : out std_logic;
61 60 SCLK : out std_logic;
62 Rz : out std_logic;
63 61 flag_sd : out std_logic;
64 62 Data : out std_logic
65 63 );
66 64 end component;
67 65
68 66
69 67 component Systeme_Clock is
70 68 generic(N :integer := 695);
71 69 port(
72 70 clk, raz : in std_logic ;
73 71 clock : out std_logic);
74 72 end component;
75 73
76 74
77 75 component Gene_SYNC is
78 76 port(
79 77 clk,raz : in std_logic;
80 78 send : in std_logic;
81 79 Sysclk : in std_logic;
82 80 OKAI_send : out std_logic;
83 81 SYNC : out std_logic);
84 82 end component;
85 83
86 84
87 85 component Serialize is
88 86 port(
89 87 clk,raz : in std_logic;
90 88 sclk : in std_logic;
91 89 vectin : in std_logic_vector(15 downto 0);
92 90 send : in std_logic;
93 91 sended : out std_logic;
94 92 Data : out std_logic);
95 93 end component;
96 94
97 95 end;
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@@ -1,131 +1,131
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_matrix.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34 34
35 35 entity APB_Matrix is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Input_SZ : integer := 16;
43 43 Result_SZ : integer := 32);
44 44 port (
45 45 clk : in std_logic; --! Horloge du composant
46 46 rst : in std_logic; --! Reset general du composant
47 47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 49 Full : in std_logic_vector(1 downto 0);
50 50 Empty : in std_logic_vector(1 downto 0);
51 51 ReadFIFO : out std_logic_vector(1 downto 0);
52 52 WriteFIFO : out std_logic;
53 53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 54 Start : out std_logic;
55 55 -- Read : out std_logic;
56 56 -- Take : out std_logic;
57 57 -- Valid : out std_logic;
58 -- Received : out std_logic;
58 Res : out std_logic_vector(Result_SZ-1 downto 0);
59 59 -- Conjugate : out std_logic;
60 60 -- OP1 : out std_logic_vector(3 downto 0);
61 61 -- OP2 : out std_logic_vector(3 downto 0);
62 62 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
63 63 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
64 64 );
65 65 end APB_Matrix;
66 66
67 67
68 68 architecture ar_APB_Matrix of APB_Matrix is
69 69
70 70 constant REVISION : integer := 1;
71 71
72 72 constant pconfig : apb_config_type := (
73 73 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
74 74 1 => apb_iobar(paddr, pmask));
75 75
76 76 type MATRIX_ctrlr_Reg is record
77 77 MATRIX_Statu : std_logic_vector(3 downto 0);
78 78 end record;
79 79
80 80 signal Rec : MATRIX_ctrlr_Reg;
81 81 signal Rdata : std_logic_vector(31 downto 0);
82 82
83 83 begin
84 84
85 85 Mspec0 : SpectralMatrix
86 86 generic map (Input_SZ,Result_SZ)
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
87 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Res,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
88 88
89 89 process(rst,clk)
90 90 begin
91 91 if(rst='0')then
92 92 Rec.MATRIX_Statu <= (others => '0');
93 93
94 94 elsif(clk'event and clk='1')then
95 95
96 96 --APB Write OP
97 97 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 98 case apbi.paddr(abits-1 downto 2) is
99 99 when "000000" =>
100 100 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
101 101 when others =>
102 102 null;
103 103 end case;
104 104 end if;
105 105
106 106 --APB READ OP
107 107 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 108 case apbi.paddr(abits-1 downto 2) is
109 109 when "000000" =>
110 110 Rdata(31 downto 4) <= (others => '0');
111 111 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
112 112 --when "000001" =>
113 113 -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
114 114 -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
115 115 -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
116 116 -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
117 117 -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
118 118 -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
119 119 -- Rdata(31 downto 24) <= X"CC";
120 120 when others =>
121 121 Rdata <= (others => '0');
122 122 end case;
123 123 end if;
124 124
125 125 end if;
126 126 apbo.pconfig <= pconfig;
127 127 end process;
128 128
129 129 apbo.prdata <= Rdata when apbi.penable = '1';
130 130
131 131 end ar_APB_MATRIX; No newline at end of file
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@@ -1,108 +1,109
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25 use lpp.lpp_matrix.all;
26 26
27 27 entity SpectralMatrix is
28 28 generic(
29 29 Input_SZ : integer := 16;
30 30 Result_SZ : integer := 32);
31 31 port(
32 32 clk : in std_logic;
33 33 reset : in std_logic;
34 34 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
35 35 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
36 36 Full : in std_logic_vector(1 downto 0);
37 37 Empty : in std_logic_vector(1 downto 0);
38 38 Statu : in std_logic_vector(3 downto 0);
39 39 ReadFIFO : out std_logic_vector(1 downto 0);
40 40 WriteFIFO : out std_logic;
41 41 Start : out std_logic;
42 42 -- Read : out std_logic;
43 43 -- Take : out std_logic;
44 44 -- Valid : out std_logic;
45 Res : out std_logic_vector(Result_SZ-1 downto 0);
45 46 -- Received : out std_logic;
46 47 -- Conjugate : out std_logic;
47 48 -- OP1 : out std_logic_vector(3 downto 0);
48 49 -- OP2 : out std_logic_vector(3 downto 0);
49 50 Result : out std_logic_vector(Result_SZ-1 downto 0)
50 51 );
51 52 end SpectralMatrix;
52 53
53 54
54 55 architecture ar_SpectralMatrix of SpectralMatrix is
55 56
56 57 signal Start_int : std_logic;
57 58 signal Read_int : std_logic;
58 59 signal Take_int : std_logic;
59 60 signal Received_int : std_logic;
60 61 signal Valid_int : std_logic;
61 62 signal Conjugate_int : std_logic;
62 63
63 64 --signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
64 65 --signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
65 66 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
66 67 --signal Res : std_logic_vector(Result_SZ-1 downto 0);
67 68
68 69
69 70 begin
70 71
71 72 ST0 : Starter
72 73 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
73 74
74 75 --IN0 : SelectInputs
75 76 -- generic map(Input_SZ)
76 77 -- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
77 78
78 79 IN1 : DriveInputs
79 80 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
80 81
81 82
82 83 CALC0 : Matrix
83 84 generic map(Input_SZ)
84 85 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
85 86
86 87
87 88 RES0 : GetResult
88 89 generic map(Result_SZ)
89 90 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
90 91
91 92
92 93 With Statu select
93 94 Conjugate_int <= '1' when "0001",
94 95 '1' when "0011",
95 96 '1' when "0110",
96 97 '1' when "1010",
97 98 '1' when "1111",
98 99 '0' when others;
99 100
100 101 Start <= Start_int;
101 102 --Read <= Read_int;
102 103 --Take <= Take_int;
103 104 --Received <= Received_int;
104 105 --Valid <= Valid_int;
105 106 --Conjugate <= Conjugate_int;
106 --Result <= Resultat;
107 Res <= Resultat;
107 108
108 109 end ar_SpectralMatrix; No newline at end of file
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@@ -1,231 +1,233
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 31
32 32 package lpp_matrix is
33 33
34 34 component APB_Matrix is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 Input_SZ : integer := 16;
42 42 Result_SZ : integer := 32);
43 43 port (
44 44 clk : in std_logic; --! Horloge du composant
45 45 rst : in std_logic; --! Reset general du composant
46 46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 48 Full : in std_logic_vector(1 downto 0);
49 49 Empty : in std_logic_vector(1 downto 0);
50 50 ReadFIFO : out std_logic_vector(1 downto 0);
51 51 WriteFIFO : out std_logic;
52 52 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 53 Start : out std_logic;
54 Res : out std_logic_vector(Result_SZ-1 downto 0);
54 55 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
55 56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 57 );
57 58 end component;
58 59
59 60
60 61 component SpectralMatrix is
61 62 generic(
62 63 Input_SZ : integer := 16;
63 64 Result_SZ : integer := 32);
64 65 port(
65 66 clk : in std_logic;
66 67 reset : in std_logic;
67 68 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
68 69 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
69 70 Full : in std_logic_vector(1 downto 0);
70 71 Empty : in std_logic_vector(1 downto 0);
71 72 Statu : in std_logic_vector(3 downto 0);
72 73 ReadFIFO : out std_logic_vector(1 downto 0);
73 74 WriteFIFO : out std_logic;
74 75 Start : out std_logic;
76 Res : out std_logic_vector(Result_SZ-1 downto 0);
75 77 Result : out std_logic_vector(Result_SZ-1 downto 0)
76 78 );
77 79 end component;
78 80
79 81
80 82 component Matrix is
81 83 generic(
82 84 Input_SZ : integer := 16);
83 85 port(
84 86 clk : in std_logic;
85 87 raz : in std_logic;
86 88 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
87 89 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
88 90 Take : in std_logic;
89 91 Received : in std_logic;
90 92 Conjugate : in std_logic;
91 93 Valid : out std_logic;
92 94 Read : out std_logic;
93 95 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
94 96 );
95 97 end component;
96 98
97 99
98 100 component ALU_Driver is
99 101 generic(
100 102 Input_SZ_1 : integer := 16;
101 103 Input_SZ_2 : integer := 16);
102 104 port(
103 105 clk : in std_logic;
104 106 reset : in std_logic;
105 107 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
106 108 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
107 109 Take : in std_logic;
108 110 Received : in std_logic;
109 111 Conjugate : in std_logic;
110 112 Valid : out std_logic;
111 113 Read : out std_logic;
112 114 CTRL : out std_logic_vector(4 downto 0);
113 115 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
114 116 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
115 117 );
116 118 end component;
117 119
118 120
119 121 component ALU_v2 is
120 122 generic(
121 123 Arith_en : integer := 1;
122 124 Logic_en : integer := 1;
123 125 Input_SZ_1 : integer := 16;
124 126 Input_SZ_2 : integer := 9);
125 127 port(
126 128 clk : in std_logic;
127 129 reset : in std_logic;
128 130 ctrl : in std_logic_vector(4 downto 0);
129 131 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
130 132 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
131 133 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
132 134 );
133 135 end component;
134 136
135 137
136 138 component MAC_v2 is
137 139 generic(
138 140 Input_SZ_A : integer := 8;
139 141 Input_SZ_B : integer := 8);
140 142 port(
141 143 clk : in std_logic;
142 144 reset : in std_logic;
143 145 clr_MAC : in std_logic;
144 146 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
145 147 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
146 148 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
147 149 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
148 150 );
149 151 end component;
150 152
151 153
152 154 component TwoComplementer is
153 155 generic(
154 156 Input_SZ : integer := 16);
155 157 port(
156 158 clk : in std_logic;
157 159 reset : in std_logic;
158 160 clr : in std_logic;
159 161 TwoComp : in std_logic;
160 162 OP : in std_logic_vector(Input_SZ-1 downto 0);
161 163 RES : out std_logic_vector(Input_SZ-1 downto 0)
162 164 );
163 165 end component;
164 166
165 167
166 168 component GetResult is
167 169 generic(
168 170 Result_SZ : integer := 32);
169 171 port(
170 172 clk : in std_logic;
171 173 raz : in std_logic;
172 174 Valid : in std_logic;
173 175 Conjugate : in std_logic;
174 176 Res : in std_logic_vector(Result_SZ-1 downto 0);
175 177 WriteFIFO : out std_logic;
176 178 Received : out std_logic;
177 179 Result : out std_logic_vector(Result_SZ-1 downto 0)
178 180 );
179 181 end component;
180 182
181 183
182 184 component SelectInputs is
183 185 generic(
184 186 Input_SZ : integer := 16);
185 187 port(
186 188 clk : in std_logic;
187 189 raz : in std_logic;
188 190 Read : in std_logic;
189 191 B1 : in std_logic_vector(Input_SZ-1 downto 0);
190 192 B2 : in std_logic_vector(Input_SZ-1 downto 0);
191 193 B3 : in std_logic_vector(Input_SZ-1 downto 0);
192 194 E1 : in std_logic_vector(Input_SZ-1 downto 0);
193 195 E2 : in std_logic_vector(Input_SZ-1 downto 0);
194 196 Conjugate : out std_logic;
195 197 Take : out std_logic;
196 198 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
197 199 Statu : out std_logic_vector(3 downto 0);
198 200 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
199 201 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
200 202 );
201 203 end component;
202 204 ---------------------------------------------------------------------------
203 205 component DriveInputs is
204 206 port(
205 207 clk : in std_logic;
206 208 raz : in std_logic;
207 209 Read : in std_logic;
208 210 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
209 211 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
210 212 -- Statu : in std_logic_vector(3 downto 0);
211 213 Conjugate : in std_logic;
212 214 Take : out std_logic;
213 215 ReadFIFO : out std_logic_vector(1 downto 0)
214 216 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
215 217 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
216 218 );
217 219 end component;
218 220
219 221 component Starter is
220 222 port(
221 223 clk : in std_logic;
222 224 raz : in std_logic;
223 225 Full : in std_logic_vector(1 downto 0);
224 226 Empty : in std_logic_vector(1 downto 0);
225 227 Conjugate : in std_logic;
226 228 received : in std_logic;
227 229 Start : out std_logic
228 230 );
229 231 end component;
230 232
231 233 end; No newline at end of file
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@@ -1,87 +1,89
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_memory.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
35 35 entity APB_FifoRead is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 49 WriteEnable : in std_logic; --! Demande d'οΏ½criture dans la mοΏ½moire, gοΏ½rοΏ½ hors de l'IP
50 RE : out std_logic;
50 51 Full : out std_logic; --! Flag, Memoire pleine
51 52 Empty : out std_logic; --! Flag, Memoire vide
52 53 DATA : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½es en entrοΏ½e de la mοΏ½moire
53 54 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 55 );
55 56 end APB_FifoRead;
56 57
57 58 --! @details Gestion de la FIFO, οΏ½criture via le bus APB, lecture interne au FPGA
58 59
59 60 architecture ar_APB_FifoRead of APB_FifoRead is
60 61
61 62 signal Low : std_logic:='0';
62 63 signal ReadEnable : std_logic;
63 64 signal FlagEmpty : std_logic;
64 65 signal FlagFull : std_logic;
65 66 --signal ReUse : std_logic;
66 67 --signal Lock : std_logic;
67 68 --signal RstMem : std_logic;
68 69 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
69 70 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
70 71 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
71 72 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
72 73
73 74 begin
74 75
75 76 APB : ApbDriver
76 77 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
77 78 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
78 79
79 80
80 81 FIFO : Top_FIFO
81 82 generic map(Data_sz,Addr_sz,addr_max_int)
82 83 port map(clk,rst,ReadEnable,WriteEnable,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
83 84
84 85 Empty <= FlagEmpty;
85 86 Full <= FlagFull;
87 RE <= ReadEnable;
86 88
87 89 end ar_APB_FifoRead; No newline at end of file
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@@ -1,171 +1,173
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31
32 32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
33 33
34 34 entity ApbDriver is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 LPP_DEVICE : integer;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 52 -- ReUse : out std_logic; --! Flag, Permet de relire la mοΏ½moire en boucle sans nouvelle donnοΏ½es
53 53 -- Lock : out std_logic; --! Flag, Permet de bloquer l'οΏ½criture dans la mοΏ½moire
54 54 -- RstMem : out std_logic; --! Flag, Reset "manuel" spοΏ½cifique au composant
55 55 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
56 56 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
57 57 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
58 58 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
59 59 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
60 60 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
61 61 );
62 62 end ApbDriver;
63 63
64 64 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
65 65
66 66 architecture ar_ApbDriver of ApbDriver is
67 67
68 68 constant REVISION : integer := 1;
69 69
70 70 constant pconfig : apb_config_type := (
71 71 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
72 72 1 => apb_iobar(paddr, pmask));
73 73
74 74 type DEVICE_ctrlr_Reg is record
75 75 DEVICE_Cfg : std_logic_vector(3 downto 0);
76 76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
77 77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
78 78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
79 79 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
80 80 end record;
81 81
82 82 signal Rec : DEVICE_ctrlr_Reg;
83 83 signal Rdata : std_logic_vector(31 downto 0);
84 84
85 85 signal FlagRE : std_logic;
86 86 signal FlagWR : std_logic;
87 87
88 88 begin
89 89
90 90 Rec.DEVICE_Cfg(0) <= FlagRE;
91 91 Rec.DEVICE_Cfg(1) <= FlagWR;
92 92 Rec.DEVICE_Cfg(2) <= FlagEmpty;
93 93 Rec.DEVICE_Cfg(3) <= FlagFull;
94 94 --ReUse <= Rec.DEVICE_Cfg(4);
95 95 --Lock <= Rec.DEVICE_Cfg(5);
96 96 --RstMem <= Rec.DEVICE_Cfg(7);
97 97
98 98 DataIn <= Rec.DEVICE_DataW;
99 99 Rec.DEVICE_DataR <= DataOut;
100 100 Rec.DEVICE_AddrW <= AddrIn;
101 101 Rec.DEVICE_AddrR <= AddrOut;
102 102
103 103
104 104
105 105 process(rst,clk)
106 106 begin
107 107 if(rst='0')then
108 108 Rec.DEVICE_DataW <= (others => '0');
109 109 FlagWR <= '0';
110 110 FlagRE <= '0';
111 111 -- Rec.DEVICE_Cfg(4) <= '0';
112 112 -- Rec.DEVICE_Cfg(5) <= '0';
113 113 -- Rec.DEVICE_Cfg(7) <= '0';
114 114
115 115 elsif(clk'event and clk='1')then
116 116
117 117 --APB Write OP
118 118 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
119 119 case apbi.paddr(abits-1 downto 2) is
120 120 when "000000" =>
121 121 FlagWR <= '1';
122 122 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
123 123 -- when "000010" =>
124 124 -- Rec.DEVICE_Cfg(7) <= apbi.pwdata(28);
125 125 -- Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
126 126 -- Rec.DEVICE_Cfg(6) <= apbi.pwdata(24);
127 127 when others =>
128 128 null;
129 129 end case;
130 130 else
131 131 FlagWR <= '0';
132 132 end if;
133 133
134 134 --APB Read OP
135 135 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
136 136 case apbi.paddr(abits-1 downto 2) is
137 137 when "000000" =>
138 FlagRE <= '1';
138 if(apbi.penable = '1')then
139 FlagRE <= '1';
140 end if;
139 141 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
140 142 when "000001" =>
141 143 -- Rdata(31 downto 8) <= X"AAAAAA";
142 144 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrR;
143 145 when "000101" =>
144 146 -- Rdata(31 downto 8) <= X"AAAAAA";
145 147 Rdata(Addr_sz-1 downto 0) <= Rec.DEVICE_AddrW;
146 148 when "000010" =>
147 149 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
148 150 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
149 151 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
150 152 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
151 153 -- Rdata(27 downto 16) <= X"000";
152 154 -- Rdata(31 downto 28) <= "000" & Rec.DEVICE_Cfg(7);
153 155 -- Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
154 156 -- Rdata(27 downto 24) <= "000" & Rec.DEVICE_Cfg(6);
155 157 Rdata(31 downto 16) <= X"CCCC";
156 158 when others =>
157 159 Rdata <= (others => '0');
158 160 end case;
159 161 else
160 162 FlagRE <= '0';
161 163 end if;
162 164
163 165 end if;
164 166 apbo.pconfig <= pconfig;
165 167 end process;
166 168
167 169 apbo.prdata <= Rdata when apbi.penable = '1';
168 170 WriteEnable <= FlagWR;
169 ReadEnable <= FlagRE;
171 ReadEnable <= FlagRE; --when apbi.penable = '1';
170 172
171 173 end ar_ApbDriver; No newline at end of file
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@@ -1,149 +1,149
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library techmap;
26 26 use techmap.gencomp.all;
27 27 use work.config.all;
28 28 use lpp.lpp_memory.all;
29 29
30 30 --! Programme de la FIFO
31 31
32 32 entity Top_FIFO is
33 33 generic(
34 34 Data_sz : integer := 16;
35 35 Addr_sz : integer := 8;
36 36 addr_max_int : integer := 256
37 37 );
38 38 port(
39 39 clk,raz : in std_logic; --! Horloge et reset general du composant
40 40 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
41 41 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
42 42 -- ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire en boucle sans nouvelle donnοΏ½es
43 43 -- Lock : in std_logic; --! Permet de bloquer l'οΏ½criture dans la mοΏ½moire
44 44 -- RstMem : in std_logic; --! Flag, Reset "manuel" spοΏ½cifique au composant
45 45 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
46 46 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
47 47 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
48 48 full : out std_logic; --! Flag, MοΏ½moire pleine
49 49 empty : out std_logic; --! Flag, MοΏ½moire vide
50 50 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
51 51 );
52 52 end Top_FIFO;
53 53
54 54 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
55 55 --! associοΏ½e a deux Drivers, un pour οΏ½crire l'autre pour lire cette mοΏ½moire
56 56
57 57 architecture ar_Top_FIFO of Top_FIFO is
58 58
59 59 component syncram_2p
60 60 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
61 61 port (
62 62 rclk : in std_ulogic;
63 63 renable : in std_ulogic;
64 64 raddress : in std_logic_vector((abits -1) downto 0);
65 65 dataout : out std_logic_vector((dbits -1) downto 0);
66 66 wclk : in std_ulogic;
67 67 write : in std_ulogic;
68 68 waddress : in std_logic_vector((abits -1) downto 0);
69 69 datain : in std_logic_vector((dbits -1) downto 0));
70 70 end component;
71 71
72 72 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
73 73 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
74 --signal Data_int : std_logic_vector(Data_sz-1 downto 0);
74 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
75 75 signal s_empty : std_logic;
76 76 signal s_full : std_logic;
77 77 --signal s_full2 : std_logic;
78 78 signal s_flag_RE : std_logic;
79 79 signal s_flag_WR : std_logic;
80 80 signal Flag_WR_reg : std_logic;
81 81 --signal rst : std_logic;
82 82 --signal RstMem_inv : std_logic;
83 83
84 84 begin
85 85
86 86 --RstMem_inv <= not RstMem;
87 87 --rst <= raz and RstMem_inv;
88 88
89 89 WR : Fifo_Write
90 90 generic map(Addr_sz,addr_max_int)
91 91 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
92 92
93 93
94 94 SRAM : syncram_2p
95 95 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
96 port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in);
96 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
97 97
98 98
99 -- Pipe : Pipeline
100 -- generic map(Data_sz)
101 -- port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
99 Pipe : Pipeline
100 generic map(Data_sz)
101 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
102 102
103 103
104 104 RE : Fifo_Read
105 105 generic map(Addr_sz,addr_max_int)
106 106 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
107 107
108 108 process(clk,raz)
109 109 begin
110 110 if(raz='0')then
111 111 s_flag_RE <= '0';
112 112 s_flag_WR <= '0';
113 113 -- s_full2 <= s_full;
114 114 Flag_WR_reg <= '0';
115 115
116 116 elsif(clk'event and clk='1')then
117 117 Flag_WR_reg <= Flag_WR;
118 118
119 119 if(s_full='0')then --2
120 120 if(s_empty='1')then
121 121 s_flag_WR <= Flag_WR_reg;
122 122 else
123 123 s_flag_WR <= Flag_WR;
124 124 end if;
125 125 else
126 126 s_flag_WR <= '0';
127 127 end if;
128 128
129 129 if(s_empty='0')then
130 130 s_flag_RE <= Flag_RE;
131 131 else
132 132 s_flag_RE <= '0';
133 133 end if;
134 134
135 135 -- if(Lock='1')then
136 136 -- s_full2 <= '1';
137 137 -- else
138 138 -- s_full2 <= s_full;
139 139 -- end if;
140 140
141 141 end if;
142 142 end process;
143 143
144 144 full <= s_full; --2
145 145 empty <= s_empty;
146 146 Addr_RE <= Raddr;
147 147 Addr_WR <= Waddr;
148 148
149 149 end ar_Top_FIFO; No newline at end of file
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@@ -1,252 +1,253
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 31
32 32 package lpp_memory is
33 33
34 34 --===========================================================|
35 35 --=================== FIFO ComplοΏ½te =========================|
36 36 --===========================================================|
37 37
38 38 component APB_FIFO is
39 39 generic (
40 40 pindex : integer := 0;
41 41 paddr : integer := 0;
42 42 pmask : integer := 16#fff#;
43 43 pirq : integer := 0;
44 44 abits : integer := 8;
45 45 Data_sz : integer := 16;
46 46 Addr_sz : integer := 8;
47 47 addr_max_int : integer := 256);
48 48 port (
49 49 clk : in std_logic;
50 50 rst : in std_logic;
51 51 apbi : in apb_slv_in_type;
52 52 Full : out std_logic;
53 53 Empty : out std_logic;
54 54 WR : out std_logic;
55 55 RE : out std_logic;
56 56 apbo : out apb_slv_out_type
57 57 );
58 58 end component;
59 59
60 60
61 61 component ApbDriver is
62 62 generic (
63 63 pindex : integer := 0;
64 64 paddr : integer := 0;
65 65 pmask : integer := 16#fff#;
66 66 pirq : integer := 0;
67 67 abits : integer := 8;
68 68 LPP_DEVICE : integer;
69 69 Data_sz : integer := 16;
70 70 Addr_sz : integer := 8;
71 71 addr_max_int : integer := 256);
72 72 port (
73 73 clk : in std_logic;
74 74 rst : in std_logic;
75 75 ReadEnable : out std_logic;
76 76 WriteEnable : out std_logic;
77 77 FlagEmpty : in std_logic;
78 78 FlagFull : in std_logic;
79 79 -- ReUse : out std_logic;
80 80 -- Lock : out std_logic;
81 81 -- RstMem : out std_logic;
82 82 DataIn : out std_logic_vector(Data_sz-1 downto 0);
83 83 DataOut : in std_logic_vector(Data_sz-1 downto 0);
84 84 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
85 85 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
86 86 apbi : in apb_slv_in_type;
87 87 apbo : out apb_slv_out_type
88 88 );
89 89 end component;
90 90
91 91
92 92 component Top_FIFO is
93 93 generic(
94 94 Data_sz : integer := 16;
95 95 Addr_sz : integer := 8;
96 96 addr_max_int : integer := 256
97 97 );
98 98 port(
99 99 clk,raz : in std_logic;
100 100 flag_RE : in std_logic;
101 101 flag_WR : in std_logic;
102 102 -- ReUse : in std_logic;
103 103 -- Lock : in std_logic;
104 104 -- RstMem : in std_logic;
105 105 Data_in : in std_logic_vector(Data_sz-1 downto 0);
106 106 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
107 107 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
108 108 full : out std_logic;
109 109 empty : out std_logic;
110 110 Data_out : out std_logic_vector(Data_sz-1 downto 0)
111 111 );
112 112 end component;
113 113
114 114
115 115 component Fifo_Read is
116 116 generic(
117 117 Addr_sz : integer := 8;
118 118 addr_max_int : integer := 256);
119 119 port(
120 120 clk : in std_logic;
121 121 raz : in std_logic;
122 122 flag_RE : in std_logic;
123 123 -- ReUse : in std_logic;
124 124 Waddr : in std_logic_vector(addr_sz-1 downto 0);
125 125 empty : out std_logic;
126 126 Raddr : out std_logic_vector(addr_sz-1 downto 0)
127 127 );
128 128 end component;
129 129
130 130
131 131 component Fifo_Write is
132 132 generic(
133 133 Addr_sz : integer := 8;
134 134 addr_max_int : integer := 256);
135 135 port(
136 136 clk : in std_logic;
137 137 raz : in std_logic;
138 138 flag_WR : in std_logic;
139 139 Raddr : in std_logic_vector(addr_sz-1 downto 0);
140 140 full : out std_logic;
141 141 Waddr : out std_logic_vector(addr_sz-1 downto 0)
142 142 );
143 143 end component;
144 144
145 145
146 146 component Pipeline is
147 147 generic(Data_sz : integer := 16);
148 148 port(
149 149 clk,raz : in std_logic;
150 150 Data_one : in std_logic_vector(Data_sz-1 downto 0);
151 151 Data_two : in std_logic_vector(Data_sz-1 downto 0);
152 152 -- ReUse : in std_logic;
153 153 flag_RE : in std_logic;
154 154 flag_WR : in std_logic;
155 155 empty : in std_logic;
156 156 Data_out : out std_logic_vector(Data_sz-1 downto 0)
157 157 );
158 158 end component;
159 159
160 160 --===========================================================|
161 161 --================= Demi FIFO Ecriture ======================|
162 162 --===========================================================|
163 163
164 164 component APB_FifoWrite is
165 165 generic (
166 166 pindex : integer := 0;
167 167 paddr : integer := 0;
168 168 pmask : integer := 16#fff#;
169 169 pirq : integer := 0;
170 170 abits : integer := 8;
171 171 Data_sz : integer := 16;
172 172 Addr_sz : integer := 8;
173 173 addr_max_int : integer := 256);
174 174 port (
175 175 clk : in std_logic;
176 176 rst : in std_logic;
177 177 apbi : in apb_slv_in_type;
178 178 ReadEnable : in std_logic;
179 179 Empty : out std_logic;
180 180 Full : out std_logic;
181 181 DATA : out std_logic_vector(Data_sz-1 downto 0);
182 182 apbo : out apb_slv_out_type
183 183 );
184 184 end component;
185 185
186 186
187 187 --component Top_FifoWrite is
188 188 -- generic(
189 189 -- Data_sz : integer := 16;
190 190 -- Addr_sz : integer := 8;
191 191 -- addr_max_int : integer := 256);
192 192 -- port(
193 193 -- clk : in std_logic;
194 194 -- raz : in std_logic;
195 195 -- flag_RE : in std_logic;
196 196 -- flag_WR : in std_logic;
197 197 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
198 198 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
199 199 -- full : out std_logic;
200 200 -- empty : out std_logic;
201 201 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
202 202 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
203 203 -- );
204 204 --end component;
205 205
206 206 --===========================================================|
207 207 --================== Demi FIFO Lecture ======================|
208 208 --===========================================================|
209 209
210 210 component APB_FifoRead is
211 211 generic (
212 212 pindex : integer := 0;
213 213 paddr : integer := 0;
214 214 pmask : integer := 16#fff#;
215 215 pirq : integer := 0;
216 216 abits : integer := 8;
217 217 Data_sz : integer := 16;
218 218 Addr_sz : integer := 8;
219 219 addr_max_int : integer := 256);
220 220 port (
221 221 clk : in std_logic;
222 222 rst : in std_logic;
223 223 apbi : in apb_slv_in_type;
224 224 WriteEnable : in std_logic;
225 RE : out std_logic;
225 226 Full : out std_logic;
226 227 Empty : out std_logic;
227 228 DATA : in std_logic_vector(Data_sz-1 downto 0);
228 229 apbo : out apb_slv_out_type
229 230 );
230 231 end component;
231 232
232 233
233 234 --component Top_FifoRead is
234 235 -- generic(
235 236 -- Data_sz : integer := 16;
236 237 -- Addr_sz : integer := 8;
237 238 -- addr_max_int : integer := 256);
238 239 -- port(
239 240 -- clk : in std_logic;
240 241 -- raz : in std_logic;
241 242 -- flag_RE : in std_logic;
242 243 -- flag_WR : in std_logic;
243 244 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
244 245 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
245 246 -- full : out std_logic;
246 247 -- empty : out std_logic;
247 248 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
248 249 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
249 250 -- );
250 251 --end component;
251 252
252 253 end;
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