##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Patch1
Alexis Jeandet -
r433:a787767be54c JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,19
1 PACKAGE=\"\"
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 DESIGNER_PACKAGE=FBGA
12 DESIGNER_PINS=324
13
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
16 MGCPART=$(PART)
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19
Show file before | Show file after | Hide comments
@@ -0,0 +1,436
1 # Actel Physical design constraints file
2 # Generated file
3
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
7
8
9 #
10 # IO banks setting
11 #
12
13
14 #
15 # I/O constraints
16 #
17
18 set_io clk_50 \
19 -pinname F7 \
20 -fixed yes \
21 -DIRECTION Inout
22
23 set_io clk_49 \
24 -pinname F8 \
25 -fixed yes \
26 -DIRECTION Inout
27
28 set_io reset \
29 -pinname J12 \
30 -fixed yes \
31 -DIRECTION Inout
32 #====================================================================
33 # BPs
34 #====================================================================
35 set_io BP0 \
36 -pinname F16 \
37 -fixed yes \
38 -DIRECTION Inout
39
40 set_io BP1 \
41 -pinname F13 \
42 -fixed yes \
43 -DIRECTION Inout
44
45 #====================================================================
46 # LEDs
47 #====================================================================
48
49 set_io LED0 \
50 -pinname R13 \
51 -fixed yes \
52 -DIRECTION Inout
53
54 set_io LED1 \
55 -pinname P13 \
56 -fixed yes \
57 -DIRECTION Inout
58
59 set_io LED2 \
60 -pinname N11 \
61 -fixed yes \
62 -DIRECTION Inout
63
64 #====================================================================
65 # UARTS
66 #====================================================================
67
68 set_io TXD1 \
69 -pinname N12 \
70 -fixed yes \
71 -DIRECTION Inout
72
73 set_io RXD1 \
74 -pinname N10 \
75 -fixed yes \
76 -DIRECTION Inout
77
78 set_io nCTS1 \
79 -pinname L13 \
80 -fixed yes \
81 -DIRECTION Inout
82
83 set_io nRTS1 \
84 -pinname M9 \
85 -fixed yes \
86 -DIRECTION Inout
87
88
89 set_io TXD2 \
90 -pinname G6 \
91 -fixed yes \
92 -DIRECTION Inout
93
94 set_io RXD2 \
95 -pinname F6 \
96 -fixed yes \
97 -DIRECTION Inout
98
99
100 #====================================================================
101 # SRAM
102 #====================================================================
103
104 #================================
105 # SRAM CTRL
106 #================================
107
108 set_io SRAM_nWE \
109 -pinname B16 \
110 -fixed yes \
111 -DIRECTION Inout
112
113 set_io SRAM_nCE1 \
114 -pinname C17 \
115 -fixed yes \
116 -DIRECTION Inout
117
118 set_io SRAM_nCE2 \
119 -pinname B17 \
120 -fixed yes \
121 -DIRECTION Inout
122
123 set_io SRAM_nOE \
124 -pinname J14 \
125 -fixed yes \
126 -DIRECTION Inout
127
128 set_io SRAM_MBE \
129 -pinname D13 \
130 -fixed yes \
131 -DIRECTION Inout
132
133 set_io SRAM_nSCRUB \
134 -pinname E13 \
135 -fixed yes \
136 -DIRECTION Inout
137
138 set_io SRAM_nBUSY \
139 -pinname D12 \
140 -fixed yes \
141 -DIRECTION Inout
142
143
144
145
146 #================================
147 # SRAM ADDRESS
148 #================================
149
150 set_io SRAM_A\[0\] \
151 -pinname T12 \
152 -fixed yes \
153 -DIRECTION Inout
154
155 set_io SRAM_A\[1\] \
156 -pinname U13 \
157 -fixed yes \
158 -DIRECTION Inout
159
160 set_io SRAM_A\[2\] \
161 -pinname T13 \
162 -fixed yes \
163 -DIRECTION Inout
164
165 set_io SRAM_A\[3\] \
166 -pinname N15 \
167 -fixed yes \
168 -DIRECTION Inout
169
170 set_io SRAM_A\[4\] \
171 -pinname P17 \
172 -fixed yes \
173 -DIRECTION Inout
174
175 set_io SRAM_A\[5\] \
176 -pinname N13 \
177 -fixed yes \
178 -DIRECTION Inout
179
180 set_io SRAM_A\[6\] \
181 -pinname M16 \
182 -fixed yes \
183 -DIRECTION Inout
184
185 set_io SRAM_A\[7\] \
186 -pinname M13 \
187 -fixed yes \
188 -DIRECTION Inout
189
190 set_io SRAM_A\[8\] \
191 -pinname U12 \
192 -fixed yes \
193 -DIRECTION Inout
194
195 set_io SRAM_A\[9\] \
196 -pinname V11 \
197 -fixed yes \
198 -DIRECTION Inout
199
200 set_io SRAM_A\[10\] \
201 -pinname V13 \
202 -fixed yes \
203 -DIRECTION Inout
204
205 set_io SRAM_A\[11\] \
206 -pinname V14 \
207 -fixed yes \
208 -DIRECTION Inout
209
210 set_io SRAM_A\[12\] \
211 -pinname V15 \
212 -fixed yes \
213 -DIRECTION Inout
214
215 set_io SRAM_A\[13\] \
216 -pinname P16 \
217 -fixed yes \
218 -DIRECTION Inout
219
220 set_io SRAM_A\[14\] \
221 -pinname N16 \
222 -fixed yes \
223 -DIRECTION Inout
224
225 set_io SRAM_A\[15\] \
226 -pinname V16 \
227 -fixed yes \
228 -DIRECTION Inout
229
230 set_io SRAM_A\[16\] \
231 -pinname V17 \
232 -fixed yes \
233 -DIRECTION Inout
234
235 set_io SRAM_A\[17\] \
236 -pinname U18 \
237 -fixed yes \
238 -DIRECTION Inout
239
240 set_io SRAM_A\[18\] \
241 -pinname R18 \
242 -fixed yes \
243 -DIRECTION Inout
244
245
246
247 #================================
248 # SRAM DATA
249 #================================
250
251 set_io SRAM_DQ\[0\] \
252 -pinname T18 \
253 -fixed yes \
254 -DIRECTION Inout
255
256 set_io SRAM_DQ\[1\] \
257 -pinname L15 \
258 -fixed yes \
259 -DIRECTION Inout
260
261 set_io SRAM_DQ\[2\] \
262 -pinname K18 \
263 -fixed yes \
264 -DIRECTION Inout
265
266 set_io SRAM_DQ\[3\] \
267 -pinname G17 \
268 -fixed yes \
269 -DIRECTION Inout
270
271 set_io SRAM_DQ\[4\] \
272 -pinname K17 \
273 -fixed yes \
274 -DIRECTION Inout
275
276 set_io SRAM_DQ\[5\] \
277 -pinname H18 \
278 -fixed yes \
279 -DIRECTION Inout
280
281 set_io SRAM_DQ\[6\] \
282 -pinname L18 \
283 -fixed yes \
284 -DIRECTION Inout
285
286 set_io SRAM_DQ\[7\] \
287 -pinname J18 \
288 -fixed yes \
289 -DIRECTION Inout
290
291 set_io SRAM_DQ\[8\] \
292 -pinname M17 \
293 -fixed yes \
294 -DIRECTION Inout
295
296 set_io SRAM_DQ\[9\] \
297 -pinname J17 \
298 -fixed yes \
299 -DIRECTION Inout
300
301 set_io SRAM_DQ\[10\] \
302 -pinname N18 \
303 -fixed yes \
304 -DIRECTION Inout
305
306 set_io SRAM_DQ\[11\] \
307 -pinname J13 \
308 -fixed yes \
309 -DIRECTION Inout
310
311 set_io SRAM_DQ\[12\] \
312 -pinname N17 \
313 -fixed yes \
314 -DIRECTION Inout
315
316 set_io SRAM_DQ\[13\] \
317 -pinname K13 \
318 -fixed yes \
319 -DIRECTION Inout
320
321 set_io SRAM_DQ\[14\] \
322 -pinname P18 \
323 -fixed yes \
324 -DIRECTION Inout
325
326 set_io SRAM_DQ\[15\] \
327 -pinname K14 \
328 -fixed yes \
329 -DIRECTION Inout
330
331 set_io SRAM_DQ\[16\] \
332 -pinname K15 \
333 -fixed yes \
334 -DIRECTION Inout
335
336 set_io SRAM_DQ\[17\] \
337 -pinname B18 \
338 -fixed yes \
339 -DIRECTION Inout
340
341 set_io SRAM_DQ\[18\] \
342 -pinname D16 \
343 -fixed yes \
344 -DIRECTION Inout
345
346 set_io SRAM_DQ\[19\] \
347 -pinname D15 \
348 -fixed yes \
349 -DIRECTION Inout
350
351 set_io SRAM_DQ\[20\] \
352 -pinname C18 \
353 -fixed yes \
354 -DIRECTION Inout
355
356 set_io SRAM_DQ\[21\] \
357 -pinname E15 \
358 -fixed yes \
359 -DIRECTION Inout
360
361 set_io SRAM_DQ\[22\] \
362 -pinname D18 \
363 -fixed yes \
364 -DIRECTION Inout
365
366 set_io SRAM_DQ\[23\] \
367 -pinname F15 \
368 -fixed yes \
369 -DIRECTION Inout
370
371 set_io SRAM_DQ\[24\] \
372 -pinname E18 \
373 -fixed yes \
374 -DIRECTION Inout
375
376 set_io SRAM_DQ\[25\] \
377 -pinname G15 \
378 -fixed yes \
379 -DIRECTION Inout
380
381 set_io SRAM_DQ\[26\] \
382 -pinname F17 \
383 -fixed yes \
384 -DIRECTION Inout
385
386 set_io SRAM_DQ\[27\] \
387 -pinname H15 \
388 -fixed yes \
389 -DIRECTION Inout
390
391 set_io SRAM_DQ\[28\] \
392 -pinname F18 \
393 -fixed yes \
394 -DIRECTION Inout
395
396 set_io SRAM_DQ\[29\] \
397 -pinname J15 \
398 -fixed yes \
399 -DIRECTION Inout
400
401 set_io SRAM_DQ\[30\] \
402 -pinname D11 \
403 -fixed yes \
404 -DIRECTION Inout
405
406 set_io SRAM_DQ\[31\] \
407 -pinname C16 \
408 -fixed yes \
409 -DIRECTION Inout
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
Show file before | Show file after | Hide comments
@@ -65,7 +65,9 ENTITY leon3_soc IS
65 --
65 --
66 NB_AHB_MASTER : INTEGER := 0;
66 NB_AHB_MASTER : INTEGER := 0;
67 NB_AHB_SLAVE : INTEGER := 0;
67 NB_AHB_SLAVE : INTEGER := 0;
68 NB_APB_SLAVE : INTEGER := 0
68 NB_APB_SLAVE : INTEGER := 0;
69 --
70 ADDRESS_SIZE : INTEGER := 20
69 );
71 );
70 PORT (
72 PORT (
71 clk : IN STD_ULOGIC;
73 clk : IN STD_ULOGIC;
@@ -82,7 +84,7 ENTITY leon3_soc IS
82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
84 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83
85
84 -- RAM --------------------------------------------------------------------
86 -- RAM --------------------------------------------------------------------
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
87 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 nSRAM_BE0 : OUT STD_LOGIC;
89 nSRAM_BE0 : OUT STD_LOGIC;
88 nSRAM_BE1 : OUT STD_LOGIC;
90 nSRAM_BE1 : OUT STD_LOGIC;
@@ -326,8 +328,8 BEGIN
326 memi.data(31-i*8 DOWNTO 24-i*8));
328 memi.data(31-i*8 DOWNTO 24-i*8));
327 END GENERATE;
329 END GENERATE;
328
330
329 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
331 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
330 PORT MAP (address, memo.address(21 DOWNTO 2));
332 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
331 nSRAM_CE_s <= NOT(memo.ramsn(0));
333 nSRAM_CE_s <= NOT(memo.ramsn(0));
332 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
334 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
333 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
335 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
@@ -394,7 +396,7 BEGIN
394 apbuarti.ctsn <= '0';
396 apbuarti.ctsn <= '0';
395 END GENERATE;
397 END GENERATE;
396 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
398 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
397
399
398 -------------------------------------------------------------------------------
400 -------------------------------------------------------------------------------
399 -- AMBA BUS -------------------------------------------------------------------
401 -- AMBA BUS -------------------------------------------------------------------
400 -------------------------------------------------------------------------------
402 -------------------------------------------------------------------------------
Show file before | Show file after | Hide comments
@@ -1,127 +1,128
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27
27
28 PACKAGE lpp_leon3_soc_pkg IS
28 PACKAGE lpp_leon3_soc_pkg IS
29
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
33
34 COMPONENT leon3_soc
34 COMPONENT leon3_soc
35 GENERIC (
35 GENERIC (
36 fabtech : INTEGER;
36 fabtech : INTEGER;
37 memtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
43 clk_freq : INTEGER;
44 NB_CPU : INTEGER;
44 NB_CPU : INTEGER;
45 ENABLE_FPU : INTEGER;
45 ENABLE_FPU : INTEGER;
46 FPU_NETLIST : INTEGER;
46 FPU_NETLIST : INTEGER;
47 ENABLE_DSU : INTEGER;
47 ENABLE_DSU : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
50 ENABLE_IRQMP : INTEGER;
50 ENABLE_IRQMP : INTEGER;
51 ENABLE_GPT : INTEGER;
51 ENABLE_GPT : INTEGER;
52 NB_AHB_MASTER : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER);
54 NB_APB_SLAVE : INTEGER;
55 PORT (
55 ADDRESS_SIZE : INTEGER);
56 clk : IN STD_ULOGIC;
56 PORT (
57 reset : IN STD_ULOGIC;
57 clk : IN STD_ULOGIC;
58 errorn : OUT STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59 ahbrxd : IN STD_ULOGIC;
59 errorn : OUT STD_ULOGIC;
60 ahbtxd : OUT STD_ULOGIC;
60 ahbrxd : IN STD_ULOGIC;
61 urxd1 : IN STD_ULOGIC;
61 ahbtxd : OUT STD_ULOGIC;
62 utxd1 : OUT STD_ULOGIC;
62 urxd1 : IN STD_ULOGIC;
63 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 utxd1 : OUT STD_ULOGIC;
64 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
65 nSRAM_BE0 : OUT STD_LOGIC;
65 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE0 : OUT STD_LOGIC;
67 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE1 : OUT STD_LOGIC;
68 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_BE2 : OUT STD_LOGIC;
69 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_BE3 : OUT STD_LOGIC;
70 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_WE : OUT STD_LOGIC;
71 nSRAM_OE : OUT STD_LOGIC;
71 nSRAM_CE : OUT STD_LOGIC;
72 apbi_ext : OUT apb_slv_in_type;
72 nSRAM_OE : OUT STD_LOGIC;
73 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
73 apbi_ext : OUT apb_slv_in_type;
74 ahbi_s_ext : OUT ahb_slv_in_type;
74 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
75 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
75 ahbi_s_ext : OUT ahb_slv_in_type;
76 ahbi_m_ext : OUT AHB_Mst_In_Type;
76 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
77 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
77 ahbi_m_ext : OUT AHB_Mst_In_Type;
78 END COMPONENT;
78 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
79
79 END COMPONENT;
80
80
81 COMPONENT leon3ft_soc
81
82 GENERIC (
82 COMPONENT leon3ft_soc
83 fabtech : INTEGER;
83 GENERIC (
84 memtech : INTEGER;
84 fabtech : INTEGER;
85 padtech : INTEGER;
85 memtech : INTEGER;
86 clktech : INTEGER;
86 padtech : INTEGER;
87 disas : INTEGER;
87 clktech : INTEGER;
88 dbguart : INTEGER;
88 disas : INTEGER;
89 pclow : INTEGER;
89 dbguart : INTEGER;
90 clk_freq : INTEGER;
90 pclow : INTEGER;
91 NB_CPU : INTEGER;
91 clk_freq : INTEGER;
92 ENABLE_FPU : INTEGER;
92 NB_CPU : INTEGER;
93 FPU_NETLIST : INTEGER;
93 ENABLE_FPU : INTEGER;
94 ENABLE_DSU : INTEGER;
94 FPU_NETLIST : INTEGER;
95 ENABLE_AHB_UART : INTEGER;
95 ENABLE_DSU : INTEGER;
96 ENABLE_APB_UART : INTEGER;
96 ENABLE_AHB_UART : INTEGER;
97 ENABLE_IRQMP : INTEGER;
97 ENABLE_APB_UART : INTEGER;
98 ENABLE_GPT : INTEGER;
98 ENABLE_IRQMP : INTEGER;
99 NB_AHB_MASTER : INTEGER;
99 ENABLE_GPT : INTEGER;
100 NB_AHB_SLAVE : INTEGER;
100 NB_AHB_MASTER : INTEGER;
101 NB_APB_SLAVE : INTEGER);
101 NB_AHB_SLAVE : INTEGER;
102 PORT (
102 NB_APB_SLAVE : INTEGER);
103 clk : IN STD_ULOGIC;
103 PORT (
104 reset : IN STD_ULOGIC;
104 clk : IN STD_ULOGIC;
105 errorn : OUT STD_ULOGIC;
105 reset : IN STD_ULOGIC;
106 ahbrxd : IN STD_ULOGIC;
106 errorn : OUT STD_ULOGIC;
107 ahbtxd : OUT STD_ULOGIC;
107 ahbrxd : IN STD_ULOGIC;
108 urxd1 : IN STD_ULOGIC;
108 ahbtxd : OUT STD_ULOGIC;
109 utxd1 : OUT STD_ULOGIC;
109 urxd1 : IN STD_ULOGIC;
110 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
110 utxd1 : OUT STD_ULOGIC;
111 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
111 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
112 nSRAM_BE0 : OUT STD_LOGIC;
112 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 nSRAM_BE1 : OUT STD_LOGIC;
113 nSRAM_BE0 : OUT STD_LOGIC;
114 nSRAM_BE2 : OUT STD_LOGIC;
114 nSRAM_BE1 : OUT STD_LOGIC;
115 nSRAM_BE3 : OUT STD_LOGIC;
115 nSRAM_BE2 : OUT STD_LOGIC;
116 nSRAM_WE : OUT STD_LOGIC;
116 nSRAM_BE3 : OUT STD_LOGIC;
117 nSRAM_CE : OUT STD_LOGIC;
117 nSRAM_WE : OUT STD_LOGIC;
118 nSRAM_OE : OUT STD_LOGIC;
118 nSRAM_CE : OUT STD_LOGIC;
119 apbi_ext : OUT apb_slv_in_type;
119 nSRAM_OE : OUT STD_LOGIC;
120 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
120 apbi_ext : OUT apb_slv_in_type;
121 ahbi_s_ext : OUT ahb_slv_in_type;
121 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
122 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
122 ahbi_s_ext : OUT ahb_slv_in_type;
123 ahbi_m_ext : OUT AHB_Mst_In_Type;
123 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
124 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
124 ahbi_m_ext : OUT AHB_Mst_In_Type;
125 END COMPONENT;
125 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
126
126 END COMPONENT;
127 END;
127
128 END;
General Comments 0
You need to be logged in to leave comments. Login now