diff --git a/boards/UT8ER1M32-test-board/Makefile.inc b/boards/UT8ER1M32-test-board/Makefile.inc new file mode 100644 --- /dev/null +++ b/boards/UT8ER1M32-test-board/Makefile.inc @@ -0,0 +1,19 @@ +PACKAGE=\"\" +SPEED=Std +SYNFREQ=50 + +TECHNOLOGY=ProASIC3E +LIBERO_DIE=IT14X14M4 +PART=A3PE3000 + +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM +DESIGNER_PACKAGE=FBGA +DESIGNER_PINS=324 + +MANUFACTURER=Actel +MGCTECHNOLOGY=Proasic3 +MGCPART=$(PART) +MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} +LIBERO_PACKAGE=fg$(DESIGNER_PINS) + diff --git a/boards/UT8ER1M32-test-board/default.pdc b/boards/UT8ER1M32-test-board/default.pdc new file mode 100644 --- /dev/null +++ b/boards/UT8ER1M32-test-board/default.pdc @@ -0,0 +1,436 @@ +# Actel Physical design constraints file +# Generated file + +# Version: 9.1 SP3 9.1.3.4 +# Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA +# Date generated: Tue Oct 18 08:21:45 2011 + + +# +# IO banks setting +# + + +# +# I/O constraints +# + +set_io clk_50 \ + -pinname F7 \ + -fixed yes \ + -DIRECTION Inout + +set_io clk_49 \ + -pinname F8 \ + -fixed yes \ + -DIRECTION Inout + +set_io reset \ + -pinname J12 \ + -fixed yes \ + -DIRECTION Inout +#==================================================================== +# BPs +#==================================================================== +set_io BP0 \ + -pinname F16 \ + -fixed yes \ + -DIRECTION Inout + +set_io BP1 \ + -pinname F13 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# LEDs +#==================================================================== + +set_io LED0 \ + -pinname R13 \ + -fixed yes \ + -DIRECTION Inout + +set_io LED1 \ + -pinname P13 \ + -fixed yes \ + -DIRECTION Inout + +set_io LED2 \ + -pinname N11 \ + -fixed yes \ + -DIRECTION Inout + +#==================================================================== +# UARTS +#==================================================================== + +set_io TXD1 \ + -pinname N12 \ + -fixed yes \ + -DIRECTION Inout + +set_io RXD1 \ + -pinname N10 \ + -fixed yes \ + -DIRECTION Inout + +set_io nCTS1 \ + -pinname L13 \ + -fixed yes \ + -DIRECTION Inout + +set_io nRTS1 \ + -pinname M9 \ + -fixed yes \ + -DIRECTION Inout + + +set_io TXD2 \ + -pinname G6 \ + -fixed yes \ + -DIRECTION Inout + +set_io RXD2 \ + -pinname F6 \ + -fixed yes \ + -DIRECTION Inout + + +#==================================================================== +# SRAM +#==================================================================== + + #================================ + # SRAM CTRL + #================================ + +set_io SRAM_nWE \ + -pinname B16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nCE1 \ + -pinname C17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nCE2 \ + -pinname B17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nOE \ + -pinname J14 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_MBE \ + -pinname D13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nSCRUB \ + -pinname E13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_nBUSY \ + -pinname D12 \ + -fixed yes \ + -DIRECTION Inout + + + + + #================================ + # SRAM ADDRESS + #================================ + +set_io SRAM_A\[0\] \ + -pinname T12 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[1\] \ + -pinname U13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[2\] \ + -pinname T13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[3\] \ + -pinname N15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[4\] \ + -pinname P17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[5\] \ + -pinname N13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[6\] \ + -pinname M16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[7\] \ + -pinname M13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[8\] \ + -pinname U12 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[9\] \ + -pinname V11 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[10\] \ + -pinname V13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[11\] \ + -pinname V14 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[12\] \ + -pinname V15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[13\] \ + -pinname P16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[14\] \ + -pinname N16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[15\] \ + -pinname V16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[16\] \ + -pinname V17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[17\] \ + -pinname U18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_A\[18\] \ + -pinname R18 \ + -fixed yes \ + -DIRECTION Inout + + + + #================================ + # SRAM DATA + #================================ + +set_io SRAM_DQ\[0\] \ + -pinname T18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[1\] \ + -pinname L15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[2\] \ + -pinname K18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[3\] \ + -pinname G17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[4\] \ + -pinname K17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[5\] \ + -pinname H18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[6\] \ + -pinname L18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[7\] \ + -pinname J18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[8\] \ + -pinname M17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[9\] \ + -pinname J17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[10\] \ + -pinname N18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[11\] \ + -pinname J13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[12\] \ + -pinname N17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[13\] \ + -pinname K13 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[14\] \ + -pinname P18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[15\] \ + -pinname K14 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[16\] \ + -pinname K15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[17\] \ + -pinname B18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[18\] \ + -pinname D16 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[19\] \ + -pinname D15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[20\] \ + -pinname C18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[21\] \ + -pinname E15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[22\] \ + -pinname D18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[23\] \ + -pinname F15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[24\] \ + -pinname E18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[25\] \ + -pinname G15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[26\] \ + -pinname F17 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[27\] \ + -pinname H15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[28\] \ + -pinname F18 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[29\] \ + -pinname J15 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[30\] \ + -pinname D11 \ + -fixed yes \ + -DIRECTION Inout + +set_io SRAM_DQ\[31\] \ + -pinname C16 \ + -fixed yes \ + -DIRECTION Inout + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -65,7 +65,9 @@ ENTITY leon3_soc IS -- NB_AHB_MASTER : INTEGER := 0; NB_AHB_SLAVE : INTEGER := 0; - NB_APB_SLAVE : INTEGER := 0 + NB_APB_SLAVE : INTEGER := 0; + -- + ADDRESS_SIZE : INTEGER := 20 ); PORT ( clk : IN STD_ULOGIC; @@ -82,7 +84,7 @@ ENTITY leon3_soc IS utxd1 : OUT STD_ULOGIC; -- UART1 tx data -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0); data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); nSRAM_BE0 : OUT STD_LOGIC; nSRAM_BE1 : OUT STD_LOGIC; @@ -326,8 +328,8 @@ BEGIN memi.data(31-i*8 DOWNTO 24-i*8)); END GENERATE; - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); + addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) + PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); nSRAM_CE_s <= NOT(memo.ramsn(0)); rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); @@ -394,7 +396,7 @@ BEGIN apbuarti.ctsn <= '0'; END GENERATE; noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - + ------------------------------------------------------------------------------- -- AMBA BUS ------------------------------------------------------------------- ------------------------------------------------------------------------------- diff --git a/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd b/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd --- a/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +++ b/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd @@ -1,127 +1,128 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; - -PACKAGE lpp_leon3_soc_pkg IS - - type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type; - type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type; - type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type; - - COMPONENT leon3_soc - GENERIC ( - fabtech : INTEGER; - memtech : INTEGER; - padtech : INTEGER; - clktech : INTEGER; - disas : INTEGER; - dbguart : INTEGER; - pclow : INTEGER; - clk_freq : INTEGER; - NB_CPU : INTEGER; - ENABLE_FPU : INTEGER; - FPU_NETLIST : INTEGER; - ENABLE_DSU : INTEGER; - ENABLE_AHB_UART : INTEGER; - ENABLE_APB_UART : INTEGER; - ENABLE_IRQMP : INTEGER; - ENABLE_GPT : INTEGER; - NB_AHB_MASTER : INTEGER; - NB_AHB_SLAVE : INTEGER; - NB_APB_SLAVE : INTEGER); - PORT ( - clk : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - ahbrxd : IN STD_ULOGIC; - ahbtxd : OUT STD_ULOGIC; - urxd1 : IN STD_ULOGIC; - utxd1 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - apbi_ext : OUT apb_slv_in_type; - apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); - ahbi_s_ext : OUT ahb_slv_in_type; - ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); - ahbi_m_ext : OUT AHB_Mst_In_Type; - ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); - END COMPONENT; - - - COMPONENT leon3ft_soc - GENERIC ( - fabtech : INTEGER; - memtech : INTEGER; - padtech : INTEGER; - clktech : INTEGER; - disas : INTEGER; - dbguart : INTEGER; - pclow : INTEGER; - clk_freq : INTEGER; - NB_CPU : INTEGER; - ENABLE_FPU : INTEGER; - FPU_NETLIST : INTEGER; - ENABLE_DSU : INTEGER; - ENABLE_AHB_UART : INTEGER; - ENABLE_APB_UART : INTEGER; - ENABLE_IRQMP : INTEGER; - ENABLE_GPT : INTEGER; - NB_AHB_MASTER : INTEGER; - NB_AHB_SLAVE : INTEGER; - NB_APB_SLAVE : INTEGER); - PORT ( - clk : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - ahbrxd : IN STD_ULOGIC; - ahbtxd : OUT STD_ULOGIC; - urxd1 : IN STD_ULOGIC; - utxd1 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - apbi_ext : OUT apb_slv_in_type; - apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); - ahbi_s_ext : OUT ahb_slv_in_type; - ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); - ahbi_m_ext : OUT AHB_Mst_In_Type; - ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); - END COMPONENT; - -END; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; + +PACKAGE lpp_leon3_soc_pkg IS + + type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type; + type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type; + type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type; + + COMPONENT leon3_soc + GENERIC ( + fabtech : INTEGER; + memtech : INTEGER; + padtech : INTEGER; + clktech : INTEGER; + disas : INTEGER; + dbguart : INTEGER; + pclow : INTEGER; + clk_freq : INTEGER; + NB_CPU : INTEGER; + ENABLE_FPU : INTEGER; + FPU_NETLIST : INTEGER; + ENABLE_DSU : INTEGER; + ENABLE_AHB_UART : INTEGER; + ENABLE_APB_UART : INTEGER; + ENABLE_IRQMP : INTEGER; + ENABLE_GPT : INTEGER; + NB_AHB_MASTER : INTEGER; + NB_AHB_SLAVE : INTEGER; + NB_APB_SLAVE : INTEGER; + ADDRESS_SIZE : INTEGER); + PORT ( + clk : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + errorn : OUT STD_ULOGIC; + ahbrxd : IN STD_ULOGIC; + ahbtxd : OUT STD_ULOGIC; + urxd1 : IN STD_ULOGIC; + utxd1 : OUT STD_ULOGIC; + address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + apbi_ext : OUT apb_slv_in_type; + apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); + ahbi_s_ext : OUT ahb_slv_in_type; + ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); + ahbi_m_ext : OUT AHB_Mst_In_Type; + ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); + END COMPONENT; + + + COMPONENT leon3ft_soc + GENERIC ( + fabtech : INTEGER; + memtech : INTEGER; + padtech : INTEGER; + clktech : INTEGER; + disas : INTEGER; + dbguart : INTEGER; + pclow : INTEGER; + clk_freq : INTEGER; + NB_CPU : INTEGER; + ENABLE_FPU : INTEGER; + FPU_NETLIST : INTEGER; + ENABLE_DSU : INTEGER; + ENABLE_AHB_UART : INTEGER; + ENABLE_APB_UART : INTEGER; + ENABLE_IRQMP : INTEGER; + ENABLE_GPT : INTEGER; + NB_AHB_MASTER : INTEGER; + NB_AHB_SLAVE : INTEGER; + NB_APB_SLAVE : INTEGER); + PORT ( + clk : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + errorn : OUT STD_ULOGIC; + ahbrxd : IN STD_ULOGIC; + ahbtxd : OUT STD_ULOGIC; + urxd1 : IN STD_ULOGIC; + utxd1 : OUT STD_ULOGIC; + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + apbi_ext : OUT apb_slv_in_type; + apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); + ahbi_s_ext : OUT ahb_slv_in_type; + ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); + ahbi_m_ext : OUT AHB_Mst_In_Type; + ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); + END COMPONENT; + +END;