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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | LIBRARY lpp; | |
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4 | USE lpp.lpp_ad_conv.ALL; | |
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5 | ||
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6 | ------------------------------------------------------------------------------- | |
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7 | ||
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8 | ENTITY TB_Data_Acquisition IS | |
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9 | ||
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10 | END TB_Data_Acquisition; | |
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11 | ||
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12 | ------------------------------------------------------------------------------- | |
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13 | ||
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14 | ARCHITECTURE tb OF TB_Data_Acquisition IS | |
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15 | ||
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16 | COMPONENT TestModule_ADS7886 | |
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17 | GENERIC ( | |
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18 | freq : INTEGER; | |
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19 | amplitude : INTEGER; | |
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20 | impulsion : INTEGER); | |
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21 | PORT ( | |
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22 | cnv_run : IN STD_LOGIC; | |
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23 | cnv : IN STD_LOGIC; | |
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24 | sck : IN STD_LOGIC; | |
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25 | sdo : OUT STD_LOGIC); | |
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26 | END COMPONENT; | |
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27 | ||
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28 | COMPONENT Top_Data_Acquisition | |
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29 | PORT ( | |
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30 | cnv_run : IN STD_LOGIC; | |
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31 | cnv : OUT STD_LOGIC; | |
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32 | sck : OUT STD_LOGIC; | |
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33 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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34 | cnv_clk : IN STD_LOGIC; | |
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35 | cnv_rstn : IN STD_LOGIC; | |
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36 | clk : IN STD_LOGIC; | |
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37 | rstn : IN STD_LOGIC); | |
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38 | END COMPONENT; | |
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39 | ||
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40 | -- component ports | |
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41 | SIGNAL cnv_rstn : STD_LOGIC; | |
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42 | SIGNAL cnv : STD_LOGIC; | |
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43 | SIGNAL rstn : STD_LOGIC; | |
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44 | SIGNAL sck : STD_LOGIC; | |
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45 | SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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46 | SIGNAL run_cnv : STD_LOGIC; | |
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47 | ||
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48 | ||
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49 | -- clock | |
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50 | signal Clk : STD_LOGIC := '1'; | |
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51 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
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52 | ||
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53 | ||
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54 | BEGIN -- tb | |
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55 | ||
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56 | MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE | |
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57 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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58 | GENERIC MAP ( | |
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59 | freq => 24*(I+1), | |
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60 | amplitude => 30000/(I+1), | |
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61 | impulsion => 0) | |
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62 | PORT MAP ( | |
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63 | cnv_run => run_cnv, | |
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64 | cnv => cnv, | |
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65 | sck => sck, | |
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66 | sdo => sdo(I)); | |
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67 | END GENERATE MODULE_ADS7886; | |
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68 | ||
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69 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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70 | GENERIC MAP ( | |
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71 | freq => 0, | |
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72 | amplitude => 30000, | |
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73 | impulsion => 1) | |
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74 | PORT MAP ( | |
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75 | cnv_run => run_cnv, | |
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76 | cnv => cnv, | |
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77 | sck => sck, | |
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78 | sdo => sdo(7)); | |
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79 | ||
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80 | ||
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81 | -- clock generation | |
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82 | Clk <= not Clk after 20 ns; -- 25 Mhz | |
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83 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz | |
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84 | ||
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85 | -- waveform generation | |
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86 | WaveGen_Proc: process | |
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87 | begin | |
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88 | -- insert signal assignments here | |
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89 | wait until Clk = '1'; | |
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90 | rstn <= '0'; | |
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91 | cnv_rstn <= '0'; | |
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92 | run_cnv <= '0'; | |
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93 | wait until Clk = '1'; | |
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94 | wait until Clk = '1'; | |
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95 | wait until Clk = '1'; | |
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96 | rstn <= '1'; | |
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97 | cnv_rstn <= '1'; | |
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98 | wait until Clk = '1'; | |
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99 | wait until Clk = '1'; | |
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100 | wait until Clk = '1'; | |
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101 | wait until Clk = '1'; | |
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102 | wait until Clk = '1'; | |
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103 | wait until Clk = '1'; | |
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104 | run_cnv <= '1'; | |
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105 | wait; | |
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106 | ||
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107 | end process WaveGen_Proc; | |
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108 | ||
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109 | ----------------------------------------------------------------------------- | |
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110 | ||
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111 | Top_Data_Acquisition_1: Top_Data_Acquisition | |
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112 | PORT MAP ( | |
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113 | cnv_run => run_cnv, | |
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114 | cnv => cnv, | |
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115 | sck => sck, | |
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116 | sdo => sdo, | |
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117 | cnv_clk => cnv_clk, | |
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118 | cnv_rstn => cnv_rstn, | |
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119 | clk => clk, | |
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120 | rstn => rstn); | |
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121 | ||
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122 | END tb; | |
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | LIBRARY lpp; | |
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4 | USE lpp.lpp_ad_conv.ALL; | |
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5 | use lpp.iir_filter.all; | |
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6 | use lpp.FILTERcfg.all; | |
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7 | ||
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8 | ENTITY Top_Data_Acquisition IS | |
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9 | PORT ( | |
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10 | -- ADS7886 | |
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11 | cnv_run : IN STD_LOGIC; | |
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12 | cnv : OUT STD_LOGIC; | |
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13 | sck : OUT STD_LOGIC; | |
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14 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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15 | -- | |
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16 | cnv_clk : IN STD_LOGIC; | |
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17 | cnv_rstn : IN STD_LOGIC; | |
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18 | -- | |
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19 | clk : IN STD_LOGIC; | |
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20 | rstn : IN STD_LOGIC | |
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21 | ||
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22 | ); | |
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23 | END Top_Data_Acquisition; | |
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24 | ||
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25 | ARCHITECTURE tb OF Top_Data_Acquisition IS | |
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26 | ||
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27 | ----------------------------------------------------------------------------- | |
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28 | CONSTANT ChanelCount : INTEGER := 8; | |
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29 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
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30 | CONSTANT ncycle_cnv : INTEGER := 500; | |
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31 | ||
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32 | ----------------------------------------------------------------------------- | |
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33 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
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34 | SIGNAL sample_val : STD_LOGIC; | |
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35 | SIGNAL sample_val_delay : STD_LOGIC; | |
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36 | ----------------------------------------------------------------------------- | |
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37 | CONSTANT Coef_SZ : integer := 9; | |
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38 | CONSTANT CoefCntPerCel: integer := 6; | |
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39 | CONSTANT CoefPerCel : integer := 5; | |
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40 | CONSTANT Cels_count : integer := 5; | |
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41 | ||
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42 | signal coefs : std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0); | |
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43 | signal coefs_JC : std_logic_vector((Coef_SZ*CoefPerCel*Cels_count)-1 downto 0); | |
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44 | signal sample_filter_in : samplT(ChanelCount-1 downto 0,17 downto 0); | |
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45 | signal sample_filter_out : samplT(ChanelCount-1 downto 0,17 downto 0); | |
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46 | -- | |
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47 | signal sample_filter_JC_out_val : STD_LOGIC; | |
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48 | signal sample_filter_JC_out : samplT(ChanelCount-1 downto 0,17 downto 0); | |
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49 | -- | |
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50 | signal sample_filter_JC_out_r_val : STD_LOGIC; | |
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51 | signal sample_filter_JC_out_r : samplT(ChanelCount-1 downto 0,17 downto 0); | |
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52 | ||
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53 | BEGIN | |
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54 | ||
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55 | -- component instantiation | |
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56 | ----------------------------------------------------------------------------- | |
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57 | DIGITAL_acquisition: ADS7886_drvr | |
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58 | GENERIC MAP ( | |
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59 | ChanelCount => ChanelCount, | |
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60 | ncycle_cnv_high => ncycle_cnv_high, | |
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61 | ncycle_cnv => ncycle_cnv) | |
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62 | PORT MAP ( | |
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63 | cnv_clk => cnv_clk, -- | |
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64 | cnv_rstn => cnv_rstn, -- | |
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65 | cnv_run => cnv_run, -- | |
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66 | cnv => cnv, -- | |
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67 | clk => clk, -- | |
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68 | rstn => rstn, -- | |
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69 | sck => sck, -- | |
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70 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
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71 | sample => sample, | |
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72 | sample_val => sample_val); | |
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73 | ||
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74 | ----------------------------------------------------------------------------- | |
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75 | ||
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76 | PROCESS (clk, rstn) | |
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77 | BEGIN -- PROCESS | |
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78 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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79 | sample_val_delay <= '0'; | |
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80 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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81 | sample_val_delay <= sample_val; | |
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82 | END IF; | |
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83 | END PROCESS; | |
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84 | ||
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85 | ----------------------------------------------------------------------------- | |
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86 | ChanelLoop: for i in 0 to ChanelCount-1 generate | |
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87 | SampleLoop: for j in 0 to 15 generate | |
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88 | sample_filter_in(i,j) <= sample(i)(j); | |
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89 | end generate; | |
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90 | ||
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91 | sample_filter_in(i,16) <= sample(i)(15); | |
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92 | sample_filter_in(i,17) <= sample(i)(15); | |
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93 | end generate; | |
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94 | ||
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95 | coefs <= CoefsInitValCst; | |
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96 | coefs_JC <= CoefsInitValCst_JC; | |
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97 | ||
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98 | FILTER: IIR_CEL_CTRLR | |
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99 | GENERIC MAP ( | |
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100 | tech => 0, | |
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101 | Sample_SZ => 18, | |
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102 | ChanelsCount => ChanelCount, | |
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103 | Coef_SZ => Coef_SZ, | |
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104 | CoefCntPerCel => CoefCntPerCel, | |
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105 | Cels_count => Cels_count, | |
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106 | Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis | |
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107 | PORT MAP ( | |
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108 | reset => rstn, | |
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109 | clk => clk, | |
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110 | sample_clk => sample_val_delay, | |
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111 | sample_in => sample_filter_in, | |
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112 | sample_out => sample_filter_out, | |
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113 | virg_pos => 7, | |
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114 | GOtest => OPEN, | |
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115 | coefs => coefs); | |
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116 | ||
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117 | IIR_CEL_CTRLR_v2_1: IIR_CEL_CTRLR_v2 | |
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118 | GENERIC MAP ( | |
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119 | tech => 0, | |
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120 | Mem_use => use_CEL, | |
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121 | Sample_SZ => 18, | |
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122 | Coef_SZ => Coef_SZ, | |
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123 | Coef_Nb => 25, -- TODO | |
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124 | Coef_sel_SZ => 5, -- TODO | |
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125 | Cels_count => Cels_count, | |
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126 | ChanelsCount => ChanelCount) | |
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127 | PORT MAP ( | |
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128 | rstn => rstn, | |
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129 | clk => clk, | |
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130 | virg_pos => 7, | |
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131 | coefs => coefs_JC, | |
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132 | sample_in_val => sample_val_delay, | |
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133 | sample_in => sample_filter_in, | |
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134 | sample_out_val => sample_filter_JC_out_val, | |
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135 | sample_out => sample_filter_JC_out); | |
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136 | ||
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137 | ----------------------------------------------------------------------------- | |
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138 | PROCESS (clk, rstn) | |
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139 | BEGIN -- PROCESS | |
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140 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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141 | sample_filter_JC_out_r_val <= '0'; | |
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142 | rst_all_chanel: FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
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143 | rst_all_bits: FOR J IN 17 DOWNTO 0 LOOP | |
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144 | sample_filter_JC_out_r(I,J) <= '0'; | |
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145 | END LOOP rst_all_bits; | |
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146 | END LOOP rst_all_chanel; | |
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147 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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148 | sample_filter_JC_out_r_val <= sample_filter_JC_out_val; | |
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149 | IF sample_filter_JC_out_val = '1' THEN | |
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150 | sample_filter_JC_out_r <= sample_filter_JC_out; | |
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151 | END IF; | |
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152 | END IF; | |
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153 | END PROCESS; | |
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154 | ||
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155 | END tb; | |
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1 | ||
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2 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd | |
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3 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd | |
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4 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd | |
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5 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd | |
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6 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd | |
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7 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd | |
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8 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
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9 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd | |
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10 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd | |
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11 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd | |
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12 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd | |
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13 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd | |
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14 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd | |
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15 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd | |
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16 | vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd | |
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17 | ||
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18 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd | |
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19 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
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20 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd | |
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21 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd | |
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22 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd | |
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23 | ||
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24 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd | |
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25 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
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26 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |
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27 | vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |
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28 | ||
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29 | ||
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30 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd | |
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31 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd | |
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32 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd | |
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33 | ||
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34 | vcom -quiet -93 -work work Top_Data_Acquisition.vhd | |
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35 | vcom -quiet -93 -work work TB_Data_Acquisition.vhd | |
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36 | ||
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37 | vsim work.TB_Data_Acquisition | |
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38 | ||
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39 | log -r * | |
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40 | do wave_data_acquisition.do | |
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41 | run 5 ms No newline at end of file | |
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1 | onerror {resume} | |
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2 | quietly WaveActivateNextPane {} 0 | |
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3 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/chanelcount | |
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4 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv_high | |
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5 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv | |
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6 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_clk | |
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7 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_rstn | |
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8 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run | |
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9 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv | |
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10 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/clk | |
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11 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/rstn | |
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12 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sck | |
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13 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sdo | |
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14 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample | |
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15 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val | |
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16 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_cycle_counter | |
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17 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_s | |
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18 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync | |
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19 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync_r | |
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20 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_done | |
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21 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_bit_counter | |
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22 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/shift_reg | |
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23 | add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run_sync | |
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24 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/tech | |
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25 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_sz | |
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26 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/chanelscount | |
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27 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coef_sz | |
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28 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefcntpercel | |
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29 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/cels_count | |
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30 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/mem_use | |
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31 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/reset | |
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32 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/clk | |
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33 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk | |
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34 | add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in | |
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35 | add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out | |
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36 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos | |
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37 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest | |
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38 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs | |
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39 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old | |
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40 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel | |
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41 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read | |
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42 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr | |
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43 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count | |
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44 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write | |
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45 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel | |
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46 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0 | |
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47 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in | |
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48 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk | |
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49 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out | |
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50 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl | |
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51 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in | |
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52 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in | |
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53 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out | |
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54 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel | |
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55 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan | |
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56 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff | |
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57 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff | |
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58 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg | |
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59 | add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state | |
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60 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run | |
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61 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv | |
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62 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck | |
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63 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo | |
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64 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk | |
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65 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn | |
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66 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk | |
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67 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn | |
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68 | add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample | |
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69 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val | |
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70 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs | |
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71 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in | |
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72 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out | |
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73 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state | |
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74 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff | |
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75 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing | |
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76 | add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing | |
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77 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk | |
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78 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset | |
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79 | add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl | |
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80 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1 | |
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81 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2 | |
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82 | add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res | |
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83 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input | |
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84 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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85 | add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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86 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn | |
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87 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk | |
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88 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos | |
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89 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs | |
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90 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src | |
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91 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata | |
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92 | add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input | |
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93 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write | |
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94 | add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read | |
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95 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst | |
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96 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 | |
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97 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous | |
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98 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input | |
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99 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff | |
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100 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl | |
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101 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in | |
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102 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out | |
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103 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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104 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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105 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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106 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample | |
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107 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s | |
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108 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff | |
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109 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s | |
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110 | add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef | |
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111 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn | |
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112 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk | |
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113 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos | |
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114 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs | |
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115 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
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116 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
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117 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
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118 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
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119 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src | |
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120 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata | |
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121 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write | |
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122 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read | |
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123 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst | |
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124 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1 | |
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125 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous | |
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126 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input | |
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127 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff | |
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128 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl | |
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129 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf | |
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130 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate | |
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131 | add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s | |
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132 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s | |
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133 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 | |
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134 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s | |
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135 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s | |
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136 | add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 | |
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137 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src | |
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138 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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139 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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140 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in | |
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141 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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142 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous | |
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143 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write | |
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144 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata | |
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145 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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146 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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147 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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148 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input | |
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149 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read | |
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150 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst | |
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151 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1 | |
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152 | add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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153 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff | |
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154 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s | |
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155 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef | |
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156 | add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff | |
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157 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input | |
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158 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in | |
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159 | add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output | |
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160 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl | |
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161 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef | |
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162 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample | |
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163 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s | |
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164 | add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output | |
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165 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state | |
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166 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing | |
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167 | add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing | |
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168 | add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out | |
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169 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn | |
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170 | add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk | |
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171 | add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray | |
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172 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter | |
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173 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst | |
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174 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1 | |
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175 | add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous | |
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176 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write | |
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177 | add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen | |
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178 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr | |
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179 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd | |
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180 | add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in | |
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181 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read | |
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182 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren | |
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183 | add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr | |
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184 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd | |
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185 | add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out | |
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186 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val | |
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187 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in | |
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188 | add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val | |
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189 | add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out | |
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190 | add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) | |
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191 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk | |
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192 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset | |
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193 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac | |
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194 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add | |
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195 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1 | |
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196 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2 | |
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197 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res | |
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198 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add | |
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199 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult | |
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200 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout | |
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201 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina | |
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202 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb | |
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203 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout | |
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204 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel | |
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205 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz | |
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206 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz | |
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207 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel | |
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208 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d | |
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209 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d | |
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210 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d | |
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211 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d | |
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212 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d | |
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213 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d | |
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214 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d | |
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215 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d | |
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216 | add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d | |
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217 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val | |
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218 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot | |
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219 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state | |
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220 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out | |
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221 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s | |
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222 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2 | |
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223 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s | |
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224 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s | |
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225 | add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2 | |
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226 | TreeUpdate [SetDefaultTree] | |
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227 | WaveRestoreCursors {{Cursor 1} {4520000 ps} 0} | |
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228 | configure wave -namecolwidth 677 | |
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229 | configure wave -valuecolwidth 100 | |
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230 | configure wave -justifyvalue left | |
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231 | configure wave -signalnamewidth 0 | |
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232 | configure wave -snapdistance 10 | |
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233 | configure wave -datasetprefix 0 | |
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234 | configure wave -rowmargin 4 | |
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235 | configure wave -childrowmargin 2 | |
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236 | configure wave -gridoffset 0 | |
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237 | configure wave -gridperiod 1 | |
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238 | configure wave -griddelta 40 | |
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239 | configure wave -timeline 0 | |
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240 | configure wave -timelineunits ns | |
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241 | update | |
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242 | WaveRestoreZoom {2722930 ps} {6210191 ps} | |
| @@ -0,0 +1,256 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
|
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe PELLION | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | ||
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23 | LIBRARY IEEE; | |
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24 | USE IEEE.numeric_std.ALL; | |
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25 | USE IEEE.std_logic_1164.ALL; | |
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26 | ||
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27 | LIBRARY techmap; | |
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28 | USE techmap.gencomp.ALL; | |
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29 | ||
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30 | LIBRARY lpp; | |
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31 | USE lpp.iir_filter.ALL; | |
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32 | USE lpp.general_purpose.ALL; | |
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33 | ||
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34 | ENTITY IIR_CEL_CTRLR_v2 IS | |
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35 | GENERIC ( | |
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36 | tech : INTEGER := apa3; | |
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37 | Mem_use : INTEGER := use_RAM; | |
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38 | Sample_SZ : INTEGER := 18; | |
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39 | Coef_SZ : INTEGER := 9; | |
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40 | Coef_Nb : INTEGER := 25; | |
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41 | Coef_sel_SZ : INTEGER := 5; | |
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42 | Cels_count : INTEGER := 5; | |
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|
43 | ChanelsCount : INTEGER := 8); | |
|
|
44 | PORT ( | |
|
|
45 | rstn : IN STD_LOGIC; | |
|
|
46 | clk : IN STD_LOGIC; | |
|
|
47 | ||
|
|
48 | virg_pos : IN INTEGER; | |
|
|
49 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
|
|
50 | ||
|
|
51 | sample_in_val : IN STD_LOGIC; | |
|
|
52 | sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
|
|
53 | ||
|
|
54 | sample_out_val : OUT STD_LOGIC; | |
|
|
55 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |
|
|
56 | END IIR_CEL_CTRLR_v2; | |
|
|
57 | ||
|
|
58 | ARCHITECTURE ar_IIR_CEL_CTRLR_v2 OF IIR_CEL_CTRLR_v2 IS | |
|
|
59 | ||
|
|
60 | COMPONENT IIR_CEL_CTRLR_v2_DATAFLOW | |
|
|
61 | GENERIC ( | |
|
|
62 | tech : INTEGER; | |
|
|
63 | Mem_use : INTEGER; | |
|
|
64 | Sample_SZ : INTEGER; | |
|
|
65 | Coef_SZ : INTEGER; | |
|
|
66 | Coef_Nb : INTEGER; | |
|
|
67 | Coef_sel_SZ : INTEGER); | |
|
|
68 | PORT ( | |
|
|
69 | rstn : IN STD_LOGIC; | |
|
|
70 | clk : IN STD_LOGIC; | |
|
|
71 | virg_pos : IN INTEGER; | |
|
|
72 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
|
|
73 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
74 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
75 | ram_write : IN STD_LOGIC; | |
|
|
76 | ram_read : IN STD_LOGIC; | |
|
|
77 | raddr_rst : IN STD_LOGIC; | |
|
|
78 | raddr_add1 : IN STD_LOGIC; | |
|
|
79 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
80 | alu_sel_input : IN STD_LOGIC; | |
|
|
81 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
|
|
82 | alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
|
83 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
84 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); | |
|
|
85 | END COMPONENT; | |
|
|
86 | ||
|
|
87 | COMPONENT IIR_CEL_CTRLR_v2_CONTROL | |
|
|
88 | GENERIC ( | |
|
|
89 | Coef_sel_SZ : INTEGER; | |
|
|
90 | Cels_count : INTEGER; | |
|
|
91 | ChanelsCount : INTEGER); | |
|
|
92 | PORT ( | |
|
|
93 | rstn : IN STD_LOGIC; | |
|
|
94 | clk : IN STD_LOGIC; | |
|
|
95 | sample_in_val : IN STD_LOGIC; | |
|
|
96 | sample_in_rot : OUT STD_LOGIC; | |
|
|
97 | sample_out_val : OUT STD_LOGIC; | |
|
|
98 | sample_out_rot : OUT STD_LOGIC; | |
|
|
99 | in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
100 | ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
101 | ram_write : OUT STD_LOGIC; | |
|
|
102 | ram_read : OUT STD_LOGIC; | |
|
|
103 | raddr_rst : OUT STD_LOGIC; | |
|
|
104 | raddr_add1 : OUT STD_LOGIC; | |
|
|
105 | waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
106 | alu_sel_input : OUT STD_LOGIC; | |
|
|
107 | alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
|
|
108 | alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
|
|
109 | END COMPONENT; | |
|
|
110 | ||
|
|
111 | SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
112 | SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
113 | SIGNAL ram_write : STD_LOGIC; | |
|
|
114 | SIGNAL ram_read : STD_LOGIC; | |
|
|
115 | SIGNAL raddr_rst : STD_LOGIC; | |
|
|
116 | SIGNAL raddr_add1 : STD_LOGIC; | |
|
|
117 | SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
118 | SIGNAL alu_sel_input : STD_LOGIC; | |
|
|
119 | SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
|
|
120 | SIGNAL alu_ctrl : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
|
121 | ||
|
|
122 | SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
|
|
123 | SIGNAL sample_in_rotate : STD_LOGIC; | |
|
|
124 | SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
125 | SIGNAL sample_out_val_s : STD_LOGIC; | |
|
|
126 | SIGNAL sample_out_val_s2 : STD_LOGIC; | |
|
|
127 | SIGNAL sample_out_rot_s : STD_LOGIC; | |
|
|
128 | SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
129 | ||
|
|
130 | SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |
|
|
131 | ||
|
|
132 | BEGIN | |
|
|
133 | ||
|
|
134 | IIR_CEL_CTRLR_v2_DATAFLOW_1 : IIR_CEL_CTRLR_v2_DATAFLOW | |
|
|
135 | GENERIC MAP ( | |
|
|
136 | tech => tech, | |
|
|
137 | Mem_use => Mem_use, | |
|
|
138 | Sample_SZ => Sample_SZ, | |
|
|
139 | Coef_SZ => Coef_SZ, | |
|
|
140 | Coef_Nb => Coef_Nb, | |
|
|
141 | Coef_sel_SZ => Coef_sel_SZ) | |
|
|
142 | PORT MAP ( | |
|
|
143 | rstn => rstn, | |
|
|
144 | clk => clk, | |
|
|
145 | virg_pos => virg_pos, | |
|
|
146 | coefs => coefs, | |
|
|
147 | --CTRL | |
|
|
148 | in_sel_src => in_sel_src, | |
|
|
149 | ram_sel_Wdata => ram_sel_Wdata, | |
|
|
150 | ram_write => ram_write, | |
|
|
151 | ram_read => ram_read, | |
|
|
152 | raddr_rst => raddr_rst, | |
|
|
153 | raddr_add1 => raddr_add1, | |
|
|
154 | waddr_previous => waddr_previous, | |
|
|
155 | alu_sel_input => alu_sel_input, | |
|
|
156 | alu_sel_coeff => alu_sel_coeff, | |
|
|
157 | alu_ctrl => alu_ctrl, | |
|
|
158 | --DATA | |
|
|
159 | sample_in => sample_in_s, | |
|
|
160 | sample_out => sample_out_s); | |
|
|
161 | ||
|
|
162 | ||
|
|
163 | IIR_CEL_CTRLR_v2_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL | |
|
|
164 | GENERIC MAP ( | |
|
|
165 | Coef_sel_SZ => Coef_sel_SZ, | |
|
|
166 | Cels_count => Cels_count, | |
|
|
167 | ChanelsCount => ChanelsCount) | |
|
|
168 | PORT MAP ( | |
|
|
169 | rstn => rstn, | |
|
|
170 | clk => clk, | |
|
|
171 | sample_in_val => sample_in_val, | |
|
|
172 | sample_in_rot => sample_in_rotate, | |
|
|
173 | sample_out_val => sample_out_val_s, | |
|
|
174 | sample_out_rot => sample_out_rot_s, | |
|
|
175 | ||
|
|
176 | in_sel_src => in_sel_src, | |
|
|
177 | ram_sel_Wdata => ram_sel_Wdata, | |
|
|
178 | ram_write => ram_write, | |
|
|
179 | ram_read => ram_read, | |
|
|
180 | raddr_rst => raddr_rst, | |
|
|
181 | raddr_add1 => raddr_add1, | |
|
|
182 | waddr_previous => waddr_previous, | |
|
|
183 | alu_sel_input => alu_sel_input, | |
|
|
184 | alu_sel_coeff => alu_sel_coeff, | |
|
|
185 | alu_ctrl => alu_ctrl); | |
|
|
186 | ||
|
|
187 | ----------------------------------------------------------------------------- | |
|
|
188 | -- SAMPLE IN | |
|
|
189 | ----------------------------------------------------------------------------- | |
|
|
190 | loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE | |
|
|
191 | ||
|
|
192 | loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE | |
|
|
193 | PROCESS (clk, rstn) | |
|
|
194 | BEGIN -- PROCESS | |
|
|
195 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
196 | sample_in_buf(I, J) <= '0'; | |
|
|
197 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
198 | IF sample_in_val = '1' THEN | |
|
|
199 | sample_in_buf(I, J) <= sample_in(I, J); | |
|
|
200 | ELSIF sample_in_rotate = '1' THEN | |
|
|
201 | sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); | |
|
|
202 | END IF; | |
|
|
203 | END IF; | |
|
|
204 | END PROCESS; | |
|
|
205 | END GENERATE loop_all_chanel; | |
|
|
206 | ||
|
|
207 | sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); | |
|
|
208 | ||
|
|
209 | END GENERATE loop_all_sample; | |
|
|
210 | ||
|
|
211 | ----------------------------------------------------------------------------- | |
|
|
212 | -- SAMPLE OUT | |
|
|
213 | ----------------------------------------------------------------------------- | |
|
|
214 | PROCESS (clk, rstn) | |
|
|
215 | BEGIN -- PROCESS | |
|
|
216 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
217 | sample_out_val <= '0'; | |
|
|
218 | sample_out_val_s2 <= '0'; | |
|
|
219 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
220 | sample_out_val <= sample_out_val_s2; | |
|
|
221 | sample_out_val_s2 <= sample_out_val_s; | |
|
|
222 | END IF; | |
|
|
223 | END PROCESS; | |
|
|
224 | ||
|
|
225 | chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE | |
|
|
226 | PROCESS (clk, rstn) | |
|
|
227 | BEGIN -- PROCESS | |
|
|
228 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
229 | sample_out_s2(ChanelsCount-1, I) <= '0'; | |
|
|
230 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
231 | IF sample_out_rot_s = '1' THEN | |
|
|
232 | sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); | |
|
|
233 | END IF; | |
|
|
234 | END IF; | |
|
|
235 | END PROCESS; | |
|
|
236 | END GENERATE chanel_HIGH; | |
|
|
237 | ||
|
|
238 | chanel_more : IF ChanelsCount > 1 GENERATE | |
|
|
239 | all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE | |
|
|
240 | all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE | |
|
|
241 | PROCESS (clk, rstn) | |
|
|
242 | BEGIN -- PROCESS | |
|
|
243 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
244 | sample_out_s2(J-1, I) <= '0'; | |
|
|
245 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
246 | IF sample_out_rot_s = '1' THEN | |
|
|
247 | sample_out_s2(J-1, I) <= sample_out_s2(J, I); | |
|
|
248 | END IF; | |
|
|
249 | END IF; | |
|
|
250 | END PROCESS; | |
|
|
251 | END GENERATE all_bit; | |
|
|
252 | END GENERATE all_chanel; | |
|
|
253 | END GENERATE chanel_more; | |
|
|
254 | ||
|
|
255 | sample_out <= sample_out_s2; | |
|
|
256 | END ar_IIR_CEL_CTRLR_v2; | |
| @@ -0,0 +1,313 | |||
|
|
1 | ------------------------------------------------------------------------------ | |
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
|
4 | -- | |
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
|
8 | -- (at your option) any later version. | |
|
|
9 | -- | |
|
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
|
13 | -- GNU General Public License for more Cdetails. | |
|
|
14 | -- | |
|
|
15 | -- You should have received a copy of the GNU General Public License | |
|
|
16 | -- along with this program; if not, write to the Free Software | |
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
|
18 | ------------------------------------------------------------------------------- | |
|
|
19 | -- Author : Jean-christophe PELLION | |
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
|
21 | ------------------------------------------------------------------------------- | |
|
|
22 | ||
|
|
23 | LIBRARY IEEE; | |
|
|
24 | USE IEEE.numeric_std.ALL; | |
|
|
25 | USE IEEE.std_logic_1164.ALL; | |
|
|
26 | LIBRARY lpp; | |
|
|
27 | USE lpp.iir_filter.ALL; | |
|
|
28 | USE lpp.general_purpose.ALL; | |
|
|
29 | ||
|
|
30 | ENTITY IIR_CEL_CTRLR_v2_CONTROL IS | |
|
|
31 | GENERIC ( | |
|
|
32 | Coef_sel_SZ : INTEGER; | |
|
|
33 | Cels_count : INTEGER := 5; | |
|
|
34 | ChanelsCount : INTEGER := 1); | |
|
|
35 | PORT ( | |
|
|
36 | rstn : IN STD_LOGIC; | |
|
|
37 | clk : IN STD_LOGIC; | |
|
|
38 | ||
|
|
39 | sample_in_val : IN STD_LOGIC; | |
|
|
40 | sample_in_rot : OUT STD_LOGIC; | |
|
|
41 | sample_out_val : OUT STD_LOGIC; | |
|
|
42 | sample_out_rot : OUT STD_LOGIC; | |
|
|
43 | ||
|
|
44 | in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
45 | ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
46 | ram_write : OUT STD_LOGIC; | |
|
|
47 | ram_read : OUT STD_LOGIC; | |
|
|
48 | raddr_rst : OUT STD_LOGIC; | |
|
|
49 | raddr_add1 : OUT STD_LOGIC; | |
|
|
50 | waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
51 | alu_sel_input : OUT STD_LOGIC; | |
|
|
52 | alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
|
|
53 | alu_ctrl : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
|
54 | ); | |
|
|
55 | END IIR_CEL_CTRLR_v2_CONTROL; | |
|
|
56 | ||
|
|
57 | ARCHITECTURE ar_IIR_CEL_CTRLR_v2_CONTROL OF IIR_CEL_CTRLR_v2_CONTROL IS | |
|
|
58 | ||
|
|
59 | TYPE fsmIIR_CEL_T IS (waiting, | |
|
|
60 | first_read, | |
|
|
61 | compute_b0, | |
|
|
62 | compute_b1, | |
|
|
63 | compute_b2, | |
|
|
64 | compute_a1, | |
|
|
65 | compute_a2, | |
|
|
66 | LAST_CEL, | |
|
|
67 | wait_valid_last_output, | |
|
|
68 | wait_valid_last_output_2); | |
|
|
69 | SIGNAL IIR_CEL_STATE : fsmIIR_CEL_T; | |
|
|
70 | ||
|
|
71 | SIGNAL alu_selected_coeff : INTEGER; | |
|
|
72 | SIGNAL Chanel_ongoing : INTEGER; | |
|
|
73 | SIGNAL Cel_ongoing : INTEGER; | |
|
|
74 | ||
|
|
75 | BEGIN | |
|
|
76 | ||
|
|
77 | alu_sel_coeff <= STD_LOGIC_VECTOR(to_unsigned(alu_selected_coeff, Coef_sel_SZ)); | |
|
|
78 | ||
|
|
79 | PROCESS (clk, rstn) | |
|
|
80 | BEGIN -- PROCESS | |
|
|
81 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
82 | --REG ------------------------------------------------------------------- | |
|
|
83 | in_sel_src <= (OTHERS => '0'); -- | |
|
|
84 | --RAM_WRitE ------------------------------------------------------------- | |
|
|
85 | ram_sel_Wdata <= "00"; -- | |
|
|
86 | ram_write <= '0'; -- | |
|
|
87 | waddr_previous <= "00"; -- | |
|
|
88 | --RAM_READ -------------------------------------------------------------- | |
|
|
89 | ram_read <= '0'; -- | |
|
|
90 | raddr_rst <= '0'; -- | |
|
|
91 | raddr_add1 <= '0'; -- | |
|
|
92 | --ALU ------------------------------------------------------------------- | |
|
|
93 | alu_selected_coeff <= 0; -- | |
|
|
94 | alu_sel_input <= '0'; -- | |
|
|
95 | alu_ctrl <= (OTHERS => '0'); -- | |
|
|
96 | --OUT | |
|
|
97 | sample_out_val <= '0'; -- | |
|
|
98 | sample_out_rot <= '0'; -- | |
|
|
99 | ||
|
|
100 | Chanel_ongoing <= 0; -- | |
|
|
101 | Cel_ongoing <= 0; -- | |
|
|
102 | sample_in_rot <= '0'; | |
|
|
103 | ||
|
|
104 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
105 | ||
|
|
106 | CASE IIR_CEL_STATE IS | |
|
|
107 | WHEN waiting => | |
|
|
108 | sample_out_rot <= '0'; | |
|
|
109 | sample_in_rot <= '0'; | |
|
|
110 | sample_out_val <= '0'; | |
|
|
111 | alu_ctrl <= "0100"; | |
|
|
112 | alu_selected_coeff <= 0; | |
|
|
113 | in_sel_src <= "01"; | |
|
|
114 | ram_read <= '0'; | |
|
|
115 | ram_sel_Wdata <= "00"; | |
|
|
116 | ram_write <= '0'; | |
|
|
117 | waddr_previous <= "00"; | |
|
|
118 | IF sample_in_val = '1' THEN | |
|
|
119 | raddr_rst <= '0'; | |
|
|
120 | alu_sel_input <= '1'; | |
|
|
121 | ram_read <= '1'; | |
|
|
122 | raddr_add1 <= '1'; | |
|
|
123 | IIR_CEL_STATE <= first_read; | |
|
|
124 | Chanel_ongoing <= Chanel_ongoing + 1; | |
|
|
125 | Cel_ongoing <= 1; | |
|
|
126 | ELSE | |
|
|
127 | raddr_add1 <= '0'; | |
|
|
128 | raddr_rst <= '1'; | |
|
|
129 | Chanel_ongoing <= 0; | |
|
|
130 | Cel_ongoing <= 0; | |
|
|
131 | END IF; | |
|
|
132 | ||
|
|
133 | WHEN first_read => | |
|
|
134 | IIR_CEL_STATE <= compute_b2; | |
|
|
135 | ram_read <= '1'; | |
|
|
136 | raddr_add1 <= '1'; | |
|
|
137 | alu_ctrl <= "0010"; | |
|
|
138 | alu_sel_input <= '1'; | |
|
|
139 | in_sel_src <= "01"; | |
|
|
140 | ||
|
|
141 | ||
|
|
142 | WHEN compute_b2 => | |
|
|
143 | sample_out_rot <= '0'; | |
|
|
144 | ||
|
|
145 | sample_in_rot <= '0'; | |
|
|
146 | sample_out_val <= '0'; | |
|
|
147 | ||
|
|
148 | alu_sel_input <= '1'; | |
|
|
149 | -- | |
|
|
150 | ram_sel_Wdata <= "10"; | |
|
|
151 | ram_write <= '1'; | |
|
|
152 | waddr_previous <= "10"; | |
|
|
153 | -- | |
|
|
154 | ram_read <= '1'; | |
|
|
155 | raddr_rst <= '0'; | |
|
|
156 | raddr_add1 <= '0'; | |
|
|
157 | IF Cel_ongoing = 1 THEN | |
|
|
158 | in_sel_src <= "00"; | |
|
|
159 | ELSE | |
|
|
160 | in_sel_src <= "11"; | |
|
|
161 | END IF; | |
|
|
162 | alu_selected_coeff <= alu_selected_coeff+1; | |
|
|
163 | alu_ctrl <= "0001"; | |
|
|
164 | IIR_CEL_STATE <= compute_b1; | |
|
|
165 | ||
|
|
166 | WHEN compute_b1 => | |
|
|
167 | sample_in_rot <= '0'; | |
|
|
168 | alu_sel_input <= '0'; | |
|
|
169 | -- | |
|
|
170 | ram_sel_Wdata <= "00"; | |
|
|
171 | ram_write <= '1'; | |
|
|
172 | waddr_previous <= "01"; | |
|
|
173 | -- | |
|
|
174 | ram_read <= '1'; | |
|
|
175 | raddr_rst <= '0'; | |
|
|
176 | raddr_add1 <= '1'; | |
|
|
177 | sample_out_rot <= '0'; | |
|
|
178 | IF Cel_ongoing = 1 THEN | |
|
|
179 | in_sel_src <= "10"; | |
|
|
180 | sample_out_val <= '0'; | |
|
|
181 | ELSE | |
|
|
182 | sample_out_val <= '0'; | |
|
|
183 | in_sel_src <= "00"; | |
|
|
184 | END IF; | |
|
|
185 | alu_selected_coeff <= alu_selected_coeff+1; | |
|
|
186 | alu_ctrl <= "0001"; | |
|
|
187 | IIR_CEL_STATE <= compute_b0; | |
|
|
188 | ||
|
|
189 | WHEN compute_b0 => | |
|
|
190 | sample_out_rot <= '0'; | |
|
|
191 | sample_out_val <= '0'; | |
|
|
192 | sample_in_rot <= '0'; | |
|
|
193 | alu_sel_input <= '1'; | |
|
|
194 | ram_sel_Wdata <= "00"; | |
|
|
195 | ram_write <= '0'; | |
|
|
196 | waddr_previous <= "01"; | |
|
|
197 | ram_read <= '1'; | |
|
|
198 | raddr_rst <= '0'; | |
|
|
199 | raddr_add1 <= '0'; | |
|
|
200 | in_sel_src <= "10"; | |
|
|
201 | alu_selected_coeff <= alu_selected_coeff+1; | |
|
|
202 | alu_ctrl <= "0001"; | |
|
|
203 | IIR_CEL_STATE <= compute_a2; | |
|
|
204 | IF Cel_ongoing = Cels_count THEN | |
|
|
205 | sample_in_rot <= '1'; | |
|
|
206 | ELSE | |
|
|
207 | sample_in_rot <= '0'; | |
|
|
208 | END IF; | |
|
|
209 | ||
|
|
210 | WHEN compute_a2 => | |
|
|
211 | sample_out_val <= '0'; | |
|
|
212 | sample_out_rot <= '0'; | |
|
|
213 | alu_sel_input <= '1'; | |
|
|
214 | ram_sel_Wdata <= "00"; | |
|
|
215 | ram_write <= '0'; | |
|
|
216 | waddr_previous <= "01"; | |
|
|
217 | ram_read <= '1'; | |
|
|
218 | raddr_rst <= '0'; | |
|
|
219 | IF Cel_ongoing = Cels_count THEN | |
|
|
220 | raddr_add1 <= '1'; | |
|
|
221 | ELSE | |
|
|
222 | raddr_add1 <= '0'; | |
|
|
223 | END IF; | |
|
|
224 | in_sel_src <= "00"; | |
|
|
225 | alu_selected_coeff <= alu_selected_coeff+1; | |
|
|
226 | alu_ctrl <= "0001"; | |
|
|
227 | IIR_CEL_STATE <= compute_a1; | |
|
|
228 | sample_in_rot <= '0'; | |
|
|
229 | ||
|
|
230 | WHEN compute_a1 => | |
|
|
231 | sample_out_val <= '0'; | |
|
|
232 | sample_out_rot <= '0'; | |
|
|
233 | alu_sel_input <= '0'; | |
|
|
234 | ram_sel_Wdata <= "00"; | |
|
|
235 | ram_write <= '0'; | |
|
|
236 | waddr_previous <= "01"; | |
|
|
237 | ram_read <= '1'; | |
|
|
238 | raddr_rst <= '0'; | |
|
|
239 | alu_ctrl <= "0010"; | |
|
|
240 | sample_in_rot <= '0'; | |
|
|
241 | IF Cel_ongoing = Cels_count THEN | |
|
|
242 | alu_selected_coeff <= 0; | |
|
|
243 | ||
|
|
244 | ram_sel_Wdata <= "10"; | |
|
|
245 | raddr_add1 <= '1'; | |
|
|
246 | ram_write <= '1'; | |
|
|
247 | waddr_previous <= "10"; | |
|
|
248 | ||
|
|
249 | IF Chanel_ongoing = ChanelsCount THEN | |
|
|
250 | IIR_CEL_STATE <= wait_valid_last_output; | |
|
|
251 | ELSE | |
|
|
252 | Chanel_ongoing <= Chanel_ongoing + 1; | |
|
|
253 | Cel_ongoing <= 1; | |
|
|
254 | IIR_CEL_STATE <= LAST_CEL; | |
|
|
255 | in_sel_src <= "01"; | |
|
|
256 | END IF; | |
|
|
257 | ELSE | |
|
|
258 | raddr_add1 <= '1'; | |
|
|
259 | alu_selected_coeff <= alu_selected_coeff+1; | |
|
|
260 | Cel_ongoing <= Cel_ongoing+1; | |
|
|
261 | IIR_CEL_STATE <= compute_b2; | |
|
|
262 | END IF; | |
|
|
263 | ||
|
|
264 | WHEN LAST_CEL => | |
|
|
265 | alu_sel_input <= '1'; | |
|
|
266 | IIR_CEL_STATE <= compute_b2; | |
|
|
267 | raddr_add1 <= '1'; | |
|
|
268 | ram_sel_Wdata <= "01"; | |
|
|
269 | ram_write <= '1'; | |
|
|
270 | waddr_previous <= "10"; | |
|
|
271 | sample_out_rot <= '1'; | |
|
|
272 | ||
|
|
273 | ||
|
|
274 | WHEN wait_valid_last_output => | |
|
|
275 | IIR_CEL_STATE <= wait_valid_last_output_2; | |
|
|
276 | sample_in_rot <= '0'; | |
|
|
277 | alu_ctrl <= "0000"; | |
|
|
278 | alu_selected_coeff <= 0; | |
|
|
279 | in_sel_src <= "01"; | |
|
|
280 | ram_read <= '0'; | |
|
|
281 | raddr_rst <= '1'; | |
|
|
282 | raddr_add1 <= '1'; | |
|
|
283 | ram_sel_Wdata <= "01"; | |
|
|
284 | ram_write <= '1'; | |
|
|
285 | waddr_previous <= "10"; | |
|
|
286 | Chanel_ongoing <= 0; | |
|
|
287 | Cel_ongoing <= 0; | |
|
|
288 | sample_out_val <= '0'; | |
|
|
289 | sample_out_rot <= '1'; | |
|
|
290 | ||
|
|
291 | WHEN wait_valid_last_output_2 => | |
|
|
292 | IIR_CEL_STATE <= waiting; | |
|
|
293 | sample_in_rot <= '0'; | |
|
|
294 | alu_ctrl <= "0000"; | |
|
|
295 | alu_selected_coeff <= 0; | |
|
|
296 | in_sel_src <= "01"; | |
|
|
297 | ram_read <= '0'; | |
|
|
298 | raddr_rst <= '1'; | |
|
|
299 | raddr_add1 <= '1'; | |
|
|
300 | ram_sel_Wdata <= "10"; | |
|
|
301 | ram_write <= '1'; | |
|
|
302 | waddr_previous <= "10"; | |
|
|
303 | Chanel_ongoing <= 0; | |
|
|
304 | Cel_ongoing <= 0; | |
|
|
305 | sample_out_val <= '1'; | |
|
|
306 | sample_out_rot <= '0'; | |
|
|
307 | WHEN OTHERS => NULL; | |
|
|
308 | END CASE; | |
|
|
309 | ||
|
|
310 | END IF; | |
|
|
311 | END PROCESS; | |
|
|
312 | ||
|
|
313 | END ar_IIR_CEL_CTRLR_v2_CONTROL; | |
| @@ -0,0 +1,248 | |||
|
|
1 | ------------------------------------------------------------------------------ | |
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
|
4 | -- | |
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
|
8 | -- (at your option) any later version. | |
|
|
9 | -- | |
|
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
|
13 | -- GNU General Public License for more details. | |
|
|
14 | -- | |
|
|
15 | -- You should have received a copy of the GNU General Public License | |
|
|
16 | -- along with this program; if not, write to the Free Software | |
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
|
18 | ------------------------------------------------------------------------------- | |
|
|
19 | -- Author : Jean-christophe PELLION | |
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
|
21 | ------------------------------------------------------------------------------- | |
|
|
22 | LIBRARY IEEE; | |
|
|
23 | USE IEEE.numeric_std.ALL; | |
|
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
|
25 | LIBRARY lpp; | |
|
|
26 | USE lpp.iir_filter.ALL; | |
|
|
27 | USE lpp.general_purpose.ALL; | |
|
|
28 | ||
|
|
29 | ||
|
|
30 | ||
|
|
31 | ENTITY IIR_CEL_CTRLR_v2_DATAFLOW IS | |
|
|
32 | GENERIC( | |
|
|
33 | tech : INTEGER := 0; | |
|
|
34 | Mem_use : INTEGER := use_RAM; | |
|
|
35 | Sample_SZ : INTEGER := 16; | |
|
|
36 | Coef_SZ : INTEGER := 9; | |
|
|
37 | Coef_Nb : INTEGER := 30; | |
|
|
38 | Coef_sel_SZ : INTEGER := 5 | |
|
|
39 | ); | |
|
|
40 | PORT( | |
|
|
41 | rstn : IN STD_LOGIC; | |
|
|
42 | clk : IN STD_LOGIC; | |
|
|
43 | -- PARAMETER | |
|
|
44 | virg_pos : IN INTEGER; | |
|
|
45 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |
|
|
46 | -- CONTROL | |
|
|
47 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
48 | -- | |
|
|
49 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
50 | ram_write : IN STD_LOGIC; | |
|
|
51 | ram_read : IN STD_LOGIC; | |
|
|
52 | raddr_rst : IN STD_LOGIC; | |
|
|
53 | raddr_add1 : IN STD_LOGIC; | |
|
|
54 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
55 | -- | |
|
|
56 | alu_sel_input : IN STD_LOGIC; | |
|
|
57 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |
|
|
58 | alu_ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) | |
|
|
59 | -- DATA | |
|
|
60 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
61 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) | |
|
|
62 | ); | |
|
|
63 | END IIR_CEL_CTRLR_v2_DATAFLOW; | |
|
|
64 | ||
|
|
65 | ARCHITECTURE ar_IIR_CEL_CTRLR_v2_DATAFLOW OF IIR_CEL_CTRLR_v2_DATAFLOW IS | |
|
|
66 | ||
|
|
67 | COMPONENT RAM_CTRLR_v2 | |
|
|
68 | GENERIC ( | |
|
|
69 | tech : INTEGER; | |
|
|
70 | Input_SZ_1 : INTEGER; | |
|
|
71 | Mem_use : INTEGER); | |
|
|
72 | PORT ( | |
|
|
73 | rstn : IN STD_LOGIC; | |
|
|
74 | clk : IN STD_LOGIC; | |
|
|
75 | ram_write : IN STD_LOGIC; | |
|
|
76 | ram_read : IN STD_LOGIC; | |
|
|
77 | raddr_rst : IN STD_LOGIC; | |
|
|
78 | raddr_add1 : IN STD_LOGIC; | |
|
|
79 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
80 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
|
81 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); | |
|
|
82 | END COMPONENT; | |
|
|
83 | ||
|
|
84 | SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
85 | SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
86 | SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
87 | SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
88 | SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |
|
|
89 | SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); | |
|
|
90 | ||
|
|
91 | SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); | |
|
|
92 | SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); | |
|
|
93 | ||
|
|
94 | SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); | |
|
|
95 | ||
|
|
96 | BEGIN | |
|
|
97 | ||
|
|
98 | ----------------------------------------------------------------------------- | |
|
|
99 | -- INPUT | |
|
|
100 | ----------------------------------------------------------------------------- | |
|
|
101 | PROCESS (clk, rstn) | |
|
|
102 | BEGIN -- PROCESS | |
|
|
103 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
104 | reg_sample_in <= (OTHERS => '0'); | |
|
|
105 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
|
106 | CASE in_sel_src IS | |
|
|
107 | WHEN "00" => reg_sample_in <= reg_sample_in; | |
|
|
108 | WHEN "01" => reg_sample_in <= sample_in; | |
|
|
109 | WHEN "10" => reg_sample_in <= ram_output; | |
|
|
110 | WHEN "11" => reg_sample_in <= alu_output; | |
|
|
111 | WHEN OTHERS => NULL; | |
|
|
112 | END CASE; | |
|
|
113 | END IF; | |
|
|
114 | END PROCESS; | |
|
|
115 | ||
|
|
116 | ||
|
|
117 | ----------------------------------------------------------------------------- | |
|
|
118 | -- RAM + CTRL | |
|
|
119 | ----------------------------------------------------------------------------- | |
|
|
120 | ||
|
|
121 | ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE | |
|
|
122 | alu_output WHEN ram_sel_Wdata = "01" ELSE | |
|
|
123 | ram_output; | |
|
|
124 | ||
|
|
125 | RAM_CTRLR_v2_1: RAM_CTRLR_v2 | |
|
|
126 | GENERIC MAP ( | |
|
|
127 | tech => tech, | |
|
|
128 | Input_SZ_1 => Sample_SZ, | |
|
|
129 | Mem_use => Mem_use) | |
|
|
130 | PORT MAP ( | |
|
|
131 | clk => clk, | |
|
|
132 | rstn => rstn, | |
|
|
133 | ram_write => ram_write, | |
|
|
134 | ram_read => ram_read, | |
|
|
135 | raddr_rst => raddr_rst, | |
|
|
136 | raddr_add1 => raddr_add1, | |
|
|
137 | waddr_previous => waddr_previous, | |
|
|
138 | sample_in => ram_input, | |
|
|
139 | sample_out => ram_output); | |
|
|
140 | ||
|
|
141 | ----------------------------------------------------------------------------- | |
|
|
142 | -- MAC_ACC | |
|
|
143 | ----------------------------------------------------------------------------- | |
|
|
144 | -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) | |
|
|
145 | -- Data In : mac_sample, mac_coef | |
|
|
146 | -- Data Out: mac_output | |
|
|
147 | ||
|
|
148 | alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; | |
|
|
149 | ||
|
|
150 | coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE | |
|
|
151 | coeff_in: IF I < Coef_Nb GENERATE | |
|
|
152 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
|
|
153 | arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); | |
|
|
154 | END GENERATE all_bit; | |
|
|
155 | END GENERATE coeff_in; | |
|
|
156 | coeff_null: IF I > (Coef_Nb -1) GENERATE | |
|
|
157 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
|
|
158 | arrayCoeff(I,J) <= '0'; | |
|
|
159 | END GENERATE all_bit; | |
|
|
160 | END GENERATE coeff_null; | |
|
|
161 | END GENERATE coefftable; | |
|
|
162 | ||
|
|
163 | Coeff_Mux : MUXN | |
|
|
164 | GENERIC MAP ( | |
|
|
165 | Input_SZ => Coef_SZ, | |
|
|
166 | NbStage => Coef_sel_SZ) | |
|
|
167 | PORT MAP ( | |
|
|
168 | sel => alu_sel_coeff, | |
|
|
169 | INPUT => arrayCoeff, | |
|
|
170 | RES => alu_coef_s); | |
|
|
171 | ||
|
|
172 | ||
|
|
173 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |
|
|
174 | alu_coef(J) <= alu_coef_s(J); | |
|
|
175 | END GENERATE all_bit; | |
|
|
176 | ||
|
|
177 | ----------------------------------------------------------------------------- | |
|
|
178 | -- TODO : just for Synthesis test | |
|
|
179 | ||
|
|
180 | --PROCESS (clk, rstn) | |
|
|
181 | --BEGIN | |
|
|
182 | -- IF rstn = '0' THEN | |
|
|
183 | -- alu_coef <= (OTHERS => '0'); | |
|
|
184 | -- ELSIF clk'event AND clk = '1' THEN | |
|
|
185 | -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP | |
|
|
186 | -- alu_coef(J) <= alu_coef_s(J); | |
|
|
187 | -- END LOOP all_bit; | |
|
|
188 | -- END IF; | |
|
|
189 | --END PROCESS; | |
|
|
190 | ||
|
|
191 | ----------------------------------------------------------------------------- | |
|
|
192 | ||
|
|
193 | ||
|
|
194 | ALU_1: ALU | |
|
|
195 | GENERIC MAP ( | |
|
|
196 | Arith_en => 1, | |
|
|
197 | Input_SZ_1 => Sample_SZ, | |
|
|
198 | Input_SZ_2 => Coef_SZ) | |
|
|
199 | PORT MAP ( | |
|
|
200 | clk => clk, | |
|
|
201 | reset => rstn, | |
|
|
202 | ctrl => alu_ctrl, | |
|
|
203 | OP1 => alu_sample, | |
|
|
204 | OP2 => alu_coef, | |
|
|
205 | RES => alu_output_s); | |
|
|
206 | ||
|
|
207 | alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); | |
|
|
208 | ||
|
|
209 | sample_out <= alu_output; | |
|
|
210 | ||
|
|
211 | END ar_IIR_CEL_CTRLR_v2_DATAFLOW; | |
|
|
212 | ||
|
|
213 | ||
|
|
214 | ||
|
|
215 | ||
|
|
216 | ||
|
|
217 | ||
|
|
218 | ||
|
|
219 | ||
|
|
220 | ||
|
|
221 | ||
|
|
222 | ||
|
|
223 | ||
|
|
224 | ||
|
|
225 | ||
|
|
226 | ||
|
|
227 | ||
|
|
228 | ||
|
|
229 | ||
|
|
230 | ||
|
|
231 | ||
|
|
232 | ||
|
|
233 | ||
|
|
234 | ||
|
|
235 | ||
|
|
236 | ||
|
|
237 | ||
|
|
238 | ||
|
|
239 | ||
|
|
240 | ||
|
|
241 | ||
|
|
242 | ||
|
|
243 | ||
|
|
244 | ||
|
|
245 | ||
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|
246 | ||
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|
247 | ||
|
|
248 | ||
| @@ -0,0 +1,120 | |||
|
|
1 | ------------------------------------------------------------------------------ | |
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
|
4 | -- | |
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
|
8 | -- (at your option) any later version. | |
|
|
9 | -- | |
|
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
|
13 | -- GNU General Public License for more details. | |
|
|
14 | -- | |
|
|
15 | -- You should have received a copy of the GNU General Public License | |
|
|
16 | -- along with this program; if not, write to the Free Software | |
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
|
18 | ------------------------------------------------------------------------------- | |
|
|
19 | -- Author : Alexis Jeandet | |
|
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
|
21 | ---------------------------------------------------------------------------- | |
|
|
22 | LIBRARY IEEE; | |
|
|
23 | USE IEEE.numeric_std.ALL; | |
|
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
|
25 | LIBRARY lpp; | |
|
|
26 | USE lpp.iir_filter.ALL; | |
|
|
27 | USE lpp.FILTERcfg.ALL; | |
|
|
28 | USE lpp.general_purpose.ALL; | |
|
|
29 | LIBRARY techmap; | |
|
|
30 | USE techmap.gencomp.ALL; | |
|
|
31 | ||
|
|
32 | ENTITY RAM_CTRLR_v2 IS | |
|
|
33 | GENERIC( | |
|
|
34 | tech : INTEGER := 0; | |
|
|
35 | Input_SZ_1 : INTEGER := 16; | |
|
|
36 | Mem_use : INTEGER := use_RAM | |
|
|
37 | ); | |
|
|
38 | PORT( | |
|
|
39 | rstn : IN STD_LOGIC; | |
|
|
40 | clk : IN STD_LOGIC; | |
|
|
41 | -- R/W Ctrl | |
|
|
42 | ram_write : IN STD_LOGIC; | |
|
|
43 | ram_read : IN STD_LOGIC; | |
|
|
44 | -- ADDR Ctrl | |
|
|
45 | raddr_rst : IN STD_LOGIC; | |
|
|
46 | raddr_add1 : IN STD_LOGIC; | |
|
|
47 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
48 | -- Data | |
|
|
49 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
|
50 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) | |
|
|
51 | ); | |
|
|
52 | END RAM_CTRLR_v2; | |
|
|
53 | ||
|
|
54 | ||
|
|
55 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS | |
|
|
56 | ||
|
|
57 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
|
58 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
|
59 | SIGNAL WEN, REN : STD_LOGIC; | |
|
|
60 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
61 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
62 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
|
63 | ||
|
|
64 | BEGIN | |
|
|
65 | ||
|
|
66 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0); | |
|
|
67 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; | |
|
|
68 | ----------------------------------------------------------------------------- | |
|
|
69 | -- RAM | |
|
|
70 | ----------------------------------------------------------------------------- | |
|
|
71 | ||
|
|
72 | memCEL : IF Mem_use = use_CEL GENERATE | |
|
|
73 | WEN <= NOT ram_write; | |
|
|
74 | REN <= NOT ram_read; | |
|
|
75 | RAMblk : RAM_CEL | |
|
|
76 | GENERIC MAP(Input_SZ_1) | |
|
|
77 | PORT MAP( | |
|
|
78 | WD => WD, | |
|
|
79 | RD => RD, | |
|
|
80 | WEN => WEN, | |
|
|
81 | REN => REN, | |
|
|
82 | WADDR => WADDR, | |
|
|
83 | RADDR => RADDR, | |
|
|
84 | RWCLK => clk, | |
|
|
85 | RESET => rstn | |
|
|
86 | ) ; | |
|
|
87 | END GENERATE; | |
|
|
88 | ||
|
|
89 | memRAM : IF Mem_use = use_RAM GENERATE | |
|
|
90 | SRAM : syncram_2p | |
|
|
91 | GENERIC MAP(tech, 8, Input_SZ_1) | |
|
|
92 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); | |
|
|
93 | END GENERATE; | |
|
|
94 | ||
|
|
95 | ----------------------------------------------------------------------------- | |
|
|
96 | -- RADDR | |
|
|
97 | ----------------------------------------------------------------------------- | |
|
|
98 | PROCESS (clk, rstn) | |
|
|
99 | BEGIN -- PROCESS | |
|
|
100 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
101 | counter <= (OTHERS => '0'); | |
|
|
102 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
103 | IF raddr_rst = '1' THEN | |
|
|
104 | counter <= (OTHERS => '0'); | |
|
|
105 | ELSIF raddr_add1 = '1' THEN | |
|
|
106 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
|
|
107 | END IF; | |
|
|
108 | END IF; | |
|
|
109 | END PROCESS; | |
|
|
110 | RADDR <= counter; | |
|
|
111 | ||
|
|
112 | ----------------------------------------------------------------------------- | |
|
|
113 | -- WADDR | |
|
|
114 | ----------------------------------------------------------------------------- | |
|
|
115 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE | |
|
|
116 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE | |
|
|
117 | STD_LOGIC_VECTOR(UNSIGNED(counter)); | |
|
|
118 | ||
|
|
119 | ||
|
|
120 | END ar_RAM_CTRLR_v2; | |
| @@ -0,0 +1,16 | |||
|
|
1 | APB_IIR_CEL.vhd | |
|
|
2 | FILTER.vhd | |
|
|
3 | FILTER_RAM_CTRLR.vhd | |
|
|
4 | FILTERcfg.vhd | |
|
|
5 | FilterCTRLR.vhd | |
|
|
6 | IIR_CEL_CTRLR.vhd | |
|
|
7 | IIR_CEL_FILTER.vhd | |
|
|
8 | RAM.vhd | |
|
|
9 | RAM_CEL.vhd | |
|
|
10 | RAM_CTRLR2.vhd | |
|
|
11 | Top_Filtre_IIR.vhd | |
|
|
12 | RAM_CTRLR_v2.vhd | |
|
|
13 | IIR_CEL_CTRLR_v2_CONTROL.vhd | |
|
|
14 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
|
|
15 | IIR_CEL_CTRLR_v2.vhd | |
|
|
16 | iir_filter.vhd | |
| @@ -0,0 +1,52 | |||
|
|
1 | ENTITY GenericMUX IS | |
|
|
2 | GENERIC ( | |
|
|
3 | data_SZ : INTEGER := 8; | |
|
|
4 | input_NB : INTEGER := 2; | |
|
|
5 | NB_STAGE : INTEGER := 1); | |
|
|
6 | PORT ( | |
|
|
7 | sel : IN STD_LOGIC_VECTOR(NB_STAGE-1 DOWNTO 0); | |
|
|
8 | input : IN ARRAY(0 TO (input_NB-1)) OF STD_LOGIC_VECTOR(data_SZ-1 DOWNTO 0); | |
|
|
9 | output : OUT STD_LOGIC_VECTOR(data_SZ-1 DOWNTO 0) | |
|
|
10 | ); | |
|
|
11 | END GenericMUX; | |
|
|
12 | ||
|
|
13 | ARCHITECTURE beh OF GenericMUX IS | |
|
|
14 | ||
|
|
15 | COMPONENT GenericMUX | |
|
|
16 | GENERIC ( | |
|
|
17 | data_SZ : INTEGER; | |
|
|
18 | input_NB : INTEGER; | |
|
|
19 | NB_STAGE : INTEGER); | |
|
|
20 | PORT ( | |
|
|
21 | sel : IN STD_LOGIC_VECTOR(NB_STAGE-1 DOWNTO 0); | |
|
|
22 | input : IN ARRAY(0 TO (input_NB-1)) OF STD_LOGIC_VECTOR(data_SZ-1 DOWNTO 0); | |
|
|
23 | output : OUT STD_LOGIC_VECTOR(data_SZ-1 DOWNTO 0)); | |
|
|
24 | END COMPONENT; | |
|
|
25 | ||
|
|
26 | SIGNAL s : ARRAY(0 TO 2**(NB_STAGE-1)-1 ) OF STD_LOGIC_VECTOR(data_SZ-1 DOWNTO 0); | |
|
|
27 | ||
|
|
28 | BEGIN -- beh | |
|
|
29 | ||
|
|
30 | nb_stage_1: IF NB_STAGE = 1 GENERATE | |
|
|
31 | input_nb_2: IF input_NB > 1 GENERATE | |
|
|
32 | output <= input(0) WHEN sel = "0" ELSE input(1); | |
|
|
33 | END GENERATE input_nb_2; | |
|
|
34 | input_nb_2: IF input_NB = 1 GENERATE | |
|
|
35 | output <= input(0) ; | |
|
|
36 | END GENERATE input_nb_2; | |
|
|
37 | input_nb_2: IF input_NB < 1 GENERATE | |
|
|
38 | output <= (OTHERS => '0'); | |
|
|
39 | END GENERATE input_nb_2; | |
|
|
40 | END GENERATE nb_stage_1;<label>: IF NERIC MAP ( | |
|
|
41 | data_SZ => data_SZ, | |
|
|
42 | input_NB => 2**(NB_STAGE-1), | |
|
|
43 | NB_STifAGE => NB_STAGE-1) | |
|
|
44 | PORT MAP ( | |
|
|
45 | sel => sel(NB_STAGE-2 DOWNTO 0), | |
|
|
46 | input => s, | |
|
|
47 | output => output); | |
|
|
48 | ||
|
|
49 | ||
|
|
50 | END GENERATE nb_stages; | |
|
|
51 | ||
|
|
52 | END beh; | |
| @@ -0,0 +1,86 | |||
|
|
1 | ------------------------------------------------------------------------------ | |
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
|
4 | -- | |
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
|
8 | -- (at your option) any later version. | |
|
|
9 | -- | |
|
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
|
13 | -- GNU General Public License for more details. | |
|
|
14 | -- | |
|
|
15 | -- You should have received a copy of the GNU General Public License | |
|
|
16 | -- along with this program; if not, write to the Free Software | |
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
|
18 | ------------------------------------------------------------------------------- | |
|
|
19 | -- Author : Jean-christophe Pellion | |
|
|
20 | -- Mail : Jean-christophe.pellion@lpp.polytechnique.fr | |
|
|
21 | ------------------------------------------------------------------------------- | |
|
|
22 | LIBRARY IEEE; | |
|
|
23 | USE IEEE.numeric_std.ALL; | |
|
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
|
25 | LIBRARY lpp; | |
|
|
26 | USE lpp.general_purpose.ALL; | |
|
|
27 | ||
|
|
28 | ENTITY MUXN IS | |
|
|
29 | GENERIC( | |
|
|
30 | Input_SZ : INTEGER := 16; | |
|
|
31 | NbStage : INTEGER := 2); | |
|
|
32 | PORT( | |
|
|
33 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); | |
|
|
34 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
|
|
35 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); | |
|
|
36 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); | |
|
|
37 | END ENTITY; | |
|
|
38 | ||
|
|
39 | ARCHITECTURE ar_MUXN OF MUXN IS | |
|
|
40 | COMPONENT MUXN | |
|
|
41 | GENERIC ( | |
|
|
42 | Input_SZ : INTEGER; | |
|
|
43 | NbStage : INTEGER); | |
|
|
44 | PORT ( | |
|
|
45 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); | |
|
|
46 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); | |
|
|
47 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
|
|
48 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); | |
|
|
49 | END COMPONENT; | |
|
|
50 | ||
|
|
51 | --SIGNAL S : ARRAY (0 TO (2**(NbStage-1)-1)) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
|
|
52 | SIGNAL S: MUX_INPUT_TYPE(0 TO (2**(NbStage-1))-1,Input_SZ-1 DOWNTO 0); | |
|
|
53 | ||
|
|
54 | ||
|
|
55 | BEGIN | |
|
|
56 | ||
|
|
57 | all_input : FOR I IN 0 TO (2**(NbStage-1))-1 GENERATE | |
|
|
58 | all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE | |
|
|
59 | S(I,J) <= INPUT(2*I,J) WHEN sel(0) = '0' ELSE INPUT(2*I+1,J); | |
|
|
60 | END GENERATE all_input; | |
|
|
61 | END GENERATE all_input; | |
|
|
62 | ||
|
|
63 | NB_STAGE_1: IF NbStage = 1 GENERATE | |
|
|
64 | all_input: FOR J IN Input_SZ-1 DOWNTO 0 GENERATE | |
|
|
65 | RES(J) <= S(0,J); | |
|
|
66 | END GENERATE all_input; | |
|
|
67 | END GENERATE NB_STAGE_1; | |
|
|
68 | ||
|
|
69 | NB_STAGE_2 : IF NbStage = 2 GENERATE | |
|
|
70 | all_input: FOR I IN Input_SZ-1 DOWNTO 0 GENERATE | |
|
|
71 | RES(I) <= S(0,I) WHEN sel(1) = '0' ELSE S(1,I); | |
|
|
72 | END GENERATE all_input; | |
|
|
73 | END GENERATE NB_STAGE_2; | |
|
|
74 | ||
|
|
75 | NB_STAGE_PLUS : IF NbStage > 2 GENERATE | |
|
|
76 | MUXN_1 : MUXN | |
|
|
77 | GENERIC MAP ( | |
|
|
78 | Input_SZ => Input_SZ, | |
|
|
79 | NbStage => NbStage-1) | |
|
|
80 | PORT MAP ( | |
|
|
81 | sel => sel(NbStage-1 DOWNTO 1), | |
|
|
82 | INPUT => S, | |
|
|
83 | RES => RES); | |
|
|
84 | END GENERATE NB_STAGE_PLUS; | |
|
|
85 | ||
|
|
86 | END ar_MUXN; | |
| @@ -0,0 +1,57 | |||
|
|
1 | ------------------------------------------------------------------------------ | |
|
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
|
4 | -- | |
|
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
|
8 | -- (at your option) any later version. | |
|
|
9 | -- | |
|
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
|
13 | -- GNU General Public License for more details. | |
|
|
14 | -- | |
|
|
15 | -- You should have received a copy of the GNU General Public License | |
|
|
16 | -- along with this program; if not, write to the Free Software | |
|
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
|
18 | ------------------------------------------------------------------------------- | |
|
|
19 | -- Author : Jean-christophe PELLION | |
|
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
|
21 | ---------------------------------------------------------------------------- | |
|
|
22 | LIBRARY IEEE; | |
|
|
23 | USE IEEE.numeric_std.ALL; | |
|
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
|
25 | ||
|
|
26 | ENTITY SYNC_FF IS | |
|
|
27 | ||
|
|
28 | GENERIC ( | |
|
|
29 | NB_FF_OF_SYNC : INTEGER := 2); | |
|
|
30 | ||
|
|
31 | PORT ( | |
|
|
32 | clk : IN STD_LOGIC; | |
|
|
33 | rstn : IN STD_LOGIC; | |
|
|
34 | A : IN STD_LOGIC; | |
|
|
35 | A_sync : OUT STD_LOGIC); | |
|
|
36 | ||
|
|
37 | END SYNC_FF; | |
|
|
38 | ||
|
|
39 | ARCHITECTURE beh OF SYNC_FF IS | |
|
|
40 | SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0); | |
|
|
41 | BEGIN -- beh | |
|
|
42 | ||
|
|
43 | sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE | |
|
|
44 | PROCESS (clk, rstn) | |
|
|
45 | BEGIN -- PROCESS | |
|
|
46 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
|
47 | A_temp(I) <= '0'; | |
|
|
48 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
|
49 | A_temp(I) <= A_temp(I+1); | |
|
|
50 | END IF; | |
|
|
51 | END PROCESS; | |
|
|
52 | END GENERATE sync_loop; | |
|
|
53 | ||
|
|
54 | A_temp(NB_FF_OF_SYNC) <= A; | |
|
|
55 | A_sync <= A_temp(0); | |
|
|
56 | ||
|
|
57 | END beh; | |
| @@ -0,0 +1,120 | |||
|
|
1 | LIBRARY ieee; | |
|
|
2 | USE ieee.std_logic_1164.ALL; | |
|
|
3 | LIBRARY lpp; | |
|
|
4 | USE lpp.lpp_ad_conv.ALL; | |
|
|
5 | USE lpp.general_purpose.SYNC_FF; | |
|
|
6 | ||
|
|
7 | ------------------------------------------------------------------------------- | |
|
|
8 | ||
|
|
9 | ENTITY ADS7886_drvr_tb IS | |
|
|
10 | ||
|
|
11 | END ADS7886_drvr_tb; | |
|
|
12 | ||
|
|
13 | ------------------------------------------------------------------------------- | |
|
|
14 | ||
|
|
15 | ARCHITECTURE tb OF ADS7886_drvr_tb IS | |
|
|
16 | ||
|
|
17 | COMPONENT TestModule_ADS7886 | |
|
|
18 | GENERIC ( | |
|
|
19 | freq : INTEGER; | |
|
|
20 | amplitude : INTEGER); | |
|
|
21 | PORT ( | |
|
|
22 | cnv_run : IN STD_LOGIC; | |
|
|
23 | cnv : IN STD_LOGIC; | |
|
|
24 | sck : IN STD_LOGIC; | |
|
|
25 | sdo : OUT STD_LOGIC); | |
|
|
26 | END COMPONENT; | |
|
|
27 | ||
|
|
28 | -- component generics | |
|
|
29 | CONSTANT ChanelCount : INTEGER := 8; | |
|
|
30 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
|
|
31 | CONSTANT ncycle_cnv : INTEGER := 500; | |
|
|
32 | ||
|
|
33 | -- component ports | |
|
|
34 | SIGNAL cnv_rstn : STD_LOGIC; | |
|
|
35 | SIGNAL cnv : STD_LOGIC; | |
|
|
36 | SIGNAL rstn : STD_LOGIC; | |
|
|
37 | SIGNAL sck : STD_LOGIC; | |
|
|
38 | SIGNAL sdo : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
|
|
39 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
|
|
40 | SIGNAL sample_val : STD_LOGIC; | |
|
|
41 | SIGNAL run_cnv : STD_LOGIC; | |
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42 | ||
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43 | ||
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44 | -- clock | |
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45 | signal Clk : STD_LOGIC := '1'; | |
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46 | SIGNAL cnv_clk : STD_LOGIC := '1'; | |
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47 | ||
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48 | ||
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49 | BEGIN -- tb | |
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50 | ||
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51 | MODULE_ADS7886: FOR I IN 0 TO ChanelCount-1 GENERATE | |
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52 | TestModule_ADS7886_u: TestModule_ADS7886 | |
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53 | GENERIC MAP ( | |
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54 | freq => 256/(I+1), | |
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55 | amplitude => 300/(I+1)) | |
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56 | PORT MAP ( | |
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57 | cnv_run => run_cnv, | |
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58 | cnv => cnv, | |
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59 | sck => sck, | |
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60 | sdo => sdo(I)); | |
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61 | END GENERATE MODULE_ADS7886; | |
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62 | ||
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63 | -- component instantiation | |
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64 | DUT: ADS7886_drvr | |
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65 | GENERIC MAP ( | |
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66 | ChanelCount => ChanelCount, | |
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67 | ncycle_cnv_high => ncycle_cnv_high, | |
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68 | ncycle_cnv => ncycle_cnv) | |
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69 | PORT MAP ( | |
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70 | cnv_clk => cnv_clk, | |
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71 | cnv_rstn => cnv_rstn, | |
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72 | cnv_run => run_cnv, | |
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73 | cnv => cnv, | |
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74 | clk => clk, | |
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75 | rstn => rstn, | |
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76 | sck => sck, | |
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77 | sdo => sdo, | |
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78 | sample => sample, | |
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79 | sample_val => sample_val); | |
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80 | ||
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81 | -- clock generation | |
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82 | Clk <= not Clk after 20 ns; -- 25 Mhz | |
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83 | cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz | |
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84 | ||
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85 | -- waveform generation | |
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86 | WaveGen_Proc: process | |
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87 | begin | |
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88 | -- insert signal assignments here | |
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89 | wait until Clk = '1'; | |
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90 | rstn <= '0'; | |
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91 | cnv_rstn <= '0'; | |
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92 | run_cnv <= '0'; | |
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93 | wait until Clk = '1'; | |
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94 | wait until Clk = '1'; | |
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95 | wait until Clk = '1'; | |
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96 | rstn <= '1'; | |
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97 | cnv_rstn <= '1'; | |
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98 | wait until Clk = '1'; | |
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99 | wait until Clk = '1'; | |
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100 | wait until Clk = '1'; | |
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101 | wait until Clk = '1'; | |
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102 | wait until Clk = '1'; | |
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103 | wait until Clk = '1'; | |
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104 | run_cnv <= '1'; | |
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105 | wait; | |
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106 | ||
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107 | end process WaveGen_Proc; | |
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108 | ||
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109 | ||
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110 | ||
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111 | END tb; | |
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112 | ||
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113 | ------------------------------------------------------------------------------- | |
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114 | ||
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115 | CONFIGURATION ADS7886_drvr_tb_tb_cfg OF ADS7886_drvr_tb IS | |
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116 | FOR tb | |
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117 | END FOR; | |
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118 | END ADS7886_drvr_tb_tb_cfg; | |
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119 | ||
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120 | ------------------------------------------------------------------------------- | |
| @@ -0,0 +1,70 | |||
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
|
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe PELLION | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | LIBRARY IEEE; | |
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23 | USE IEEE.STD_LOGIC_1164.ALL; | |
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24 | USE IEEE.std_logic_arith.ALL; | |
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25 | USE IEEE.std_logic_signed.ALL; | |
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26 | USE IEEE.MATH_real.ALL; | |
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27 | ||
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28 | ENTITY TestModule_ADS7886 IS | |
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29 | GENERIC ( | |
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30 | freq : INTEGER := 24; | |
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31 | amplitude : INTEGER := 3000; | |
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32 | impulsion : INTEGER := 0 -- 1 => impulsion generation | |
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33 | ); | |
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34 | PORT ( | |
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35 | -- CONV -- | |
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36 | cnv_run : IN STD_LOGIC; | |
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37 | cnv : IN STD_LOGIC; | |
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38 | ||
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39 | -- DATA -- | |
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40 | sck : IN STD_LOGIC; | |
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41 | sdo : OUT STD_LOGIC | |
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42 | ); | |
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43 | END TestModule_ADS7886; | |
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44 | ||
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45 | ARCHITECTURE beh OF TestModule_ADS7886 IS | |
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46 | SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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47 | SIGNAL n : INTEGER := 0; | |
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48 | BEGIN -- beh | |
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49 | ||
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50 | PROCESS (cnv, sck) | |
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51 | BEGIN -- PROCESS | |
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52 | IF cnv = '0' AND cnv'EVENT THEN | |
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53 | n <= n + 1; | |
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54 | IF impulsion = 1 THEN | |
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55 | IF n = 1 THEN | |
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56 | reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16); | |
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57 | ELSE | |
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58 | reg <= conv_std_logic_vector(integer(REAL(0)) , 16); | |
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59 | END IF; | |
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60 | ELSE | |
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61 | reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16); | |
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62 | END IF; | |
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63 | ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge | |
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64 | reg(15) <= 'X'; | |
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65 | reg(14 DOWNTO 0) <= reg(15 DOWNTO 1); | |
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66 | END IF; | |
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67 | END PROCESS; | |
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68 | sdo <= reg(0); | |
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69 | ||
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70 | END beh; | |
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