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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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use lpp.iir_filter.all;
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use lpp.FILTERcfg.all;
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ENTITY Top_Data_Acquisition IS
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PORT (
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-- ADS7886
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cnv_run : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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--
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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--
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC
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);
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END Top_Data_Acquisition;
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ARCHITECTURE tb OF Top_Data_Acquisition IS
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-----------------------------------------------------------------------------
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CONSTANT ChanelCount : INTEGER := 8;
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CONSTANT ncycle_cnv_high : INTEGER := 79;
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CONSTANT ncycle_cnv : INTEGER := 500;
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-----------------------------------------------------------------------------
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SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
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SIGNAL sample_val : STD_LOGIC;
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SIGNAL sample_val_delay : STD_LOGIC;
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-----------------------------------------------------------------------------
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CONSTANT Coef_SZ : integer := 9;
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CONSTANT CoefCntPerCel: integer := 6;
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CONSTANT CoefPerCel : integer := 5;
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CONSTANT Cels_count : integer := 5;
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signal coefs : std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0);
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signal coefs_JC : std_logic_vector((Coef_SZ*CoefPerCel*Cels_count)-1 downto 0);
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signal sample_filter_in : samplT(ChanelCount-1 downto 0,17 downto 0);
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signal sample_filter_out : samplT(ChanelCount-1 downto 0,17 downto 0);
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--
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signal sample_filter_JC_out_val : STD_LOGIC;
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signal sample_filter_JC_out : samplT(ChanelCount-1 downto 0,17 downto 0);
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--
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signal sample_filter_JC_out_r_val : STD_LOGIC;
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signal sample_filter_JC_out_r : samplT(ChanelCount-1 downto 0,17 downto 0);
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BEGIN
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-- component instantiation
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-----------------------------------------------------------------------------
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DIGITAL_acquisition: ADS7886_drvr
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GENERIC MAP (
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ChanelCount => ChanelCount,
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ncycle_cnv_high => ncycle_cnv_high,
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ncycle_cnv => ncycle_cnv)
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PORT MAP (
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cnv_clk => cnv_clk, --
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cnv_rstn => cnv_rstn, --
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cnv_run => cnv_run, --
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cnv => cnv, --
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clk => clk, --
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rstn => rstn, --
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sck => sck, --
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sdo => sdo(ChanelCount-1 DOWNTO 0), --
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sample => sample,
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sample_val => sample_val);
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_val_delay <= '0';
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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sample_val_delay <= sample_val;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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ChanelLoop: for i in 0 to ChanelCount-1 generate
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SampleLoop: for j in 0 to 15 generate
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sample_filter_in(i,j) <= sample(i)(j);
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end generate;
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sample_filter_in(i,16) <= sample(i)(15);
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sample_filter_in(i,17) <= sample(i)(15);
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end generate;
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coefs <= CoefsInitValCst;
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coefs_JC <= CoefsInitValCst_JC;
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FILTER: IIR_CEL_CTRLR
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GENERIC MAP (
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tech => 0,
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Sample_SZ => 18,
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ChanelsCount => ChanelCount,
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Coef_SZ => Coef_SZ,
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CoefCntPerCel => CoefCntPerCel,
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Cels_count => Cels_count,
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Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
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PORT MAP (
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reset => rstn,
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clk => clk,
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sample_clk => sample_val_delay,
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sample_in => sample_filter_in,
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sample_out => sample_filter_out,
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virg_pos => 7,
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GOtest => OPEN,
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coefs => coefs);
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IIR_CEL_CTRLR_v2_1: IIR_CEL_CTRLR_v2
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GENERIC MAP (
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tech => 0,
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Mem_use => use_CEL,
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Sample_SZ => 18,
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Coef_SZ => Coef_SZ,
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Coef_Nb => 25, -- TODO
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Coef_sel_SZ => 5, -- TODO
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Cels_count => Cels_count,
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ChanelsCount => ChanelCount)
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PORT MAP (
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rstn => rstn,
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clk => clk,
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virg_pos => 7,
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coefs => coefs_JC,
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sample_in_val => sample_val_delay,
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sample_in => sample_filter_in,
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sample_out_val => sample_filter_JC_out_val,
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sample_out => sample_filter_JC_out);
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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sample_filter_JC_out_r_val <= '0';
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rst_all_chanel: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
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rst_all_bits: FOR J IN 17 DOWNTO 0 LOOP
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sample_filter_JC_out_r(I,J) <= '0';
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END LOOP rst_all_bits;
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END LOOP rst_all_chanel;
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ELSIF clk'event AND clk = '1' THEN -- rising clock edge
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sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
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IF sample_filter_JC_out_val = '1' THEN
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sample_filter_JC_out_r <= sample_filter_JC_out;
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END IF;
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END IF;
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END PROCESS;
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END tb;
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