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DAC8581 driver added
Jeandet Alexis -
r271:a0ad26a05201 alexis
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:26:29 12/07/2013
6 -- Design Name:
7 -- Module Name: DAC8581 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.numeric_std.all;
23 library LPP;
24 use lpp.lpp_cna.all;
25
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 use IEEE.NUMERIC_STD.ALL;
29
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 --library UNISIM;
33 --use UNISIM.VComponents.all;
34
35 entity DAC8581 is
36 generic(
37 clkfreq : integer := 100;
38 ChanCount : integer := 8
39 );
40 Port ( clk : in STD_LOGIC;
41 rstn : in STD_LOGIC;
42 smpclk : in STD_LOGIC;
43 sclk : out STD_LOGIC;
44 csn : out STD_LOGIC;
45 sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0);
46 smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
47 );
48 end DAC8581;
49
50 architecture Behavioral of DAC8581 is
51
52 signal smpclk_reg : std_logic;
53 signal sclk_gen : std_logic_vector(3 downto 0);
54 signal sclk_net : std_logic;
55 signal load : std_logic;
56 signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
57 signal csn_sreg : std_logic_vector(15 downto 0);
58
59 begin
60
61
62
63 sclk_net <= sclk_gen(1);
64 sclk <= sclk_net;
65
66 process(rstn,clk)
67 begin
68 if rstn ='0' then
69 smpclk_reg <= '0';
70 sclk_gen <= "0000";
71 load <= '0';
72 elsif clk'event and clk = '1' then
73 smpclk_reg <= smpclk;
74 sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1);
75 if smpclk_reg = '0' and smpclk = '1' then
76 load <= '1';
77 else
78 load <= '0';
79 end if;
80
81 end if;
82 end process;
83
84 process(load,sclk_net)
85 begin
86 if load ='1' then
87 data_sreg <= smp_in;
88 csn_sreg <= (others => '0');
89
90 elsif sclk_net'event and sclk_net = '1' then
91 all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
92 all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
93 data_sreg(I,J+1) <= data_sreg(I,J);
94 END LOOP all_bits0;
95 data_sreg(I,0) <= '1';
96 END LOOP all_chanel0;
97 csn_sreg <= csn_sreg(14 downto 0) & '1';
98 end if;
99 end process;
100
101 process(rstn,sclk_net)
102 begin
103 if rstn ='0' then
104 all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
105 sdo(I) <= '1';
106 END LOOP all_chanel2;
107 csn <= '1';
108 elsif sclk_net'event and sclk_net = '0' then
109 all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
110 sdo(I) <= data_sreg(I,15);
111 END LOOP all_chanel1;
112 csn <= csn_sreg(15);
113 end if;
114 end process;
115
116
117
118 end Behavioral;
119
120
121
122
123
124
125
126
127
128
129
130
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1 library ieee;
1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
4 library grlib, techmap;
5 use grlib.amba.all;
5 use grlib.amba.all;
6 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
9 use techmap.allclkgen.all;
10 library gaisler;
10 library gaisler;
11 use gaisler.memctrl.all;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
14 use gaisler.misc.all;
15 library esa;
15 library esa;
16 use esa.memoryctrl.all;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
17 --use gaisler.sim.all;
18 library lpp;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
22 use lpp.general_purpose.all;
23 use lpp.lpp_cna.all;
23
24
24 Library UNISIM;
25 Library UNISIM;
25 use UNISIM.vcomponents.all;
26 use UNISIM.vcomponents.all;
26
27
27
28
28 use work.config.all;
29 use work.config.all;
29 --==================================================================
30 --==================================================================
30 --
31 --
31 --
32 --
32 -- FPGA FREQ = 100MHz
33 -- FPGA FREQ = 100MHz
33 --
34 --
34 --
35 --
35 --==================================================================
36 --==================================================================
36
37
37 entity BeagleSynth is
38 entity BeagleSynth is
38 generic (
39 generic (
39 fabtech : integer := CFG_FABTECH;
40 fabtech : integer := CFG_FABTECH;
40 memtech : integer := CFG_MEMTECH;
41 memtech : integer := CFG_MEMTECH;
41 padtech : integer := CFG_PADTECH;
42 padtech : integer := CFG_PADTECH;
42 clktech : integer := CFG_CLKTECH
43 clktech : integer := CFG_CLKTECH
43 );
44 );
44 port (
45 port (
45 reset : in std_ulogic;
46 reset : in std_ulogic;
46 clk : in std_ulogic;
47 clk : in std_ulogic;
47 DAC_nCLR : out std_ulogic;
48 DAC_nCLR : out std_ulogic;
48 DAC_nCS : out std_ulogic;
49 DAC_nCS : out std_ulogic;
49 CAL_IN_SCK : out std_ulogic;
50 CAL_IN_SCK : out std_ulogic;
50 DAC_SDI : out std_ulogic_vector(7 downto 0);
51 DAC_SDI : out std_logic_vector(7 downto 0);
51 TXD : out std_ulogic;
52 TXD : out std_ulogic;
52 RXD : in std_ulogic;
53 RXD : in std_ulogic;
53 urxd1 : in std_ulogic;
54 urxd1 : in std_ulogic;
54 utxd1 : out std_ulogic;
55 utxd1 : out std_ulogic;
55 LED : out std_ulogic_vector(2 downto 0);
56 LED : out std_ulogic_vector(2 downto 0);
56 --------------------------------------------------------
57 --------------------------------------------------------
57 ---- SDRAM
58 ---- SDRAM
58 ---- For SDRAM config have a look on leon3-altera-ep1c20
59 ---- For SDRAM config have a look on leon3-altera-ep1c20
59 ---- design from GRLIB, the IS42S32400E is similar to
60 ---- design from GRLIB, the IS42S32400E is similar to
60 ---- MT48LC4M32B2.
61 ---- MT48LC4M32B2.
61 --------------------------------------------------------
62 --------------------------------------------------------
62 sdcke : out std_logic; -- clk en
63 sdcke : out std_logic; -- clk en
63 sdcsn : out std_logic; -- chip sel
64 sdcsn : out std_logic; -- chip sel
64 sdwen : out std_logic; -- write en
65 sdwen : out std_logic; -- write en
65 sdrasn : out std_logic; -- row addr stb
66 sdrasn : out std_logic; -- row addr stb
66 sdcasn : out std_logic; -- col addr stb
67 sdcasn : out std_logic; -- col addr stb
67 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
68 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
68 sdclk : out std_logic; -- sdram clk output
69 sdclk : out std_logic; -- sdram clk output
69 sdba : out std_logic_vector (1 downto 0); -- bank select address
70 sdba : out std_logic_vector (1 downto 0); -- bank select address
70 Address : out std_logic_vector(11 downto 0); -- sdram address
71 Address : out std_logic_vector(11 downto 0); -- sdram address
71 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
72 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
72 );
73 );
73 end;
74 end;
74
75
75 architecture rtl of BeagleSynth is
76 architecture rtl of BeagleSynth is
76 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
77 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
77 CFG_GRETH+CFG_AHB_JTAG;
78 CFG_GRETH+CFG_AHB_JTAG;
78 constant maxahbm : integer := maxahbmsp;
79 constant maxahbm : integer := maxahbmsp;
79 constant IOAEN : integer := CFG_CAN;
80 constant IOAEN : integer := CFG_CAN;
80 constant boardfreq : integer := 100000;
81 constant boardfreq : integer := 100000;
81
82
82 signal clk2x : std_ulogic;
83 signal clk2x : std_ulogic;
83 signal lclk : std_ulogic;
84 signal lclk : std_ulogic;
84 signal clkm : std_ulogic;
85 signal clkm : std_ulogic;
85 signal rstn : std_ulogic;
86 signal rstn : std_ulogic;
86 signal rst : std_ulogic;
87 signal rst : std_ulogic;
87 signal rstraw : std_ulogic;
88 signal rstraw : std_ulogic;
88 signal pciclk : std_ulogic;
89 signal pciclk : std_ulogic;
89 signal sdclkl : std_ulogic;
90 signal sdclkl : std_ulogic;
90 signal sdclkl_DDR2 : std_ulogic;
91 signal sdclkl_DDR2 : std_ulogic;
91 signal cgi : clkgen_in_type;
92 signal cgi : clkgen_in_type;
92 signal cgo : clkgen_out_type;
93 signal cgo : clkgen_out_type;
93
94
94 --- AHB / APB
95 --- AHB / APB
95 signal apbi : apb_slv_in_type;
96 signal apbi : apb_slv_in_type;
96 signal apbo : apb_slv_out_vector := (others => apb_none);
97 signal apbo : apb_slv_out_vector := (others => apb_none);
97 signal ahbsi : ahb_slv_in_type;
98 signal ahbsi : ahb_slv_in_type;
98 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
99 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
99 signal ahbmi : ahb_mst_in_type;
100 signal ahbmi : ahb_mst_in_type;
100 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
101 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
101
102
102 --- MEM CTRLR
103 --- MEM CTRLR
103 signal sdi : sdctrl_in_type;
104 signal sdi : sdctrl_in_type;
104 signal sdo : sdctrl_out_type;
105 signal sdo : sdctrl_out_type;
105
106
106 --UART
107 --UART
107 signal ahbuarti : uart_in_type;
108 signal ahbuarti : uart_in_type;
108 signal ahbuarto : uart_out_type;
109 signal ahbuarto : uart_out_type;
109 signal apbuarti : uart_in_type;
110 signal apbuarti : uart_in_type;
110 signal apbuarto : uart_out_type;
111 signal apbuarto : uart_out_type;
111
112
112 signal led2int : std_logic;
113 signal led2int : std_logic;
113
114
115
116 signal DAC0_DATA : std_logic_vector(15 downto 0);
117 signal DAC1_DATA : std_logic_vector(15 downto 0);
118 signal DAC2_DATA : std_logic_vector(15 downto 0);
119 signal DAC3_DATA : std_logic_vector(15 downto 0);
120 signal DAC4_DATA : std_logic_vector(15 downto 0);
121 signal DAC5_DATA : std_logic_vector(15 downto 0);
122 signal DAC6_DATA : std_logic_vector(15 downto 0);
123 signal DAC7_DATA : std_logic_vector(15 downto 0);
124
125 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
126 signal smpclk : std_logic;
127 signal smpclk_reg : std_logic;
128 signal DAC_SDO : std_logic;
129
114 begin
130 begin
115
131
116 DAC_nCLR <= '1';
132 DAC_nCLR <= '1';
117 DAC_nCS <= '1';
133 --DAC_nCS <= SYNC;
118 CAL_IN_SCK <= '1';
134 --CAL_IN_SCK <= '1';
119 DAC_SDI <= (others =>'1');
135 --DAC_SDI <= (others =>'1');
120
136
121 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
137 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
122 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
138 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
123 --rstn <= reset;
139 --rstn <= reset;
124 --lclk <= clk;
140 --lclk <= clk;
125 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
141 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
126
142
127 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
143 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
128 clkgen0 : clkgen -- clock generator
144 clkgen0 : clkgen -- clock generator
129 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
145 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
130 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
146 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
131
147
132 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
148 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
133 --sdclk <= sdclkl;
149 --sdclk <= sdclkl;
134 sdclk <= sdclkl_DDR2;
150 sdclk <= sdclkl_DDR2;
135
151
136 LED(1) <= not cgo.clklock;
152 LED(1) <= not cgo.clklock;
137 LED(0) <= cgo.clklock;
153 LED(0) <= cgo.clklock;
138
154
139 ODDR2_inst : ODDR2
155 ODDR2_inst : ODDR2
140 generic map(
156 generic map(
141 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
157 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
142 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
158 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
143 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
159 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
144 port map (
160 port map (
145 Q => sdclkl_DDR2, -- 1-bit output data
161 Q => sdclkl_DDR2, -- 1-bit output data
146 C0 => sdclkl, -- 1-bit clock input
162 C0 => sdclkl, -- 1-bit clock input
147 C1 => not sdclkl, -- 1-bit clock input
163 C1 => not sdclkl, -- 1-bit clock input
148 CE => '1', -- 1-bit clock enable input
164 CE => '1', -- 1-bit clock enable input
149 D0 => '1', -- 1-bit data input (associated with C0)
165 D0 => '1', -- 1-bit data input (associated with C0)
150 D1 => '0', -- 1-bit data input (associated with C1)
166 D1 => '0', -- 1-bit data input (associated with C1)
151 R => '0', -- 1-bit reset input
167 R => '0', -- 1-bit reset input
152 S => '0' -- 1-bit set input
168 S => '0' -- 1-bit set input
153 );
169 );
154
170
155 ----------------------------------------------------------------------
171 ----------------------------------------------------------------------
156 --- AHB CONTROLLER -------------------------------------------------
172 --- AHB CONTROLLER -------------------------------------------------
157 ----------------------------------------------------------------------
173 ----------------------------------------------------------------------
158
174
159 ahb0 : ahbctrl -- AHB arbiter/multiplexer
175 ahb0 : ahbctrl -- AHB arbiter/multiplexer
160 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
176 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
161 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
177 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
162 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
178 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
163 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
179 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
164
180
165 ----------------------------------------------------------------------
181 ----------------------------------------------------------------------
166 --- AHB UART -------------------------------------------------------
182 --- AHB UART -------------------------------------------------------
167 ----------------------------------------------------------------------
183 ----------------------------------------------------------------------
168
184
169 dcomgen : if CFG_AHB_UART = 1 generate
185 dcomgen : if CFG_AHB_UART = 1 generate
170 dcom0: ahbuart -- Debug UART
186 dcom0: ahbuart -- Debug UART
171 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
187 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
172 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
188 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
173 ahbuarti.rxd <= RXD;
189 ahbuarti.rxd <= RXD;
174 TXD <= ahbuarto.txd;
190 TXD <= ahbuarto.txd;
175 end generate;
191 end generate;
176 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
192 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
177
193
178 ----------------------------------------------------------------------
194 ----------------------------------------------------------------------
179 --- APB Bridge -----------------------------------------------------
195 --- APB Bridge -----------------------------------------------------
180 ----------------------------------------------------------------------
196 ----------------------------------------------------------------------
181
197
182 apb0 : apbctrl -- AHB/APB bridge
198 apb0 : apbctrl -- AHB/APB bridge
183 generic map (hindex => 1, haddr => CFG_APBADDR)
199 generic map (hindex => 1, haddr => CFG_APBADDR)
184 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
200 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
185
201
186 ----------------------------------------------------------------------
202 ----------------------------------------------------------------------
187 --- APB UART -------------------------------------------------------
203 --- APB UART -------------------------------------------------------
188 ----------------------------------------------------------------------
204 ----------------------------------------------------------------------
189
205
190 ua1 : if CFG_UART1_ENABLE /= 0 generate
206 ua1 : if CFG_UART1_ENABLE /= 0 generate
191 uart1 : apbuart -- UART 1
207 uart1 : apbuart -- UART 1
192 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
208 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
193 fifosize => CFG_UART1_FIFO)
209 fifosize => CFG_UART1_FIFO)
194 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
210 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
195 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
211 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
196 apbuarti.ctsn <= '0';
212 apbuarti.ctsn <= '0';
197 end generate;
213 end generate;
198 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
214 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
199
215
200
216
201
217
202
218
203 --div0: Clk_divider
219 --div0: Clk_divider
204 -- generic map( 100000000,1)
220 -- generic map( 100000000,1)
205 -- Port map( clkm,rstn,LED(2));
221 -- Port map( clkm,rstn,LED(2));
206
222
207 LED(2) <= led2int;
223 LED(2) <= led2int;
208
224
209 process(clkm,rstn)
225 process(clkm,rstn)
210 begin
226 begin
211 if rstn = '0' then
227 if rstn = '0' then
212 led2int <= '0';
228 led2int <= '0';
213 elsif clkm'event and clkm='1' then
229 elsif clkm'event and clkm='1' then
214 led2int <= not led2int;
230 led2int <= not led2int;
215 end if;
231 end if;
216 end process;
232 end process;
217
233
218
234
219
235
220
236
221 sdc : sdctrl
237 sdc : sdctrl
222 generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
238 generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
223 invclk => 0,sdbits =>32)
239 invclk => 0,sdbits =>32)
224 port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
240 port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
225
241
226
242
227
243
228 --Alternative data pad instantiation with vectored bdrive
244 --Alternative data pad instantiation with vectored bdrive
229 sd_pad : iopadvv generic map (tech=> padtech,width => 32)
245 sd_pad : iopadvv generic map (tech=> padtech,width => 32)
230 port map (
246 port map (
231 data(31 downto 0),
247 data(31 downto 0),
232 sdo.data(31 downto 0),
248 sdo.data(31 downto 0),
233 sdo.vbdrive(31 downto 0),
249 sdo.vbdrive(31 downto 0),
234 sdi.data(31 downto 0));
250 sdi.data(31 downto 0));
235
251
236
252
237 -- connect memory controller outputs to entity output signals
253 -- connect memory controller outputs to entity output signals
238 Address <= sdo.address(13 downto 2);
254 Address <= sdo.address(13 downto 2);
239 --sdba <= sdo.address(16 downto 15);
255 --sdba <= sdo.address(16 downto 15);
240 sdba <= "00";
256 sdba <= "00";
241 sdcke <= sdo.sdcke(0);
257 sdcke <= sdo.sdcke(0);
242 sdwen <= sdo.sdwen;
258 sdwen <= sdo.sdwen;
243 sdcsn <= sdo.sdcsn(0);
259 sdcsn <= sdo.sdcsn(0);
244 sdrasn <= sdo.rasn;
260 sdrasn <= sdo.rasn;
245 sdcasn <= sdo.casn;
261 sdcasn <= sdo.casn;
246 sddqm <= sdo.dqm(3 downto 0);
262 sddqm <= sdo.dqm(3 downto 0);
247
263
248
264
265 DAC0 : DAC8581
266 generic map(100,8)
267 Port map(
268 clk => clkm,
269 rstn => rstn,
270 smpclk => smpclk,
271 sclk => CAL_IN_SCK,
272 csn => DAC_nCS,
273 sdo => DAC_SDI,
274 smp_in => DAC_DATA
275 );
276
277
278
279 smpclk0: Clk_divider
280 GENERIC map(OSC_freqHz => 50000000,
281 TargetFreq_Hz => 256000)
282 PORT map( clk => clkm,
283 reset => rstn,
284 clk_divided => smpclk
285 );
286
287 all_bits: FOR I in 15 downto 0 GENERATE
288 DAC_DATA(0,I) <= DAC0_DATA(I);
289 DAC_DATA(1,I) <= DAC1_DATA(I);
290 DAC_DATA(2,I) <= DAC2_DATA(I);
291 DAC_DATA(3,I) <= DAC3_DATA(I);
292 DAC_DATA(4,I) <= DAC4_DATA(I);
293 DAC_DATA(5,I) <= DAC5_DATA(I);
294 DAC_DATA(6,I) <= DAC6_DATA(I);
295 DAC_DATA(7,I) <= DAC7_DATA(I);
296 end GENERATE;
297
298 process(clkm,rstn)
299 begin
300 if rstn ='0' then
301 DAC0_DATA <= X"0000";
302 DAC1_DATA <= X"0000";
303 DAC2_DATA <= X"0000";
304 DAC3_DATA <= X"0000";
305 DAC4_DATA <= X"0000";
306 DAC5_DATA <= X"0000";
307 DAC6_DATA <= X"0000";
308 DAC7_DATA <= X"0000";
309 smpclk_reg <= smpclk;
310 elsif clkm'event and clkm = '1' then
311 smpclk_reg <= smpclk;
312 if smpclk_reg = '0' and smpclk = '1' then
313 DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
314 DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
315 DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
316 DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
317 DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
318 DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
319 DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
320 DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
321 -- DAC_DATA <= "0100000000000000";
322 end if;
323 end if;
324 end process;
325
249
326
250 end rtl;
327 end rtl;
251
328
252
329
253
330
Show file before | Show file after | Hide comments
@@ -1,71 +1,72
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library LPP;
25 use lpp.lpp_cna.all;
26 use lpp.lpp_cna.all;
26
27
27 --! Programme du Convertisseur Num�rique/Analogique
28 --! Programme du Convertisseur Numrique/Analogique
28
29
29 entity DacDriver is
30 entity DacDriver is
30 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
31 generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz
31 port(
32 port(
32 clk : in std_logic; --! Horloge du composant
33 clk : in std_logic; --! Horloge du composant
33 rst : in std_logic; --! Reset general du composant
34 rst : in std_logic; --! Reset general du composant
34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits
36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 Readn : out std_logic;
39 Readn : out std_logic;
39 Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
40 Ready : out std_logic; --! Flag, signale la fin de la srialisation d'une donne
40 Data : out std_logic --! Donn�e num�rique s�rialis�
41 Data : out std_logic --! Donne numrique srialis
41 );
42 );
42 end entity;
43 end entity;
43
44
44 --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
45 --! @details Un driver C va permettre de gnerer un tableau de donnes sur 16 bits,
45 --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
46 --! qui seront srialis pour tre ensuite diriges vers le convertisseur.
46
47
47 architecture ar_DacDriver of DacDriver is
48 architecture ar_DacDriver of DacDriver is
48
49
49 signal s_SCLK : std_logic;
50 signal s_SCLK : std_logic;
50 signal Send : std_logic;
51 signal Send : std_logic;
51
52
52 begin
53 begin
53
54
54 SystemCLK : Systeme_Clock
55 SystemCLK : Systeme_Clock
55 generic map (cpt_serial)
56 generic map (cpt_serial)
56 port map (clk,rst,s_SCLK);
57 port map (clk,rst,s_SCLK);
57
58
58
59
59 Signal_sync : Gene_SYNC
60 Signal_sync : Gene_SYNC
60 port map (s_SCLK,rst,enable,Send,SYNC);
61 port map (s_SCLK,rst,enable,Send,SYNC);
61
62
62
63
63 Serial : serialize
64 Serial : serialize
64 port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
65 port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
65
66
66 RenGEN : ReadFifo_GEN
67 RenGEN : ReadFifo_GEN
67 port map (clk,rst,Send,Readn);
68 port map (clk,rst,Send,Readn);
68
69
69 SCLK <= s_SCLK;
70 SCLK <= s_SCLK;
70
71
71 end architecture; No newline at end of file
72 end architecture;
Show file before | Show file after | Hide comments
@@ -1,108 +1,126
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant intgr dans le lon
31
32 package lpp_cna is
33
34 TYPE CNA_16bit_T IS ARRAY(NATURAL RANGE <>,NATURAL RANGE <>) of std_logic;
31
35
32 package lpp_cna is
36 component DAC8581 is
37 generic(
38 clkfreq : integer := 100;
39 ChanCount : integer := 8
40 );
41 Port ( clk : in STD_LOGIC;
42 rstn : in STD_LOGIC;
43 smpclk : in STD_LOGIC;
44 sclk : out STD_LOGIC;
45 csn : out STD_LOGIC;
46 sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0);
47 smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
48 );
49 end component;
50
33
51
34 component APB_DAC is
52 component APB_DAC is
35 generic (
53 generic (
36 pindex : integer := 0;
54 pindex : integer := 0;
37 paddr : integer := 0;
55 paddr : integer := 0;
38 pmask : integer := 16#fff#;
56 pmask : integer := 16#fff#;
39 pirq : integer := 0;
57 pirq : integer := 0;
40 abits : integer := 8;
58 abits : integer := 8;
41 cpt_serial : integer := 6);
59 cpt_serial : integer := 6);
42 port (
60 port (
43 clk : in std_logic;
61 clk : in std_logic;
44 rst : in std_logic;
62 rst : in std_logic;
45 apbi : in apb_slv_in_type;
63 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
64 apbo : out apb_slv_out_type;
47 DataIN : in std_logic_vector(15 downto 0);
65 DataIN : in std_logic_vector(15 downto 0);
48 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
66 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
49 Readn : out std_logic;
67 Readn : out std_logic;
50 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
68 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
51 SCLK : out std_logic; --! Horloge systeme du convertisseur
69 SCLK : out std_logic; --! Horloge systeme du convertisseur
52 DATA : out std_logic
70 DATA : out std_logic
53 );
71 );
54 end component;
72 end component;
55
73
56
74
57 component DacDriver is
75 component DacDriver is
58 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
76 generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz
59 port(
77 port(
60 clk : in std_logic;
78 clk : in std_logic;
61 rst : in std_logic;
79 rst : in std_logic;
62 enable : in std_logic;
80 enable : in std_logic;
63 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
81 Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits
64 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
82 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
65 SCLK : out std_logic; --! Horloge systeme du convertisseur
83 SCLK : out std_logic; --! Horloge systeme du convertisseur
66 Readn : out std_logic;
84 Readn : out std_logic;
67 Ready : out std_logic;
85 Ready : out std_logic;
68 Data : out std_logic
86 Data : out std_logic
69 );
87 );
70 end component;
88 end component;
71
89
72
90
73 component Systeme_Clock is
91 component Systeme_Clock is
74 generic(N :integer := 695);
92 generic(N :integer := 695);
75 port(
93 port(
76 clk, raz : in std_logic ;
94 clk, raz : in std_logic ;
77 sclk : out std_logic);
95 sclk : out std_logic);
78 end component;
96 end component;
79
97
80
98
81 component Gene_SYNC is
99 component Gene_SYNC is
82 port(
100 port(
83 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
101 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
84 enable : in std_logic; --! Autorise ou non l'utilisation du composant
102 enable : in std_logic; --! Autorise ou non l'utilisation du composant
85 Send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
103 Send : out std_logic; --! Flag, Autorise l'envoi (srialisation) d'une nouvelle donne
86 SYNC : out std_logic); --! Signal de synchronisation du convertisseur g�n�r�
104 SYNC : out std_logic); --! Signal de synchronisation du convertisseur gnr
87 end component;
105 end component;
88
106
89
107
90 component Serialize is
108 component Serialize is
91 port(
109 port(
92 clk,raz : in std_logic;
110 clk,raz : in std_logic;
93 sclk : in std_logic;
111 sclk : in std_logic;
94 vectin : in std_logic_vector(15 downto 0);
112 vectin : in std_logic_vector(15 downto 0);
95 send : in std_logic;
113 send : in std_logic;
96 sended : out std_logic;
114 sended : out std_logic;
97 Data : out std_logic);
115 Data : out std_logic);
98 end component;
116 end component;
99
117
100 component ReadFifo_GEN is
118 component ReadFifo_GEN is
101 port(
119 port(
102 clk,raz : in std_logic; --! Horloge et Reset du composant
120 clk,raz : in std_logic; --! Horloge et Reset du composant
103 SYNC : in std_logic;
121 SYNC : in std_logic;
104 Readn : out std_logic
122 Readn : out std_logic
105 );
123 );
106 end component;
124 end component;
107
125
108 end; No newline at end of file
126 end;
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