diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd --- a/designs/BeagleSynth/BeagleSynth.vhd +++ b/designs/BeagleSynth/BeagleSynth.vhd @@ -20,6 +20,7 @@ use lpp.lpp_ad_conv.all; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.general_purpose.all; +use lpp.lpp_cna.all; Library UNISIM; use UNISIM.vcomponents.all; @@ -47,7 +48,7 @@ entity BeagleSynth is DAC_nCLR : out std_ulogic; DAC_nCS : out std_ulogic; CAL_IN_SCK : out std_ulogic; - DAC_SDI : out std_ulogic_vector(7 downto 0); + DAC_SDI : out std_logic_vector(7 downto 0); TXD : out std_ulogic; RXD : in std_ulogic; urxd1 : in std_ulogic; @@ -111,12 +112,27 @@ signal apbuarto : uart_out_type; signal led2int : std_logic; + +signal DAC0_DATA : std_logic_vector(15 downto 0); +signal DAC1_DATA : std_logic_vector(15 downto 0); +signal DAC2_DATA : std_logic_vector(15 downto 0); +signal DAC3_DATA : std_logic_vector(15 downto 0); +signal DAC4_DATA : std_logic_vector(15 downto 0); +signal DAC5_DATA : std_logic_vector(15 downto 0); +signal DAC6_DATA : std_logic_vector(15 downto 0); +signal DAC7_DATA : std_logic_vector(15 downto 0); + +signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); +signal smpclk : std_logic; +signal smpclk_reg : std_logic; +signal DAC_SDO : std_logic; + begin DAC_nCLR <= '1'; -DAC_nCS <= '1'; -CAL_IN_SCK <= '1'; -DAC_SDI <= (others =>'1'); +--DAC_nCS <= SYNC; +--CAL_IN_SCK <= '1'; +--DAC_SDI <= (others =>'1'); resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); @@ -246,6 +262,67 @@ sdcasn <= sdo.casn; sddqm <= sdo.dqm(3 downto 0); +DAC0 : DAC8581 + generic map(100,8) + Port map( + clk => clkm, + rstn => rstn, + smpclk => smpclk, + sclk => CAL_IN_SCK, + csn => DAC_nCS, + sdo => DAC_SDI, + smp_in => DAC_DATA + ); + + + + smpclk0: Clk_divider + GENERIC map(OSC_freqHz => 50000000, + TargetFreq_Hz => 256000) + PORT map( clk => clkm, + reset => rstn, + clk_divided => smpclk + ); + +all_bits: FOR I in 15 downto 0 GENERATE + DAC_DATA(0,I) <= DAC0_DATA(I); + DAC_DATA(1,I) <= DAC1_DATA(I); + DAC_DATA(2,I) <= DAC2_DATA(I); + DAC_DATA(3,I) <= DAC3_DATA(I); + DAC_DATA(4,I) <= DAC4_DATA(I); + DAC_DATA(5,I) <= DAC5_DATA(I); + DAC_DATA(6,I) <= DAC6_DATA(I); + DAC_DATA(7,I) <= DAC7_DATA(I); +end GENERATE; + +process(clkm,rstn) +begin +if rstn ='0' then + DAC0_DATA <= X"0000"; + DAC1_DATA <= X"0000"; + DAC2_DATA <= X"0000"; + DAC3_DATA <= X"0000"; + DAC4_DATA <= X"0000"; + DAC5_DATA <= X"0000"; + DAC6_DATA <= X"0000"; + DAC7_DATA <= X"0000"; + smpclk_reg <= smpclk; +elsif clkm'event and clkm = '1' then + smpclk_reg <= smpclk; + if smpclk_reg = '0' and smpclk = '1' then + DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1); + DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2); + DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3); + DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4); + DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5); + DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6); + DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7); + DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8); +-- DAC_DATA <= "0100000000000000"; + end if; +end if; +end process; + end rtl; diff --git a/lib/lpp/lpp_cna/DAC8581.vhd b/lib/lpp/lpp_cna/DAC8581.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/DAC8581.vhd @@ -0,0 +1,130 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:26:29 12/07/2013 +-- Design Name: +-- Module Name: DAC8581 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; +library LPP; +use lpp.lpp_cna.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity DAC8581 is + generic( + clkfreq : integer := 100; + ChanCount : integer := 8 + ); + Port ( clk : in STD_LOGIC; + rstn : in STD_LOGIC; + smpclk : in STD_LOGIC; + sclk : out STD_LOGIC; + csn : out STD_LOGIC; + sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0); + smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0) + ); +end DAC8581; + +architecture Behavioral of DAC8581 is + +signal smpclk_reg : std_logic; +signal sclk_gen : std_logic_vector(3 downto 0); +signal sclk_net : std_logic; +signal load : std_logic; +signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0); +signal csn_sreg : std_logic_vector(15 downto 0); + +begin + + + +sclk_net <= sclk_gen(1); +sclk <= sclk_net; + +process(rstn,clk) +begin +if rstn ='0' then + smpclk_reg <= '0'; + sclk_gen <= "0000"; + load <= '0'; +elsif clk'event and clk = '1' then + smpclk_reg <= smpclk; + sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1); + if smpclk_reg = '0' and smpclk = '1' then + load <= '1'; + else + load <= '0'; + end if; + +end if; +end process; + +process(load,sclk_net) +begin +if load ='1' then + data_sreg <= smp_in; + csn_sreg <= (others => '0'); + +elsif sclk_net'event and sclk_net = '1' then + all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP + all_bits0 : FOR J IN 14 DOWNTO 0 LOOP + data_sreg(I,J+1) <= data_sreg(I,J); + END LOOP all_bits0; + data_sreg(I,0) <= '1'; + END LOOP all_chanel0; + csn_sreg <= csn_sreg(14 downto 0) & '1'; +end if; +end process; + +process(rstn,sclk_net) +begin +if rstn ='0' then + all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP + sdo(I) <= '1'; + END LOOP all_chanel2; + csn <= '1'; +elsif sclk_net'event and sclk_net = '0' then + all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP + sdo(I) <= data_sreg(I,15); + END LOOP all_chanel1; + csn <= csn_sreg(15); +end if; +end process; + + + +end Behavioral; + + + + + + + + + + + + diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd --- a/lib/lpp/lpp_cna/DacDriver.vhd +++ b/lib/lpp/lpp_cna/DacDriver.vhd @@ -21,28 +21,29 @@ ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; +use IEEE.numeric_std.all; +library LPP; use lpp.lpp_cna.all; ---! Programme du Convertisseur Numérique/Analogique +--! Programme du Convertisseur Numrique/Analogique entity DacDriver is -generic(cpt_serial : integer := 6); --! Générique contenant le résultat de la division clk/sclk !!! clk=25Mhz +generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz port( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant enable : in std_logic; --! Autorise ou non l'utilisation du composant - Data_IN : in std_logic_vector(15 downto 0); --! Donnée Numérique d'entrée sur 16 bits + Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits SYNC : out std_logic; --! Signal de synchronisation du convertisseur SCLK : out std_logic; --! Horloge systeme du convertisseur Readn : out std_logic; - Ready : out std_logic; --! Flag, signale la fin de la sérialisation d'une donnée - Data : out std_logic --! Donnée numérique sérialisé + Ready : out std_logic; --! Flag, signale la fin de la srialisation d'une donne + Data : out std_logic --! Donne numrique srialis ); end entity; ---! @details Un driver C va permettre de génerer un tableau de données sur 16 bits, ---! qui seront sérialisé pour étre ensuite dirigées vers le convertisseur. +--! @details Un driver C va permettre de gnerer un tableau de donnes sur 16 bits, +--! qui seront srialis pour tre ensuite diriges vers le convertisseur. architecture ar_DacDriver of DacDriver is diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -27,9 +27,27 @@ use std.textio.all; library lpp; use lpp.lpp_amba.all; ---! Package contenant tous les programmes qui forment le composant intégré dans le léon +--! Package contenant tous les programmes qui forment le composant intgr dans le lon + +package lpp_cna is + +TYPE CNA_16bit_T IS ARRAY(NATURAL RANGE <>,NATURAL RANGE <>) of std_logic; -package lpp_cna is +component DAC8581 is + generic( + clkfreq : integer := 100; + ChanCount : integer := 8 + ); + Port ( clk : in STD_LOGIC; + rstn : in STD_LOGIC; + smpclk : in STD_LOGIC; + sclk : out STD_LOGIC; + csn : out STD_LOGIC; + sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0); + smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0) + ); +end component; + component APB_DAC is generic ( @@ -55,12 +73,12 @@ end component; component DacDriver is -generic(cpt_serial : integer := 6); --! Générique contenant le résultat de la division clk/sclk !!! clk=25Mhz +generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz port( clk : in std_logic; rst : in std_logic; enable : in std_logic; - Data_IN : in std_logic_vector(15 downto 0); --! Donnée Numérique d'entrée sur 16 bits + Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits SYNC : out std_logic; --! Signal de synchronisation du convertisseur SCLK : out std_logic; --! Horloge systeme du convertisseur Readn : out std_logic; @@ -82,8 +100,8 @@ component Gene_SYNC is port( SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant enable : in std_logic; --! Autorise ou non l'utilisation du composant - Send : out std_logic; --! Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée - SYNC : out std_logic); --! Signal de synchronisation du convertisseur généré + Send : out std_logic; --! Flag, Autorise l'envoi (srialisation) d'une nouvelle donne + SYNC : out std_logic); --! Signal de synchronisation du convertisseur gnr end component; @@ -105,4 +123,4 @@ component ReadFifo_GEN is ); end component; -end; \ No newline at end of file +end;