##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

DAC8581 driver added
Jeandet Alexis -
r271:a0ad26a05201 alexis
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,130
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:26:29 12/07/2013
6 -- Design Name:
7 -- Module Name: DAC8581 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.numeric_std.all;
23 library LPP;
24 use lpp.lpp_cna.all;
25
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 use IEEE.NUMERIC_STD.ALL;
29
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 --library UNISIM;
33 --use UNISIM.VComponents.all;
34
35 entity DAC8581 is
36 generic(
37 clkfreq : integer := 100;
38 ChanCount : integer := 8
39 );
40 Port ( clk : in STD_LOGIC;
41 rstn : in STD_LOGIC;
42 smpclk : in STD_LOGIC;
43 sclk : out STD_LOGIC;
44 csn : out STD_LOGIC;
45 sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0);
46 smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
47 );
48 end DAC8581;
49
50 architecture Behavioral of DAC8581 is
51
52 signal smpclk_reg : std_logic;
53 signal sclk_gen : std_logic_vector(3 downto 0);
54 signal sclk_net : std_logic;
55 signal load : std_logic;
56 signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
57 signal csn_sreg : std_logic_vector(15 downto 0);
58
59 begin
60
61
62
63 sclk_net <= sclk_gen(1);
64 sclk <= sclk_net;
65
66 process(rstn,clk)
67 begin
68 if rstn ='0' then
69 smpclk_reg <= '0';
70 sclk_gen <= "0000";
71 load <= '0';
72 elsif clk'event and clk = '1' then
73 smpclk_reg <= smpclk;
74 sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1);
75 if smpclk_reg = '0' and smpclk = '1' then
76 load <= '1';
77 else
78 load <= '0';
79 end if;
80
81 end if;
82 end process;
83
84 process(load,sclk_net)
85 begin
86 if load ='1' then
87 data_sreg <= smp_in;
88 csn_sreg <= (others => '0');
89
90 elsif sclk_net'event and sclk_net = '1' then
91 all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
92 all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
93 data_sreg(I,J+1) <= data_sreg(I,J);
94 END LOOP all_bits0;
95 data_sreg(I,0) <= '1';
96 END LOOP all_chanel0;
97 csn_sreg <= csn_sreg(14 downto 0) & '1';
98 end if;
99 end process;
100
101 process(rstn,sclk_net)
102 begin
103 if rstn ='0' then
104 all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
105 sdo(I) <= '1';
106 END LOOP all_chanel2;
107 csn <= '1';
108 elsif sclk_net'event and sclk_net = '0' then
109 all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
110 sdo(I) <= data_sreg(I,15);
111 END LOOP all_chanel1;
112 csn <= csn_sreg(15);
113 end if;
114 end process;
115
116
117
118 end Behavioral;
119
120
121
122
123
124
125
126
127
128
129
130
Show file before | Show file after | Hide comments
@@ -20,6 +20,7 use lpp.lpp_ad_conv.all;
20 20 use lpp.lpp_amba.all;
21 21 use lpp.apb_devices_list.all;
22 22 use lpp.general_purpose.all;
23 use lpp.lpp_cna.all;
23 24
24 25 Library UNISIM;
25 26 use UNISIM.vcomponents.all;
@@ -47,7 +48,7 entity BeagleSynth is
47 48 DAC_nCLR : out std_ulogic;
48 49 DAC_nCS : out std_ulogic;
49 50 CAL_IN_SCK : out std_ulogic;
50 DAC_SDI : out std_ulogic_vector(7 downto 0);
51 DAC_SDI : out std_logic_vector(7 downto 0);
51 52 TXD : out std_ulogic;
52 53 RXD : in std_ulogic;
53 54 urxd1 : in std_ulogic;
@@ -111,12 +112,27 signal apbuarto : uart_out_type;
111 112
112 113 signal led2int : std_logic;
113 114
115
116 signal DAC0_DATA : std_logic_vector(15 downto 0);
117 signal DAC1_DATA : std_logic_vector(15 downto 0);
118 signal DAC2_DATA : std_logic_vector(15 downto 0);
119 signal DAC3_DATA : std_logic_vector(15 downto 0);
120 signal DAC4_DATA : std_logic_vector(15 downto 0);
121 signal DAC5_DATA : std_logic_vector(15 downto 0);
122 signal DAC6_DATA : std_logic_vector(15 downto 0);
123 signal DAC7_DATA : std_logic_vector(15 downto 0);
124
125 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
126 signal smpclk : std_logic;
127 signal smpclk_reg : std_logic;
128 signal DAC_SDO : std_logic;
129
114 130 begin
115 131
116 132 DAC_nCLR <= '1';
117 DAC_nCS <= '1';
118 CAL_IN_SCK <= '1';
119 DAC_SDI <= (others =>'1');
133 --DAC_nCS <= SYNC;
134 --CAL_IN_SCK <= '1';
135 --DAC_SDI <= (others =>'1');
120 136
121 137 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
122 138 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
@@ -246,6 +262,67 sdcasn <= sdo.casn;
246 262 sddqm <= sdo.dqm(3 downto 0);
247 263
248 264
265 DAC0 : DAC8581
266 generic map(100,8)
267 Port map(
268 clk => clkm,
269 rstn => rstn,
270 smpclk => smpclk,
271 sclk => CAL_IN_SCK,
272 csn => DAC_nCS,
273 sdo => DAC_SDI,
274 smp_in => DAC_DATA
275 );
276
277
278
279 smpclk0: Clk_divider
280 GENERIC map(OSC_freqHz => 50000000,
281 TargetFreq_Hz => 256000)
282 PORT map( clk => clkm,
283 reset => rstn,
284 clk_divided => smpclk
285 );
286
287 all_bits: FOR I in 15 downto 0 GENERATE
288 DAC_DATA(0,I) <= DAC0_DATA(I);
289 DAC_DATA(1,I) <= DAC1_DATA(I);
290 DAC_DATA(2,I) <= DAC2_DATA(I);
291 DAC_DATA(3,I) <= DAC3_DATA(I);
292 DAC_DATA(4,I) <= DAC4_DATA(I);
293 DAC_DATA(5,I) <= DAC5_DATA(I);
294 DAC_DATA(6,I) <= DAC6_DATA(I);
295 DAC_DATA(7,I) <= DAC7_DATA(I);
296 end GENERATE;
297
298 process(clkm,rstn)
299 begin
300 if rstn ='0' then
301 DAC0_DATA <= X"0000";
302 DAC1_DATA <= X"0000";
303 DAC2_DATA <= X"0000";
304 DAC3_DATA <= X"0000";
305 DAC4_DATA <= X"0000";
306 DAC5_DATA <= X"0000";
307 DAC6_DATA <= X"0000";
308 DAC7_DATA <= X"0000";
309 smpclk_reg <= smpclk;
310 elsif clkm'event and clkm = '1' then
311 smpclk_reg <= smpclk;
312 if smpclk_reg = '0' and smpclk = '1' then
313 DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
314 DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
315 DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
316 DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
317 DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
318 DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
319 DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
320 DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
321 -- DAC_DATA <= "0100000000000000";
322 end if;
323 end if;
324 end process;
325
249 326
250 327 end rtl;
251 328
Show file before | Show file after | Hide comments
@@ -21,28 +21,29
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library LPP;
25 26 use lpp.lpp_cna.all;
26 27
27 --! Programme du Convertisseur Num�rique/Analogique
28 --! Programme du Convertisseur Numrique/Analogique
28 29
29 30 entity DacDriver is
30 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
31 generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz
31 32 port(
32 33 clk : in std_logic; --! Horloge du composant
33 34 rst : in std_logic; --! Reset general du composant
34 35 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits
36 37 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 38 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 39 Readn : out std_logic;
39 Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
40 Data : out std_logic --! Donn�e num�rique s�rialis�
40 Ready : out std_logic; --! Flag, signale la fin de la srialisation d'une donne
41 Data : out std_logic --! Donne numrique srialis
41 42 );
42 43 end entity;
43 44
44 --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
45 --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
45 --! @details Un driver C va permettre de gnerer un tableau de donnes sur 16 bits,
46 --! qui seront srialis pour tre ensuite diriges vers le convertisseur.
46 47
47 48 architecture ar_DacDriver of DacDriver is
48 49
Show file before | Show file after | Hide comments
@@ -27,9 +27,27 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant intgr dans le lon
31
32 package lpp_cna is
33
34 TYPE CNA_16bit_T IS ARRAY(NATURAL RANGE <>,NATURAL RANGE <>) of std_logic;
31 35
32 package lpp_cna is
36 component DAC8581 is
37 generic(
38 clkfreq : integer := 100;
39 ChanCount : integer := 8
40 );
41 Port ( clk : in STD_LOGIC;
42 rstn : in STD_LOGIC;
43 smpclk : in STD_LOGIC;
44 sclk : out STD_LOGIC;
45 csn : out STD_LOGIC;
46 sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0);
47 smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
48 );
49 end component;
50
33 51
34 52 component APB_DAC is
35 53 generic (
@@ -55,12 +73,12 end component;
55 73
56 74
57 75 component DacDriver is
58 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
76 generic(cpt_serial : integer := 6); --! Gnrique contenant le rsultat de la division clk/sclk !!! clk=25Mhz
59 77 port(
60 78 clk : in std_logic;
61 79 rst : in std_logic;
62 80 enable : in std_logic;
63 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
81 Data_IN : in std_logic_vector(15 downto 0); --! Donne Numrique d'entre sur 16 bits
64 82 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
65 83 SCLK : out std_logic; --! Horloge systeme du convertisseur
66 84 Readn : out std_logic;
@@ -82,8 +100,8 component Gene_SYNC is
82 100 port(
83 101 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
84 102 enable : in std_logic; --! Autorise ou non l'utilisation du composant
85 Send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
86 SYNC : out std_logic); --! Signal de synchronisation du convertisseur g�n�r�
103 Send : out std_logic; --! Flag, Autorise l'envoi (srialisation) d'une nouvelle donne
104 SYNC : out std_logic); --! Signal de synchronisation du convertisseur gnr
87 105 end component;
88 106
89 107
@@ -105,4 +123,4 component ReadFifo_GEN is
105 123 );
106 124 end component;
107 125
108 end; No newline at end of file
126 end;
General Comments 0
You need to be logged in to leave comments. Login now