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MINI LFR blank project
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r266:9d30a6656705 MINI_LFR_BLANK_PROJECT JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.iir_filter.ALL;
43 USE lpp.general_purpose.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
46
47 ENTITY MINI_LFR_top IS
48
49 PORT (
50 clk_50 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
53 --BPs
54 BP0 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
56 --LEDs
57 LED0 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
60 --UARTs
61 TXD1 : IN STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
65
66 TXD2 : IN STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
72
73 --EXT CONNECTOR
74 IO0 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
86
87 --SPACE WIRE
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
97 -- MINI LFR ADC INPUTS
98 ADC_nCS : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101
102 -- SRAM
103 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 );
110
111 END MINI_LFR_top;
112
113
114 ARCHITECTURE beh OF MINI_LFR_top IS
115 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_25 : STD_LOGIC := '0';
117 -----------------------------------------------------------------------------
118 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 --
121 SIGNAL errorn : STD_LOGIC;
122 -- UART AHB ---------------------------------------------------------------
123 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
124 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
125
126 -- UART APB ---------------------------------------------------------------
127 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
128 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
129 --
130 SIGNAL I00_s : STD_LOGIC;
131 --
132 CONSTANT NB_APB_SLAVE : INTEGER := 1;
133 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
134 CONSTANT NB_AHB_MASTER : INTEGER := 1;
135
136 SIGNAL apbi_ext : apb_slv_in_type;
137 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
138 SIGNAL ahbi_s_ext : ahb_slv_in_type;
139 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
140 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
141 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
142
143 BEGIN -- beh
144
145 -----------------------------------------------------------------------------
146 -- CLK
147 -----------------------------------------------------------------------------
148
149 PROCESS(clk_50)
150 BEGIN
151 IF clk_50'EVENT AND clk_50 = '1' THEN
152 clk_50_s <= NOT clk_50_s;
153 END IF;
154 END PROCESS;
155
156 PROCESS(clk_50_s)
157 BEGIN
158 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
159 clk_25 <= NOT clk_25;
160 END IF;
161 END PROCESS;
162
163 -----------------------------------------------------------------------------
164
165 PROCESS (clk_25, reset)
166 BEGIN -- PROCESS
167 IF reset = '0' THEN -- asynchronous reset (active low)
168 LED0 <= '0';
169 LED1 <= '0';
170 LED2 <= '0';
171 IO1 <= '0';
172 IO2 <= '1';
173 IO3 <= '0';
174 IO4 <= '0';
175 IO5 <= '0';
176 IO6 <= '0';
177 IO7 <= '0';
178 IO8 <= '0';
179 IO9 <= '0';
180 IO10 <= '0';
181 IO11 <= '0';
182 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
183 LED0 <= '0';
184 LED1 <= '1';
185 LED2 <= BP0;
186 IO1 <= '1';
187 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
188 IO3 <= ADC_SDO(0);
189 IO4 <= ADC_SDO(1);
190 IO5 <= ADC_SDO(2);
191 IO6 <= ADC_SDO(3);
192 IO7 <= ADC_SDO(4);
193 IO8 <= ADC_SDO(5);
194 IO9 <= ADC_SDO(6);
195 IO10 <= ADC_SDO(7);
196 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
197 END IF;
198 END PROCESS;
199
200 PROCESS (clk_49, reset)
201 BEGIN -- PROCESS
202 IF reset = '0' THEN -- asynchronous reset (active low)
203 I00_s <= '0';
204 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
205 I00_s <= NOT I00_s;
206 END IF;
207 END PROCESS;
208 IO0 <= I00_s;
209
210 --UARTs
211 nCTS1 <= '1';
212 nCTS2 <= '1';
213 nDCD2 <= '1';
214
215 --EXT CONNECTOR
216
217 --SPACE WIRE
218 SPW_EN <= '0'; -- 0 => off
219
220 SPW_NOM_DOUT <= '0';
221 SPW_NOM_SOUT <= '0';
222 SPW_RED_DOUT <= '0';
223 SPW_RED_SOUT <= '0';
224
225 ADC_nCS <= '0';
226 ADC_CLK <= '0';
227
228
229 leon3_soc_1: leon3_soc
230 GENERIC MAP (
231 fabtech => apa3e,
232 memtech => apa3e,
233 padtech => inferred,
234 clktech => inferred,
235 disas => 0,
236 dbguart => 0,
237 pclow => 2,
238 clk_freq => 25000,
239 NB_CPU => 1,
240 ENABLE_FPU => 0,
241 FPU_NETLIST => 0,
242 ENABLE_DSU => 1,
243 ENABLE_AHB_UART => 1,
244 ENABLE_APB_UART => 1,
245 ENABLE_IRQMP => 1,
246 ENABLE_GPT => 1,
247 NB_AHB_MASTER => NB_AHB_MASTER,
248 NB_AHB_SLAVE => NB_AHB_SLAVE,
249 NB_APB_SLAVE => NB_APB_SLAVE)
250 PORT MAP (
251 clk => clk_25,
252 reset => reset,
253 errorn => errorn,
254 ahbrxd => TXD1,
255 ahbtxd => RXD1,
256 urxd1 => TXD2,
257 utxd1 => RXD2,
258 address => SRAM_A,
259 data => SRAM_DQ,
260 nSRAM_BE0 => SRAM_nBE(0),
261 nSRAM_BE1 => SRAM_nBE(1),
262 nSRAM_BE2 => SRAM_nBE(2),
263 nSRAM_BE3 => SRAM_nBE(3),
264 nSRAM_WE => SRAM_nWE,
265 nSRAM_CE => SRAM_CE,
266 nSRAM_OE => SRAM_nOE,
267
268 apbi_ext => apbi_ext,
269 apbo_ext => apbo_ext,
270 ahbi_s_ext => ahbi_s_ext,
271 ahbo_s_ext => ahbo_s_ext,
272 ahbi_m_ext => ahbi_m_ext,
273 ahbo_m_ext => ahbo_m_ext);
274
275 END beh;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44
45 ENTITY leon3_soc IS
46 GENERIC (
47 fabtech : INTEGER := apa3e;
48 memtech : INTEGER := apa3e;
49 padtech : INTEGER := inferred;
50 clktech : INTEGER := inferred;
51 disas : INTEGER := 0; -- Enable disassembly to console
52 dbguart : INTEGER := 0; -- Print UART on console
53 pclow : INTEGER := 2;
54 --
55 clk_freq : INTEGER := 25000; --kHz
56 --
57 NB_CPU : INTEGER := 1;
58 ENABLE_FPU : INTEGER := 1;
59 FPU_NETLIST : INTEGER := 1;
60 ENABLE_DSU : INTEGER := 1;
61 ENABLE_AHB_UART : INTEGER := 1;
62 ENABLE_APB_UART : INTEGER := 1;
63 ENABLE_IRQMP : INTEGER := 1;
64 ENABLE_GPT : INTEGER := 1;
65 --
66 NB_AHB_MASTER : INTEGER := 0;
67 NB_AHB_SLAVE : INTEGER := 0;
68 NB_APB_SLAVE : INTEGER := 0
69 );
70 PORT (
71 clk : IN STD_ULOGIC;
72 reset : IN STD_ULOGIC;
73
74 errorn : OUT STD_ULOGIC;
75
76 -- UART AHB ---------------------------------------------------------------
77 ahbrxd : IN STD_ULOGIC; -- DSU rx data
78 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
79
80 -- UART APB ---------------------------------------------------------------
81 urxd1 : IN STD_ULOGIC; -- UART1 rx data
82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83
84 -- RAM --------------------------------------------------------------------
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 nSRAM_BE0 : OUT STD_LOGIC;
88 nSRAM_BE1 : OUT STD_LOGIC;
89 nSRAM_BE2 : OUT STD_LOGIC;
90 nSRAM_BE3 : OUT STD_LOGIC;
91 nSRAM_WE : OUT STD_LOGIC;
92 nSRAM_CE : OUT STD_LOGIC;
93 nSRAM_OE : OUT STD_LOGIC;
94
95 -- APB --------------------------------------------------------------------
96 apbi_ext : OUT apb_slv_in_type;
97 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
98 -- AHB_Slave --------------------------------------------------------------
99 ahbi_s_ext : OUT ahb_slv_in_type;
100 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
101 -- AHB_Master -------------------------------------------------------------
102 ahbi_m_ext : OUT AHB_Mst_In_Type;
103 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
104
105 );
106 END;
107
108 ARCHITECTURE Behavioral OF leon3_soc IS
109
110 -----------------------------------------------------------------------------
111 -- CONFIG -------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
114 -- Clock generator
115 constant CFG_CLKMUL : integer := (1);
116 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
117 constant CFG_OCLKDIV : integer := (1);
118 constant CFG_CLK_NOFB : integer := 0;
119 -- LEON3 processor core
120 constant CFG_LEON3 : integer := 1;
121 constant CFG_NCPU : integer := NB_CPU;
122 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
123 constant CFG_V8 : integer := 0;
124 constant CFG_MAC : integer := 0;
125 constant CFG_SVT : integer := 0;
126 constant CFG_RSTADDR : integer := 16#00000#;
127 constant CFG_LDDEL : integer := (1);
128 constant CFG_NWP : integer := (0);
129 constant CFG_PWD : integer := 1*2;
130 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
131 -- 1*(8 + 16 * 0) => grfpu-light
132 -- 1*(8 + 16 * 1) => netlist
133 -- 0*(8 + 16 * 0) => No FPU
134 -- 0*(8 + 16 * 1) => No FPU;
135 constant CFG_ICEN : integer := 1;
136 constant CFG_ISETS : integer := 1;
137 constant CFG_ISETSZ : integer := 4;
138 constant CFG_ILINE : integer := 4;
139 constant CFG_IREPL : integer := 0;
140 constant CFG_ILOCK : integer := 0;
141 constant CFG_ILRAMEN : integer := 0;
142 constant CFG_ILRAMADDR: integer := 16#8E#;
143 constant CFG_ILRAMSZ : integer := 1;
144 constant CFG_DCEN : integer := 1;
145 constant CFG_DSETS : integer := 1;
146 constant CFG_DSETSZ : integer := 4;
147 constant CFG_DLINE : integer := 4;
148 constant CFG_DREPL : integer := 0;
149 constant CFG_DLOCK : integer := 0;
150 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
151 constant CFG_DLRAMEN : integer := 0;
152 constant CFG_DLRAMADDR: integer := 16#8F#;
153 constant CFG_DLRAMSZ : integer := 1;
154 constant CFG_MMUEN : integer := 0;
155 constant CFG_ITLBNUM : integer := 2;
156 constant CFG_DTLBNUM : integer := 2;
157 constant CFG_TLB_TYPE : integer := 1 + 0*2;
158 constant CFG_TLB_REP : integer := 1;
159
160 constant CFG_DSU : integer := ENABLE_DSU;
161 constant CFG_ITBSZ : integer := 0;
162 constant CFG_ATBSZ : integer := 0;
163
164 -- AMBA settings
165 constant CFG_DEFMST : integer := (0);
166 constant CFG_RROBIN : integer := 1;
167 constant CFG_SPLIT : integer := 0;
168 constant CFG_AHBIO : integer := 16#FFF#;
169 constant CFG_APBADDR : integer := 16#800#;
170
171 -- DSU UART
172 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
173
174 -- LEON2 memory controller
175 constant CFG_MCTRL_SDEN : integer := 0;
176
177 -- UART 1
178 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
179 constant CFG_UART1_FIFO : integer := 1;
180
181 -- LEON3 interrupt controller
182 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
183
184 -- Modular timer
185 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
186 constant CFG_GPT_NTIM : integer := (2);
187 constant CFG_GPT_SW : integer := (8);
188 constant CFG_GPT_TW : integer := (32);
189 constant CFG_GPT_IRQ : integer := (8);
190 constant CFG_GPT_SEPIRQ : integer := 1;
191 constant CFG_GPT_WDOGEN : integer := 0;
192 constant CFG_GPT_WDOG : integer := 16#0#;
193 -----------------------------------------------------------------------------
194
195 -----------------------------------------------------------------------------
196 -- SIGNALs
197 -----------------------------------------------------------------------------
198 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
199 -- CLK & RST --
200 SIGNAL clk2x : STD_ULOGIC;
201 SIGNAL clkmn : STD_ULOGIC;
202 SIGNAL clkm : STD_ULOGIC;
203 SIGNAL rstn : STD_ULOGIC;
204 SIGNAL rstraw : STD_ULOGIC;
205 SIGNAL pciclk : STD_ULOGIC;
206 SIGNAL sdclkl : STD_ULOGIC;
207 SIGNAL cgi : clkgen_in_type;
208 SIGNAL cgo : clkgen_out_type;
209 --- AHB / APB
210 SIGNAL apbi : apb_slv_in_type;
211 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
212 SIGNAL ahbsi : ahb_slv_in_type;
213 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
214 SIGNAL ahbmi : ahb_mst_in_type;
215 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
216 --UART
217 SIGNAL ahbuarti : uart_in_type;
218 SIGNAL ahbuarto : uart_out_type;
219 SIGNAL apbuarti : uart_in_type;
220 SIGNAL apbuarto : uart_out_type;
221 --MEM CTRLR
222 SIGNAL memi : memory_in_type;
223 SIGNAL memo : memory_out_type;
224 SIGNAL wpo : wprot_out_type;
225 SIGNAL sdo : sdram_out_type;
226 --IRQ
227 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
228 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
229 --Timer
230 SIGNAL gpti : gptimer_in_type;
231 SIGNAL gpto : gptimer_out_type;
232 --DSU
233 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
234 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
235 SIGNAL dsui : dsu_in_type;
236 SIGNAL dsuo : dsu_out_type;
237 -----------------------------------------------------------------------------
238 BEGIN
239
240
241 ----------------------------------------------------------------------
242 --- Reset and Clock generation -------------------------------------
243 ----------------------------------------------------------------------
244
245 cgi.pllctrl <= "00";
246 cgi.pllrst <= rstraw;
247
248 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
249
250 clkgen0 : clkgen -- clock generator
251 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
252 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
253 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
254
255 ----------------------------------------------------------------------
256 --- LEON3 processor / DSU / IRQ ------------------------------------
257 ----------------------------------------------------------------------
258
259 l3 : IF CFG_LEON3 = 1 GENERATE
260 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
261 u0 : leon3s -- LEON3 processor
262 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
263 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
264 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
265 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
266 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
267 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
268 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
269 irqi(i), irqo(i), dbgi(i), dbgo(i));
270 END GENERATE;
271 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
272
273 dsugen : IF CFG_DSU = 1 GENERATE
274 dsu0 : dsu3 -- LEON3 Debug Support Unit
275 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
276 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
277 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
278 dsui.enable <= '1';
279 dsui.break <= '0';
280 END GENERATE;
281 END GENERATE;
282
283 nodsu : IF CFG_DSU = 0 GENERATE
284 ahbso(2) <= ahbs_none;
285 dsuo.tstop <= '0';
286 dsuo.active <= '0';
287 END GENERATE;
288
289 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
290 irqctrl0 : irqmp -- interrupt controller
291 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
292 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
293 END GENERATE;
294 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
295 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
296 irqi(i).irl <= "0000";
297 END GENERATE;
298 apbo(2) <= apb_none;
299 END GENERATE;
300
301 ----------------------------------------------------------------------
302 --- Memory controllers ---------------------------------------------
303 ----------------------------------------------------------------------
304 memctrlr : mctrl GENERIC MAP (
305 hindex => 0,
306 pindex => 0,
307 paddr => 0,
308 srbanks => 1
309 )
310 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
311
312 memi.brdyn <= '1';
313 memi.bexcn <= '1';
314 memi.writen <= '1';
315 memi.wrn <= "1111";
316 memi.bwidth <= "10";
317
318 bdr : FOR i IN 0 TO 3 GENERATE
319 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
320 PORT MAP (
321 data(31-i*8 DOWNTO 24-i*8),
322 memo.data(31-i*8 DOWNTO 24-i*8),
323 memo.bdrive(i),
324 memi.data(31-i*8 DOWNTO 24-i*8));
325 END GENERATE;
326
327 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
328 PORT MAP (address, memo.address(21 DOWNTO 2));
329
330 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
331 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
332 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
333 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
334 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
335 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
336 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
337
338 ----------------------------------------------------------------------
339 --- AHB CONTROLLER -------------------------------------------------
340 ----------------------------------------------------------------------
341 ahb0 : ahbctrl -- AHB arbiter/multiplexer
342 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
343 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
344 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
345 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
346
347 ----------------------------------------------------------------------
348 --- AHB UART -------------------------------------------------------
349 ----------------------------------------------------------------------
350 dcomgen : IF CFG_AHB_UART = 1 GENERATE
351 dcom0 : ahbuart
352 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
353 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
354 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
355 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
356 END GENERATE;
357 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
358
359 ----------------------------------------------------------------------
360 --- APB Bridge -----------------------------------------------------
361 ----------------------------------------------------------------------
362 apb0 : apbctrl -- AHB/APB bridge
363 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
364 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
365
366 ----------------------------------------------------------------------
367 --- GPT Timer ------------------------------------------------------
368 ----------------------------------------------------------------------
369 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
370 timer0 : gptimer -- timer unit
371 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
372 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
373 nbits => CFG_GPT_TW)
374 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
375 gpti.dhalt <= dsuo.tstop;
376 gpti.extclk <= '0';
377 END GENERATE;
378 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
379
380
381 ----------------------------------------------------------------------
382 --- APB UART -------------------------------------------------------
383 ----------------------------------------------------------------------
384 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
385 uart1 : apbuart -- UART 1
386 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
387 fifosize => CFG_UART1_FIFO)
388 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
389 apbuarti.rxd <= urxd1;
390 apbuarti.extclk <= '0';
391 utxd1 <= apbuarto.txd;
392 apbuarti.ctsn <= '0';
393 END GENERATE;
394 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
395
396 -------------------------------------------------------------------------------
397 -- AMBA BUS -------------------------------------------------------------------
398 -------------------------------------------------------------------------------
399
400 -- APB --------------------------------------------------------------------
401 apbi_ext <= apbi;
402 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
403 max_16_apb: IF I + 5 < 16 GENERATE
404 apbo(I+5)<= apbo_ext(I+5);
405 END GENERATE max_16_apb;
406 END GENERATE all_apb;
407 -- AHB_Slave --------------------------------------------------------------
408 ahbi_s_ext <= ahbsi;
409 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
410 max_16_ahbs: IF I + 3 < 16 GENERATE
411 ahbso(I+3) <= ahbo_s_ext(I+3);
412 END GENERATE max_16_ahbs;
413 END GENERATE all_ahbs;
414 -- AHB_Master -------------------------------------------------------------
415 ahbi_m_ext <= ahbmi;
416 all_ahbm: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
417 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
418 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
419 END GENERATE max_16_ahbm;
420 END GENERATE all_ahbm;
421
422
423
424 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27
28 PACKAGE lpp_leon3_soc_pkg IS
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
34 COMPONENT leon3_soc
35 GENERIC (
36 fabtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
44 NB_CPU : INTEGER;
45 ENABLE_FPU : INTEGER;
46 FPU_NETLIST : INTEGER;
47 ENABLE_DSU : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
50 ENABLE_IRQMP : INTEGER;
51 ENABLE_GPT : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER);
55 PORT (
56 clk : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
58 errorn : OUT STD_ULOGIC;
59 ahbrxd : IN STD_ULOGIC;
60 ahbtxd : OUT STD_ULOGIC;
61 urxd1 : IN STD_ULOGIC;
62 utxd1 : OUT STD_ULOGIC;
63 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
64 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 nSRAM_BE0 : OUT STD_LOGIC;
66 nSRAM_BE1 : OUT STD_LOGIC;
67 nSRAM_BE2 : OUT STD_LOGIC;
68 nSRAM_BE3 : OUT STD_LOGIC;
69 nSRAM_WE : OUT STD_LOGIC;
70 nSRAM_CE : OUT STD_LOGIC;
71 nSRAM_OE : OUT STD_LOGIC;
72 apbi_ext : OUT apb_slv_in_type;
73 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
74 ahbi_s_ext : OUT ahb_slv_in_type;
75 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
76 ahbi_m_ext : OUT AHB_Mst_In_Type;
77 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
78 END COMPONENT;
79
80 END;
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1 lpp_leon3_soc_pkg.vhd
2 leon3_soc.vhd
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@@ -1,46 +1,50
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES=config.vhd leon3mp.vhd MINI-LFR-top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
14 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
15 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
16 CLEAN=soft-clean
17 CLEAN=soft-clean
17
18
18 TECHLIBS = proasic3e
19 TECHLIBS = proasic3e
19
20
20 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 tmtc openchip hynix ihp gleichmann micron usbhc
22 tmtc openchip hynix ihp gleichmann micron usbhc
22
23
23 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
25 ./amba_lcd_16x2_ctrlr \
26 ./amba_lcd_16x2_ctrlr \
26 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_delay \
29 ./general_purpose/lpp_delay \
29 ./dsp/lpp_fft \
30 ./dsp/lpp_fft \
30 ./lpp_bootloader \
31 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_cna \
32 ./lpp_demux \
33 ./lpp_demux \
33 ./lpp_matrix \
34 ./lpp_matrix \
34 ./lpp_uart \
35 ./lpp_uart \
35 ./lpp_usb \
36 ./lpp_usb \
36 ./lpp_Header \
37 ./lpp_Header \
37
38
38 FILESKIP = i2cmst.vhd \
39 FILESKIP =lpp_lfr_ms.vhd \
40 i2cmst.vhd \
39 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
40 APB_SIMPLE_DIODE.vhd
42 APB_SIMPLE_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
41
45
42 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
47 include $(GRLIB)/software/leon3/Makefile
44
48
45 ################## project specific targets ##########################
49 ################## project specific targets ##########################
46
50
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@@ -1,286 +1,275
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
35 USE gaisler.spacewire.ALL; -- PLE
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 USE work.config.ALL;
39 LIBRARY lpp;
38 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
42 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
43 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
46
46
47 ENTITY MINI_LFR_top IS
47 ENTITY MINI_LFR_top IS
48
48
49 PORT (
49 PORT (
50 clk_50 : IN STD_LOGIC;
50 clk_50 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
53 --BPs
53 --BPs
54 BP0 : IN STD_LOGIC;
54 BP0 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
56 --LEDs
56 --LEDs
57 LED0 : OUT STD_LOGIC;
57 LED0 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
60 --UARTs
60 --UARTs
61 TXD1 : IN STD_LOGIC;
61 TXD1 : IN STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
65
65
66 TXD2 : IN STD_LOGIC;
66 TXD2 : IN STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
72
72
73 --EXT CONNECTOR
73 --EXT CONNECTOR
74 IO0 : INOUT STD_LOGIC;
74 IO0 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
86
86
87 --SPACE WIRE
87 --SPACE WIRE
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_SIN : IN STD_LOGIC;
90 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_SIN : IN STD_LOGIC;
94 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
97 -- MINI LFR ADC INPUTS
97 -- MINI LFR ADC INPUTS
98 ADC_nCS : OUT STD_LOGIC;
98 ADC_nCS : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101
101
102 -- SRAM
102 -- SRAM
103 SRAM_nWE : OUT STD_LOGIC;
103 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 );
109 );
110
110
111 END MINI_LFR_top;
111 END MINI_LFR_top;
112
112
113
113
114 ARCHITECTURE beh OF MINI_LFR_top IS
114 ARCHITECTURE beh OF MINI_LFR_top IS
115
115 SIGNAL clk_50_s : STD_LOGIC := '0';
116 COMPONENT leon3_soc
116 SIGNAL clk_25 : STD_LOGIC := '0';
117 GENERIC (
118 fabtech : INTEGER;
119 memtech : INTEGER;
120 padtech : INTEGER;
121 clktech : INTEGER;
122 disas : INTEGER;
123 dbguart : INTEGER;
124 pclow : INTEGER);
125 PORT (
126 clk100MHz : IN STD_ULOGIC;
127 reset : IN STD_ULOGIC;
128 errorn : OUT STD_ULOGIC;
129 ahbrxd : IN STD_ULOGIC;
130 ahbtxd : OUT STD_ULOGIC;
131 urxd1 : IN STD_ULOGIC;
132 utxd1 : OUT STD_ULOGIC;
133 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
134 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 nSRAM_BE0 : OUT STD_LOGIC;
136 nSRAM_BE1 : OUT STD_LOGIC;
137 nSRAM_BE2 : OUT STD_LOGIC;
138 nSRAM_BE3 : OUT STD_LOGIC;
139 nSRAM_WE : OUT STD_LOGIC;
140 nSRAM_CE : OUT STD_LOGIC;
141 nSRAM_OE : OUT STD_LOGIC;
142 spw1_din : IN STD_LOGIC;
143 spw1_sin : IN STD_LOGIC;
144 spw1_dout : OUT STD_LOGIC;
145 spw1_sout : OUT STD_LOGIC;
146 spw2_din : IN STD_LOGIC;
147 spw2_sin : IN STD_LOGIC;
148 spw2_dout : OUT STD_LOGIC;
149 spw2_sout : OUT STD_LOGIC;
150 apbi_ext : OUT apb_slv_in_type;
151 apbo_wfp : IN apb_slv_out_type;
152 apbo_ltm : IN apb_slv_out_type;
153 ahbi_ext : OUT AHB_Mst_In_Type;
154 ahbo_wfp : IN AHB_Mst_Out_Type);
155 END COMPONENT;
156
157 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
158 SIGNAL apbi : apb_slv_in_type;
159 SIGNAL apbo_wfp : apb_slv_out_type;
160 SIGNAL apbo_ltm : apb_slv_out_type;
161 SIGNAL ahbi : AHB_Mst_In_Type;
162 SIGNAL ahbo_wfp : AHB_Mst_Out_Type;
163 --
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
166 --
120 --
167 SIGNAL errorn : STD_LOGIC;
121 SIGNAL errorn : STD_LOGIC;
168 -- UART AHB ---------------------------------------------------------------
122 -- UART AHB ---------------------------------------------------------------
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
123 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
124 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
171
125
172 -- UART APB ---------------------------------------------------------------
126 -- UART APB ---------------------------------------------------------------
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
127 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
128 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
175 --
129 --
176 SIGNAL I00_s : STD_LOGIC;
130 SIGNAL I00_s : STD_LOGIC;
131 --
132 CONSTANT NB_APB_SLAVE : INTEGER := 1;
133 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
134 CONSTANT NB_AHB_MASTER : INTEGER := 1;
135
136 SIGNAL apbi_ext : apb_slv_in_type;
137 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
138 SIGNAL ahbi_s_ext : ahb_slv_in_type;
139 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
140 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
141 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
177
142
178 BEGIN -- beh
143 BEGIN -- beh
179
144
180 PROCESS (clk_50, reset)
145 -----------------------------------------------------------------------------
146 -- CLK
147 -----------------------------------------------------------------------------
148
149 PROCESS(clk_50)
150 BEGIN
151 IF clk_50'EVENT AND clk_50 = '1' THEN
152 clk_50_s <= NOT clk_50_s;
153 END IF;
154 END PROCESS;
155
156 PROCESS(clk_50_s)
157 BEGIN
158 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
159 clk_25 <= NOT clk_25;
160 END IF;
161 END PROCESS;
162
163 -----------------------------------------------------------------------------
164
165 PROCESS (clk_25, reset)
181 BEGIN -- PROCESS
166 BEGIN -- PROCESS
182 IF reset = '0' THEN -- asynchronous reset (active low)
167 IF reset = '0' THEN -- asynchronous reset (active low)
183 LED0 <= '0';
168 LED0 <= '0';
184 LED1 <= '0';
169 LED1 <= '0';
185 LED2 <= '0';
170 LED2 <= '0';
186 IO1 <= '0';
171 IO1 <= '0';
187 IO2 <= '1';
172 IO2 <= '1';
188 IO3 <= '0';
173 IO3 <= '0';
189 IO4 <= '0';
174 IO4 <= '0';
190 IO5 <= '0';
175 IO5 <= '0';
191 IO6 <= '0';
176 IO6 <= '0';
192 IO7 <= '0';
177 IO7 <= '0';
193 IO8 <= '0';
178 IO8 <= '0';
194 IO9 <= '0';
179 IO9 <= '0';
195 IO10 <= '0';
180 IO10 <= '0';
196 IO11 <= '0';
181 IO11 <= '0';
197 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
182 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
198 LED0 <= '0';
183 LED0 <= '0';
199 LED1 <= '1';
184 LED1 <= '1';
200 LED2 <= BP0;
185 LED2 <= BP0;
201 IO1 <= '1';
186 IO1 <= '1';
202 IO2 <= '0';
187 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
203 IO3 <= ADC_SDO(0);
188 IO3 <= ADC_SDO(0);
204 IO4 <= ADC_SDO(1);
189 IO4 <= ADC_SDO(1);
205 IO5 <= ADC_SDO(2);
190 IO5 <= ADC_SDO(2);
206 IO6 <= ADC_SDO(3);
191 IO6 <= ADC_SDO(3);
207 IO7 <= ADC_SDO(4);
192 IO7 <= ADC_SDO(4);
208 IO8 <= ADC_SDO(5);
193 IO8 <= ADC_SDO(5);
209 IO9 <= ADC_SDO(6);
194 IO9 <= ADC_SDO(6);
210 IO10 <= ADC_SDO(7);
195 IO10 <= ADC_SDO(7);
211 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
196 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
212 END IF;
197 END IF;
213 END PROCESS;
198 END PROCESS;
214
199
215 PROCESS (clk_49, reset)
200 PROCESS (clk_49, reset)
216 BEGIN -- PROCESS
201 BEGIN -- PROCESS
217 IF reset = '0' THEN -- asynchronous reset (active low)
202 IF reset = '0' THEN -- asynchronous reset (active low)
218 I00_s <= '0';
203 I00_s <= '0';
219 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
204 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
220 I00_s <= NOT I00_s;
205 I00_s <= NOT I00_s;
221 END IF;
206 END IF;
222 END PROCESS;
207 END PROCESS;
223 IO0 <= I00_s;
208 IO0 <= I00_s;
224
209
225 --UARTs
210 --UARTs
226 nCTS1 <= '1';
211 nCTS1 <= '1';
227 nCTS2 <= '1';
212 nCTS2 <= '1';
228 nDCD2 <= '1';
213 nDCD2 <= '1';
229
214
230 --EXT CONNECTOR
215 --EXT CONNECTOR
231
216
232 --SPACE WIRE
217 --SPACE WIRE
233 SPW_EN <= '0'; -- 0 => off
218 SPW_EN <= '0'; -- 0 => off
219
220 SPW_NOM_DOUT <= '0';
221 SPW_NOM_SOUT <= '0';
222 SPW_RED_DOUT <= '0';
223 SPW_RED_SOUT <= '0';
234
224
235 ADC_nCS <= '0';
225 ADC_nCS <= '0';
236 ADC_CLK <= '0';
226 ADC_CLK <= '0';
237
227
238 leon3mp_1: leon3_soc
228
229 leon3_soc_1: leon3_soc
239 GENERIC MAP (
230 GENERIC MAP (
240 fabtech => CFG_FABTECH,
231 fabtech => apa3e,
241 memtech => CFG_MEMTECH,
232 memtech => apa3e,
242 padtech => CFG_PADTECH,
233 padtech => inferred,
243 clktech => CFG_CLKTECH,
234 clktech => inferred,
244 disas => CFG_DISAS,
235 disas => 0,
245 dbguart => CFG_DUART,
236 dbguart => 0,
246 pclow => CFG_PCLOW)
237 pclow => 2,
238 clk_freq => 25000,
239 NB_CPU => 1,
240 ENABLE_FPU => 0,
241 FPU_NETLIST => 0,
242 ENABLE_DSU => 1,
243 ENABLE_AHB_UART => 1,
244 ENABLE_APB_UART => 1,
245 ENABLE_IRQMP => 1,
246 ENABLE_GPT => 1,
247 NB_AHB_MASTER => NB_AHB_MASTER,
248 NB_AHB_SLAVE => NB_AHB_SLAVE,
249 NB_APB_SLAVE => NB_APB_SLAVE)
247 PORT MAP (
250 PORT MAP (
248 clk100MHz => clk_50, --
251 clk => clk_25,
249 reset => reset, --
252 reset => reset,
250 errorn => errorn, --
253 errorn => errorn,
254 ahbrxd => TXD1,
255 ahbtxd => RXD1,
256 urxd1 => TXD2,
257 utxd1 => RXD2,
258 address => SRAM_A,
259 data => SRAM_DQ,
260 nSRAM_BE0 => SRAM_nBE(0),
261 nSRAM_BE1 => SRAM_nBE(1),
262 nSRAM_BE2 => SRAM_nBE(2),
263 nSRAM_BE3 => SRAM_nBE(3),
264 nSRAM_WE => SRAM_nWE,
265 nSRAM_CE => SRAM_CE,
266 nSRAM_OE => SRAM_nOE,
251
267
252 ahbrxd => TXD1, --
268 apbi_ext => apbi_ext,
253 ahbtxd => RXD1, --
269 apbo_ext => apbo_ext,
254 urxd1 => TXD2, --
270 ahbi_s_ext => ahbi_s_ext,
255 utxd1 => RXD2, --
271 ahbo_s_ext => ahbo_s_ext,
256 --RAM
272 ahbi_m_ext => ahbi_m_ext,
257 address => SRAM_A, --
273 ahbo_m_ext => ahbo_m_ext);
258 data => SRAM_DQ, --
259 nSRAM_BE0 => SRAM_nBE(0), --
260 nSRAM_BE1 => SRAM_nBE(1), --
261 nSRAM_BE2 => SRAM_nBE(2), --
262 nSRAM_BE3 => SRAM_nBE(3), --
263 nSRAM_WE => SRAM_nWE, --
264 nSRAM_CE => SRAM_CE, --
265 nSRAM_OE => SRAM_nOE, --
266 --SPW
267 spw1_din => SPW_NOM_DIN, --
268 spw1_sin => SPW_NOM_SIN, --
269 spw1_dout => SPW_NOM_DOUT, --
270 spw1_sout => SPW_NOM_SOUT, --
271 spw2_din => SPW_RED_DIN, --
272 spw2_sin => SPW_RED_SIN, --
273 spw2_dout => SPW_RED_DOUT, --
274 spw2_sout => SPW_RED_SOUT, --
275
276 apbi_ext => apbi, --
277 apbo_wfp => apbo_wfp, --
278 apbo_ltm => apbo_ltm, -- lfr time management
279 ahbi_ext => ahbi, --
280 ahbo_wfp => ahbo_wfp); --
281
274
282 apbo_wfp <= apb_none;
283 apbo_ltm <= apb_none;
284 ahbo_wfp <= ahbm_none;
285
286 END beh;
275 END beh;
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@@ -1,52 +1,50
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= config.vhd \
13 VHDLSYNFILES= MINI_LFR_top.vhd
14 MINI_LFR_top.vhd \
15 leon3_soc.vhd
16
14
17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
18 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
19 CLEAN=soft-clean
17 CLEAN=soft-clean
20
18
21 TECHLIBS = proasic3e
19 TECHLIBS = proasic3e
22
20
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc
22 tmtc openchip hynix ihp gleichmann micron usbhc
25
23
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./amba_lcd_16x2_ctrlr \
26 ./amba_lcd_16x2_ctrlr \
29 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_delay \
29 ./general_purpose/lpp_delay \
32 ./dsp/lpp_fft \
30 ./dsp/lpp_fft \
33 ./lpp_bootloader \
31 ./lpp_bootloader \
34 ./lpp_cna \
32 ./lpp_cna \
35 ./lpp_demux \
33 ./lpp_demux \
36 ./lpp_matrix \
34 ./lpp_matrix \
37 ./lpp_uart \
35 ./lpp_uart \
38 ./lpp_usb \
36 ./lpp_usb \
39 ./lpp_Header \
37 ./lpp_Header \
40
38
41 FILESKIP =lpp_lfr_ms.vhd \
39 FILESKIP =lpp_lfr_ms.vhd \
42 i2cmst.vhd \
40 i2cmst.vhd \
43 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
44 APB_SIMPLE_DIODE.vhd \
42 APB_SIMPLE_DIODE.vhd \
45 Top_MatrixSpec.vhd \
43 Top_MatrixSpec.vhd \
46 APB_FFT.vhd
44 APB_FFT.vhd
47
45
48 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/software/leon3/Makefile
47 include $(GRLIB)/software/leon3/Makefile
50
48
51 ################## project specific targets ##########################
49 ################## project specific targets ##########################
52
50
Show file before | Show file after | Hide comments
@@ -1,452 +1,357
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
44
45 ENTITY leon3_soc IS
45 ENTITY leon3_soc IS
46 GENERIC (
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
53 pclow : INTEGER := CFG_PCLOW
54 );
54 );
55 PORT (
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
56 clk100MHz : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
58
58
59 errorn : OUT STD_ULOGIC;
59 errorn : OUT STD_ULOGIC;
60
60
61 -- UART AHB ---------------------------------------------------------------
61 -- UART AHB ---------------------------------------------------------------
62 ahbrxd : IN STD_ULOGIC; -- DSU rx data
62 ahbrxd : IN STD_ULOGIC; -- DSU rx data
63 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
63 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
64
64
65 -- UART APB ---------------------------------------------------------------
65 -- UART APB ---------------------------------------------------------------
66 urxd1 : IN STD_ULOGIC; -- UART1 rx data
66 urxd1 : IN STD_ULOGIC; -- UART1 rx data
67 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
67 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
68
68
69 -- RAM --------------------------------------------------------------------
69 -- RAM --------------------------------------------------------------------
70 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
70 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
71 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 nSRAM_BE0 : OUT STD_LOGIC;
72 nSRAM_BE0 : OUT STD_LOGIC;
73 nSRAM_BE1 : OUT STD_LOGIC;
73 nSRAM_BE1 : OUT STD_LOGIC;
74 nSRAM_BE2 : OUT STD_LOGIC;
74 nSRAM_BE2 : OUT STD_LOGIC;
75 nSRAM_BE3 : OUT STD_LOGIC;
75 nSRAM_BE3 : OUT STD_LOGIC;
76 nSRAM_WE : OUT STD_LOGIC;
76 nSRAM_WE : OUT STD_LOGIC;
77 nSRAM_CE : OUT STD_LOGIC;
77 nSRAM_CE : OUT STD_LOGIC;
78 nSRAM_OE : OUT STD_LOGIC;
78 nSRAM_OE : OUT STD_LOGIC;
79
79
80 -- APB --------------------------------------------------------------------
81
82
80 -- SPW --------------------------------------------------------------------
83 -- SPW --------------------------------------------------------------------
81 spw1_din : IN STD_LOGIC; -- PLE
84 spw1_din : IN STD_LOGIC; -- PLE
82 spw1_sin : IN STD_LOGIC; -- PLE
85 spw1_sin : IN STD_LOGIC; -- PLE
83 spw1_dout : OUT STD_LOGIC; -- PLE
86 spw1_dout : OUT STD_LOGIC; -- PLE
84 spw1_sout : OUT STD_LOGIC; -- PLE
87 spw1_sout : OUT STD_LOGIC; -- PLE
85
88
86 spw2_din : IN STD_LOGIC; -- JCPE --TODO
89 spw2_din : IN STD_LOGIC; -- JCPE --TODO
87 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
90 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
88 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
91 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
89 spw2_sout : OUT STD_LOGIC;
92 spw2_sout : OUT STD_LOGIC;
90
93
91 -- WAVEFORM PICKER --------------------------------------------------------
94 -- WAVEFORM PICKER --------------------------------------------------------
92 apbi_ext : OUT apb_slv_in_type;
95 apbi_ext : OUT apb_slv_in_type;
93 apbo_wfp : IN apb_slv_out_type;
96 apbo_wfp : IN apb_slv_out_type;
94 apbo_ltm : IN apb_slv_out_type;
97 apbo_ltm : IN apb_slv_out_type;
95 ahbi_ext : OUT AHB_Mst_In_Type;
98 ahbi_ext : OUT AHB_Mst_In_Type;
96 ahbo_wfp : IN AHB_Mst_Out_Type
99 ahbo_wfp : IN AHB_Mst_Out_Type
97
100
98 );
101 );
99 END;
102 END;
100
103
101 ARCHITECTURE Behavioral OF leon3_soc IS
104 ARCHITECTURE Behavioral OF leon3_soc IS
102
105
103 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
104 -- CFG_GRETH+CFG_AHB_JTAG;
107 -- CFG_GRETH+CFG_AHB_JTAG;
105 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
106 CFG_AHB_UART
109 CFG_AHB_UART
107 +2;
110 +2;
108 -- 1 is for the SpaceWire module grspw, which is a master
111 -- 1 is for the SpaceWire module grspw, which is a master
109 -- 1 is for the LFR
112 -- 1 is for the LFR
110
113
111 CONSTANT maxahbm : INTEGER := maxahbmsp;
114 CONSTANT maxahbm : INTEGER := maxahbmsp;
112
115
113 --Clk & Rst g�n�
116 --Clk & Rst g�n�
114 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL resetnl : STD_ULOGIC;
119 SIGNAL resetnl : STD_ULOGIC;
117 SIGNAL clk2x : STD_ULOGIC;
120 SIGNAL clk2x : STD_ULOGIC;
118 SIGNAL lclk2x : STD_ULOGIC;
121 -- SIGNAL lclk2x : STD_ULOGIC;
119 SIGNAL lclk25MHz : STD_ULOGIC;
122 SIGNAL lclk25MHz : STD_ULOGIC;
120 SIGNAL lclk50MHz : STD_ULOGIC;
123 SIGNAL lclk50MHz : STD_ULOGIC;
121 SIGNAL lclk100MHz : STD_ULOGIC;
124 SIGNAL lclk100MHz : STD_ULOGIC;
122 SIGNAL clkm : STD_ULOGIC;
125 SIGNAL clkm : STD_ULOGIC;
123 SIGNAL rstn : STD_ULOGIC;
126 SIGNAL rstn : STD_ULOGIC;
124 SIGNAL rstraw : STD_ULOGIC;
127 SIGNAL rstraw : STD_ULOGIC;
125 SIGNAL pciclk : STD_ULOGIC;
128 SIGNAL pciclk : STD_ULOGIC;
126 SIGNAL sdclkl : STD_ULOGIC;
129 SIGNAL sdclkl : STD_ULOGIC;
127 SIGNAL cgi : clkgen_in_type;
130 SIGNAL cgi : clkgen_in_type;
128 SIGNAL cgo : clkgen_out_type;
131 SIGNAL cgo : clkgen_out_type;
129 --- AHB / APB
132 --- AHB / APB
130 SIGNAL apbi : apb_slv_in_type;
133 SIGNAL apbi : apb_slv_in_type;
131 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
134 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
132 SIGNAL ahbsi : ahb_slv_in_type;
135 SIGNAL ahbsi : ahb_slv_in_type;
133 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
136 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
134 SIGNAL ahbmi : ahb_mst_in_type;
137 SIGNAL ahbmi : ahb_mst_in_type;
135 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
138 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
136 --UART
139 --UART
137 SIGNAL ahbuarti : uart_in_type;
140 SIGNAL ahbuarti : uart_in_type;
138 SIGNAL ahbuarto : uart_out_type;
141 SIGNAL ahbuarto : uart_out_type;
139 SIGNAL apbuarti : uart_in_type;
142 SIGNAL apbuarti : uart_in_type;
140 SIGNAL apbuarto : uart_out_type;
143 SIGNAL apbuarto : uart_out_type;
141 --MEM CTRLR
144 --MEM CTRLR
142 SIGNAL memi : memory_in_type;
145 SIGNAL memi : memory_in_type;
143 SIGNAL memo : memory_out_type;
146 SIGNAL memo : memory_out_type;
144 SIGNAL wpo : wprot_out_type;
147 SIGNAL wpo : wprot_out_type;
145 SIGNAL sdo : sdram_out_type;
148 SIGNAL sdo : sdram_out_type;
146 SIGNAL ramcs : STD_ULOGIC;
149 SIGNAL ramcs : STD_ULOGIC;
147 --IRQ
150 --IRQ
148 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
149 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
152 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
150 --Timer
153 --Timer
151 SIGNAL gpti : gptimer_in_type;
154 SIGNAL gpti : gptimer_in_type;
152 SIGNAL gpto : gptimer_out_type;
155 SIGNAL gpto : gptimer_out_type;
153 --GPIO
156 --GPIO
154 SIGNAL gpioi : gpio_in_type;
157 SIGNAL gpioi : gpio_in_type;
155 SIGNAL gpioo : gpio_out_type;
158 SIGNAL gpioo : gpio_out_type;
156 --DSU
159 --DSU
157 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
158 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
161 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
159 SIGNAL dsui : dsu_in_type;
162 SIGNAL dsui : dsu_in_type;
160 SIGNAL dsuo : dsu_out_type;
163 SIGNAL dsuo : dsu_out_type;
161
164
162 ---------------------------------------------------------------------
165 ---------------------------------------------------------------------
163 --- AJOUT TEST ------------------------Signaux----------------------
166 --- AJOUT TEST ------------------------Signaux----------------------
164 ---------------------------------------------------------------------
167 ---------------------------------------------------------------------
165
168
166 ---------------------------------------------------------------------
169 ---------------------------------------------------------------------
167 CONSTANT IOAEN : INTEGER := CFG_CAN;
170 CONSTANT IOAEN : INTEGER := CFG_CAN;
168 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
171 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
169
172
170 -- Spacewire signals
173 -- Spacewire signals
171 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
174 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
172 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
175 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
173 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
176 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
174 SIGNAL spw_rxtxclk : STD_ULOGIC;
177 SIGNAL spw_rxtxclk : STD_ULOGIC;
175 SIGNAL spw_rxclkn : STD_ULOGIC;
178 SIGNAL spw_rxclkn : STD_ULOGIC;
176 SIGNAL spw_clk : STD_LOGIC;
179 SIGNAL spw_clk : STD_LOGIC;
177 SIGNAL swni : grspw_in_type; -- PLE
180 SIGNAL swni : grspw_in_type; -- PLE
178 SIGNAL swno : grspw_out_type; -- PLE
181 SIGNAL swno : grspw_out_type; -- PLE
179 SIGNAL clkmn : STD_ULOGIC; -- PLE
182 SIGNAL clkmn : STD_ULOGIC; -- PLE
180 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
183 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
181 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
182
185
183 BEGIN
186 BEGIN
184
187
185
188
186 ----------------------------------------------------------------------
189 ----------------------------------------------------------------------
187 --- Reset and Clock generation -------------------------------------
190 --- Reset and Clock generation -------------------------------------
188 ----------------------------------------------------------------------
191 ----------------------------------------------------------------------
189
192
190 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
193 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
191 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
194 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
192
195
193 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
196 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
194
197
195
198
196 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
199 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
197
200
198 clkgen0 : clkgen -- clock generator
201 clkgen0 : clkgen -- clock generator
199 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
202 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
200 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
203 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
201 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
204 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
202
205
203 PROCESS(lclk100MHz)
206
204 BEGIN
205 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
206 lclk50MHz <= NOT lclk50MHz;
207 END IF;
208 END PROCESS;
209
207
210 PROCESS(lclk50MHz)
208 -- lclk2x <= lclk50MHz;
211 BEGIN
212 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
213 lclk25MHz <= NOT lclk25MHz;
214 END IF;
215 END PROCESS;
216
217 lclk2x <= lclk50MHz;
218 spw_clk <= lclk50MHz;
219
209
220 ----------------------------------------------------------------------
210 ----------------------------------------------------------------------
221 --- LEON3 processor / DSU / IRQ ------------------------------------
211 --- LEON3 processor / DSU / IRQ ------------------------------------
222 ----------------------------------------------------------------------
212 ----------------------------------------------------------------------
223
213
224 l3 : IF CFG_LEON3 = 1 GENERATE
214 l3 : IF CFG_LEON3 = 1 GENERATE
225 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
215 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
226 u0 : leon3s -- LEON3 processor
216 u0 : leon3s -- LEON3 processor
227 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
217 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
228 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
218 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
229 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
219 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
230 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
220 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
231 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
221 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
232 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
222 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
233 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
223 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
234 irqi(i), irqo(i), dbgi(i), dbgo(i));
224 irqi(i), irqo(i), dbgi(i), dbgo(i));
235 END GENERATE;
225 END GENERATE;
236 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
226 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
237
227
238 dsugen : IF CFG_DSU = 1 GENERATE
228 dsugen : IF CFG_DSU = 1 GENERATE
239 dsu0 : dsu3 -- LEON3 Debug Support Unit
229 dsu0 : dsu3 -- LEON3 Debug Support Unit
240 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
230 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
241 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
231 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
242 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
232 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
243 dsui.enable <= '1';
233 dsui.enable <= '1';
244 dsui.break <= '0';
234 dsui.break <= '0';
245 END GENERATE;
235 END GENERATE;
246 END GENERATE;
236 END GENERATE;
247
237
248 nodsu : IF CFG_DSU = 0 GENERATE
238 nodsu : IF CFG_DSU = 0 GENERATE
249 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
239 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
250 END GENERATE;
240 END GENERATE;
251
241
252 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
242 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
253 irqctrl0 : irqmp -- interrupt controller
243 irqctrl0 : irqmp -- interrupt controller
254 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
244 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
255 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
245 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
256 END GENERATE;
246 END GENERATE;
257 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
247 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
258 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
248 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
259 irqi(i).irl <= "0000";
249 irqi(i).irl <= "0000";
260 END GENERATE;
250 END GENERATE;
261 apbo(2) <= apb_none;
251 apbo(2) <= apb_none;
262 END GENERATE;
252 END GENERATE;
263
253
264 ----------------------------------------------------------------------
254 ----------------------------------------------------------------------
265 --- Memory controllers ---------------------------------------------
255 --- Memory controllers ---------------------------------------------
266 ----------------------------------------------------------------------
256 ----------------------------------------------------------------------
267 memctrlr : mctrl GENERIC MAP (
257 memctrlr : mctrl GENERIC MAP (
268 hindex => 0,
258 hindex => 0,
269 pindex => 0,
259 pindex => 0,
270 paddr => 0,
260 paddr => 0,
271 srbanks => 1
261 srbanks => 1
272 )
262 )
273 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
263 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
274
264
275 memi.brdyn <= '1';
265 memi.brdyn <= '1';
276 memi.bexcn <= '1';
266 memi.bexcn <= '1';
277 memi.writen <= '1';
267 memi.writen <= '1';
278 memi.wrn <= "1111";
268 memi.wrn <= "1111";
279 memi.bwidth <= "10";
269 memi.bwidth <= "10";
280
270
281 bdr : FOR i IN 0 TO 3 GENERATE
271 bdr : FOR i IN 0 TO 3 GENERATE
282 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
272 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
283 PORT MAP (
273 PORT MAP (
284 data(31-i*8 DOWNTO 24-i*8),
274 data(31-i*8 DOWNTO 24-i*8),
285 memo.data(31-i*8 DOWNTO 24-i*8),
275 memo.data(31-i*8 DOWNTO 24-i*8),
286 memo.bdrive(i),
276 memo.bdrive(i),
287 memi.data(31-i*8 DOWNTO 24-i*8));
277 memi.data(31-i*8 DOWNTO 24-i*8));
288 END GENERATE;
278 END GENERATE;
289
279
290 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
280 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
291 PORT MAP (address, memo.address(21 DOWNTO 2));
281 PORT MAP (address, memo.address(21 DOWNTO 2));
292
282
293 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
283 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
294 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
284 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
295 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
285 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
296 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
286 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
297 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
287 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
298 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
288 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
299 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
289 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
300
290
301 ----------------------------------------------------------------------
291 ----------------------------------------------------------------------
302 --- AHB CONTROLLER -------------------------------------------------
292 --- AHB CONTROLLER -------------------------------------------------
303 ----------------------------------------------------------------------
293 ----------------------------------------------------------------------
304 ahb0 : ahbctrl -- AHB arbiter/multiplexer
294 ahb0 : ahbctrl -- AHB arbiter/multiplexer
305 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
295 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
306 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
296 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
307 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
297 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
308 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
298 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
309
299
310 ----------------------------------------------------------------------
300 ----------------------------------------------------------------------
311 --- AHB UART -------------------------------------------------------
301 --- AHB UART -------------------------------------------------------
312 ----------------------------------------------------------------------
302 ----------------------------------------------------------------------
313 dcomgen : IF CFG_AHB_UART = 1 GENERATE
303 dcomgen : IF CFG_AHB_UART = 1 GENERATE
314 dcom0 : ahbuart
304 dcom0 : ahbuart
315 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
305 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
316 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
306 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
317 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
307 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
318 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
308 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
319 END GENERATE;
309 END GENERATE;
320 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
310 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
321
311
322 ----------------------------------------------------------------------
312 ----------------------------------------------------------------------
323 --- APB Bridge -----------------------------------------------------
313 --- APB Bridge -----------------------------------------------------
324 ----------------------------------------------------------------------
314 ----------------------------------------------------------------------
325 apb0 : apbctrl -- AHB/APB bridge
315 apb0 : apbctrl -- AHB/APB bridge
326 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
316 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
327 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
317 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
328
318
329 ----------------------------------------------------------------------
319 ----------------------------------------------------------------------
330 --- GPT Timer ------------------------------------------------------
320 --- GPT Timer ------------------------------------------------------
331 ----------------------------------------------------------------------
321 ----------------------------------------------------------------------
332 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
322 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
333 timer0 : gptimer -- timer unit
323 timer0 : gptimer -- timer unit
334 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
324 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
335 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
325 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
336 nbits => CFG_GPT_TW)
326 nbits => CFG_GPT_TW)
337 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
327 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
338 gpti.dhalt <= dsuo.tstop;
328 gpti.dhalt <= dsuo.tstop;
339 gpti.extclk <= '0';
329 gpti.extclk <= '0';
340 END GENERATE;
330 END GENERATE;
341 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
331 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
342
332
343
333
344 ----------------------------------------------------------------------
334 ----------------------------------------------------------------------
345 --- APB UART -------------------------------------------------------
335 --- APB UART -------------------------------------------------------
346 ----------------------------------------------------------------------
336 ----------------------------------------------------------------------
347 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
337 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
348 uart1 : apbuart -- UART 1
338 uart1 : apbuart -- UART 1
349 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
339 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
350 fifosize => CFG_UART1_FIFO)
340 fifosize => CFG_UART1_FIFO)
351 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
341 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
352 apbuarti.rxd <= urxd1;
342 apbuarti.rxd <= urxd1;
353 apbuarti.extclk <= '0';
343 apbuarti.extclk <= '0';
354 utxd1 <= apbuarto.txd;
344 utxd1 <= apbuarto.txd;
355 apbuarti.ctsn <= '0';
345 apbuarti.ctsn <= '0';
356 END GENERATE;
346 END GENERATE;
357 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
347 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
358
359 -----------------------------------------------------------------------
360 --- SpaceWire --------------------------------------------------------
361 -----------------------------------------------------------------------
362
363 spw_rxtxclk <= spw_clk;
364 spw_rxclkn <= NOT spw_rxtxclk;
365
366 -- PADS for SPW1
367 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
368 PORT MAP (spw1_din, dtmp(0));
369 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
370 PORT MAP (spw1_sin, stmp(0));
371 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
372 PORT MAP (spw1_dout, swno.d(0));
373 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
374 PORT MAP (spw1_sout, swno.s(0));
375 -- PADS FOR SPW2
376 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
377 PORT MAP (spw2_din, dtmp(1));
378 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
379 PORT MAP (spw2_sin, stmp(1));
380 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
381 PORT MAP (spw2_dout, swno.d(1));
382 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
383 PORT MAP (spw2_sout, swno.s(1));
384
385 -- GRSPW PHY
386 --spw1_input: if CFG_SPW_GRSPW = 1 generate
387 spw_inputloop : FOR j IN 0 TO 1 GENERATE
388 spw_phy0 : grspw_phy
389 GENERIC MAP(
390 tech => fabtech,
391 rxclkbuftype => 1,
392 scantest => 0)
393 PORT MAP(
394 rxrst => swno.rxrst,
395 di => dtmp(j),
396 si => stmp(j),
397 rxclko => spw_rxclk(j),
398 do => swni.d(j),
399 ndo => swni.nd(j*5+4 DOWNTO j*5),
400 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
401 END GENERATE spw_inputloop;
402
403 -- SPW core
404 sw0 : grspwm
405 GENERIC MAP(
406 tech => apa3e,
407 hindex => 1,
408 pindex => 5,
409 paddr => 5,
410 pirq => 11,
411 sysfreq => 25000, -- CPU_FREQ
412 rmap => 1,
413 rmapcrc => 1,
414 fifosize1 => 16,
415 fifosize2 => 16,
416 rxclkbuftype => 1,
417 rxunaligned => 0,
418 rmapbufs => 4,
419 ft => 0,
420 netlist => 0,
421 ports => 2,
422 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
423 memtech => apa3e,
424 destkey => 2,
425 spwcore => 1
426 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
427 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
428 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
429 )
430 PORT MAP(rstn, clkm, spw_rxclk(0),
431 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
432 ahbmi, ahbmo(1), apbi, apbo(5),
433 swni, swno);
434
435 swni.tickin <= '0';
436 swni.rmapen <= '1';
437 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
438 swni.tickinraw <= '0';
439 swni.timein <= (OTHERS => '0');
440 swni.dcrstval <= (OTHERS => '0');
441 swni.timerrstval <= (OTHERS => '0');
442
443 -------------------------------------------------------------------------------
348 -------------------------------------------------------------------------------
444 -- LFR
349 -- LFR
445 -------------------------------------------------------------------------------
350 -------------------------------------------------------------------------------
446 apbi_ext <= apbi;
351 apbi_ext <= apbi;
447 apbo(15) <= apbo_wfp;
352 apbo(15) <= apbo_wfp;
448 apbo(6) <= apbo_ltm;
353 apbo(6) <= apbo_ltm;
449 ahbi_ext <= ahbmi;
354 ahbi_ext <= ahbmi;
450 ahbmo(2) <= ahbo_wfp;
355 ahbmo(2) <= ahbo_wfp;
451
356
452 END Behavioral;
357 END Behavioral;
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@@ -1,23 +1,24
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./general_purpose
2 ./general_purpose
3 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
4 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
5 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
6 ./lpp_amba
7 ./dsp/iir_filter
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 ./dsp/lpp_fft
10 ./lfr_time_management
10 ./lfr_time_management
11 ./lpp_ad_Conv
11 ./lpp_ad_Conv
12 ./lpp_bootloader
12 ./lpp_bootloader
13 ./lpp_cna
13 ./lpp_cna
14 ./lpp_demux
14 ./lpp_demux
15 ./lpp_Header
15 ./lpp_Header
16 ./lpp_matrix
16 ./lpp_matrix
17 ./lpp_memory
17 ./lpp_memory
18 ./lpp_dma
18 ./lpp_dma
19 ./lpp_uart
19 ./lpp_uart
20 ./lpp_usb
20 ./lpp_usb
21 ./lpp_waveform
21 ./lpp_waveform
22 ./lpp_top_lfr
22 ./lpp_top_lfr
23 ./lpp_Header
23 ./lpp_Header
24 ./lpp_leon3_soc
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