# HG changeset patch # User pellion # Date 2013-12-06 14:33:02 # Node ID 9d30a66567050a1e820b4eb9c91a6f365443c616 # Parent e57df7c34edf79a3ab7f9aaf857618d7727797aa MINI LFR blank project diff --git a/designs/MINI-LFR/MINI-LFR-top.vhd b/designs/MINI-LFR/MINI-LFR-top.vhd deleted file mode 100644 --- a/designs/MINI-LFR/MINI-LFR-top.vhd +++ /dev/null @@ -1,456 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -USE work.config.ALL; -LIBRARY lpp; ---use lpp.lpp_amba.all; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; ---use lpp.lpp_uart.all; ---use lpp.lpp_matrix.all; ---use lpp.lpp_delay.all; ---use lpp.lpp_fft.all; ---use lpp.fft_components.all; -use lpp.iir_filter.all; -USE lpp.general_purpose.ALL; ---use lpp.Filtercfg.all; -USE lpp.lpp_lfr_time_management.ALL; -- PLE ---use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; -- PLE - spw1_sin : IN STD_LOGIC; -- PLE - spw1_dout : OUT STD_LOGIC; -- PLE - spw1_sout : OUT STD_LOGIC; -- PLE - - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - - --------------------------------------------------------------------------- - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF leon3mp IS - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; - CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ - CFG_AHB_UART+ - CFG_GRETH+ - CFG_AHB_JTAG - +2; -- 1 is for the SpaceWire module grspw2, which is a master - CONSTANT maxahbm : INTEGER := maxahbmsp; - ---Clk & Rst g�n� - SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL resetnl : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL lclk25MHz : STD_ULOGIC; - SIGNAL lclk50MHz : STD_ULOGIC; - SIGNAL lclk100MHz : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; ---- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); ---UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; ---MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - SIGNAL ramcs : STD_ULOGIC; ---IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); ---Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; ---DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - CONSTANT IOAEN : INTEGER := CFG_CAN; - CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - --- Spacewire signals - SIGNAL dtmp : STD_ULOGIC; -- PLE - SIGNAL stmp : STD_ULOGIC; -- PLE - SIGNAL rxclko : STD_ULOGIC; -- PLE - SIGNAL swni : grspw_in_type; -- PLE - SIGNAL swno : grspw_out_type; -- PLE - SIGNAL clkmn : STD_ULOGIC; -- PLE - SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 - --- AD Converter RHF1401 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; - - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - led(2) <= dsuo.active; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4) - PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - led(0) <= NOT ahbuarti.rxd; - led(1) <= NOT ahbuarto.txd; - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- -spw: IF CFG_SPW_ENABLE /= 0 GENERATE - lfrtimemanagement0 : apb_lfr_time_management - GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) - PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); -END GENERATE; -IF CFG_SPW_ENABLE = 0 GENERATE - apbo(6) <= apb_none; -END GENERATE; ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ -spw: IF CFG_SPW_ENABLE /= 0 GENERATE - spw_phy0 : grspw2_phy - GENERIC MAP( - scantest => 0, - tech => memtech, - input_type => 0) -- self_clocking mode - PORT MAP( - rstn => rstn, - rxclki => clkm, - rxclkin => clkmn, - nrxclki => clkm, -- not used in self-clocking - di => dtmp, - si => stmp, - do => swni.d(1 DOWNTO 0), - dov => swni.dv(1 DOWNTO 0), - dconnect => swni.dconnect(1 DOWNTO 0), - rxclko => rxclko); - - sw0 : grspwm - GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, - usegen => 1, -- sysfreq not used by the core version 2? usegen? - nsync => 1, -- nsync not used by the core version 2? - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 2, - rxunaligned => 0, - spwcore => 2, - memtech => apa3e, - nodeaddr => 254, - destkey => 2, -- added nodeaddr and destkey parameters - rmapbufs => 4, - netlist => 0, - ft => 0, - ports => 2) - PORT MAP( - rstn, clkm, - rxclko, rxclko, - txclk, txclk, - ahbmi, ahbmo(1), - apbi, apbo(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00001001"; - - spw1_dout <= swno.d(0); - spw1_sout <= swno.s(0); - dtmp <= spw1_din; - stmp <= spw1_sin; - - txclk <= lclk100MHz; - - END GENERATE; - IF CFG_SPW_ENABLE = 0 GENERATE - ahbmo(1) <= ahbm_none; - apbo(5) <= apb_none; - END GENERATE; - - -END Behavioral; diff --git a/designs/MINI-LFR/MINI_LFR_top.vhd b/designs/MINI-LFR/MINI_LFR_top.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR/MINI_LFR_top.vhd @@ -0,0 +1,275 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY MINI_LFR_top IS + + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END MINI_LFR_top; + + +ARCHITECTURE beh OF MINI_LFR_top IS + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; + ----------------------------------------------------------------------------- + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + -- + SIGNAL errorn : STD_LOGIC; + -- UART AHB --------------------------------------------------------------- + SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data + SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data + SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data + -- + SIGNAL I00_s : STD_LOGIC; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 1; + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + + PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + + PROCESS(clk_50_s) + BEGIN + IF clk_50_s'EVENT AND clk_50_s = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + IO1 <= '0'; + IO2 <= '1'; + IO3 <= '0'; + IO4 <= '0'; + IO5 <= '0'; + IO6 <= '0'; + IO7 <= '0'; + IO8 <= '0'; + IO9 <= '0'; + IO10 <= '0'; + IO11 <= '0'; + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0; + IO1 <= '1'; + IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; + IO3 <= ADC_SDO(0); + IO4 <= ADC_SDO(1); + IO5 <= ADC_SDO(2); + IO6 <= ADC_SDO(3); + IO7 <= ADC_SDO(4); + IO8 <= ADC_SDO(5); + IO9 <= ADC_SDO(6); + IO10 <= ADC_SDO(7); + IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; + END IF; + END PROCESS; + + PROCESS (clk_49, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + I00_s <= '0'; + ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge + I00_s <= NOT I00_s; + END IF; + END PROCESS; + IO0 <= I00_s; + + --UARTs + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + + --EXT CONNECTOR + + --SPACE WIRE + SPW_EN <= '0'; -- 0 => off + + SPW_NOM_DOUT <= '0'; + SPW_NOM_SOUT <= '0'; + SPW_RED_DOUT <= '0'; + SPW_RED_SOUT <= '0'; + + ADC_nCS <= '0'; + ADC_CLK <= '0'; + + + leon3_soc_1: leon3_soc + GENERIC MAP ( + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + NB_CPU => 1, + ENABLE_FPU => 0, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE) + PORT MAP ( + clk => clk_25, + reset => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, + + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); + +END beh; diff --git a/designs/MINI-LFR/Makefile b/designs/MINI-LFR/Makefile --- a/designs/MINI-LFR/Makefile +++ b/designs/MINI-LFR/Makefile @@ -1,7 +1,7 @@ VHDLIB=../.. SCRIPTSDIR=$(VHDLIB)/scripts/ GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=MINI_LFR +TOP=MINI_LFR_top BOARD=MINI-LFR include $(VHDLIB)/boards/$(BOARD)/Makefile.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) @@ -10,7 +10,8 @@ QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf EFFORT=high XSTOPT= SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES=config.vhd leon3mp.vhd MINI-LFR-top.vhd +VHDLSYNFILES= MINI_LFR_top.vhd + PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean @@ -35,9 +36,12 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt ./lpp_usb \ ./lpp_Header \ -FILESKIP = i2cmst.vhd \ +FILESKIP =lpp_lfr_ms.vhd \ + i2cmst.vhd \ APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd + APB_SIMPLE_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/MINI-LFR/config.vhd b/designs/MINI-LFR/config.vhd deleted file mode 100644 --- a/designs/MINI-LFR/config.vhd +++ /dev/null @@ -1,185 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (2); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - --- SPACEWIRE - constant CFG_SPW_ENABLE : integer := 0; - - -end; diff --git a/designs/MINI-LFR/leon3mp.vhd b/designs/MINI-LFR/leon3mp.vhd deleted file mode 100644 --- a/designs/MINI-LFR/leon3mp.vhd +++ /dev/null @@ -1,330 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -USE work.config.ALL; -LIBRARY lpp; ---use lpp.lpp_amba.all; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; ---use lpp.lpp_uart.all; ---use lpp.lpp_matrix.all; ---use lpp.lpp_delay.all; ---use lpp.lpp_fft.all; ---use lpp.fft_components.all; -use lpp.iir_filter.all; -USE lpp.general_purpose.ALL; ---use lpp.Filtercfg.all; -USE lpp.lpp_lfr_time_management.ALL; -- PLE ---use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; -- PLE - spw1_sin : IN STD_LOGIC; -- PLE - spw1_dout : OUT STD_LOGIC; -- PLE - spw1_sout : OUT STD_LOGIC; -- PLE - - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - - --------------------------------------------------------------------------- - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF leon3mp IS - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; - CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ - CFG_AHB_UART+ - CFG_GRETH+ - CFG_AHB_JTAG - +2; -- 1 is for the SpaceWire module grspw2, which is a master - CONSTANT maxahbm : INTEGER := maxahbmsp; - ---Clk & Rst g�n� - SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL clk2x : STD_ULOGIC; - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL lclk25MHz : STD_ULOGIC; - SIGNAL lclk50MHz : STD_ULOGIC; - SIGNAL lclk100MHz : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; ---- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); ---UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; ---MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - SIGNAL ramcs : STD_ULOGIC; ---IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); ---Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; ---DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - CONSTANT IOAEN : INTEGER := CFG_CAN; - CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - --- Spacewire signals - SIGNAL dtmp : STD_ULOGIC; -- PLE - SIGNAL stmp : STD_ULOGIC; -- PLE - SIGNAL rxclko : STD_ULOGIC; -- PLE - SIGNAL swni : grspw_in_type; -- PLE - SIGNAL swno : grspw_out_type; -- PLE - SIGNAL clkmn : STD_ULOGIC; -- PLE - SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 - --- AD Converter RHF1401 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; - - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - - - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4) - PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - led(0) <= NOT ahbuarti.rxd; - led(1) <= NOT ahbuarto.txd; - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - - - - -END Behavioral; \ No newline at end of file diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd --- a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd @@ -35,7 +35,6 @@ USE gaisler.misc.ALL; USE gaisler.spacewire.ALL; -- PLE LIBRARY esa; USE esa.memoryctrl.ALL; -USE work.config.ALL; LIBRARY lpp; USE lpp.lpp_memory.ALL; USE lpp.lpp_ad_conv.ALL; @@ -43,6 +42,7 @@ USE lpp.lpp_lfr_pkg.ALL; USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; ENTITY MINI_LFR_top IS @@ -112,55 +112,9 @@ END MINI_LFR_top; ARCHITECTURE beh OF MINI_LFR_top IS - - COMPONENT leon3_soc - GENERIC ( - fabtech : INTEGER; - memtech : INTEGER; - padtech : INTEGER; - clktech : INTEGER; - disas : INTEGER; - dbguart : INTEGER; - pclow : INTEGER); - PORT ( - clk100MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - errorn : OUT STD_ULOGIC; - ahbrxd : IN STD_ULOGIC; - ahbtxd : OUT STD_ULOGIC; - urxd1 : IN STD_ULOGIC; - utxd1 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - apbi_ext : OUT apb_slv_in_type; - apbo_wfp : IN apb_slv_out_type; - apbo_ltm : IN apb_slv_out_type; - ahbi_ext : OUT AHB_Mst_In_Type; - ahbo_wfp : IN AHB_Mst_Out_Type); - END COMPONENT; - + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; ----------------------------------------------------------------------------- - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo_wfp : apb_slv_out_type; - SIGNAL apbo_ltm : apb_slv_out_type; - SIGNAL ahbi : AHB_Mst_In_Type; - SIGNAL ahbo_wfp : AHB_Mst_Out_Type; - -- SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); -- @@ -174,10 +128,41 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data -- SIGNAL I00_s : STD_LOGIC; + -- + CONSTANT NB_APB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_SLAVE : INTEGER := 1; + CONSTANT NB_AHB_MASTER : INTEGER := 1; + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); BEGIN -- beh - PROCESS (clk_50, reset) + ----------------------------------------------------------------------------- + -- CLK + ----------------------------------------------------------------------------- + + PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk_50_s <= NOT clk_50_s; + END IF; + END PROCESS; + + PROCESS(clk_50_s) + BEGIN + IF clk_50_s'EVENT AND clk_50_s = '1' THEN + clk_25 <= NOT clk_25; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + PROCESS (clk_25, reset) BEGIN -- PROCESS IF reset = '0' THEN -- asynchronous reset (active low) LED0 <= '0'; @@ -194,12 +179,12 @@ BEGIN -- beh IO9 <= '0'; IO10 <= '0'; IO11 <= '0'; - ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge + ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge LED0 <= '0'; LED1 <= '1'; LED2 <= BP0; IO1 <= '1'; - IO2 <= '0'; + IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; IO3 <= ADC_SDO(0); IO4 <= ADC_SDO(1); IO5 <= ADC_SDO(2); @@ -231,56 +216,60 @@ BEGIN -- beh --SPACE WIRE SPW_EN <= '0'; -- 0 => off + + SPW_NOM_DOUT <= '0'; + SPW_NOM_SOUT <= '0'; + SPW_RED_DOUT <= '0'; + SPW_RED_SOUT <= '0'; ADC_nCS <= '0'; ADC_CLK <= '0'; - - leon3mp_1: leon3_soc + + + leon3_soc_1: leon3_soc GENERIC MAP ( - fabtech => CFG_FABTECH, - memtech => CFG_MEMTECH, - padtech => CFG_PADTECH, - clktech => CFG_CLKTECH, - disas => CFG_DISAS, - dbguart => CFG_DUART, - pclow => CFG_PCLOW) + fabtech => apa3e, + memtech => apa3e, + padtech => inferred, + clktech => inferred, + disas => 0, + dbguart => 0, + pclow => 2, + clk_freq => 25000, + NB_CPU => 1, + ENABLE_FPU => 0, + FPU_NETLIST => 0, + ENABLE_DSU => 1, + ENABLE_AHB_UART => 1, + ENABLE_APB_UART => 1, + ENABLE_IRQMP => 1, + ENABLE_GPT => 1, + NB_AHB_MASTER => NB_AHB_MASTER, + NB_AHB_SLAVE => NB_AHB_SLAVE, + NB_APB_SLAVE => NB_APB_SLAVE) PORT MAP ( - clk100MHz => clk_50, -- - reset => reset, -- - errorn => errorn, -- + clk => clk_25, + reset => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, - ahbrxd => TXD1, -- - ahbtxd => RXD1, -- - urxd1 => TXD2, -- - utxd1 => RXD2, -- - --RAM - address => SRAM_A, -- - data => SRAM_DQ, -- - nSRAM_BE0 => SRAM_nBE(0), -- - nSRAM_BE1 => SRAM_nBE(1), -- - nSRAM_BE2 => SRAM_nBE(2), -- - nSRAM_BE3 => SRAM_nBE(3), -- - nSRAM_WE => SRAM_nWE, -- - nSRAM_CE => SRAM_CE, -- - nSRAM_OE => SRAM_nOE, -- - --SPW - spw1_din => SPW_NOM_DIN, -- - spw1_sin => SPW_NOM_SIN, -- - spw1_dout => SPW_NOM_DOUT, -- - spw1_sout => SPW_NOM_SOUT, -- - spw2_din => SPW_RED_DIN, -- - spw2_sin => SPW_RED_SIN, -- - spw2_dout => SPW_RED_DOUT, -- - spw2_sout => SPW_RED_SOUT, -- - - apbi_ext => apbi, -- - apbo_wfp => apbo_wfp, -- - apbo_ltm => apbo_ltm, -- lfr time management - ahbi_ext => ahbi, -- - ahbo_wfp => ahbo_wfp); -- + apbi_ext => apbi_ext, + apbo_ext => apbo_ext, + ahbi_s_ext => ahbi_s_ext, + ahbo_s_ext => ahbo_s_ext, + ahbi_m_ext => ahbi_m_ext, + ahbo_m_ext => ahbo_m_ext); - apbo_wfp <= apb_none; - apbo_ltm <= apb_none; - ahbo_wfp <= ahbm_none; - END beh; diff --git a/designs/MINI-LFR_waveformPicker/Makefile b/designs/MINI-LFR_waveformPicker/Makefile --- a/designs/MINI-LFR_waveformPicker/Makefile +++ b/designs/MINI-LFR_waveformPicker/Makefile @@ -10,9 +10,7 @@ QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf EFFORT=high XSTOPT= SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -VHDLSYNFILES= config.vhd \ - MINI_LFR_top.vhd \ - leon3_soc.vhd +VHDLSYNFILES= MINI_LFR_top.vhd PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut diff --git a/designs/MINI-LFR_waveformPicker/leon3_soc.vhd b/designs/MINI-LFR_waveformPicker/leon3_soc.vhd --- a/designs/MINI-LFR_waveformPicker/leon3_soc.vhd +++ b/designs/MINI-LFR_waveformPicker/leon3_soc.vhd @@ -77,6 +77,9 @@ ENTITY leon3_soc IS nSRAM_CE : OUT STD_LOGIC; nSRAM_OE : OUT STD_LOGIC; + -- APB -------------------------------------------------------------------- + + -- SPW -------------------------------------------------------------------- spw1_din : IN STD_LOGIC; -- PLE spw1_sin : IN STD_LOGIC; -- PLE @@ -115,7 +118,7 @@ ARCHITECTURE Behavioral OF leon3_soc IS SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL resetnl : STD_ULOGIC; SIGNAL clk2x : STD_ULOGIC; - SIGNAL lclk2x : STD_ULOGIC; +-- SIGNAL lclk2x : STD_ULOGIC; SIGNAL lclk25MHz : STD_ULOGIC; SIGNAL lclk50MHz : STD_ULOGIC; SIGNAL lclk100MHz : STD_ULOGIC; @@ -200,22 +203,9 @@ BEGIN CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; + - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - spw_clk <= lclk50MHz; +-- lclk2x <= lclk50MHz; ---------------------------------------------------------------------- --- LEON3 processor / DSU / IRQ ------------------------------------ @@ -355,91 +345,6 @@ BEGIN apbuarti.ctsn <= '0'; END GENERATE; noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => fabtech, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm - GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn, clkm, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbmi, ahbmo(1), apbi, apbo(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - ------------------------------------------------------------------------------- -- LFR ------------------------------------------------------------------------------- diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -21,3 +21,4 @@ ./lpp_waveform ./lpp_top_lfr ./lpp_Header +./lpp_leon3_soc diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -0,0 +1,424 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY leon3_soc IS + GENERIC ( + fabtech : INTEGER := apa3e; + memtech : INTEGER := apa3e; + padtech : INTEGER := inferred; + clktech : INTEGER := inferred; + disas : INTEGER := 0; -- Enable disassembly to console + dbguart : INTEGER := 0; -- Print UART on console + pclow : INTEGER := 2; + -- + clk_freq : INTEGER := 25000; --kHz + -- + NB_CPU : INTEGER := 1; + ENABLE_FPU : INTEGER := 1; + FPU_NETLIST : INTEGER := 1; + ENABLE_DSU : INTEGER := 1; + ENABLE_AHB_UART : INTEGER := 1; + ENABLE_APB_UART : INTEGER := 1; + ENABLE_IRQMP : INTEGER := 1; + ENABLE_GPT : INTEGER := 1; + -- + NB_AHB_MASTER : INTEGER := 0; + NB_AHB_SLAVE : INTEGER := 0; + NB_APB_SLAVE : INTEGER := 0 + ); + PORT ( + clk : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- APB -------------------------------------------------------------------- + apbi_ext : OUT apb_slv_in_type; + apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); + -- AHB_Slave -------------------------------------------------------------- + ahbi_s_ext : OUT ahb_slv_in_type; + ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); + -- AHB_Master ------------------------------------------------------------- + ahbi_m_ext : OUT AHB_Mst_In_Type; + ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) + + ); +END; + +ARCHITECTURE Behavioral OF leon3_soc IS + + ----------------------------------------------------------------------------- + -- CONFIG ------------------------------------------------------------------- + ----------------------------------------------------------------------------- + + -- Clock generator + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_CLK_NOFB : integer := 0; + -- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := NB_CPU; + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); + -- 1*(8 + 16 * 0) => grfpu-light + -- 1*(8 + 16 * 1) => netlist + -- 0*(8 + 16 * 0) => No FPU + -- 0*(8 + 16 * 1) => No FPU; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + + constant CFG_DSU : integer := ENABLE_DSU; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + + -- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + + -- DSU UART + constant CFG_AHB_UART : integer := ENABLE_AHB_UART; + + -- LEON2 memory controller + constant CFG_MCTRL_SDEN : integer := 0; + + -- UART 1 + constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; + constant CFG_UART1_FIFO : integer := 1; + + -- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; + + -- Modular timer + constant CFG_GPT_ENABLE : integer := ENABLE_GPT; + constant CFG_GPT_NTIM : integer := (2); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- SIGNALs + ----------------------------------------------------------------------------- + CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; + -- CLK & RST -- + SIGNAL clk2x : STD_ULOGIC; + SIGNAL clkmn : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; + --- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + --UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; + --MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + --IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); + --Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; + --DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + ----------------------------------------------------------------------------- +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + cgi.pllctrl <= "00"; + cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) + PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; + dsuo.tstop <= '0'; + dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => 0, nahbm => maxahbmsp, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- AMBA BUS ------------------------------------------------------------------- +------------------------------------------------------------------------------- + + -- APB -------------------------------------------------------------------- + apbi_ext <= apbi; + all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE + max_16_apb: IF I + 5 < 16 GENERATE + apbo(I+5)<= apbo_ext(I+5); + END GENERATE max_16_apb; + END GENERATE all_apb; + -- AHB_Slave -------------------------------------------------------------- + ahbi_s_ext <= ahbsi; + all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE + max_16_ahbs: IF I + 3 < 16 GENERATE + ahbso(I+3) <= ahbo_s_ext(I+3); + END GENERATE max_16_ahbs; + END GENERATE all_ahbs; + -- AHB_Master ------------------------------------------------------------- + ahbi_m_ext <= ahbmi; + all_ahbm: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE + max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE + ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); + END GENERATE max_16_ahbm; + END GENERATE all_ahbm; + + + +END Behavioral; diff --git a/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd b/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; + +PACKAGE lpp_leon3_soc_pkg IS + + type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type; + type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type; + type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type; + + COMPONENT leon3_soc + GENERIC ( + fabtech : INTEGER; + memtech : INTEGER; + padtech : INTEGER; + clktech : INTEGER; + disas : INTEGER; + dbguart : INTEGER; + pclow : INTEGER; + clk_freq : INTEGER; + NB_CPU : INTEGER; + ENABLE_FPU : INTEGER; + FPU_NETLIST : INTEGER; + ENABLE_DSU : INTEGER; + ENABLE_AHB_UART : INTEGER; + ENABLE_APB_UART : INTEGER; + ENABLE_IRQMP : INTEGER; + ENABLE_GPT : INTEGER; + NB_AHB_MASTER : INTEGER; + NB_AHB_SLAVE : INTEGER; + NB_APB_SLAVE : INTEGER); + PORT ( + clk : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + errorn : OUT STD_ULOGIC; + ahbrxd : IN STD_ULOGIC; + ahbtxd : OUT STD_ULOGIC; + urxd1 : IN STD_ULOGIC; + utxd1 : OUT STD_ULOGIC; + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + apbi_ext : OUT apb_slv_in_type; + apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); + ahbi_s_ext : OUT ahb_slv_in_type; + ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); + ahbi_m_ext : OUT AHB_Mst_In_Type; + ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); + END COMPONENT; + +END; diff --git a/lib/lpp/lpp_leon3_soc/vhdlsyn.txt b/lib/lpp/lpp_leon3_soc/vhdlsyn.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_leon3_soc/vhdlsyn.txt @@ -0,0 +1,2 @@ +lpp_leon3_soc_pkg.vhd +leon3_soc.vhd