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ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
Alexis Jeandet -
r220:9cd9574d2765 alexis
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@@ -0,0 +1,77
1 #!/bin/bash
2 #"======================================================================================="
3 #"---------------------------------------------------------------------------------------"
4 #" LPP VHDL lib makeDirs "
5 #" Copyright (C) 2010 Laboratory of Plasmas Physic. "
6 #"======================================================================================="
7 #----------------------------------------------------------------------------------------
8 # This file is a part of the LPP VHDL IP LIBRARY
9 # Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
10 #
11 # This program is free software; you can redistribute it and/or modify
12 # it under the terms of the GNU General Public License as published by
13 # the Free Software Foundation; either version 3 of the License, or
14 # (at your option) any later version.
15 #
16 # This program is distributed in the hope that it will be useful,
17 # but WITHOUT ANY WARRANTY; without even the implied warranty of
18 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 # GNU General Public License for more details.
20 #
21 # You should have received a copy of the GNU General Public License
22 # along with this program; if not, write to the Free Software
23 # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #----------------------------------------------------------------------------------------
25
26 function fullpath() {
27 if test $# -gt 0
28 then
29 cd $1
30 echo `pwd`
31 fi
32 }
33
34 function relpath() {
35 if test $# -gt 1
36 then
37 source=`fullpath $1`
38 target=`fullpath $2`
39
40 common_part=$source # for now
41 result="" # for now
42
43 while [[ "${target#$common_part}" == "${target}" ]]; do
44 # no match, means that candidate common part is not correct
45 # go up one level (reduce common part)
46 common_part="$(dirname $common_part)"
47 # and record that we went back, with correct / handling
48 if [[ -z $result ]]; then
49 result=".."
50 else
51 result="../$result"
52 fi
53 done
54
55 if [[ $common_part == "/" ]]; then
56 # special case for root (no common path)
57 result="$result/"
58 fi
59
60 # since we now have identified the common part,
61 # compute the non-common part
62 forward_part="${target#$common_part}"
63
64 # and now stick all parts together
65 if [[ -n $result ]] && [[ -n $forward_part ]]; then
66 result="$result$forward_part"
67 elif [[ -n $forward_part ]]; then
68 # extra slash removal
69 result="${forward_part:1}"
70 fi
71
72 echo $result
73 fi
74 }
75
76 PATH1=`pwd`
77 echo `relpath $PATH1 $GRLIB` No newline at end of file
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@@ -77,6 +77,8 Signal PROTO_DATAOUT : std_logic
77 77
78 78 Signal clk80 : std_logic;
79 79
80 signal cgi : clkgen_in_type;
81 signal cgo : clkgen_out_type;
80 82
81 83
82 84 begin
@@ -88,28 +90,33 DataRTX_echo <= DataRTX; --P48
88 90 ck_int0 : CLKINT
89 91 port map(Clock,clk_48);
90 92
91 DEFPLL: IF simu = 0 generate
92 PLL : entity work.PLL0
93 port map(
94 POWERDOWN => '1',
95 CLKA => clk_48,
96 LOCK => RaZ,
97 GLA => clk80,
98 GLB => clk --33.3MHz
99 );
100 end generate;
93 RaZ <= cgo.clklock;
101 94
95 CLKGEN : entity clkgen
96 generic map(
97 tech => CFG_CLKTECH,
98 clk_mul => CFG_CLKMUL,
99 clk_div => CFG_CLKDIV,
100 freq => BOARDFREQ, -- clock frequency in KHz
101 clk_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkA
102 clkb_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkB
103 clkc_odiv => CFG_OCLKDIV) -- Proasic3/Fusion output divider clkC
104 port map(
105 clkin => clk_48,
106 pciclkin => '0',
107 clk => clk, -- main clock
108 clkn => open, -- inverted main clock
109 clk2x => open, -- 2x clock
110 sdclk => open, -- SDRAM clock
111 pciclk => open, -- PCI clock
112 cgi => cgi,
113 cgo => cgo,
114 clk4x => open, -- 4x clock
115 clk1xu => open, -- unscaled 1X clock
116 clk2xu => open, -- unscaled 2X clock
117 clkb => clk80, -- Proasic3/Fusion clkB
118 clkc => open); -- Proasic3/Fusion clkC
102 119
103 SIMPLL: IF simu = 1 generate
104 PLL : entity work.PLL0Sim
105 port map(
106 POWERDOWN => '1',
107 CLKA => clk_48,
108 LOCK => RaZ,
109 GLA => clk80,
110 GLB => clk
111 );
112 end generate;
113 120
114 121
115 122 gene3_3M : entity Clk_Divider2
@@ -279,4 +286,3 end ar_TOP_EGSE2;
279 286
280 287
281 288
282
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@@ -24,10 +24,10 architecture ar_ICI_EGSE_PROTOCOL of ICI
24 24
25 25 type DATA_pipe_t is array(NATURAL RANGE <>) of std_logic_vector (WordSize-1 downto 0);
26 26
27 signal DATA_pipe : DATA_pipe_t(10 downto 0);
28 signal WR_pipe : std_logic_vector(10 downto 0);
27 signal DATA_pipe : DATA_pipe_t(12 downto 0);
28 signal WR_pipe : std_logic_vector(12 downto 0);
29 29 signal headerSended : std_logic := '0';
30
30 signal counter : std_logic_vector(7 downto 0):=(others => '0');
31 31
32 32 begin
33 33
@@ -39,35 +39,41 DATAOUT <= DATA_pipe(0);
39 39 process(reset,clk)
40 40 begin
41 41 if reset = '0' then
42 WR_pipe(10 downto 0) <= (others => '1');
43 rstloop: for i in 0 to 10 loop
42 WR_pipe(12 downto 0) <= (others => '1');
43 counter <= (others => '0');
44 rstloop: for i in 0 to 12 loop
44 45 DATA_pipe(i) <= X"00";
45 46 end loop;
46 47 headerSended <= '0';
47 48 elsif clk'event and clk ='1' then
48 49 if WordCnt_in = 1 and headerSended = '0' then
50 counter <= (others => '0');
49 51 WR_pipe(4 downto 1) <= (others => '0');
50 52 WR_pipe(1) <= '0';
51 53 WR_pipe(3) <= '0';
52 54 WR_pipe(5) <= '0';
53 55 WR_pipe(7) <= '0';
54 56 WR_pipe(9) <= '0';
55 DATA_pipe(1) <= X"0F";
57 WR_pipe(11) <= '0';
58 DATA_pipe(1) <= counter; -- Size
56 59 DATA_pipe(3) <= X"5a";
57 DATA_pipe(5) <= X"a5";
58 DATA_pipe(7) <= X"F0";
59 DATA_pipe(9) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize));
60 DATA_pipe(5) <= X"f0";
61 DATA_pipe(7) <= X"0f";
62 DATA_pipe(9) <= X"a5";
63 DATA_pipe(11) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize));
60 64 WR_pipe(0) <= '1';
61 65 WR_pipe(2) <= '1';
62 66 WR_pipe(4) <= '1';
63 67 WR_pipe(6) <= '1';
64 68 WR_pipe(8) <= '1';
65 69 WR_pipe(10) <= '1';
70 WR_pipe(12) <= '1';
66 71 DATA_pipe(0) <= X"00";
67 72 DATA_pipe(2) <= X"00";
68 73 DATA_pipe(4) <= X"00";
69 74 DATA_pipe(6) <= X"00";
70 75 DATA_pipe(10) <= X"00";
76 DATA_pipe(12) <= X"00";
71 77 headerSended <= '1';
72 78 elsif (FULL = '0') then
73 79 if WordCnt_in /= 1 then
@@ -83,8 +89,13 rstloop: for i in 0 to 10 loop
83 89 DATA_pipe(7) <= DATA_pipe(8);
84 90 DATA_pipe(8) <= DATA_pipe(9);
85 91 DATA_pipe(9) <= DATA_pipe(10);
86 DATA_pipe(10) <= DATAIN;
87 WR_pipe(10 downto 0) <= WEN & WR_pipe(10 downto 1);
92 DATA_pipe(10) <= DATA_pipe(11);
93 DATA_pipe(11) <= DATA_pipe(12);
94 DATA_pipe(12) <= DATAIN;
95 WR_pipe(12 downto 0) <= WEN & WR_pipe(12 downto 1);
96 if(WR_pipe(0) = '0') then
97 counter <= std_logic_vector(UNSIGNED(counter) + 1);
98 end if;
88 99 else
89 100 WR_pipe(0) <= '1';
90 101 if WordCnt_in /= 1 then
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@@ -1,5 +1,7
1 GRLIB=../..
1 #GRLIB=../..
2 2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 5 TOP=TOP_EGSE2
4 6 BOARD=GSE_ICI
5 7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
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@@ -28,13 +28,14 package config is
28 28 constant CFG_SCAN : integer := 0;
29 29
30 30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (5);
33 constant CFG_CLKDIV : integer := (10);
34 constant CFG_OCLKDIV : integer := (1);
31 constant CFG_CLKTECH : integer := apa3;
32 constant CFG_CLKMUL : integer := (25);
33 constant CFG_CLKDIV : integer := (9);
34 constant CFG_OCLKDIV : integer := (4);
35 35 constant CFG_PCIDLL : integer := 0;
36 36 constant CFG_PCISYSCLK: integer := 0;
37 37 constant CFG_CLK_NOFB : integer := 0;
38 constant BOARDFREQ : integer := 48000;
38 39
39 40
40 41 end;
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