diff --git a/designs/EGSE_ICI/EGSE_ICI.vhd b/designs/EGSE_ICI/EGSE_ICI.vhd --- a/designs/EGSE_ICI/EGSE_ICI.vhd +++ b/designs/EGSE_ICI/EGSE_ICI.vhd @@ -77,6 +77,8 @@ Signal PROTO_DATAOUT : std_logic Signal clk80 : std_logic; +signal cgi : clkgen_in_type; +signal cgo : clkgen_out_type; begin @@ -88,28 +90,33 @@ DataRTX_echo <= DataRTX; --P48 ck_int0 : CLKINT port map(Clock,clk_48); -DEFPLL: IF simu = 0 generate - PLL : entity work.PLL0 - port map( - POWERDOWN => '1', - CLKA => clk_48, - LOCK => RaZ, - GLA => clk80, - GLB => clk --33.3MHz - ); -end generate; +RaZ <= cgo.clklock; +CLKGEN : entity clkgen + generic map( + tech => CFG_CLKTECH, + clk_mul => CFG_CLKMUL, + clk_div => CFG_CLKDIV, + freq => BOARDFREQ, -- clock frequency in KHz + clk_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkA + clkb_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkB + clkc_odiv => CFG_OCLKDIV) -- Proasic3/Fusion output divider clkC + port map( + clkin => clk_48, + pciclkin => '0', + clk => clk, -- main clock + clkn => open, -- inverted main clock + clk2x => open, -- 2x clock + sdclk => open, -- SDRAM clock + pciclk => open, -- PCI clock + cgi => cgi, + cgo => cgo, + clk4x => open, -- 4x clock + clk1xu => open, -- unscaled 1X clock + clk2xu => open, -- unscaled 2X clock + clkb => clk80, -- Proasic3/Fusion clkB + clkc => open); -- Proasic3/Fusion clkC -SIMPLL: IF simu = 1 generate - PLL : entity work.PLL0Sim - port map( - POWERDOWN => '1', - CLKA => clk_48, - LOCK => RaZ, - GLA => clk80, - GLB => clk - ); -end generate; gene3_3M : entity Clk_Divider2 @@ -279,4 +286,3 @@ end ar_TOP_EGSE2; - diff --git a/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd b/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd --- a/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd +++ b/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd @@ -24,10 +24,10 @@ architecture ar_ICI_EGSE_PROTOCOL of ICI type DATA_pipe_t is array(NATURAL RANGE <>) of std_logic_vector (WordSize-1 downto 0); -signal DATA_pipe : DATA_pipe_t(10 downto 0); -signal WR_pipe : std_logic_vector(10 downto 0); +signal DATA_pipe : DATA_pipe_t(12 downto 0); +signal WR_pipe : std_logic_vector(12 downto 0); signal headerSended : std_logic := '0'; - +signal counter : std_logic_vector(7 downto 0):=(others => '0'); begin @@ -39,35 +39,41 @@ DATAOUT <= DATA_pipe(0); process(reset,clk) begin if reset = '0' then - WR_pipe(10 downto 0) <= (others => '1'); -rstloop: for i in 0 to 10 loop + WR_pipe(12 downto 0) <= (others => '1'); + counter <= (others => '0'); +rstloop: for i in 0 to 12 loop DATA_pipe(i) <= X"00"; end loop; headerSended <= '0'; elsif clk'event and clk ='1' then if WordCnt_in = 1 and headerSended = '0' then + counter <= (others => '0'); WR_pipe(4 downto 1) <= (others => '0'); WR_pipe(1) <= '0'; WR_pipe(3) <= '0'; WR_pipe(5) <= '0'; WR_pipe(7) <= '0'; WR_pipe(9) <= '0'; - DATA_pipe(1) <= X"0F"; + WR_pipe(11) <= '0'; + DATA_pipe(1) <= counter; -- Size DATA_pipe(3) <= X"5a"; - DATA_pipe(5) <= X"a5"; - DATA_pipe(7) <= X"F0"; - DATA_pipe(9) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize)); + DATA_pipe(5) <= X"f0"; + DATA_pipe(7) <= X"0f"; + DATA_pipe(9) <= X"a5"; + DATA_pipe(11) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize)); WR_pipe(0) <= '1'; WR_pipe(2) <= '1'; WR_pipe(4) <= '1'; WR_pipe(6) <= '1'; WR_pipe(8) <= '1'; WR_pipe(10) <= '1'; + WR_pipe(12) <= '1'; DATA_pipe(0) <= X"00"; DATA_pipe(2) <= X"00"; DATA_pipe(4) <= X"00"; DATA_pipe(6) <= X"00"; DATA_pipe(10) <= X"00"; + DATA_pipe(12) <= X"00"; headerSended <= '1'; elsif (FULL = '0') then if WordCnt_in /= 1 then @@ -83,8 +89,13 @@ rstloop: for i in 0 to 10 loop DATA_pipe(7) <= DATA_pipe(8); DATA_pipe(8) <= DATA_pipe(9); DATA_pipe(9) <= DATA_pipe(10); - DATA_pipe(10) <= DATAIN; - WR_pipe(10 downto 0) <= WEN & WR_pipe(10 downto 1); + DATA_pipe(10) <= DATA_pipe(11); + DATA_pipe(11) <= DATA_pipe(12); + DATA_pipe(12) <= DATAIN; + WR_pipe(12 downto 0) <= WEN & WR_pipe(12 downto 1); + if(WR_pipe(0) = '0') then + counter <= std_logic_vector(UNSIGNED(counter) + 1); + end if; else WR_pipe(0) <= '1'; if WordCnt_in /= 1 then diff --git a/designs/EGSE_ICI/Makefile b/designs/EGSE_ICI/Makefile --- a/designs/EGSE_ICI/Makefile +++ b/designs/EGSE_ICI/Makefile @@ -1,5 +1,7 @@ -GRLIB=../.. +#GRLIB=../.. VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) TOP=TOP_EGSE2 BOARD=GSE_ICI include $(GRLIB)/boards/$(BOARD)/Makefile.inc diff --git a/designs/EGSE_ICI/config.vhd b/designs/EGSE_ICI/config.vhd --- a/designs/EGSE_ICI/config.vhd +++ b/designs/EGSE_ICI/config.vhd @@ -28,13 +28,14 @@ package config is constant CFG_SCAN : integer := 0; -- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (5); - constant CFG_CLKDIV : integer := (10); - constant CFG_OCLKDIV : integer := (1); + constant CFG_CLKTECH : integer := apa3; + constant CFG_CLKMUL : integer := (25); + constant CFG_CLKDIV : integer := (9); + constant CFG_OCLKDIV : integer := (4); constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; + constant BOARDFREQ : integer := 48000; end; diff --git a/scripts/lpp_relpath.sh b/scripts/lpp_relpath.sh new file mode 100644 --- /dev/null +++ b/scripts/lpp_relpath.sh @@ -0,0 +1,77 @@ +#!/bin/bash +#"=======================================================================================" +#"---------------------------------------------------------------------------------------" +#" LPP VHDL lib makeDirs " +#" Copyright (C) 2010 Laboratory of Plasmas Physic. " +#"=======================================================================================" +#---------------------------------------------------------------------------------------- +# This file is a part of the LPP VHDL IP LIBRARY +# Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#---------------------------------------------------------------------------------------- + +function fullpath() { + if test $# -gt 0 + then + cd $1 + echo `pwd` + fi +} + +function relpath() { + if test $# -gt 1 + then + source=`fullpath $1` + target=`fullpath $2` + + common_part=$source # for now + result="" # for now + + while [[ "${target#$common_part}" == "${target}" ]]; do + # no match, means that candidate common part is not correct + # go up one level (reduce common part) + common_part="$(dirname $common_part)" + # and record that we went back, with correct / handling + if [[ -z $result ]]; then + result=".." + else + result="../$result" + fi + done + + if [[ $common_part == "/" ]]; then + # special case for root (no common path) + result="$result/" + fi + + # since we now have identified the common part, + # compute the non-common part + forward_part="${target#$common_part}" + + # and now stick all parts together + if [[ -n $result ]] && [[ -n $forward_part ]]; then + result="$result$forward_part" + elif [[ -n $forward_part ]]; then + # extra slash removal + result="${forward_part:1}" + fi + + echo $result + fi +} + +PATH1=`pwd` +echo `relpath $PATH1 $GRLIB` \ No newline at end of file