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Divide clk49 by 2 before sending to time_managment and adc_driver.
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench
2 -- LEON3 Demonstration design test bench
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 ------------------------------------------------------------------------------
4 ------------------------------------------------------------------------------
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 --
7 --
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 -- IN ADVANCE IN WRITING.
10 -- IN ADVANCE IN WRITING.
11 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
12
12
13 LIBRARY ieee;
13 LIBRARY ieee;
14 USE ieee.std_logic_1164.ALL;
14 USE ieee.std_logic_1164.ALL;
15
15
16 --LIBRARY std;
16 --LIBRARY std;
17 --USE std.textio.ALL;
17 --USE std.textio.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 LIBRARY gaisler;
22 LIBRARY gaisler;
23 USE gaisler.memctrl.ALL;
23 USE gaisler.memctrl.ALL;
24 USE gaisler.leon3.ALL;
24 USE gaisler.leon3.ALL;
25 USE gaisler.uart.ALL;
25 USE gaisler.uart.ALL;
26 USE gaisler.misc.ALL;
26 USE gaisler.misc.ALL;
27 USE gaisler.libdcom.ALL;
27 USE gaisler.libdcom.ALL;
28 USE gaisler.sim.ALL;
28 USE gaisler.sim.ALL;
29 USE gaisler.jtagtst.ALL;
29 USE gaisler.jtagtst.ALL;
30 USE gaisler.misc.ALL;
30 USE gaisler.misc.ALL;
31 LIBRARY techmap;
31 LIBRARY techmap;
32 USE techmap.gencomp.ALL;
32 USE techmap.gencomp.ALL;
33 LIBRARY esa;
33 LIBRARY esa;
34 USE esa.memoryctrl.ALL;
34 USE esa.memoryctrl.ALL;
35 --LIBRARY micron;
35 --LIBRARY micron;
36 --USE micron.components.ALL;
36 --USE micron.components.ALL;
37 LIBRARY lpp;
37 LIBRARY lpp;
38 USE lpp.lpp_waveform_pkg.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.testbench_package.ALL;
41 USE lpp.testbench_package.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
46
46
47 ENTITY testbench IS
47 ENTITY testbenc h IS
48 END;
48 END;
49
49
50 ARCHITECTURE behav OF testbench IS
50 ARCHITECTURE behav OF testbench IS
51 -- REG ADDRESS
51 -- REG ADDRESS
52 CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15;
52 CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15;
53 CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15;
53 CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15;
54 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
54 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
55 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
55 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
56 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
56 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
57 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
57 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
58 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
58 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
59 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
59 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
60 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
60 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
61 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
61 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
62 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
62 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
63 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
63 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
64 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
64 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
65 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
65 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
66 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
66 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
67 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
67 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
68 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
68 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
69 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
69 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
70 -- RAM ADDRESS
70 -- RAM ADDRESS
71 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
71 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
72 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
72 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
73 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
73 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
74 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
74 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
75
75
76
76
77 -- Common signal
77 -- Common signal
78 SIGNAL clk49_152MHz : STD_LOGIC := '0';
78 SIGNAL clk49_152MHz : STD_LOGIC := '0';
79 SIGNAL clk25MHz : STD_LOGIC := '0';
79 SIGNAL clk25MHz : STD_LOGIC := '0';
80 SIGNAL rstn : STD_LOGIC := '0';
80 SIGNAL rstn : STD_LOGIC := '0';
81
81
82 -- ADC interface
82 -- ADC interface
83 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
83 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
84 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
84 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
85 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
85 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
86
86
87 -- AD Converter RHF1401
87 -- AD Converter RHF1401
88 SIGNAL sample : Samples14v(7 DOWNTO 0);
88 SIGNAL sample : Samples14v(7 DOWNTO 0);
89 SIGNAL sample_val : STD_LOGIC;
89 SIGNAL sample_val : STD_LOGIC;
90
90
91 -- AHB/APB SIGNAL
91 -- AHB/APB SIGNAL
92 SIGNAL apbi : apb_slv_in_type;
92 SIGNAL apbi : apb_slv_in_type;
93 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
93 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
94 SIGNAL ahbsi : ahb_slv_in_type;
94 SIGNAL ahbsi : ahb_slv_in_type;
95 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
95 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
96 SIGNAL ahbmi : ahb_mst_in_type;
96 SIGNAL ahbmi : ahb_mst_in_type;
97 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
97 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
98
98
99 SIGNAL bias_fail_bw : STD_LOGIC;
99 SIGNAL bias_fail_bw : STD_LOGIC;
100
100
101 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
102 -- LPP_WAVEFORM
102 -- LPP_WAVEFORM
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 CONSTANT data_size : INTEGER := 96;
104 CONSTANT data_size : INTEGER := 96;
105 CONSTANT nb_burst_available_size : INTEGER := 50;
105 CONSTANT nb_burst_available_size : INTEGER := 50;
106 CONSTANT nb_snapshot_param_size : INTEGER := 2;
106 CONSTANT nb_snapshot_param_size : INTEGER := 2;
107 CONSTANT delta_vector_size : INTEGER := 2;
107 CONSTANT delta_vector_size : INTEGER := 2;
108 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
108 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
109
109
110 SIGNAL reg_run : STD_LOGIC;
110 SIGNAL reg_run : STD_LOGIC;
111 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
111 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
112 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL enable_f0 : STD_LOGIC;
117 SIGNAL enable_f0 : STD_LOGIC;
118 SIGNAL enable_f1 : STD_LOGIC;
118 SIGNAL enable_f1 : STD_LOGIC;
119 SIGNAL enable_f2 : STD_LOGIC;
119 SIGNAL enable_f2 : STD_LOGIC;
120 SIGNAL enable_f3 : STD_LOGIC;
120 SIGNAL enable_f3 : STD_LOGIC;
121 SIGNAL burst_f0 : STD_LOGIC;
121 SIGNAL burst_f0 : STD_LOGIC;
122 SIGNAL burst_f1 : STD_LOGIC;
122 SIGNAL burst_f1 : STD_LOGIC;
123 SIGNAL burst_f2 : STD_LOGIC;
123 SIGNAL burst_f2 : STD_LOGIC;
124 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
124 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
125 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
125 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
126 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL data_f0_in_valid : STD_LOGIC;
133 SIGNAL data_f0_in_valid : STD_LOGIC;
134 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL data_f1_in_valid : STD_LOGIC;
136 SIGNAL data_f1_in_valid : STD_LOGIC;
137 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL data_f2_in_valid : STD_LOGIC;
139 SIGNAL data_f2_in_valid : STD_LOGIC;
140 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL data_f3_in_valid : STD_LOGIC;
142 SIGNAL data_f3_in_valid : STD_LOGIC;
143 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL data_f0_data_out_valid : STD_LOGIC;
146 SIGNAL data_f0_data_out_valid : STD_LOGIC;
147 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
147 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
148 SIGNAL data_f0_data_out_ack : STD_LOGIC;
148 SIGNAL data_f0_data_out_ack : STD_LOGIC;
149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
153 SIGNAL data_f1_data_out_ack : STD_LOGIC;
153 SIGNAL data_f1_data_out_ack : STD_LOGIC;
154 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL data_f2_data_out_valid : STD_LOGIC;
156 SIGNAL data_f2_data_out_valid : STD_LOGIC;
157 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
157 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
158 SIGNAL data_f2_data_out_ack : STD_LOGIC;
158 SIGNAL data_f2_data_out_ack : STD_LOGIC;
159 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f3_data_out_valid : STD_LOGIC;
161 SIGNAL data_f3_data_out_valid : STD_LOGIC;
162 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
162 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f3_data_out_ack : STD_LOGIC;
163 SIGNAL data_f3_data_out_ack : STD_LOGIC;
164
164
165 --MEM CTRLR
165 --MEM CTRLR
166 SIGNAL memi : memory_in_type;
166 SIGNAL memi : memory_in_type;
167 SIGNAL memo : memory_out_type;
167 SIGNAL memo : memory_out_type;
168 SIGNAL wpo : wprot_out_type;
168 SIGNAL wpo : wprot_out_type;
169 SIGNAL sdo : sdram_out_type;
169 SIGNAL sdo : sdram_out_type;
170
170
171 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0);
171 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0);
172 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL nSRAM_BE0 : STD_LOGIC;
173 SIGNAL nSRAM_BE0 : STD_LOGIC;
174 SIGNAL nSRAM_BE1 : STD_LOGIC;
174 SIGNAL nSRAM_BE1 : STD_LOGIC;
175 SIGNAL nSRAM_BE2 : STD_LOGIC;
175 SIGNAL nSRAM_BE2 : STD_LOGIC;
176 SIGNAL nSRAM_BE3 : STD_LOGIC;
176 SIGNAL nSRAM_BE3 : STD_LOGIC;
177 SIGNAL nSRAM_WE : STD_LOGIC;
177 SIGNAL nSRAM_WE : STD_LOGIC;
178 SIGNAL nSRAM_CE : STD_LOGIC;
178 SIGNAL nSRAM_CE : STD_LOGIC;
179 SIGNAL nSRAM_OE : STD_LOGIC;
179 SIGNAL nSRAM_OE : STD_LOGIC;
180
180
181 CONSTANT padtech : INTEGER := inferred;
181 CONSTANT padtech : INTEGER := inferred;
182 SIGNAL not_ramsn_0 : STD_LOGIC;
182 SIGNAL not_ramsn_0 : STD_LOGIC;
183
183
184
184
185 BEGIN
185 BEGIN
186
186
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188
188
189 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
189 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
190 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
190 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
191
191
192 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
193
193
194 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
194 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
195 TestModule_RHF1401_1 : TestModule_RHF1401
195 TestModule_RHF1401_1 : TestModule_RHF1401
196 GENERIC MAP (
196 GENERIC MAP (
197 freq => 24*(I+1),
197 freq => 24*(I+1),
198 amplitude => 8000/(I+1),
198 amplitude => 8000/(I+1),
199 impulsion => 0)
199 impulsion => 0)
200 PORT MAP (
200 PORT MAP (
201 ADC_smpclk => ADC_smpclk,
201 ADC_smpclk => ADC_smpclk,
202 ADC_OEB_bar => ADC_OEB_bar_CH(I),
202 ADC_OEB_bar => ADC_OEB_bar_CH(I),
203 ADC_data => ADC_data);
203 ADC_data => ADC_data);
204 END GENERATE MODULE_RHF1401;
204 END GENERATE MODULE_RHF1401;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
208 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
209 GENERIC MAP (
209 GENERIC MAP (
210 ChanelCount => 8,
210 ChanelCount => 8,
211 ncycle_cnv_high => 79,
211 ncycle_cnv_high => 79,
212 ncycle_cnv => 500)
212 ncycle_cnv => 500)
213 PORT MAP (
213 PORT MAP (
214 cnv_clk => clk49_152MHz,
214 cnv_clk => clk49_152MHz,
215 cnv_rstn => rstn,
215 cnv_rstn => rstn,
216 cnv => ADC_smpclk,
216 cnv => ADC_smpclk,
217 clk => clk25MHz,
217 clk => clk25MHz,
218 rstn => rstn,
218 rstn => rstn,
219 ADC_data => ADC_data,
219 ADC_data => ADC_data,
220 ADC_nOE => ADC_OEB_bar_CH,
220 ADC_nOE => ADC_OEB_bar_CH,
221 sample => sample,
221 sample => sample,
222 sample_val => sample_val);
222 sample_val => sample_val);
223
223
224 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
225
225
226 lpp_lfr_1 : lpp_lfr
226 lpp_lfr_1 : lpp_lfr
227 GENERIC MAP (
227 GENERIC MAP (
228 Mem_use => use_CEL, -- use_RAM
228 Mem_use => use_CEL, -- use_RAM
229 nb_data_by_buffer_size => 32,
229 nb_data_by_buffer_size => 32,
230 nb_word_by_buffer_size => 30,
230 nb_word_by_buffer_size => 30,
231 nb_snapshot_param_size => 32,
231 nb_snapshot_param_size => 32,
232 delta_vector_size => 32,
232 delta_vector_size => 32,
233 delta_vector_size_f0_2 => 32,
233 delta_vector_size_f0_2 => 32,
234 pindex => INDEX_WAVEFORM_PICKER,
234 pindex => INDEX_WAVEFORM_PICKER,
235 paddr => ADDR_WAVEFORM_PICKER,
235 paddr => ADDR_WAVEFORM_PICKER,
236 pmask => 16#fff#,
236 pmask => 16#fff#,
237 pirq_ms => 6,
237 pirq_ms => 6,
238 pirq_wfp => 14,
238 pirq_wfp => 14,
239 hindex => 0,
239 hindex => 0,
240 top_lfr_version => X"00000001")
240 top_lfr_version => X"00000001")
241 PORT MAP (
241 PORT MAP (
242 clk => clk25MHz,
242 clk => clk25MHz,
243 rstn => rstn,
243 rstn => rstn,
244 sample_B => sample(2 DOWNTO 0),
244 sample_B => sample(2 DOWNTO 0),
245 sample_E => sample(7 DOWNTO 3),
245 sample_E => sample(7 DOWNTO 3),
246 sample_val => sample_val,
246 sample_val => sample_val,
247 apbi => apbi,
247 apbi => apbi,
248 apbo => apbo(15),
248 apbo => apbo(15),
249 ahbi => ahbmi,
249 ahbi => ahbmi,
250 ahbo => ahbmo(0),
250 ahbo => ahbmo(0),
251 coarse_time => coarse_time,
251 coarse_time => coarse_time,
252 fine_time => fine_time,
252 fine_time => fine_time,
253 data_shaping_BW => bias_fail_bw);
253 data_shaping_BW => bias_fail_bw);
254
254
255 -----------------------------------------------------------------------------
255 -----------------------------------------------------------------------------
256 --- AHB CONTROLLER -------------------------------------------------
256 --- AHB CONTROLLER -------------------------------------------------
257 ahb0 : ahbctrl -- AHB arbiter/multiplexer
257 ahb0 : ahbctrl -- AHB arbiter/multiplexer
258 GENERIC MAP (defmast => 0, split => 0,
258 GENERIC MAP (defmast => 0, split => 0,
259 rrobin => 1, ioaddr => 16#FFF#,
259 rrobin => 1, ioaddr => 16#FFF#,
260 ioen => 0, nahbm => 1, nahbs => 1)
260 ioen => 0, nahbm => 1, nahbs => 1)
261 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
261 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
262
262
263 --- AHB RAM ----------------------------------------------------------
263 --- AHB RAM ----------------------------------------------------------
264 --ahbram0 : ahbram
264 --ahbram0 : ahbram
265 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
265 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
266 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
266 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
267 --ahbram1 : ahbram
267 --ahbram1 : ahbram
268 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
268 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
269 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
269 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
270 --ahbram2 : ahbram
270 --ahbram2 : ahbram
271 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
271 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
272 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
272 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
273 --ahbram3 : ahbram
273 --ahbram3 : ahbram
274 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
274 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
275 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
275 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
276
276
277 -----------------------------------------------------------------------------
277 -----------------------------------------------------------------------------
278 ----------------------------------------------------------------------
278 ----------------------------------------------------------------------
279 --- Memory controllers ---------------------------------------------
279 --- Memory controllers ---------------------------------------------
280 ----------------------------------------------------------------------
280 ----------------------------------------------------------------------
281 memctrlr : mctrl GENERIC MAP (
281 memctrlr : mctrl GENERIC MAP (
282 hindex => 0,
282 hindex => 0,
283 pindex => 0,
283 pindex => 0,
284 paddr => 0,
284 paddr => 0,
285 srbanks => 1
285 srbanks => 1
286 )
286 )
287 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
287 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
288
288
289 memi.brdyn <= '1';
289 memi.brdyn <= '1';
290 memi.bexcn <= '1';
290 memi.bexcn <= '1';
291 memi.writen <= '1';
291 memi.writen <= '1';
292 memi.wrn <= "1111";
292 memi.wrn <= "1111";
293 memi.bwidth <= "10";
293 memi.bwidth <= "10";
294
294
295 bdr : FOR i IN 0 TO 3 GENERATE
295 bdr : FOR i IN 0 TO 3 GENERATE
296 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
296 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
297 PORT MAP (
297 PORT MAP (
298 data(31-i*8 DOWNTO 24-i*8),
298 data(31-i*8 DOWNTO 24-i*8),
299 memo.data(31-i*8 DOWNTO 24-i*8),
299 memo.data(31-i*8 DOWNTO 24-i*8),
300 memo.bdrive(i),
300 memo.bdrive(i),
301 memi.data(31-i*8 DOWNTO 24-i*8));
301 memi.data(31-i*8 DOWNTO 24-i*8));
302 END GENERATE;
302 END GENERATE;
303
303
304 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
304 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
305 PORT MAP (address, memo.address(21 DOWNTO 2));
305 PORT MAP (address, memo.address(21 DOWNTO 2));
306
306
307 not_ramsn_0 <= NOT(memo.ramsn(0));
307 not_ramsn_0 <= NOT(memo.ramsn(0));
308
308
309 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
309 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
310 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
310 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
311 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
311 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
312 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
312 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
313 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
313 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
314 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
314 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
315 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
315 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
316
316
317 async_1Mx16_0: CY7C1061DV33
317 async_1Mx16_0: CY7C1061DV33
318 GENERIC MAP (
318 GENERIC MAP (
319 ADDR_BITS => 20,
319 ADDR_BITS => 20,
320 DATA_BITS => 16,
320 DATA_BITS => 16,
321 depth => 1048576,
321 depth => 1048576,
322 TimingInfo => TRUE,
322 TimingInfo => TRUE,
323 TimingChecks => '1')
323 TimingChecks => '1')
324 PORT MAP (
324 PORT MAP (
325 CE1_b => '0',
325 CE1_b => '0',
326 CE2 => nSRAM_CE,
326 CE2 => nSRAM_CE,
327 WE_b => nSRAM_WE,
327 WE_b => nSRAM_WE,
328 OE_b => nSRAM_OE,
328 OE_b => nSRAM_OE,
329 BHE_b => nSRAM_BE1,
329 BHE_b => nSRAM_BE1,
330 BLE_b => nSRAM_BE0,
330 BLE_b => nSRAM_BE0,
331 A => address,
331 A => address,
332 DQ => data(15 DOWNTO 0));
332 DQ => data(15 DOWNTO 0));
333
333
334 async_1Mx16_1: CY7C1061DV33
334 async_1Mx16_1: CY7C1061DV33
335 GENERIC MAP (
335 GENERIC MAP (
336 ADDR_BITS => 20,
336 ADDR_BITS => 20,
337 DATA_BITS => 16,
337 DATA_BITS => 16,
338 depth => 1048576,
338 depth => 1048576,
339 TimingInfo => TRUE,
339 TimingInfo => TRUE,
340 TimingChecks => '1')
340 TimingChecks => '1')
341 PORT MAP (
341 PORT MAP (
342 CE1_b => '0',
342 CE1_b => '0',
343 CE2 => nSRAM_CE,
343 CE2 => nSRAM_CE,
344 WE_b => nSRAM_WE,
344 WE_b => nSRAM_WE,
345 OE_b => nSRAM_OE,
345 OE_b => nSRAM_OE,
346 BHE_b => nSRAM_BE3,
346 BHE_b => nSRAM_BE3,
347 BLE_b => nSRAM_BE2,
347 BLE_b => nSRAM_BE2,
348 A => address,
348 A => address,
349 DQ => data(31 DOWNTO 16));
349 DQ => data(31 DOWNTO 16));
350
350
351
351
352 -----------------------------------------------------------------------------
352 -----------------------------------------------------------------------------
353
353
354 WaveGen_Proc : PROCESS
354 WaveGen_Proc : PROCESS
355 BEGIN
355 BEGIN
356
356
357 -- insert signal assignments here
357 -- insert signal assignments here
358 WAIT UNTIL clk25MHz = '1';
358 WAIT UNTIL clk25MHz = '1';
359 rstn <= '0';
359 rstn <= '0';
360 apbi.psel(15) <= '0';
360 apbi.psel(15) <= '0';
361 apbi.pwrite <= '0';
361 apbi.pwrite <= '0';
362 apbi.penable <= '0';
362 apbi.penable <= '0';
363 apbi.paddr <= (OTHERS => '0');
363 apbi.paddr <= (OTHERS => '0');
364 apbi.pwdata <= (OTHERS => '0');
364 apbi.pwdata <= (OTHERS => '0');
365 fine_time <= (OTHERS => '0');
365 fine_time <= (OTHERS => '0');
366 coarse_time <= (OTHERS => '0');
366 coarse_time <= (OTHERS => '0');
367 WAIT UNTIL clk25MHz = '1';
367 WAIT UNTIL clk25MHz = '1';
368 -- ahbmi.HGRANT(2) <= '1';
368 -- ahbmi.HGRANT(2) <= '1';
369 -- ahbmi.HREADY <= '1';
369 -- ahbmi.HREADY <= '1';
370 -- ahbmi.HRESP <= HRESP_OKAY;
370 -- ahbmi.HRESP <= HRESP_OKAY;
371
371
372 WAIT UNTIL clk25MHz = '1';
372 WAIT UNTIL clk25MHz = '1';
373 WAIT UNTIL clk25MHz = '1';
373 WAIT UNTIL clk25MHz = '1';
374 rstn <= '1';
374 rstn <= '1';
375 WAIT UNTIL clk25MHz = '1';
375 WAIT UNTIL clk25MHz = '1';
376 WAIT UNTIL clk25MHz = '1';
376 WAIT UNTIL clk25MHz = '1';
377 ---------------------------------------------------------------------------
377 ---------------------------------------------------------------------------
378 -- CONFIGURATION STEP
378 -- CONFIGURATION STEP
379 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
379 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
380 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
380 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
381 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
381 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
382 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
382 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
383
383
384 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
384 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
385 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
385 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
386 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
386 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
387 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
387 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
388 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
388 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
389
389
390 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
390 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
391 --
391 --
392 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
392 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
393 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
393 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
394 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
394 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
395
395
396
396
397 WAIT UNTIL clk25MHz = '1';
397 WAIT UNTIL clk25MHz = '1';
398 WAIT UNTIL clk25MHz = '1';
398 WAIT UNTIL clk25MHz = '1';
399 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
399 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
400 WAIT UNTIL clk25MHz = '1';
400 WAIT UNTIL clk25MHz = '1';
401 WAIT UNTIL clk25MHz = '1';
401 WAIT UNTIL clk25MHz = '1';
402 WAIT UNTIL clk25MHz = '1';
402 WAIT UNTIL clk25MHz = '1';
403 WAIT UNTIL clk25MHz = '1';
403 WAIT UNTIL clk25MHz = '1';
404 WAIT UNTIL clk25MHz = '1';
404 WAIT UNTIL clk25MHz = '1';
405 WAIT UNTIL clk25MHz = '1';
405 WAIT UNTIL clk25MHz = '1';
406 WAIT FOR 1 us;
406 WAIT FOR 1 us;
407 coarse_time <= X"00000001";
407 coarse_time <= X"00000001";
408 ---------------------------------------------------------------------------
408 ---------------------------------------------------------------------------
409 -- RUN STEP
409 -- RUN STEP
410 WAIT FOR 200 ms;
410 WAIT FOR 200 ms;
411 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
411 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
412 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
412 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
413 WAIT FOR 10 us;
413 WAIT FOR 10 us;
414 WAIT UNTIL clk25MHz = '1';
414 WAIT UNTIL clk25MHz = '1';
415 WAIT UNTIL clk25MHz = '1';
415 WAIT UNTIL clk25MHz = '1';
416 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
416 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
417 WAIT UNTIL clk25MHz = '1';
417 WAIT UNTIL clk25MHz = '1';
418 coarse_time <= X"00000010";
418 coarse_time <= X"00000010";
419 WAIT FOR 100 ms;
419 WAIT FOR 100 ms;
420 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
420 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
421 WAIT FOR 10 us;
421 WAIT FOR 10 us;
422 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
422 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
423 WAIT FOR 200 ms;
423 WAIT FOR 200 ms;
424 REPORT "*** END simulation ***" SEVERITY failure;
424 REPORT "*** END simulation ***" SEVERITY failure;
425
425
426
426
427 WAIT;
427 WAIT;
428
428
429 END PROCESS WaveGen_Proc;
429 END PROCESS WaveGen_Proc;
430 -----------------------------------------------------------------------------
430 -----------------------------------------------------------------------------
431
431
432 -----------------------------------------------------------------------------
432 -----------------------------------------------------------------------------
433 -- IRQ
433 -- IRQ
434 -----------------------------------------------------------------------------
434 -----------------------------------------------------------------------------
435 PROCESS (clk25MHz, rstn)
435 PROCESS (clk25MHz, rstn)
436 BEGIN -- PROCESS
436 BEGIN -- PROCESS
437 IF rstn = '0' THEN -- asynchronous reset (active low)
437 IF rstn = '0' THEN -- asynchronous reset (active low)
438
438
439 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
439 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
440
440
441 END IF;
441 END IF;
442 END PROCESS;
442 END PROCESS;
443 -----------------------------------------------------------------------------
443 -----------------------------------------------------------------------------
444
444
445 END;
445 END;
Show file before | Show file after | Hide comments
@@ -1,492 +1,503
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 --
122 --
122 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
123 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126
127
127 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
131 --
131 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
132
133
133 -- CONSTANTS
134 -- CONSTANTS
134 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 --
136 --
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139
140
140 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146
147
147 -- Spacewire signals
148 -- Spacewire signals
148 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
156 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158
159
159 --GPIO
160 --GPIO
160 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
162
163
163 -- AD Converter ADS7886
164 -- AD Converter ADS7886
164 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169
170
170 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171
172
173 -----------------------------------------------------------------------------
174
172 BEGIN -- beh
175 BEGIN -- beh
173
176
174 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
175 -- CLK
178 -- CLK
176 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
177
180
178 PROCESS(clk_50)
181 PROCESS(clk_50)
179 BEGIN
182 BEGIN
180 IF clk_50'EVENT AND clk_50 = '1' THEN
183 IF clk_50'EVENT AND clk_50 = '1' THEN
181 clk_50_s <= NOT clk_50_s;
184 clk_50_s <= NOT clk_50_s;
182 END IF;
185 END IF;
183 END PROCESS;
186 END PROCESS;
184
187
185 PROCESS(clk_50_s)
188 PROCESS(clk_50_s)
186 BEGIN
189 BEGIN
187 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
190 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
188 clk_25 <= NOT clk_25;
191 clk_25 <= NOT clk_25;
189 END IF;
192 END IF;
190 END PROCESS;
193 END PROCESS;
191
194
195 PROCESS(clk_49)
196 BEGIN
197 IF clk_49'EVENT AND clk_49 = '1' THEN
198 clk_24 <= NOT clk_24;
199 END IF;
200 END PROCESS;
201
192 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
193
203
194 PROCESS (clk_25, reset)
204 PROCESS (clk_25, reset)
195 BEGIN -- PROCESS
205 BEGIN -- PROCESS
196 IF reset = '0' THEN -- asynchronous reset (active low)
206 IF reset = '0' THEN -- asynchronous reset (active low)
197 LED0 <= '0';
207 LED0 <= '0';
198 LED1 <= '0';
208 LED1 <= '0';
199 LED2 <= '0';
209 LED2 <= '0';
200 --IO1 <= '0';
210 --IO1 <= '0';
201 --IO2 <= '1';
211 --IO2 <= '1';
202 --IO3 <= '0';
212 --IO3 <= '0';
203 --IO4 <= '0';
213 --IO4 <= '0';
204 --IO5 <= '0';
214 --IO5 <= '0';
205 --IO6 <= '0';
215 --IO6 <= '0';
206 --IO7 <= '0';
216 --IO7 <= '0';
207 --IO8 <= '0';
217 --IO8 <= '0';
208 --IO9 <= '0';
218 --IO9 <= '0';
209 --IO10 <= '0';
219 --IO10 <= '0';
210 --IO11 <= '0';
220 --IO11 <= '0';
211 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
212 LED0 <= '0';
222 LED0 <= '0';
213 LED1 <= '1';
223 LED1 <= '1';
214 LED2 <= BP0;
224 LED2 <= BP0;
215 --IO1 <= '1';
225 --IO1 <= '1';
216 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
217 --IO3 <= ADC_SDO(0);
227 --IO3 <= ADC_SDO(0);
218 --IO4 <= ADC_SDO(1);
228 --IO4 <= ADC_SDO(1);
219 --IO5 <= ADC_SDO(2);
229 --IO5 <= ADC_SDO(2);
220 --IO6 <= ADC_SDO(3);
230 --IO6 <= ADC_SDO(3);
221 --IO7 <= ADC_SDO(4);
231 --IO7 <= ADC_SDO(4);
222 --IO8 <= ADC_SDO(5);
232 --IO8 <= ADC_SDO(5);
223 --IO9 <= ADC_SDO(6);
233 --IO9 <= ADC_SDO(6);
224 --IO10 <= ADC_SDO(7);
234 --IO10 <= ADC_SDO(7);
225 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 END IF;
236 END IF;
227 END PROCESS;
237 END PROCESS;
228
238
229 PROCESS (clk_49, reset)
239 PROCESS (clk_24, reset)
230 BEGIN -- PROCESS
240 BEGIN -- PROCESS
231 IF reset = '0' THEN -- asynchronous reset (active low)
241 IF reset = '0' THEN -- asynchronous reset (active low)
232 I00_s <= '0';
242 I00_s <= '0';
233 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
234 I00_s <= NOT I00_s;
244 I00_s <= NOT I00_s;
235 END IF;
245 END IF;
236 END PROCESS;
246 END PROCESS;
237 -- IO0 <= I00_s;
247 -- IO0 <= I00_s;
238
248
239 --UARTs
249 --UARTs
240 nCTS1 <= '1';
250 nCTS1 <= '1';
241 nCTS2 <= '1';
251 nCTS2 <= '1';
242 nDCD2 <= '1';
252 nDCD2 <= '1';
243
253
244 --EXT CONNECTOR
254 --EXT CONNECTOR
245
255
246 --SPACE WIRE
256 --SPACE WIRE
247
257
248 leon3_soc_1 : leon3_soc
258 leon3_soc_1 : leon3_soc
249 GENERIC MAP (
259 GENERIC MAP (
250 fabtech => apa3e,
260 fabtech => apa3e,
251 memtech => apa3e,
261 memtech => apa3e,
252 padtech => inferred,
262 padtech => inferred,
253 clktech => inferred,
263 clktech => inferred,
254 disas => 0,
264 disas => 0,
255 dbguart => 0,
265 dbguart => 0,
256 pclow => 2,
266 pclow => 2,
257 clk_freq => 25000,
267 clk_freq => 25000,
258 NB_CPU => 1,
268 NB_CPU => 1,
259 ENABLE_FPU => 1,
269 ENABLE_FPU => 1,
260 FPU_NETLIST => 0,
270 FPU_NETLIST => 0,
261 ENABLE_DSU => 1,
271 ENABLE_DSU => 1,
262 ENABLE_AHB_UART => 1,
272 ENABLE_AHB_UART => 1,
263 ENABLE_APB_UART => 1,
273 ENABLE_APB_UART => 1,
264 ENABLE_IRQMP => 1,
274 ENABLE_IRQMP => 1,
265 ENABLE_GPT => 1,
275 ENABLE_GPT => 1,
266 NB_AHB_MASTER => NB_AHB_MASTER,
276 NB_AHB_MASTER => NB_AHB_MASTER,
267 NB_AHB_SLAVE => NB_AHB_SLAVE,
277 NB_AHB_SLAVE => NB_AHB_SLAVE,
268 NB_APB_SLAVE => NB_APB_SLAVE)
278 NB_APB_SLAVE => NB_APB_SLAVE)
269 PORT MAP (
279 PORT MAP (
270 clk => clk_25,
280 clk => clk_25,
271 reset => reset,
281 reset => reset,
272 errorn => errorn,
282 errorn => errorn,
273 ahbrxd => TXD1,
283 ahbrxd => TXD1,
274 ahbtxd => RXD1,
284 ahbtxd => RXD1,
275 urxd1 => TXD2,
285 urxd1 => TXD2,
276 utxd1 => RXD2,
286 utxd1 => RXD2,
277 address => SRAM_A,
287 address => SRAM_A,
278 data => SRAM_DQ,
288 data => SRAM_DQ,
279 nSRAM_BE0 => SRAM_nBE(0),
289 nSRAM_BE0 => SRAM_nBE(0),
280 nSRAM_BE1 => SRAM_nBE(1),
290 nSRAM_BE1 => SRAM_nBE(1),
281 nSRAM_BE2 => SRAM_nBE(2),
291 nSRAM_BE2 => SRAM_nBE(2),
282 nSRAM_BE3 => SRAM_nBE(3),
292 nSRAM_BE3 => SRAM_nBE(3),
283 nSRAM_WE => SRAM_nWE,
293 nSRAM_WE => SRAM_nWE,
284 nSRAM_CE => SRAM_CE,
294 nSRAM_CE => SRAM_CE,
285 nSRAM_OE => SRAM_nOE,
295 nSRAM_OE => SRAM_nOE,
286
296
287 apbi_ext => apbi_ext,
297 apbi_ext => apbi_ext,
288 apbo_ext => apbo_ext,
298 apbo_ext => apbo_ext,
289 ahbi_s_ext => ahbi_s_ext,
299 ahbi_s_ext => ahbi_s_ext,
290 ahbo_s_ext => ahbo_s_ext,
300 ahbo_s_ext => ahbo_s_ext,
291 ahbi_m_ext => ahbi_m_ext,
301 ahbi_m_ext => ahbi_m_ext,
292 ahbo_m_ext => ahbo_m_ext);
302 ahbo_m_ext => ahbo_m_ext);
293
303
294 -------------------------------------------------------------------------------
304 -------------------------------------------------------------------------------
295 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
305 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
296 -------------------------------------------------------------------------------
306 -------------------------------------------------------------------------------
297 apb_lfr_time_management_1 : apb_lfr_time_management
307 apb_lfr_time_management_1 : apb_lfr_time_management
298 GENERIC MAP (
308 GENERIC MAP (
299 pindex => 6,
309 pindex => 6,
300 paddr => 6,
310 paddr => 6,
301 pmask => 16#fff#,
311 pmask => 16#fff#,
302 pirq => 12)
312 pirq => 12,
313 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
303 PORT MAP (
314 PORT MAP (
304 clk25MHz => clk_25,
315 clk25MHz => clk_25,
305 clk49_152MHz => clk_49,
316 clk49_152MHz => clk_24, -- 49.152MHz/2
306 resetn => reset,
317 resetn => reset,
307 grspw_tick => swno.tickout,
318 grspw_tick => swno.tickout,
308 apbi => apbi_ext,
319 apbi => apbi_ext,
309 apbo => apbo_ext(6),
320 apbo => apbo_ext(6),
310 coarse_time => coarse_time,
321 coarse_time => coarse_time,
311 fine_time => fine_time);
322 fine_time => fine_time);
312
323
313 -----------------------------------------------------------------------
324 -----------------------------------------------------------------------
314 --- SpaceWire --------------------------------------------------------
325 --- SpaceWire --------------------------------------------------------
315 -----------------------------------------------------------------------
326 -----------------------------------------------------------------------
316
327
317 SPW_EN <= '1';
328 SPW_EN <= '1';
318
329
319 spw_clk <= clk_50_s;
330 spw_clk <= clk_50_s;
320 spw_rxtxclk <= spw_clk;
331 spw_rxtxclk <= spw_clk;
321 spw_rxclkn <= NOT spw_rxtxclk;
332 spw_rxclkn <= NOT spw_rxtxclk;
322
333
323 -- PADS for SPW1
334 -- PADS for SPW1
324 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
335 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
325 PORT MAP (SPW_NOM_DIN, dtmp(0));
336 PORT MAP (SPW_NOM_DIN, dtmp(0));
326 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
337 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
327 PORT MAP (SPW_NOM_SIN, stmp(0));
338 PORT MAP (SPW_NOM_SIN, stmp(0));
328 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
339 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
329 PORT MAP (SPW_NOM_DOUT, swno.d(0));
340 PORT MAP (SPW_NOM_DOUT, swno.d(0));
330 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
341 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
331 PORT MAP (SPW_NOM_SOUT, swno.s(0));
342 PORT MAP (SPW_NOM_SOUT, swno.s(0));
332 -- PADS FOR SPW2
343 -- PADS FOR SPW2
333 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
344 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
334 PORT MAP (SPW_RED_SIN, dtmp(1));
345 PORT MAP (SPW_RED_SIN, dtmp(1));
335 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 PORT MAP (SPW_RED_DIN, stmp(1));
347 PORT MAP (SPW_RED_DIN, stmp(1));
337 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
348 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_RED_DOUT, swno.d(1));
349 PORT MAP (SPW_RED_DOUT, swno.d(1));
339 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
350 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_RED_SOUT, swno.s(1));
351 PORT MAP (SPW_RED_SOUT, swno.s(1));
341
352
342 -- GRSPW PHY
353 -- GRSPW PHY
343 --spw1_input: if CFG_SPW_GRSPW = 1 generate
354 --spw1_input: if CFG_SPW_GRSPW = 1 generate
344 spw_inputloop : FOR j IN 0 TO 1 GENERATE
355 spw_inputloop : FOR j IN 0 TO 1 GENERATE
345 spw_phy0 : grspw_phy
356 spw_phy0 : grspw_phy
346 GENERIC MAP(
357 GENERIC MAP(
347 tech => apa3e,
358 tech => apa3e,
348 rxclkbuftype => 1,
359 rxclkbuftype => 1,
349 scantest => 0)
360 scantest => 0)
350 PORT MAP(
361 PORT MAP(
351 rxrst => swno.rxrst,
362 rxrst => swno.rxrst,
352 di => dtmp(j),
363 di => dtmp(j),
353 si => stmp(j),
364 si => stmp(j),
354 rxclko => spw_rxclk(j),
365 rxclko => spw_rxclk(j),
355 do => swni.d(j),
366 do => swni.d(j),
356 ndo => swni.nd(j*5+4 DOWNTO j*5),
367 ndo => swni.nd(j*5+4 DOWNTO j*5),
357 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
368 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
358 END GENERATE spw_inputloop;
369 END GENERATE spw_inputloop;
359
370
360 -- SPW core
371 -- SPW core
361 sw0 : grspwm GENERIC MAP(
372 sw0 : grspwm GENERIC MAP(
362 tech => apa3e,
373 tech => apa3e,
363 hindex => 1,
374 hindex => 1,
364 pindex => 5,
375 pindex => 5,
365 paddr => 5,
376 paddr => 5,
366 pirq => 11,
377 pirq => 11,
367 sysfreq => 25000, -- CPU_FREQ
378 sysfreq => 25000, -- CPU_FREQ
368 rmap => 1,
379 rmap => 1,
369 rmapcrc => 1,
380 rmapcrc => 1,
370 fifosize1 => 16,
381 fifosize1 => 16,
371 fifosize2 => 16,
382 fifosize2 => 16,
372 rxclkbuftype => 1,
383 rxclkbuftype => 1,
373 rxunaligned => 0,
384 rxunaligned => 0,
374 rmapbufs => 4,
385 rmapbufs => 4,
375 ft => 0,
386 ft => 0,
376 netlist => 0,
387 netlist => 0,
377 ports => 2,
388 ports => 2,
378 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
389 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
379 memtech => apa3e,
390 memtech => apa3e,
380 destkey => 2,
391 destkey => 2,
381 spwcore => 1
392 spwcore => 1
382 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
393 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
383 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
394 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
384 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
395 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
385 )
396 )
386 PORT MAP(reset, clk_25, spw_rxclk(0),
397 PORT MAP(reset, clk_25, spw_rxclk(0),
387 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
398 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
388 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
399 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
389 swni, swno);
400 swni, swno);
390
401
391 swni.tickin <= '0';
402 swni.tickin <= '0';
392 swni.rmapen <= '1';
403 swni.rmapen <= '1';
393 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
404 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
394 swni.tickinraw <= '0';
405 swni.tickinraw <= '0';
395 swni.timein <= (OTHERS => '0');
406 swni.timein <= (OTHERS => '0');
396 swni.dcrstval <= (OTHERS => '0');
407 swni.dcrstval <= (OTHERS => '0');
397 swni.timerrstval <= (OTHERS => '0');
408 swni.timerrstval <= (OTHERS => '0');
398
409
399 -------------------------------------------------------------------------------
410 -------------------------------------------------------------------------------
400 -- LFR ------------------------------------------------------------------------
411 -- LFR ------------------------------------------------------------------------
401 -------------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
402 lpp_lfr_1 : lpp_lfr
413 lpp_lfr_1 : lpp_lfr
403 GENERIC MAP (
414 GENERIC MAP (
404 Mem_use => use_RAM,
415 Mem_use => use_RAM,
405 nb_data_by_buffer_size => 32,
416 nb_data_by_buffer_size => 32,
406 nb_word_by_buffer_size => 30,
417 nb_word_by_buffer_size => 30,
407 nb_snapshot_param_size => 32,
418 nb_snapshot_param_size => 32,
408 delta_vector_size => 32,
419 delta_vector_size => 32,
409 delta_vector_size_f0_2 => 7, -- log2(96)
420 delta_vector_size_f0_2 => 7, -- log2(96)
410 pindex => 15,
421 pindex => 15,
411 paddr => 15,
422 paddr => 15,
412 pmask => 16#fff#,
423 pmask => 16#fff#,
413 pirq_ms => 6,
424 pirq_ms => 6,
414 pirq_wfp => 14,
425 pirq_wfp => 14,
415 hindex => 2,
426 hindex => 2,
416 top_lfr_version => X"0000000B")
427 top_lfr_version => X"00000C") -- aa.bb.cc version
417 PORT MAP (
428 PORT MAP (
418 clk => clk_25,
429 clk => clk_25,
419 rstn => reset,
430 rstn => reset,
420 sample_B => sample(2 DOWNTO 0),
431 sample_B => sample(2 DOWNTO 0),
421 sample_E => sample(7 DOWNTO 3),
432 sample_E => sample(7 DOWNTO 3),
422 sample_val => sample_val,
433 sample_val => sample_val,
423 apbi => apbi_ext,
434 apbi => apbi_ext,
424 apbo => apbo_ext(15),
435 apbo => apbo_ext(15),
425 ahbi => ahbi_m_ext,
436 ahbi => ahbi_m_ext,
426 ahbo => ahbo_m_ext(2),
437 ahbo => ahbo_m_ext(2),
427 coarse_time => coarse_time,
438 coarse_time => coarse_time,
428 fine_time => fine_time,
439 fine_time => fine_time,
429 data_shaping_BW => bias_fail_sw_sig);
440 data_shaping_BW => bias_fail_sw_sig);
430
441
431 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
432 GENERIC MAP(
443 GENERIC MAP(
433 ChannelCount => 8,
444 ChannelCount => 8,
434 SampleNbBits => 14,
445 SampleNbBits => 14,
435 ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
446 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
436 ncycle_cnv => 500) -- 49 152 000 / 98304
447 ncycle_cnv => 250) -- 49 152 000 / 98304 /2
437 PORT MAP (
448 PORT MAP (
438 -- CONV
449 -- CONV
439 cnv_clk => clk_49,
450 cnv_clk => clk_24,
440 cnv_rstn => reset,
451 cnv_rstn => reset,
441 cnv => ADC_nCS_sig,
452 cnv => ADC_nCS_sig,
442 -- DATA
453 -- DATA
443 clk => clk_25,
454 clk => clk_25,
444 rstn => reset,
455 rstn => reset,
445 sck => ADC_CLK_sig,
456 sck => ADC_CLK_sig,
446 sdo => ADC_SDO_sig,
457 sdo => ADC_SDO_sig,
447 -- SAMPLE
458 -- SAMPLE
448 sample => sample,
459 sample => sample,
449 sample_val => sample_val);
460 sample_val => sample_val);
450
461
451 IO10 <= ADC_SDO_sig(5);
462 IO10 <= ADC_SDO_sig(5);
452 IO9 <= ADC_SDO_sig(4);
463 IO9 <= ADC_SDO_sig(4);
453 IO8 <= ADC_SDO_sig(3);
464 IO8 <= ADC_SDO_sig(3);
454
465
455 ADC_nCS <= ADC_nCS_sig;
466 ADC_nCS <= ADC_nCS_sig;
456 ADC_CLK <= ADC_CLK_sig;
467 ADC_CLK <= ADC_CLK_sig;
457 ADC_SDO_sig <= ADC_SDO;
468 ADC_SDO_sig <= ADC_SDO;
458
469
459 ----------------------------------------------------------------------
470 ----------------------------------------------------------------------
460 --- GPIO -----------------------------------------------------------
471 --- GPIO -----------------------------------------------------------
461 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
462
473
463 grgpio0 : grgpio
474 grgpio0 : grgpio
464 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
465 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
466
477
467 pio_pad_0 : iopad
478 pio_pad_0 : iopad
468 GENERIC MAP (tech => CFG_PADTECH)
479 GENERIC MAP (tech => CFG_PADTECH)
469 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
470 pio_pad_1 : iopad
481 pio_pad_1 : iopad
471 GENERIC MAP (tech => CFG_PADTECH)
482 GENERIC MAP (tech => CFG_PADTECH)
472 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
473 pio_pad_2 : iopad
484 pio_pad_2 : iopad
474 GENERIC MAP (tech => CFG_PADTECH)
485 GENERIC MAP (tech => CFG_PADTECH)
475 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
476 pio_pad_3 : iopad
487 pio_pad_3 : iopad
477 GENERIC MAP (tech => CFG_PADTECH)
488 GENERIC MAP (tech => CFG_PADTECH)
478 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
479 pio_pad_4 : iopad
490 pio_pad_4 : iopad
480 GENERIC MAP (tech => CFG_PADTECH)
491 GENERIC MAP (tech => CFG_PADTECH)
481 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
482 pio_pad_5 : iopad
493 pio_pad_5 : iopad
483 GENERIC MAP (tech => CFG_PADTECH)
494 GENERIC MAP (tech => CFG_PADTECH)
484 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
485 pio_pad_6 : iopad
496 pio_pad_6 : iopad
486 GENERIC MAP (tech => CFG_PADTECH)
497 GENERIC MAP (tech => CFG_PADTECH)
487 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
488 pio_pad_7 : iopad
499 pio_pad_7 : iopad
489 GENERIC MAP (tech => CFG_PADTECH)
500 GENERIC MAP (tech => CFG_PADTECH)
490 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
491
502
492 END beh;
503 END beh;
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1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
31
31
32 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
33
33
34 GENERIC(
34 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
39 );
39 nb_wait_pediod : INTEGER := 375
40
40 );
41 PORT (
41
42 clk25MHz : IN STD_LOGIC; --! Clock
42 PORT (
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
43 clk25MHz : IN STD_LOGIC; --! Clock
44 resetn : IN STD_LOGIC; --! Reset
44 clk49_152MHz : IN STD_LOGIC; --! secondary clock
45
45 resetn : IN STD_LOGIC; --! Reset
46 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
46
47 apbi : IN apb_slv_in_type; --! APB slave input signals
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 apbo : OUT apb_slv_out_type; --! APB slave output signals
48 apbi : IN apb_slv_in_type; --! APB slave input signals
49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
51 );
51 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52
52 );
53 END apb_lfr_time_management;
53
54
54 END apb_lfr_time_management;
55 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
55
56
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57 CONSTANT REVISION : INTEGER := 1;
57
58 CONSTANT pconfig : apb_config_type := (
58 CONSTANT REVISION : INTEGER := 1;
59 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
59 CONSTANT pconfig : apb_config_type := (
60 1 => apb_iobar(paddr, pmask)
60 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
61 );
61 1 => apb_iobar(paddr, pmask)
62
62 );
63 TYPE apb_lfr_time_management_Reg IS RECORD
63
64 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 TYPE apb_lfr_time_management_Reg IS RECORD
65 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
67 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 END RECORD;
68 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
69
69 END RECORD;
70 SIGNAL r : apb_lfr_time_management_Reg;
70
71 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 SIGNAL r : apb_lfr_time_management_Reg;
72 SIGNAL force_tick : STD_LOGIC;
72 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL previous_force_tick : STD_LOGIC;
73 SIGNAL force_tick : STD_LOGIC;
74 SIGNAL soft_tick : STD_LOGIC;
74 SIGNAL previous_force_tick : STD_LOGIC;
75
75 SIGNAL soft_tick : STD_LOGIC;
76 SIGNAL irq1 : STD_LOGIC;
76
77 SIGNAL irq2 : STD_LOGIC;
77 SIGNAL irq1 : STD_LOGIC;
78
78 SIGNAL irq2 : STD_LOGIC;
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
79
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 SIGNAL coarsetime_reg_updated : STD_LOGIC;
81
81 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
82 SIGNAL coarse_time_new : STD_LOGIC;
82
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
83 SIGNAL coarse_time_new : STD_LOGIC;
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL coarse_time_new_49 : STD_LOGIC;
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 SIGNAL fine_time_new : STD_LOGIC;
87
88 SIGNAL fine_time_new_temp : STD_LOGIC;
88 SIGNAL fine_time_new : STD_LOGIC;
89 SIGNAL fine_time_new_49 : STD_LOGIC;
89 SIGNAL fine_time_new_temp : STD_LOGIC;
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 SIGNAL fine_time_new_49 : STD_LOGIC;
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL tick : STD_LOGIC;
92 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 SIGNAL new_timecode : STD_LOGIC;
93 SIGNAL tick : STD_LOGIC;
94 SIGNAL new_coarsetime : STD_LOGIC;
94 SIGNAL new_timecode : STD_LOGIC;
95
95 SIGNAL new_coarsetime : STD_LOGIC;
96 BEGIN
96
97 -----------------------------------------------------------------------------
97 BEGIN
98 -- TODO
98 -----------------------------------------------------------------------------
99 -- IRQ 1 & 2
99 -- TODO
100 -----------------------------------------------------------------------------
100 -- IRQ 1 & 2
101 irq2 <= '0';
101 -----------------------------------------------------------------------------
102 irq1 <= '0';
102 irq2 <= '0';
103
103 irq1 <= '0';
104
104
105 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
105
106 --irq1_gen : IF I = pirq GENERATE
106 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
107 apbo.pirq(pirq) <= irq1;
107 --irq1_gen : IF I = pirq GENERATE
108 --END GENERATE irq1_gen;
108 apbo.pirq(pirq) <= irq1;
109 --irq2_gen : IF I = pirq+1 GENERATE
109 --END GENERATE irq1_gen;
110 apbo.pirq(pirq+1) <= irq2;
110 --irq2_gen : IF I = pirq+1 GENERATE
111 -- END GENERATE irq2_gen;
111 apbo.pirq(pirq+1) <= irq2;
112 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
112 -- END GENERATE irq2_gen;
113 -- apbo.pirq(I) <= '0';
113 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
114 -- END GENERATE others_irq;
114 -- apbo.pirq(I) <= '0';
115 --END GENERATE all_irq_gen;
115 -- END GENERATE others_irq;
116
116 --END GENERATE all_irq_gen;
117 PROCESS(resetn, clk25MHz)
117
118 BEGIN
118 PROCESS(resetn, clk25MHz)
119
119 BEGIN
120 IF resetn = '0' THEN
120
121 Rdata <= (OTHERS => '0');
121 IF resetn = '0' THEN
122 r.coarse_time_load <= x"80000000";
122 Rdata <= (OTHERS => '0');
123 r.ctrl <= x"00000000";
123 r.coarse_time_load <= x"80000000";
124 force_tick <= '0';
124 r.ctrl <= x"00000000";
125 previous_force_tick <= '0';
125 force_tick <= '0';
126 soft_tick <= '0';
126 previous_force_tick <= '0';
127
127 soft_tick <= '0';
128 coarsetime_reg_updated <= '0';
128
129
129 coarsetime_reg_updated <= '0';
130 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
130
131 coarsetime_reg_updated <= '0';
131 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
132
132 coarsetime_reg_updated <= '0';
133 force_tick <= r.ctrl(0);
133
134 previous_force_tick <= force_tick;
134 force_tick <= r.ctrl(0);
135 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
135 previous_force_tick <= force_tick;
136 soft_tick <= '1';
136 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
137 ELSE
137 soft_tick <= '1';
138 soft_tick <= '0';
138 ELSE
139 END IF;
139 soft_tick <= '0';
140
140 END IF;
141 --APB Write OP
141
142 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
142 --APB Write OP
143 CASE apbi.paddr(7 DOWNTO 2) IS
143 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
144 WHEN "000000" =>
144 CASE apbi.paddr(7 DOWNTO 2) IS
145 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
145 WHEN "000000" =>
146 WHEN "000001" =>
146 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
147 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
147 WHEN "000001" =>
148 coarsetime_reg_updated <= '1';
148 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
149 WHEN OTHERS =>
149 coarsetime_reg_updated <= '1';
150 END CASE;
150 WHEN OTHERS =>
151 ELSIF r.ctrl(0) = '1' THEN
151 END CASE;
152 r.ctrl(0) <= '0';
152 ELSIF r.ctrl(0) = '1' THEN
153 END IF;
153 r.ctrl(0) <= '0';
154
154 END IF;
155 --APB READ OP
155
156 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
156 --APB READ OP
157 CASE apbi.paddr(7 DOWNTO 2) IS
157 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
158 WHEN "000000" =>
158 CASE apbi.paddr(7 DOWNTO 2) IS
159 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
159 WHEN "000000" =>
160 WHEN "000001" =>
160 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
161 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
161 WHEN "000001" =>
162 WHEN "000010" =>
162 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
163 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
163 WHEN "000010" =>
164 WHEN "000011" =>
164 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
165 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
165 WHEN "000011" =>
166 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
166 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
167 WHEN OTHERS =>
167 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
168 Rdata(31 DOWNTO 0) <= x"00000000";
168 WHEN OTHERS =>
169 END CASE;
169 Rdata(31 DOWNTO 0) <= x"00000000";
170 END IF;
170 END CASE;
171
171 END IF;
172 END IF;
172
173 END PROCESS;
173 END IF;
174
174 END PROCESS;
175 apbo.prdata <= Rdata;
175
176 apbo.pconfig <= pconfig;
176 apbo.prdata <= Rdata;
177 apbo.pindex <= pindex;
177 apbo.pconfig <= pconfig;
178
178 apbo.pindex <= pindex;
179 coarse_time <= r.coarse_time;
179
180 fine_time <= r.fine_time;
180 coarse_time <= r.coarse_time;
181 -----------------------------------------------------------------------------
181 fine_time <= r.fine_time;
182
182 -----------------------------------------------------------------------------
183 coarsetime_reg <= r.coarse_time_load;
183
184 r.coarse_time <= coarse_time_s;
184 coarsetime_reg <= r.coarse_time_load;
185 r.fine_time <= fine_time_s;
185 r.coarse_time <= coarse_time_s;
186 -----------------------------------------------------------------------------
186 r.fine_time <= fine_time_s;
187 -- IN coarsetime_reg_updated
187 -----------------------------------------------------------------------------
188 -- IN coarsetime_reg
188 -- IN coarsetime_reg_updated
189
189 -- IN coarsetime_reg
190 -- OUT coarse_time_s -- ok
190
191 -- OUT fine_time_s -- ok
191 -- OUT coarse_time_s -- ok
192 -----------------------------------------------------------------------------
192 -- OUT fine_time_s -- ok
193
193 -----------------------------------------------------------------------------
194 tick <= grspw_tick OR soft_tick;
194
195
195 tick <= grspw_tick OR soft_tick;
196 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
196
197 GENERIC MAP (
197 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
198 NB_FF_OF_SYNC => 2)
198 GENERIC MAP (
199 PORT MAP (
199 NB_FF_OF_SYNC => 2)
200 clk_in => clk25MHz,
200 PORT MAP (
201 clk_out => clk49_152MHz,
201 clk_in => clk25MHz,
202 rstn => resetn,
202 clk_out => clk49_152MHz,
203 sin => tick,
203 rstn => resetn,
204 sout => new_timecode);
204 sin => tick,
205
205 sout => new_timecode);
206 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
206
207 GENERIC MAP (
207 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
208 NB_FF_OF_SYNC => 2)
208 GENERIC MAP (
209 PORT MAP (
209 NB_FF_OF_SYNC => 2)
210 clk_in => clk25MHz,
210 PORT MAP (
211 clk_out => clk49_152MHz,
211 clk_in => clk25MHz,
212 rstn => resetn,
212 clk_out => clk49_152MHz,
213 sin => coarsetime_reg_updated,
213 rstn => resetn,
214 sout => new_coarsetime);
214 sin => coarsetime_reg_updated,
215
215 sout => new_coarsetime);
216 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
216
217 -- GENERIC MAP (
217 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
218 -- NB_FF_OF_SYNC => 2)
218 -- GENERIC MAP (
219 -- PORT MAP (
219 -- NB_FF_OF_SYNC => 2)
220 -- clk_in => clk49_152MHz,
220 -- PORT MAP (
221 -- clk_out => clk25MHz,
221 -- clk_in => clk49_152MHz,
222 -- rstn => resetn,
222 -- clk_out => clk25MHz,
223 -- sin => 9,
223 -- rstn => resetn,
224 -- sout => );
224 -- sin => 9,
225
225 -- sout => );
226 SYNC_FF_1: SYNC_FF
226
227 GENERIC MAP (
227 SYNC_FF_1: SYNC_FF
228 NB_FF_OF_SYNC => 2)
228 GENERIC MAP (
229 PORT MAP (
229 NB_FF_OF_SYNC => 2)
230 clk => clk25MHz,
230 PORT MAP (
231 rstn => resetn,
231 clk => clk25MHz,
232 A => fine_time_new_49,
232 rstn => resetn,
233 A_sync => fine_time_new_temp);
233 A => fine_time_new_49,
234
234 A_sync => fine_time_new_temp);
235 lpp_front_detection_1: lpp_front_detection
235
236 PORT MAP (
236 lpp_front_detection_1: lpp_front_detection
237 clk => clk25MHz,
237 PORT MAP (
238 rstn => resetn,
238 clk => clk25MHz,
239 sin => fine_time_new_temp,
239 rstn => resetn,
240 sout => fine_time_new);
240 sin => fine_time_new_temp,
241
241 sout => fine_time_new);
242 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
242
243 GENERIC MAP (
243 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
244 NB_FF_OF_SYNC => 2)
244 GENERIC MAP (
245 PORT MAP (
245 NB_FF_OF_SYNC => 2)
246 clk_in => clk49_152MHz,
246 PORT MAP (
247 clk_out => clk25MHz,
247 clk_in => clk49_152MHz,
248 rstn => resetn,
248 clk_out => clk25MHz,
249 sin => coarse_time_new_49,
249 rstn => resetn,
250 sout => coarse_time_new);
250 sin => coarse_time_new_49,
251
251 sout => coarse_time_new);
252 PROCESS (clk25MHz, resetn)
252
253 BEGIN -- PROCESS
253 PROCESS (clk25MHz, resetn)
254 IF resetn = '0' THEN -- asynchronous reset (active low)
254 BEGIN -- PROCESS
255 fine_time_s <= (OTHERS => '0');
255 IF resetn = '0' THEN -- asynchronous reset (active low)
256 coarse_time_s <= (OTHERS => '0');
256 fine_time_s <= (OTHERS => '0');
257 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
257 coarse_time_s <= (OTHERS => '0');
258 IF fine_time_new = '1' THEN
258 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
259 fine_time_s <= fine_time_49;
259 IF fine_time_new = '1' THEN
260 END IF;
260 fine_time_s <= fine_time_49;
261 IF coarse_time_new = '1' THEN
261 END IF;
262 coarse_time_s <= coarse_time_49;
262 IF coarse_time_new = '1' THEN
263 END IF;
263 coarse_time_s <= coarse_time_49;
264 END IF;
264 END IF;
265 END PROCESS;
265 END IF;
266
266 END PROCESS;
267 -----------------------------------------------------------------------------
267
268 -- LFR_TIME_MANAGMENT
268 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
269 -- LFR_TIME_MANAGMENT
270 lfr_time_management_1 : lfr_time_management
270 -----------------------------------------------------------------------------
271 GENERIC MAP (
271 lfr_time_management_1 : lfr_time_management
272 nb_time_code_missing_limit => 60)
272 GENERIC MAP (
273 PORT MAP (
273 nb_time_code_missing_limit => 60,
274 clk => clk49_152MHz,
274 nb_wait_pediod => 375)
275 rstn => resetn,
275 PORT MAP (
276
276 clk => clk49_152MHz,
277 new_timecode => new_timecode,
277 rstn => resetn,
278 new_coarsetime => new_coarsetime,
278
279 coarsetime_reg => coarsetime_reg,
279 new_timecode => new_timecode,
280
280 new_coarsetime => new_coarsetime,
281 fine_time => fine_time_49,
281 coarsetime_reg => coarsetime_reg,
282 fine_time_new => fine_time_new_49,
282
283 coarse_time => coarse_time_49,
283 fine_time => fine_time_49,
284 coarse_time_new => coarse_time_new_49);
284 fine_time_new => fine_time_new_49,
285
285 coarse_time => coarse_time_49,
286 END Behavioral;
286 coarse_time_new => coarse_time_new_49);
287
288 END Behavioral; No newline at end of file
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@@ -1,111 +1,112
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:14:05 07/02/2012
5 -- Create Date: 11:14:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lfr_time_management - Behavioral
7 -- Module Name: lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.lpp_lfr_time_management.ALL;
24 USE lpp.lpp_lfr_time_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 nb_time_code_missing_limit : INTEGER := 60
28 nb_time_code_missing_limit : INTEGER := 60;
29 nb_wait_pediod : INTEGER := 375
29 );
30 );
30 PORT (
31 PORT (
31 clk : IN STD_LOGIC;
32 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
33
34
34 new_timecode : IN STD_LOGIC; -- transition signal information
35 new_timecode : IN STD_LOGIC; -- transition signal information
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37
38
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time_new : OUT STD_LOGIC;
40 fine_time_new : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 coarse_time_new : OUT STD_LOGIC
42 coarse_time_new : OUT STD_LOGIC
42 );
43 );
43 END lfr_time_management;
44 END lfr_time_management;
44
45
45 ARCHITECTURE Behavioral OF lfr_time_management IS
46 ARCHITECTURE Behavioral OF lfr_time_management IS
46
47
47 SIGNAL counter_clear : STD_LOGIC;
48 SIGNAL counter_clear : STD_LOGIC;
48 SIGNAL counter_full : STD_LOGIC;
49 SIGNAL counter_full : STD_LOGIC;
49
50
50 SIGNAL nb_time_code_missing : INTEGER;
51 SIGNAL nb_time_code_missing : INTEGER;
51 SIGNAL coarse_time_s : INTEGER;
52 SIGNAL coarse_time_s : INTEGER;
52
53
53 SIGNAL new_coarsetime_s : STD_LOGIC;
54 SIGNAL new_coarsetime_s : STD_LOGIC;
54
55
55 BEGIN
56 BEGIN
56
57
57 lpp_counter_1 : lpp_counter
58 lpp_counter_1 : lpp_counter
58 GENERIC MAP (
59 GENERIC MAP (
59 nb_wait_period => 750,
60 nb_wait_period => 750,
60 nb_bit_of_data => 16)
61 nb_bit_of_data => 16)
61 PORT MAP (
62 PORT MAP (
62 clk => clk,
63 clk => clk,
63 rstn => rstn,
64 rstn => rstn,
64 clear => counter_clear,
65 clear => counter_clear,
65 full => counter_full,
66 full => counter_full,
66 data => fine_time,
67 data => fine_time,
67 new_data => fine_time_new);
68 new_data => fine_time_new);
68
69
69 PROCESS (clk, rstn)
70 PROCESS (clk, rstn)
70 BEGIN -- PROCESS
71 BEGIN -- PROCESS
71 IF rstn = '0' THEN -- asynchronous reset (active low)
72 IF rstn = '0' THEN -- asynchronous reset (active low)
72 nb_time_code_missing <= 0;
73 nb_time_code_missing <= 0;
73 counter_clear <= '0';
74 counter_clear <= '0';
74 coarse_time_s <= 0;
75 coarse_time_s <= 0;
75 coarse_time_new <= '0';
76 coarse_time_new <= '0';
76 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
77 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
77 IF new_coarsetime = '1' THEN
78 IF new_coarsetime = '1' THEN
78 new_coarsetime_s <= '1';
79 new_coarsetime_s <= '1';
79 ELSIF new_timecode = '1' THEN
80 ELSIF new_timecode = '1' THEN
80 new_coarsetime_s <= '0';
81 new_coarsetime_s <= '0';
81 END IF;
82 END IF;
82
83
83 IF new_timecode = '1' THEN
84 IF new_timecode = '1' THEN
84 coarse_time_new <= '1';
85 coarse_time_new <= '1';
85 IF new_coarsetime_s = '1' THEN
86 IF new_coarsetime_s = '1' THEN
86 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
87 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
87 ELSE
88 ELSE
88 coarse_time_s <= coarse_time_s + 1;
89 coarse_time_s <= coarse_time_s + 1;
89 END IF;
90 END IF;
90 nb_time_code_missing <= 0;
91 nb_time_code_missing <= 0;
91 counter_clear <= '1';
92 counter_clear <= '1';
92 ELSE
93 ELSE
93 coarse_time_new <= '0';
94 coarse_time_new <= '0';
94 counter_clear <= '0';
95 counter_clear <= '0';
95 IF counter_full = '1' THEN
96 IF counter_full = '1' THEN
96 coarse_time_new <= '1';
97 coarse_time_new <= '1';
97 coarse_time_s <= coarse_time_s + 1;
98 coarse_time_s <= coarse_time_s + 1;
98 IF nb_time_code_missing = nb_time_code_missing_limit THEN
99 IF nb_time_code_missing = nb_time_code_missing_limit THEN
99 nb_time_code_missing <= nb_time_code_missing_limit;
100 nb_time_code_missing <= nb_time_code_missing_limit;
100 ELSE
101 ELSE
101 nb_time_code_missing <= nb_time_code_missing + 1;
102 nb_time_code_missing <= nb_time_code_missing + 1;
102 END IF;
103 END IF;
103 END IF;
104 END IF;
104 END IF;
105 END IF;
105 END IF;
106 END IF;
106 END PROCESS;
107 END PROCESS;
107
108
108 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
109 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
109 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
110 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
110
111
111 END Behavioral;
112 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,81 +1,83
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 13:04:01 07/02/2012
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26
26
27 PACKAGE lpp_lfr_time_management IS
27 PACKAGE lpp_lfr_time_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_TIME_MANAGEMENT
31
31
32 COMPONENT apb_lfr_time_management IS
32 COMPONENT apb_lfr_time_management IS
33 GENERIC(
33 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
34 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0
37 pirq : INTEGER := 0;
38 nb_wait_pediod : INTEGER := 375
38 );
39 );
39 PORT (
40 PORT (
40 clk25MHz : IN STD_LOGIC; --! Clock
41 clk25MHz : IN STD_LOGIC; --! Clock
41 clk49_152MHz : IN STD_LOGIC; --! secondary clock
42 clk49_152MHz : IN STD_LOGIC; --! secondary clock
42 resetn : IN STD_LOGIC; --! Reset
43 resetn : IN STD_LOGIC; --! Reset
43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
44 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
44 apbi : IN apb_slv_in_type; --! APB slave input signals
45 apbi : IN apb_slv_in_type; --! APB slave input signals
45 apbo : OUT apb_slv_out_type; --! APB slave output signals
46 apbo : OUT apb_slv_out_type; --! APB slave output signals
46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
47 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
48 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
48 );
49 );
49 END COMPONENT;
50 END COMPONENT;
50
51
51 COMPONENT lfr_time_management
52 COMPONENT lfr_time_management
52 GENERIC (
53 GENERIC (
53 nb_time_code_missing_limit : INTEGER);
54 nb_time_code_missing_limit : INTEGER;
55 nb_wait_pediod : INTEGER := 375);
54 PORT (
56 PORT (
55 clk : IN STD_LOGIC;
57 clk : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
57 new_timecode : IN STD_LOGIC;
59 new_timecode : IN STD_LOGIC;
58 new_coarsetime : IN STD_LOGIC;
60 new_coarsetime : IN STD_LOGIC;
59 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
61 fine_time_new : OUT STD_LOGIC;
63 fine_time_new : OUT STD_LOGIC;
62 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 coarse_time_new : OUT STD_LOGIC
65 coarse_time_new : OUT STD_LOGIC
64 );
66 );
65 END COMPONENT;
67 END COMPONENT;
66
68
67 COMPONENT lpp_counter
69 COMPONENT lpp_counter
68 GENERIC (
70 GENERIC (
69 nb_wait_period : INTEGER;
71 nb_wait_period : INTEGER;
70 nb_bit_of_data : INTEGER);
72 nb_bit_of_data : INTEGER);
71 PORT (
73 PORT (
72 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
73 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
74 clear : IN STD_LOGIC;
76 clear : IN STD_LOGIC;
75 full : OUT STD_LOGIC;
77 full : OUT STD_LOGIC;
76 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
78 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
77 new_data : OUT STD_LOGIC );
79 new_data : OUT STD_LOGIC );
78 END COMPONENT;
80 END COMPONENT;
79
81
80 END lpp_lfr_time_management;
82 END lpp_lfr_time_management;
81
83
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