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Divide clk49 by 2 before sending to time_managment and adc_driver.
pellion -
r293:97140aa08ede JC
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@@ -44,7 +44,7 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
46
46
47 ENTITY testbench IS
47 ENTITY testbenc h IS
48 END;
48 END;
49
49
50 ARCHITECTURE behav OF testbench IS
50 ARCHITECTURE behav OF testbench IS
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@@ -115,6 +115,7 END MINI_LFR_top;
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -169,6 +170,8 ARCHITECTURE beh OF MINI_LFR_top IS
169
170
170 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171
172
173 -----------------------------------------------------------------------------
174
172 BEGIN -- beh
175 BEGIN -- beh
173
176
174 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
@@ -189,6 +192,13 BEGIN -- beh
189 END IF;
192 END IF;
190 END PROCESS;
193 END PROCESS;
191
194
195 PROCESS(clk_49)
196 BEGIN
197 IF clk_49'EVENT AND clk_49 = '1' THEN
198 clk_24 <= NOT clk_24;
199 END IF;
200 END PROCESS;
201
192 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
193
203
194 PROCESS (clk_25, reset)
204 PROCESS (clk_25, reset)
@@ -226,11 +236,11 BEGIN -- beh
226 END IF;
236 END IF;
227 END PROCESS;
237 END PROCESS;
228
238
229 PROCESS (clk_49, reset)
239 PROCESS (clk_24, reset)
230 BEGIN -- PROCESS
240 BEGIN -- PROCESS
231 IF reset = '0' THEN -- asynchronous reset (active low)
241 IF reset = '0' THEN -- asynchronous reset (active low)
232 I00_s <= '0';
242 I00_s <= '0';
233 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
234 I00_s <= NOT I00_s;
244 I00_s <= NOT I00_s;
235 END IF;
245 END IF;
236 END PROCESS;
246 END PROCESS;
@@ -299,10 +309,11 BEGIN -- beh
299 pindex => 6,
309 pindex => 6,
300 paddr => 6,
310 paddr => 6,
301 pmask => 16#fff#,
311 pmask => 16#fff#,
302 pirq => 12)
312 pirq => 12,
313 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
303 PORT MAP (
314 PORT MAP (
304 clk25MHz => clk_25,
315 clk25MHz => clk_25,
305 clk49_152MHz => clk_49,
316 clk49_152MHz => clk_24, -- 49.152MHz/2
306 resetn => reset,
317 resetn => reset,
307 grspw_tick => swno.tickout,
318 grspw_tick => swno.tickout,
308 apbi => apbi_ext,
319 apbi => apbi_ext,
@@ -413,7 +424,7 BEGIN -- beh
413 pirq_ms => 6,
424 pirq_ms => 6,
414 pirq_wfp => 14,
425 pirq_wfp => 14,
415 hindex => 2,
426 hindex => 2,
416 top_lfr_version => X"0000000B")
427 top_lfr_version => X"00000C") -- aa.bb.cc version
417 PORT MAP (
428 PORT MAP (
418 clk => clk_25,
429 clk => clk_25,
419 rstn => reset,
430 rstn => reset,
@@ -432,11 +443,11 BEGIN -- beh
432 GENERIC MAP(
443 GENERIC MAP(
433 ChannelCount => 8,
444 ChannelCount => 8,
434 SampleNbBits => 14,
445 SampleNbBits => 14,
435 ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63
446 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
436 ncycle_cnv => 500) -- 49 152 000 / 98304
447 ncycle_cnv => 250) -- 49 152 000 / 98304 /2
437 PORT MAP (
448 PORT MAP (
438 -- CONV
449 -- CONV
439 cnv_clk => clk_49,
450 cnv_clk => clk_24,
440 cnv_rstn => reset,
451 cnv_rstn => reset,
441 cnv => ADC_nCS_sig,
452 cnv => ADC_nCS_sig,
442 -- DATA
453 -- DATA
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@@ -1,286 +1,288
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
31
31
32 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
33
33
34 GENERIC(
34 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
39 );
39 nb_wait_pediod : INTEGER := 375
40
40 );
41 PORT (
41
42 clk25MHz : IN STD_LOGIC; --! Clock
42 PORT (
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
43 clk25MHz : IN STD_LOGIC; --! Clock
44 resetn : IN STD_LOGIC; --! Reset
44 clk49_152MHz : IN STD_LOGIC; --! secondary clock
45
45 resetn : IN STD_LOGIC; --! Reset
46 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
46
47 apbi : IN apb_slv_in_type; --! APB slave input signals
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 apbo : OUT apb_slv_out_type; --! APB slave output signals
48 apbi : IN apb_slv_in_type; --! APB slave input signals
49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
51 );
51 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52
52 );
53 END apb_lfr_time_management;
53
54
54 END apb_lfr_time_management;
55 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
55
56
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57 CONSTANT REVISION : INTEGER := 1;
57
58 CONSTANT pconfig : apb_config_type := (
58 CONSTANT REVISION : INTEGER := 1;
59 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
59 CONSTANT pconfig : apb_config_type := (
60 1 => apb_iobar(paddr, pmask)
60 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
61 );
61 1 => apb_iobar(paddr, pmask)
62
62 );
63 TYPE apb_lfr_time_management_Reg IS RECORD
63
64 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 TYPE apb_lfr_time_management_Reg IS RECORD
65 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
67 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 END RECORD;
68 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
69
69 END RECORD;
70 SIGNAL r : apb_lfr_time_management_Reg;
70
71 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 SIGNAL r : apb_lfr_time_management_Reg;
72 SIGNAL force_tick : STD_LOGIC;
72 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL previous_force_tick : STD_LOGIC;
73 SIGNAL force_tick : STD_LOGIC;
74 SIGNAL soft_tick : STD_LOGIC;
74 SIGNAL previous_force_tick : STD_LOGIC;
75
75 SIGNAL soft_tick : STD_LOGIC;
76 SIGNAL irq1 : STD_LOGIC;
76
77 SIGNAL irq2 : STD_LOGIC;
77 SIGNAL irq1 : STD_LOGIC;
78
78 SIGNAL irq2 : STD_LOGIC;
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
79
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
80 SIGNAL coarsetime_reg_updated : STD_LOGIC;
81
81 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
82 SIGNAL coarse_time_new : STD_LOGIC;
82
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
83 SIGNAL coarse_time_new : STD_LOGIC;
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL coarse_time_new_49 : STD_LOGIC;
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 SIGNAL fine_time_new : STD_LOGIC;
87
88 SIGNAL fine_time_new_temp : STD_LOGIC;
88 SIGNAL fine_time_new : STD_LOGIC;
89 SIGNAL fine_time_new_49 : STD_LOGIC;
89 SIGNAL fine_time_new_temp : STD_LOGIC;
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 SIGNAL fine_time_new_49 : STD_LOGIC;
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL tick : STD_LOGIC;
92 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 SIGNAL new_timecode : STD_LOGIC;
93 SIGNAL tick : STD_LOGIC;
94 SIGNAL new_coarsetime : STD_LOGIC;
94 SIGNAL new_timecode : STD_LOGIC;
95
95 SIGNAL new_coarsetime : STD_LOGIC;
96 BEGIN
96
97 -----------------------------------------------------------------------------
97 BEGIN
98 -- TODO
98 -----------------------------------------------------------------------------
99 -- IRQ 1 & 2
99 -- TODO
100 -----------------------------------------------------------------------------
100 -- IRQ 1 & 2
101 irq2 <= '0';
101 -----------------------------------------------------------------------------
102 irq1 <= '0';
102 irq2 <= '0';
103
103 irq1 <= '0';
104
104
105 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
105
106 --irq1_gen : IF I = pirq GENERATE
106 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
107 apbo.pirq(pirq) <= irq1;
107 --irq1_gen : IF I = pirq GENERATE
108 --END GENERATE irq1_gen;
108 apbo.pirq(pirq) <= irq1;
109 --irq2_gen : IF I = pirq+1 GENERATE
109 --END GENERATE irq1_gen;
110 apbo.pirq(pirq+1) <= irq2;
110 --irq2_gen : IF I = pirq+1 GENERATE
111 -- END GENERATE irq2_gen;
111 apbo.pirq(pirq+1) <= irq2;
112 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
112 -- END GENERATE irq2_gen;
113 -- apbo.pirq(I) <= '0';
113 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
114 -- END GENERATE others_irq;
114 -- apbo.pirq(I) <= '0';
115 --END GENERATE all_irq_gen;
115 -- END GENERATE others_irq;
116
116 --END GENERATE all_irq_gen;
117 PROCESS(resetn, clk25MHz)
117
118 BEGIN
118 PROCESS(resetn, clk25MHz)
119
119 BEGIN
120 IF resetn = '0' THEN
120
121 Rdata <= (OTHERS => '0');
121 IF resetn = '0' THEN
122 r.coarse_time_load <= x"80000000";
122 Rdata <= (OTHERS => '0');
123 r.ctrl <= x"00000000";
123 r.coarse_time_load <= x"80000000";
124 force_tick <= '0';
124 r.ctrl <= x"00000000";
125 previous_force_tick <= '0';
125 force_tick <= '0';
126 soft_tick <= '0';
126 previous_force_tick <= '0';
127
127 soft_tick <= '0';
128 coarsetime_reg_updated <= '0';
128
129
129 coarsetime_reg_updated <= '0';
130 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
130
131 coarsetime_reg_updated <= '0';
131 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
132
132 coarsetime_reg_updated <= '0';
133 force_tick <= r.ctrl(0);
133
134 previous_force_tick <= force_tick;
134 force_tick <= r.ctrl(0);
135 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
135 previous_force_tick <= force_tick;
136 soft_tick <= '1';
136 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
137 ELSE
137 soft_tick <= '1';
138 soft_tick <= '0';
138 ELSE
139 END IF;
139 soft_tick <= '0';
140
140 END IF;
141 --APB Write OP
141
142 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
142 --APB Write OP
143 CASE apbi.paddr(7 DOWNTO 2) IS
143 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
144 WHEN "000000" =>
144 CASE apbi.paddr(7 DOWNTO 2) IS
145 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
145 WHEN "000000" =>
146 WHEN "000001" =>
146 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
147 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
147 WHEN "000001" =>
148 coarsetime_reg_updated <= '1';
148 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
149 WHEN OTHERS =>
149 coarsetime_reg_updated <= '1';
150 END CASE;
150 WHEN OTHERS =>
151 ELSIF r.ctrl(0) = '1' THEN
151 END CASE;
152 r.ctrl(0) <= '0';
152 ELSIF r.ctrl(0) = '1' THEN
153 END IF;
153 r.ctrl(0) <= '0';
154
154 END IF;
155 --APB READ OP
155
156 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
156 --APB READ OP
157 CASE apbi.paddr(7 DOWNTO 2) IS
157 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
158 WHEN "000000" =>
158 CASE apbi.paddr(7 DOWNTO 2) IS
159 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
159 WHEN "000000" =>
160 WHEN "000001" =>
160 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
161 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
161 WHEN "000001" =>
162 WHEN "000010" =>
162 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
163 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
163 WHEN "000010" =>
164 WHEN "000011" =>
164 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
165 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
165 WHEN "000011" =>
166 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
166 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
167 WHEN OTHERS =>
167 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
168 Rdata(31 DOWNTO 0) <= x"00000000";
168 WHEN OTHERS =>
169 END CASE;
169 Rdata(31 DOWNTO 0) <= x"00000000";
170 END IF;
170 END CASE;
171
171 END IF;
172 END IF;
172
173 END PROCESS;
173 END IF;
174
174 END PROCESS;
175 apbo.prdata <= Rdata;
175
176 apbo.pconfig <= pconfig;
176 apbo.prdata <= Rdata;
177 apbo.pindex <= pindex;
177 apbo.pconfig <= pconfig;
178
178 apbo.pindex <= pindex;
179 coarse_time <= r.coarse_time;
179
180 fine_time <= r.fine_time;
180 coarse_time <= r.coarse_time;
181 -----------------------------------------------------------------------------
181 fine_time <= r.fine_time;
182
182 -----------------------------------------------------------------------------
183 coarsetime_reg <= r.coarse_time_load;
183
184 r.coarse_time <= coarse_time_s;
184 coarsetime_reg <= r.coarse_time_load;
185 r.fine_time <= fine_time_s;
185 r.coarse_time <= coarse_time_s;
186 -----------------------------------------------------------------------------
186 r.fine_time <= fine_time_s;
187 -- IN coarsetime_reg_updated
187 -----------------------------------------------------------------------------
188 -- IN coarsetime_reg
188 -- IN coarsetime_reg_updated
189
189 -- IN coarsetime_reg
190 -- OUT coarse_time_s -- ok
190
191 -- OUT fine_time_s -- ok
191 -- OUT coarse_time_s -- ok
192 -----------------------------------------------------------------------------
192 -- OUT fine_time_s -- ok
193
193 -----------------------------------------------------------------------------
194 tick <= grspw_tick OR soft_tick;
194
195
195 tick <= grspw_tick OR soft_tick;
196 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
196
197 GENERIC MAP (
197 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
198 NB_FF_OF_SYNC => 2)
198 GENERIC MAP (
199 PORT MAP (
199 NB_FF_OF_SYNC => 2)
200 clk_in => clk25MHz,
200 PORT MAP (
201 clk_out => clk49_152MHz,
201 clk_in => clk25MHz,
202 rstn => resetn,
202 clk_out => clk49_152MHz,
203 sin => tick,
203 rstn => resetn,
204 sout => new_timecode);
204 sin => tick,
205
205 sout => new_timecode);
206 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
206
207 GENERIC MAP (
207 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
208 NB_FF_OF_SYNC => 2)
208 GENERIC MAP (
209 PORT MAP (
209 NB_FF_OF_SYNC => 2)
210 clk_in => clk25MHz,
210 PORT MAP (
211 clk_out => clk49_152MHz,
211 clk_in => clk25MHz,
212 rstn => resetn,
212 clk_out => clk49_152MHz,
213 sin => coarsetime_reg_updated,
213 rstn => resetn,
214 sout => new_coarsetime);
214 sin => coarsetime_reg_updated,
215
215 sout => new_coarsetime);
216 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
216
217 -- GENERIC MAP (
217 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
218 -- NB_FF_OF_SYNC => 2)
218 -- GENERIC MAP (
219 -- PORT MAP (
219 -- NB_FF_OF_SYNC => 2)
220 -- clk_in => clk49_152MHz,
220 -- PORT MAP (
221 -- clk_out => clk25MHz,
221 -- clk_in => clk49_152MHz,
222 -- rstn => resetn,
222 -- clk_out => clk25MHz,
223 -- sin => 9,
223 -- rstn => resetn,
224 -- sout => );
224 -- sin => 9,
225
225 -- sout => );
226 SYNC_FF_1: SYNC_FF
226
227 GENERIC MAP (
227 SYNC_FF_1: SYNC_FF
228 NB_FF_OF_SYNC => 2)
228 GENERIC MAP (
229 PORT MAP (
229 NB_FF_OF_SYNC => 2)
230 clk => clk25MHz,
230 PORT MAP (
231 rstn => resetn,
231 clk => clk25MHz,
232 A => fine_time_new_49,
232 rstn => resetn,
233 A_sync => fine_time_new_temp);
233 A => fine_time_new_49,
234
234 A_sync => fine_time_new_temp);
235 lpp_front_detection_1: lpp_front_detection
235
236 PORT MAP (
236 lpp_front_detection_1: lpp_front_detection
237 clk => clk25MHz,
237 PORT MAP (
238 rstn => resetn,
238 clk => clk25MHz,
239 sin => fine_time_new_temp,
239 rstn => resetn,
240 sout => fine_time_new);
240 sin => fine_time_new_temp,
241
241 sout => fine_time_new);
242 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
242
243 GENERIC MAP (
243 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
244 NB_FF_OF_SYNC => 2)
244 GENERIC MAP (
245 PORT MAP (
245 NB_FF_OF_SYNC => 2)
246 clk_in => clk49_152MHz,
246 PORT MAP (
247 clk_out => clk25MHz,
247 clk_in => clk49_152MHz,
248 rstn => resetn,
248 clk_out => clk25MHz,
249 sin => coarse_time_new_49,
249 rstn => resetn,
250 sout => coarse_time_new);
250 sin => coarse_time_new_49,
251
251 sout => coarse_time_new);
252 PROCESS (clk25MHz, resetn)
252
253 BEGIN -- PROCESS
253 PROCESS (clk25MHz, resetn)
254 IF resetn = '0' THEN -- asynchronous reset (active low)
254 BEGIN -- PROCESS
255 fine_time_s <= (OTHERS => '0');
255 IF resetn = '0' THEN -- asynchronous reset (active low)
256 coarse_time_s <= (OTHERS => '0');
256 fine_time_s <= (OTHERS => '0');
257 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
257 coarse_time_s <= (OTHERS => '0');
258 IF fine_time_new = '1' THEN
258 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
259 fine_time_s <= fine_time_49;
259 IF fine_time_new = '1' THEN
260 END IF;
260 fine_time_s <= fine_time_49;
261 IF coarse_time_new = '1' THEN
261 END IF;
262 coarse_time_s <= coarse_time_49;
262 IF coarse_time_new = '1' THEN
263 END IF;
263 coarse_time_s <= coarse_time_49;
264 END IF;
264 END IF;
265 END PROCESS;
265 END IF;
266
266 END PROCESS;
267 -----------------------------------------------------------------------------
267
268 -- LFR_TIME_MANAGMENT
268 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
269 -- LFR_TIME_MANAGMENT
270 lfr_time_management_1 : lfr_time_management
270 -----------------------------------------------------------------------------
271 GENERIC MAP (
271 lfr_time_management_1 : lfr_time_management
272 nb_time_code_missing_limit => 60)
272 GENERIC MAP (
273 PORT MAP (
273 nb_time_code_missing_limit => 60,
274 clk => clk49_152MHz,
274 nb_wait_pediod => 375)
275 rstn => resetn,
275 PORT MAP (
276
276 clk => clk49_152MHz,
277 new_timecode => new_timecode,
277 rstn => resetn,
278 new_coarsetime => new_coarsetime,
278
279 coarsetime_reg => coarsetime_reg,
279 new_timecode => new_timecode,
280
280 new_coarsetime => new_coarsetime,
281 fine_time => fine_time_49,
281 coarsetime_reg => coarsetime_reg,
282 fine_time_new => fine_time_new_49,
282
283 coarse_time => coarse_time_49,
283 fine_time => fine_time_49,
284 coarse_time_new => coarse_time_new_49);
284 fine_time_new => fine_time_new_49,
285
285 coarse_time => coarse_time_49,
286 END Behavioral;
286 coarse_time_new => coarse_time_new_49);
287
288 END Behavioral; No newline at end of file
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@@ -25,7 +25,8 USE lpp.lpp_lfr_time_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 nb_time_code_missing_limit : INTEGER := 60
28 nb_time_code_missing_limit : INTEGER := 60;
29 nb_wait_pediod : INTEGER := 375
29 );
30 );
30 PORT (
31 PORT (
31 clk : IN STD_LOGIC;
32 clk : IN STD_LOGIC;
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@@ -34,7 +34,8 PACKAGE lpp_lfr_time_management IS
34 pindex : INTEGER := 0; --! APB slave index
34 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0
37 pirq : INTEGER := 0;
38 nb_wait_pediod : INTEGER := 375
38 );
39 );
39 PORT (
40 PORT (
40 clk25MHz : IN STD_LOGIC; --! Clock
41 clk25MHz : IN STD_LOGIC; --! Clock
@@ -50,7 +51,8 PACKAGE lpp_lfr_time_management IS
50
51
51 COMPONENT lfr_time_management
52 COMPONENT lfr_time_management
52 GENERIC (
53 GENERIC (
53 nb_time_code_missing_limit : INTEGER);
54 nb_time_code_missing_limit : INTEGER;
55 nb_wait_pediod : INTEGER := 375);
54 PORT (
56 PORT (
55 clk : IN STD_LOGIC;
57 clk : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
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