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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 #VHDLSIMFILES=testbench.vhd
17 #SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39
40 FILESKIP = i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48
49 ################## project specific targets ##########################
50
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44 use lpp.lpp_cna.all;
45
46
47 ENTITY leon3mp IS
48 GENERIC (
49 fabtech : INTEGER := CFG_FABTECH;
50 memtech : INTEGER := CFG_MEMTECH;
51 padtech : INTEGER := CFG_PADTECH;
52 clktech : INTEGER := CFG_CLKTECH;
53 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
54 dbguart : INTEGER := CFG_DUART; -- Print UART on console
55 pclow : INTEGER := CFG_PCLOW
56 );
57 PORT (
58 clk100MHz : IN STD_ULOGIC;
59 clk49_152MHz : IN STD_ULOGIC;
60 reset : IN STD_ULOGIC;
61
62 errorn : OUT STD_ULOGIC;
63
64 -- UART AHB ---------------------------------------------------------------
65 ahbrxd : IN STD_ULOGIC; -- DSU rx data
66 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
67
68 -- UART APB ---------------------------------------------------------------
69 urxd1 : IN STD_ULOGIC; -- UART1 rx data
70 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
71
72 -- RAM --------------------------------------------------------------------
73 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
74 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 nSRAM_BE0 : OUT STD_LOGIC;
76 nSRAM_BE1 : OUT STD_LOGIC;
77 nSRAM_BE2 : OUT STD_LOGIC;
78 nSRAM_BE3 : OUT STD_LOGIC;
79 nSRAM_WE : OUT STD_LOGIC;
80 nSRAM_CE : OUT STD_LOGIC;
81 nSRAM_OE : OUT STD_LOGIC;
82
83 -- SPW --------------------------------------------------------------------
84 spw1_din : IN STD_LOGIC; -- PLE
85 spw1_sin : IN STD_LOGIC; -- PLE
86 spw1_dout : OUT STD_LOGIC; -- PLE
87 spw1_sout : OUT STD_LOGIC; -- PLE
88
89 spw2_din : IN STD_LOGIC; -- JCPE --TODO
90 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
91 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
92 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
93
94 -- ADC --------------------------------------------------------------------
95 bias_fail_sw : OUT STD_LOGIC;
96 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
97 ADC_smpclk : OUT STD_LOGIC;
98 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
99
100 -- SCM CALIBRATION --------------------------------------------------------
101 SCM_CAL_EN : OUT STD_LOGIC; -- TODO A6
102 SCM_CAL_DIN : OUT STD_LOGIC; -- TODO A4
103 SCM_CAL_SCLK : OUT STD_LOGIC; -- TODO A5
104 SCM_CAL_nSYNC : OUT STD_LOGIC; -- TODO B6
105
106 ---------------------------------------------------------------------------
107 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
108 );
109 END;
110
111 ARCHITECTURE Behavioral OF leon3mp IS
112
113 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
114 -- CFG_GRETH+CFG_AHB_JTAG;
115 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
116 CFG_AHB_UART
117 +2;
118 -- 1 is for the SpaceWire module grspw, which is a master
119 -- 1 is for the LFR
120
121 CONSTANT maxahbm : INTEGER := maxahbmsp;
122
123 --Clk & Rst gοΏ½nοΏ½
124 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL resetnl : STD_ULOGIC;
127 SIGNAL clk2x : STD_ULOGIC;
128 SIGNAL lclk2x : STD_ULOGIC;
129 SIGNAL lclk25MHz : STD_ULOGIC;
130 SIGNAL lclk50MHz : STD_ULOGIC;
131 SIGNAL lclk100MHz : STD_ULOGIC;
132 SIGNAL clkm : STD_ULOGIC;
133 SIGNAL rstn : STD_ULOGIC;
134 SIGNAL rstraw : STD_ULOGIC;
135 SIGNAL pciclk : STD_ULOGIC;
136 SIGNAL sdclkl : STD_ULOGIC;
137 SIGNAL cgi : clkgen_in_type;
138 SIGNAL cgo : clkgen_out_type;
139 --- AHB / APB
140 SIGNAL apbi : apb_slv_in_type;
141 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
142 SIGNAL ahbsi : ahb_slv_in_type;
143 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
144 SIGNAL ahbmi : ahb_mst_in_type;
145 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
146 --UART
147 SIGNAL ahbuarti : uart_in_type;
148 SIGNAL ahbuarto : uart_out_type;
149 SIGNAL apbuarti : uart_in_type;
150 SIGNAL apbuarto : uart_out_type;
151 --MEM CTRLR
152 SIGNAL memi : memory_in_type;
153 SIGNAL memo : memory_out_type;
154 SIGNAL wpo : wprot_out_type;
155 SIGNAL sdo : sdram_out_type;
156 SIGNAL ramcs : STD_ULOGIC;
157 --IRQ
158 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
159 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
160 --Timer
161 SIGNAL gpti : gptimer_in_type;
162 SIGNAL gpto : gptimer_out_type;
163 --GPIO
164 SIGNAL gpioi : gpio_in_type;
165 SIGNAL gpioo : gpio_out_type;
166 --DSU
167 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
168 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
169 SIGNAL dsui : dsu_in_type;
170 SIGNAL dsuo : dsu_out_type;
171
172 ---------------------------------------------------------------------
173 --- AJOUT TEST ------------------------Signaux----------------------
174 ---------------------------------------------------------------------
175
176 ---------------------------------------------------------------------
177 CONSTANT IOAEN : INTEGER := CFG_CAN;
178 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
179
180 -- time management signal
181 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
183
184 -- Spacewire signals
185 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
186 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
187 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
188 SIGNAL spw_rxtxclk : STD_ULOGIC;
189 SIGNAL spw_rxclkn : STD_ULOGIC;
190 SIGNAL spw_clk : STD_LOGIC;
191 SIGNAL swni : grspw_in_type; -- PLE
192 SIGNAL swno : grspw_out_type; -- PLE
193 SIGNAL clkmn : STD_ULOGIC; -- PLE
194 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
195
196 -- AD Converter RHF1401
197 SIGNAL sample : Samples14v(7 DOWNTO 0);
198 SIGNAL sample_val : STD_LOGIC;
199 -----------------------------------------------------------------------------
200 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
201
202 BEGIN
203
204
205 ----------------------------------------------------------------------
206 --- Reset and Clock generation -------------------------------------
207 ----------------------------------------------------------------------
208
209 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
210 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
211
212 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
213
214
215 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
216
217 clkgen0 : clkgen -- clock generator
218 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
219 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
220 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
221
222 PROCESS(lclk100MHz)
223 BEGIN
224 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
225 lclk50MHz <= NOT lclk50MHz;
226 END IF;
227 END PROCESS;
228
229 PROCESS(lclk50MHz)
230 BEGIN
231 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
232 lclk25MHz <= NOT lclk25MHz;
233 END IF;
234 END PROCESS;
235
236 lclk2x <= lclk50MHz;
237 spw_clk <= lclk50MHz;
238
239 ----------------------------------------------------------------------
240 --- LEON3 processor / DSU / IRQ ------------------------------------
241 ----------------------------------------------------------------------
242
243 l3 : IF CFG_LEON3 = 1 GENERATE
244 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
245 u0 : leon3s -- LEON3 processor
246 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
247 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
248 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
249 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
250 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
251 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
252 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
253 irqi(i), irqo(i), dbgi(i), dbgo(i));
254 END GENERATE;
255 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
256
257 dsugen : IF CFG_DSU = 1 GENERATE
258 dsu0 : dsu3 -- LEON3 Debug Support Unit
259 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
260 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
261 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
262 dsui.enable <= '1';
263 dsui.break <= '0';
264 led(2) <= dsuo.active;
265 END GENERATE;
266 END GENERATE;
267
268 nodsu : IF CFG_DSU = 0 GENERATE
269 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
270 END GENERATE;
271
272 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
273 irqctrl0 : irqmp -- interrupt controller
274 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
275 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
276 END GENERATE;
277 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
278 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
279 irqi(i).irl <= "0000";
280 END GENERATE;
281 apbo(2) <= apb_none;
282 END GENERATE;
283
284 ----------------------------------------------------------------------
285 --- Memory controllers ---------------------------------------------
286 ----------------------------------------------------------------------
287 memctrlr : mctrl GENERIC MAP (
288 hindex => 0,
289 pindex => 0,
290 paddr => 0,
291 srbanks => 1
292 )
293 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
294
295 memi.brdyn <= '1';
296 memi.bexcn <= '1';
297 memi.writen <= '1';
298 memi.wrn <= "1111";
299 memi.bwidth <= "10";
300
301 bdr : FOR i IN 0 TO 3 GENERATE
302 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
303 PORT MAP (
304 data(31-i*8 DOWNTO 24-i*8),
305 memo.data(31-i*8 DOWNTO 24-i*8),
306 memo.bdrive(i),
307 memi.data(31-i*8 DOWNTO 24-i*8));
308 END GENERATE;
309
310 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
311 PORT MAP (address, memo.address(21 DOWNTO 2));
312
313 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
314 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
315 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
316 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
317 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
318 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
319 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
320
321 ----------------------------------------------------------------------
322 --- AHB CONTROLLER -------------------------------------------------
323 ----------------------------------------------------------------------
324 ahb0 : ahbctrl -- AHB arbiter/multiplexer
325 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
326 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
327 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
328 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
329
330 ----------------------------------------------------------------------
331 --- AHB UART -------------------------------------------------------
332 ----------------------------------------------------------------------
333 dcomgen : IF CFG_AHB_UART = 1 GENERATE
334 dcom0 : ahbuart
335 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
336 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
337 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
338 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
339 led(0) <= NOT ahbuarti.rxd;
340 led(1) <= NOT ahbuarto.txd;
341 END GENERATE;
342 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
343
344 ----------------------------------------------------------------------
345 --- APB Bridge -----------------------------------------------------
346 ----------------------------------------------------------------------
347 apb0 : apbctrl -- AHB/APB bridge
348 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
349 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
350
351 ----------------------------------------------------------------------
352 --- GPT Timer ------------------------------------------------------
353 ----------------------------------------------------------------------
354 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
355 timer0 : gptimer -- timer unit
356 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
357 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
358 nbits => CFG_GPT_TW)
359 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
360 gpti.dhalt <= dsuo.tstop;
361 gpti.extclk <= '0';
362 END GENERATE;
363 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
364
365
366 ----------------------------------------------------------------------
367 --- APB UART -------------------------------------------------------
368 ----------------------------------------------------------------------
369 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
370 uart1 : apbuart -- UART 1
371 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
372 fifosize => CFG_UART1_FIFO)
373 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
374 apbuarti.rxd <= urxd1;
375 apbuarti.extclk <= '0';
376 utxd1 <= apbuarto.txd;
377 apbuarti.ctsn <= '0';
378 END GENERATE;
379 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
380
381 -------------------------------------------------------------------------------
382 -- APB_DAC --------------------------------------------------------------------
383 -------------------------------------------------------------------------------
384 APB_DAC_1: APB_DAC
385 GENERIC MAP (
386 pindex => 14,
387 paddr => 14,
388 pmask => 16#fff#,
389 pirq => 13,
390 abits => 8)
391 PORT MAP (
392 clk => clk,
393 rst => rst,
394 apbi => apbi,
395 apbo => apbo(14),
396
397 Cal_EN => SCM_CAL_EN,
398 SYNC => SCM_CAL_nSYNC,
399 SCLK => SCM_CAL_SCLK,
400 DATA => SCM_CAL_DIN);
401
402 -------------------------------------------------------------------------------
403 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
404 -------------------------------------------------------------------------------
405 apb_lfr_time_management_1: apb_lfr_time_management
406 GENERIC MAP (
407 pindex => 6,
408 paddr => 6,
409 pmask => 16#fff#,
410 pirq => 12)
411 PORT MAP (
412 clk25MHz => clkm,
413 clk49_152MHz => clk49_152MHz,
414 resetn => rstn,
415 grspw_tick => swno.tickout,
416 apbi => apbi,
417 apbo => apbo(6),
418 coarse_time => coarse_time,
419 fine_time => fine_time);
420
421 -----------------------------------------------------------------------
422 --- SpaceWire --------------------------------------------------------
423 -----------------------------------------------------------------------
424
425 spw_rxtxclk <= spw_clk;
426 spw_rxclkn <= NOT spw_rxtxclk;
427
428 -- PADS for SPW1
429 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
430 PORT MAP (spw1_din, dtmp(0));
431 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
432 PORT MAP (spw1_sin, stmp(0));
433 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
434 PORT MAP (spw1_dout, swno.d(0));
435 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
436 PORT MAP (spw1_sout, swno.s(0));
437 -- PADS FOR SPW2
438 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
439 PORT MAP (spw2_din, dtmp(1));
440 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
441 PORT MAP (spw2_sin, stmp(1));
442 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
443 PORT MAP (spw2_dout, swno.d(1));
444 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
445 PORT MAP (spw2_sout, swno.s(1));
446
447 -- GRSPW PHY
448 --spw1_input: if CFG_SPW_GRSPW = 1 generate
449 spw_inputloop : FOR j IN 0 TO 1 GENERATE
450 spw_phy0 : grspw_phy
451 GENERIC MAP(
452 tech => fabtech,
453 rxclkbuftype => 1,
454 scantest => 0)
455 PORT MAP(
456 rxrst => swno.rxrst,
457 di => dtmp(j),
458 si => stmp(j),
459 rxclko => spw_rxclk(j),
460 do => swni.d(j),
461 ndo => swni.nd(j*5+4 DOWNTO j*5),
462 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
463 END GENERATE spw_inputloop;
464
465 -- SPW core
466 sw0 : grspwm
467 GENERIC MAP(
468 tech => apa3e,
469 hindex => 1,
470 pindex => 5,
471 paddr => 5,
472 pirq => 11,
473 sysfreq => 25000, -- CPU_FREQ
474 rmap => 1,
475 rmapcrc => 1,
476 fifosize1 => 16,
477 fifosize2 => 16,
478 rxclkbuftype => 1,
479 rxunaligned => 0,
480 rmapbufs => 4,
481 ft => 0,
482 netlist => 0,
483 ports => 2,
484 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
485 memtech => apa3e,
486 destkey => 2,
487 spwcore => 1
488 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
489 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
490 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
491 )
492 PORT MAP(rstn, clkm, spw_rxclk(0),
493 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
494 ahbmi, ahbmo(1), apbi, apbo(5),
495 swni, swno);
496
497 swni.tickin <= '0';
498 swni.rmapen <= '1';
499 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
500 swni.tickinraw <= '0';
501 swni.timein <= (OTHERS => '0');
502 swni.dcrstval <= (OTHERS => '0');
503 swni.timerrstval <= (OTHERS => '0');
504
505 -------------------------------------------------------------------------------
506 -- LFR
507 -------------------------------------------------------------------------------
508 lpp_lfr_1 : lpp_lfr
509 GENERIC MAP (
510 Mem_use => use_RAM,
511 nb_data_by_buffer_size => 32,
512 nb_word_by_buffer_size => 30,
513 nb_snapshot_param_size => 32,
514 delta_vector_size => 32,
515 delta_vector_size_f0_2 => 7, -- log2(96)
516 pindex => 15,
517 paddr => 15,
518 pmask => 16#fff#,
519 pirq_ms => 6,
520 pirq_wfp => 14,
521 hindex => 2,
522 top_lfr_version => X"00000005")
523 PORT MAP (
524 clk => clkm,
525 rstn => rstn,
526 sample_B => sample(2 DOWNTO 0),
527 sample_E => sample(7 DOWNTO 3),
528 sample_val => sample_val,
529 apbi => apbi,
530 apbo => apbo(15),
531 ahbi => ahbmi,
532 ahbo => ahbmo(2),
533 coarse_time => coarse_time,
534 fine_time => fine_time,
535 data_shaping_BW => bias_fail_sw);
536
537 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
538 GENERIC MAP (
539 ChanelCount => 8,
540 ncycle_cnv_high => 79,
541 ncycle_cnv => 500)
542 PORT MAP (
543 cnv_clk => clk49_152MHz,
544 cnv_rstn => rstn,
545 cnv => ADC_smpclk,
546 clk => clkm,
547 rstn => rstn,
548 ADC_data => ADC_data,
549 ADC_nOE => ADC_OEB_bar_CH,
550 sample => sample,
551 sample_val => sample_val);
552
553 END Behavioral;
Show file before | Show file after | Hide comments
@@ -37,7 +37,8 DIRSKIP = b1553 pcif leon2 leon2ft crypt
37 ./lpp_uart \
37 ./lpp_uart \
38 ./lpp_usb \
38 ./lpp_usb \
39
39
40 FILESKIP = i2cmst.vhd \
40 FILESKIP = lpp_lfr_ms.vhd \
41 i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
Show file before | Show file after | Hide comments
@@ -190,6 +190,15 ARCHITECTURE Behavioral OF leon3mp IS
190 SIGNAL sample_val : STD_LOGIC;
190 SIGNAL sample_val : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
193 -----------------------------------------------------------------------------
194 SIGNAL debug_f0_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
195 SIGNAL debug_f0_data_valid : STD_LOGIC;
196 SIGNAL debug_f1_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
197 SIGNAL debug_f1_data_valid : STD_LOGIC;
198 SIGNAL debug_f2_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
199 SIGNAL debug_f2_data_valid : STD_LOGIC;
200 SIGNAL debug_f3_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
201 SIGNAL debug_f3_data_valid : STD_LOGIC;
193
202
194 BEGIN
203 BEGIN
195
204
@@ -490,7 +499,7 BEGIN
490 pirq_ms => 6,
499 pirq_ms => 6,
491 pirq_wfp => 14,
500 pirq_wfp => 14,
492 hindex => 2,
501 hindex => 2,
493 top_lfr_version => X"00000005")
502 top_lfr_version => X"00000007")
494 PORT MAP (
503 PORT MAP (
495 clk => clkm,
504 clk => clkm,
496 rstn => rstn,
505 rstn => rstn,
@@ -503,7 +512,18 BEGIN
503 ahbo => ahbmo(2),
512 ahbo => ahbmo(2),
504 coarse_time => coarse_time,
513 coarse_time => coarse_time,
505 fine_time => fine_time,
514 fine_time => fine_time,
506 data_shaping_BW => bias_fail_sw);
515 data_shaping_BW => bias_fail_sw,
516
517 -------------------------------------------------------------------------
518 debug_f0_data => debug_f0_data ,
519 debug_f0_data_valid => debug_f0_data_valid,
520 debug_f1_data => debug_f1_data ,
521 debug_f1_data_valid => debug_f1_data_valid,
522 debug_f2_data => debug_f2_data ,
523 debug_f2_data_valid => debug_f2_data_valid,
524 debug_f3_data => debug_f3_data ,
525 debug_f3_data_valid => debug_f3_data_valid
526 );
507
527
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
528 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
509 GENERIC MAP (
529 GENERIC MAP (
Show file before | Show file after | Hide comments
@@ -223,6 +223,24 ARCHITECTURE beh OF lpp_lfr IS
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
225
226 -----------------------------------------------------------------------------
227 -- DEBUG
228 -----------------------------------------------------------------------------
229 --
230 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
231 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
232 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
233 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
234
235 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243
226 BEGIN
244 BEGIN
227
245
228 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
246 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -321,7 +339,26 BEGIN
321 addr_data_f1 => addr_data_f1,
339 addr_data_f1 => addr_data_f1,
322 addr_data_f2 => addr_data_f2,
340 addr_data_f2 => addr_data_f2,
323 addr_data_f3 => addr_data_f3,
341 addr_data_f3 => addr_data_f3,
324 start_date => start_date);
342 start_date => start_date,
343 ---------------------------------------------------------------------------
344 debug_reg0 => debug_reg0,
345 debug_reg1 => debug_reg1,
346 debug_reg2 => debug_reg2,
347 debug_reg3 => debug_reg3,
348 debug_reg4 => debug_reg4,
349 debug_reg5 => debug_reg5,
350 debug_reg6 => debug_reg6,
351 debug_reg7 => debug_reg7);
352
353 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
354 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
355 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
356 -----------------------------------------------------------------------------
357 sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
358 sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
359 sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
360 sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
361
325
362
326 -----------------------------------------------------------------------------
363 -----------------------------------------------------------------------------
327 lpp_waveform_1: lpp_waveform
364 lpp_waveform_1 : lpp_waveform
@@ -368,19 +405,19 BEGIN
368 --f0
405 --f0
369 addr_data_f0 => addr_data_f0,
406 addr_data_f0 => addr_data_f0,
370 data_f0_in_valid => sample_f0_val,
407 data_f0_in_valid => sample_f0_val,
371 data_f0_in => sample_f0_data,
408 data_f0_in => sample_f0_data_debug, -- TODO : debug
372 --f1
409 --f1
373 addr_data_f1 => addr_data_f1,
410 addr_data_f1 => addr_data_f1,
374 data_f1_in_valid => sample_f1_val,
411 data_f1_in_valid => sample_f1_val,
375 data_f1_in => sample_f1_data,
412 data_f1_in => sample_f1_data_debug, -- TODO : debug,
376 --f2
413 --f2
377 addr_data_f2 => addr_data_f2,
414 addr_data_f2 => addr_data_f2,
378 data_f2_in_valid => sample_f2_val,
415 data_f2_in_valid => sample_f2_val,
379 data_f2_in => sample_f2_data,
416 data_f2_in => sample_f2_data_debug, -- TODO : debug,
380 --f3
417 --f3
381 addr_data_f3 => addr_data_f3,
418 addr_data_f3 => addr_data_f3,
382 data_f3_in_valid => sample_f3_val,
419 data_f3_in_valid => sample_f3_val,
383 data_f3_in => sample_f3_data,
420 data_f3_in => sample_f3_data_debug, -- TODO : debug,
384 -- OUTPUT -- DMA interface
421 -- OUTPUT -- DMA interface
385 --f0
422 --f0
386 data_f0_addr_out => data_f0_addr_out_s,
423 data_f0_addr_out => data_f0_addr_out_s,
@@ -435,7 +472,7 BEGIN
435 data_f2_data_out_valid_burst <= '0';
472 data_f2_data_out_valid_burst <= '0';
436 data_f3_data_out_valid <= '0';
473 data_f3_data_out_valid <= '0';
437 data_f3_data_out_valid_burst <= '0';
474 data_f3_data_out_valid_burst <= '0';
438 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
475 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
439 data_f0_data_out_valid <= data_f0_data_out_valid_s;
476 data_f0_data_out_valid <= data_f0_data_out_valid_s;
440 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
477 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
441 data_f1_data_out_valid <= data_f1_data_out_valid_s;
478 data_f1_data_out_valid <= data_f1_data_out_valid_s;
@@ -482,7 +519,7 BEGIN
482 dma_sel <= (OTHERS => '0');
519 dma_sel <= (OTHERS => '0');
483 dma_send <= '0';
520 dma_send <= '0';
484 dma_valid_burst <= '0';
521 dma_valid_burst <= '0';
485 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
522 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
486 -- IF dma_sel = "0000" OR dma_send = '1' THEN
523 -- IF dma_sel = "0000" OR dma_send = '1' THEN
487 IF dma_sel = "0000" OR dma_done = '1' THEN
524 IF dma_sel = "0000" OR dma_done = '1' THEN
488 dma_sel <= dma_rr_grant;
525 dma_sel <= dma_rr_grant;
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@@ -121,7 +121,16 ENTITY lpp_lfr_apbreg IS
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
125 ---------------------------------------------------------------------------
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
125
134
126 ---------------------------------------------------------------------------
135 ---------------------------------------------------------------------------
127 );
136 );
@@ -368,6 +377,15 BEGIN -- beh
368 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
369 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
370 ----------------------------------------------------
379 ----------------------------------------------------
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
388 ----------------------------------------------------
371 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
372 WHEN OTHERS => NULL;
390 WHEN OTHERS => NULL;
373 END CASE;
391 END CASE;
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@@ -178,7 +178,16 PACKAGE lpp_lfr_pkg IS
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
182 ---------------------------------------------------------------------------
183 debug_reg0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 debug_reg7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
182 END COMPONENT;
191 END COMPONENT;
183
192
184 COMPONENT lpp_top_ms
193 COMPONENT lpp_top_ms
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@@ -183,6 +183,7 ARCHITECTURE beh OF lpp_waveform IS
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
186 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
186 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188
189
@@ -322,9 +323,22 BEGIN -- beh
322 data_out(3,I) <= data_f3_out(I);
323 data_out(3,I) <= data_f3_out(I);
323 END GENERATE all_bit_of_data_out;
324 END GENERATE all_bit_of_data_out;
324
325
326 -----------------------------------------------------------------------------
327 -- TODO : debug
328 -----------------------------------------------------------------------------
329 --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
330 -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
331 -- time_out_2(J,I) <= time_out(J)(I);
332 -- END GENERATE all_sample_of_time_out;
333 --END GENERATE all_bit_of_time_out;
334 time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
335 time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
336 time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
337 time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
338
325 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
339 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
326 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
340 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
327 time_out_2(J,I) <= time_out(J)(I);
341 time_out_2(J,I) <= time_out_debug(J)(I);
328 END GENERATE all_sample_of_time_out;
342 END GENERATE all_sample_of_time_out;
329 END GENERATE all_bit_of_time_out;
343 END GENERATE all_bit_of_time_out;
330
344
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