# HG changeset patch # User pellion # Date 2013-11-25 11:15:03 # Node ID 943e2fb08d5322b1f5c4ee814818b634e62558ea # Parent 8311b94bb8604a65f48bf8a90afb08b08fba1c31 temp diff --git a/designs/LFR-em-WaveFormPicker/Makefile b/designs/LFR-em-WaveFormPicker/Makefile --- a/designs/LFR-em-WaveFormPicker/Makefile +++ b/designs/LFR-em-WaveFormPicker/Makefile @@ -37,7 +37,8 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt ./lpp_uart \ ./lpp_usb \ -FILESKIP = i2cmst.vhd \ +FILESKIP = lpp_lfr_ms.vhd \ + i2cmst.vhd \ APB_MULTI_DIODE.vhd \ APB_MULTI_DIODE.vhd \ Top_MatrixSpec.vhd \ diff --git a/designs/LFR-em-WaveFormPicker/leon3mp.vhd b/designs/LFR-em-WaveFormPicker/leon3mp.vhd --- a/designs/LFR-em-WaveFormPicker/leon3mp.vhd +++ b/designs/LFR-em-WaveFormPicker/leon3mp.vhd @@ -190,6 +190,15 @@ ARCHITECTURE Behavioral OF leon3mp IS SIGNAL sample_val : STD_LOGIC; ----------------------------------------------------------------------------- SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL debug_f0_data : STD_LOGIC_VECTOR(95 DOWNTO 0); + SIGNAL debug_f0_data_valid : STD_LOGIC; + SIGNAL debug_f1_data : STD_LOGIC_VECTOR(95 DOWNTO 0); + SIGNAL debug_f1_data_valid : STD_LOGIC; + SIGNAL debug_f2_data : STD_LOGIC_VECTOR(95 DOWNTO 0); + SIGNAL debug_f2_data_valid : STD_LOGIC; + SIGNAL debug_f3_data : STD_LOGIC_VECTOR(95 DOWNTO 0); + SIGNAL debug_f3_data_valid : STD_LOGIC; BEGIN @@ -490,7 +499,7 @@ BEGIN pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00000005") + top_lfr_version => X"00000007") PORT MAP ( clk => clkm, rstn => rstn, @@ -503,7 +512,18 @@ BEGIN ahbo => ahbmo(2), coarse_time => coarse_time, fine_time => fine_time, - data_shaping_BW => bias_fail_sw); + data_shaping_BW => bias_fail_sw, + + ------------------------------------------------------------------------- + debug_f0_data => debug_f0_data , + debug_f0_data_valid => debug_f0_data_valid, + debug_f1_data => debug_f1_data , + debug_f1_data_valid => debug_f1_data_valid, + debug_f2_data => debug_f2_data , + debug_f2_data_valid => debug_f2_data_valid, + debug_f3_data => debug_f3_data , + debug_f3_data_valid => debug_f3_data_valid + ); top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 GENERIC MAP ( diff --git a/designs/LFR-em/.config b/designs/LFR-em/.config new file mode 100644 --- /dev/null +++ b/designs/LFR-em/.config @@ -0,0 +1,288 @@ +# +# Automatically generated make config: don't edit +# + +# +# Synthesis +# +# CONFIG_SYN_INFERRED is not set +# CONFIG_SYN_STRATIX is not set +# CONFIG_SYN_STRATIXII is not set +# CONFIG_SYN_STRATIXIII is not set +# CONFIG_SYN_CYCLONEIII is not set +# CONFIG_SYN_ALTERA is not set +# CONFIG_SYN_AXCEL is not set +# CONFIG_SYN_PROASIC is not set +# CONFIG_SYN_PROASICPLUS is not set +CONFIG_SYN_PROASIC3=y +# CONFIG_SYN_UT025CRH is not set +# CONFIG_SYN_ATC18 is not set +# CONFIG_SYN_ATC18RHA is not set +# CONFIG_SYN_CUSTOM1 is not set +# CONFIG_SYN_EASIC90 is not set +# CONFIG_SYN_IHP25 is not set +# CONFIG_SYN_IHP25RH is not set +# CONFIG_SYN_LATTICE is not set +# CONFIG_SYN_ECLIPSE is not set +# CONFIG_SYN_PEREGRINE is not set +# CONFIG_SYN_RH_LIB18T is not set +# CONFIG_SYN_RHUMC is not set +# CONFIG_SYN_SMIC13 is not set +# CONFIG_SYN_SPARTAN2 is not set +# CONFIG_SYN_SPARTAN3 is not set +# CONFIG_SYN_SPARTAN3E is not set +# CONFIG_SYN_VIRTEX is not set +# CONFIG_SYN_VIRTEXE is not set +# CONFIG_SYN_VIRTEX2 is not set +# CONFIG_SYN_VIRTEX4 is not set +# CONFIG_SYN_VIRTEX5 is not set +# CONFIG_SYN_UMC is not set +# CONFIG_SYN_TSMC90 is not set +# CONFIG_SYN_INFER_RAM is not set +# CONFIG_SYN_INFER_PADS is not set +# CONFIG_SYN_NO_ASYNC is not set +# CONFIG_SYN_SCAN is not set + +# +# Clock generation +# +# CONFIG_CLK_INFERRED is not set +# CONFIG_CLK_HCLKBUF is not set +# CONFIG_CLK_ALTDLL is not set +# CONFIG_CLK_LATDLL is not set +CONFIG_CLK_PRO3PLL=y +# CONFIG_CLK_LIB18T is not set +# CONFIG_CLK_RHUMC is not set +# CONFIG_CLK_CLKDLL is not set +# CONFIG_CLK_DCM is not set +CONFIG_CLK_MUL=2 +CONFIG_CLK_DIV=8 +CONFIG_OCLK_DIV=2 +# CONFIG_PCI_SYSCLK is not set +CONFIG_LEON3=y +CONFIG_PROC_NUM=1 + +# +# Processor +# + +# +# Integer unit +# +CONFIG_IU_NWINDOWS=8 +# CONFIG_IU_V8MULDIV is not set +# CONFIG_IU_SVT is not set +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=0 +# CONFIG_PWD is not set +CONFIG_IU_RSTADDR=00000 + +# +# Floating-point unit +# +# CONFIG_FPU_ENABLE is not set + +# +# Cache system +# +CONFIG_ICACHE_ENABLE=y +CONFIG_ICACHE_ASSO1=y +# CONFIG_ICACHE_ASSO2 is not set +# CONFIG_ICACHE_ASSO3 is not set +# CONFIG_ICACHE_ASSO4 is not set +# CONFIG_ICACHE_SZ1 is not set +# CONFIG_ICACHE_SZ2 is not set +CONFIG_ICACHE_SZ4=y +# CONFIG_ICACHE_SZ8 is not set +# CONFIG_ICACHE_SZ16 is not set +# CONFIG_ICACHE_SZ32 is not set +# CONFIG_ICACHE_SZ64 is not set +# CONFIG_ICACHE_SZ128 is not set +# CONFIG_ICACHE_SZ256 is not set +# CONFIG_ICACHE_LZ16 is not set +CONFIG_ICACHE_LZ32=y +CONFIG_DCACHE_ENABLE=y +CONFIG_DCACHE_ASSO1=y +# CONFIG_DCACHE_ASSO2 is not set +# CONFIG_DCACHE_ASSO3 is not set +# CONFIG_DCACHE_ASSO4 is not set +# CONFIG_DCACHE_SZ1 is not set +# CONFIG_DCACHE_SZ2 is not set +CONFIG_DCACHE_SZ4=y +# CONFIG_DCACHE_SZ8 is not set +# CONFIG_DCACHE_SZ16 is not set +# CONFIG_DCACHE_SZ32 is not set +# CONFIG_DCACHE_SZ64 is not set +# CONFIG_DCACHE_SZ128 is not set +# CONFIG_DCACHE_SZ256 is not set +# CONFIG_DCACHE_LZ16 is not set +CONFIG_DCACHE_LZ32=y +# CONFIG_DCACHE_SNOOP is not set +CONFIG_CACHE_FIXED=0 + +# +# MMU +# +CONFIG_MMU_ENABLE=y +# CONFIG_MMU_COMBINED is not set +CONFIG_MMU_SPLIT=y +# CONFIG_MMU_REPARRAY is not set +CONFIG_MMU_REPINCREMENT=y +# CONFIG_MMU_I2 is not set +# CONFIG_MMU_I4 is not set +CONFIG_MMU_I8=y +# CONFIG_MMU_I16 is not set +# CONFIG_MMU_I32 is not set +# CONFIG_MMU_D2 is not set +# CONFIG_MMU_D4 is not set +CONFIG_MMU_D8=y +# CONFIG_MMU_D16 is not set +# CONFIG_MMU_D32 is not set +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +# CONFIG_MMU_PAGE_8K is not set +# CONFIG_MMU_PAGE_16K is not set +# CONFIG_MMU_PAGE_32K is not set +# CONFIG_MMU_PAGE_PROG is not set + +# +# Debug Support Unit +# +# CONFIG_DSU_ENABLE is not set + +# +# Fault-tolerance +# + +# +# VHDL debug settings +# +# CONFIG_IU_DISAS is not set +# CONFIG_DEBUG_PC32 is not set + +# +# AMBA configuration +# +CONFIG_AHB_DEFMST=0 +CONFIG_AHB_RROBIN=y +# CONFIG_AHB_SPLIT is not set +CONFIG_AHB_IOADDR=FFF +CONFIG_APB_HADDR=800 +# CONFIG_AHB_MON is not set + +# +# Debug Link +# +CONFIG_DSU_UART=y +# CONFIG_DSU_JTAG is not set + +# +# Peripherals +# + +# +# Memory controllers +# + +# +# 8/32-bit PROM/SRAM controller +# +CONFIG_SRCTRL=y +# CONFIG_SRCTRL_8BIT is not set +CONFIG_SRCTRL_PROMWS=3 +CONFIG_SRCTRL_RAMWS=0 +CONFIG_SRCTRL_IOWS=0 +# CONFIG_SRCTRL_RMW is not set +CONFIG_SRCTRL_SRBANKS1=y +# CONFIG_SRCTRL_SRBANKS2 is not set +# CONFIG_SRCTRL_SRBANKS3 is not set +# CONFIG_SRCTRL_SRBANKS4 is not set +# CONFIG_SRCTRL_SRBANKS5 is not set +# CONFIG_SRCTRL_BANKSZ0 is not set +# CONFIG_SRCTRL_BANKSZ1 is not set +# CONFIG_SRCTRL_BANKSZ2 is not set +# CONFIG_SRCTRL_BANKSZ3 is not set +# CONFIG_SRCTRL_BANKSZ4 is not set +# CONFIG_SRCTRL_BANKSZ5 is not set +# CONFIG_SRCTRL_BANKSZ6 is not set +# CONFIG_SRCTRL_BANKSZ7 is not set +# CONFIG_SRCTRL_BANKSZ8 is not set +# CONFIG_SRCTRL_BANKSZ9 is not set +# CONFIG_SRCTRL_BANKSZ10 is not set +# CONFIG_SRCTRL_BANKSZ11 is not set +# CONFIG_SRCTRL_BANKSZ12 is not set +# CONFIG_SRCTRL_BANKSZ13 is not set +CONFIG_SRCTRL_ROMASEL=19 + +# +# Leon2 memory controller +# +CONFIG_MCTRL_LEON2=y +# CONFIG_MCTRL_8BIT is not set +# CONFIG_MCTRL_16BIT is not set +# CONFIG_MCTRL_5CS is not set +# CONFIG_MCTRL_SDRAM is not set + +# +# PC133 SDRAM controller +# +# CONFIG_SDCTRL is not set + +# +# On-chip RAM/ROM +# +# CONFIG_AHBROM_ENABLE is not set +# CONFIG_AHBRAM_ENABLE is not set + +# +# Ethernet +# +# CONFIG_GRETH_ENABLE is not set + +# +# CAN +# +# CONFIG_CAN_ENABLE is not set + +# +# PCI +# +# CONFIG_PCI_SIMPLE_TARGET is not set +# CONFIG_PCI_MASTER_TARGET is not set +# CONFIG_PCI_ARBITER is not set +# CONFIG_PCI_TRACE is not set + +# +# Spacewire +# +# CONFIG_SPW_ENABLE is not set + +# +# UARTs, timers and irq control +# +CONFIG_UART1_ENABLE=y +# CONFIG_UA1_FIFO1 is not set +# CONFIG_UA1_FIFO2 is not set +CONFIG_UA1_FIFO4=y +# CONFIG_UA1_FIFO8 is not set +# CONFIG_UA1_FIFO16 is not set +# CONFIG_UA1_FIFO32 is not set +# CONFIG_UART2_ENABLE is not set +CONFIG_IRQ3_ENABLE=y +# CONFIG_IRQ3_SEC is not set +CONFIG_GPT_ENABLE=y +CONFIG_GPT_NTIM=2 +CONFIG_GPT_SW=8 +CONFIG_GPT_TW=32 +CONFIG_GPT_IRQ=8 +CONFIG_GPT_SEPIRQ=y +CONFIG_GPT_WDOGEN=y +CONFIG_GPT_WDOG=FFFF +CONFIG_GRGPIO_ENABLE=y +CONFIG_GRGPIO_WIDTH=8 +CONFIG_GRGPIO_IMASK=0000 + +# +# VHDL Debugging +# +# CONFIG_DEBUG_UART is not set diff --git a/designs/LFR-em/Makefile b/designs/LFR-em/Makefile new file mode 100644 --- /dev/null +++ b/designs/LFR-em/Makefile @@ -0,0 +1,50 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES=config.vhd leon3mp.vhd +#VHDLSIMFILES=testbench.vhd +#SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/LFR-em/config.vhd b/designs/LFR-em/config.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR-em/config.vhd @@ -0,0 +1,182 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is + + +-- Technology and synthesis options + constant CFG_FABTECH : integer := apa3e; + constant CFG_MEMTECH : integer := apa3e; + constant CFG_PADTECH : integer := inferred; + constant CFG_NOASYNC : integer := 0; + constant CFG_SCAN : integer := 0; + +-- Clock generator + constant CFG_CLKTECH : integer := inferred; + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; + +-- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := (1); + --constant CFG_NWIN : integer := (7); -- PLE + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist + --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE + constant CFG_GRFPUSH : integer := 0; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DFIXED : integer := 16#00F3#; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + constant CFG_DSU : integer := 1; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + constant CFG_LEON3FT_EN : integer := 0; + constant CFG_IUFT_EN : integer := 0; + constant CFG_FPUFT_EN : integer := 0; + constant CFG_RF_ERRINJ : integer := 0; + constant CFG_CACHE_FT_EN : integer := 0; + constant CFG_CACHE_ERRINJ : integer := 0; + constant CFG_LEON3_NETLIST: integer := 0; + constant CFG_DISAS : integer := 0 + 0; + constant CFG_PCLOW : integer := 2; + +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + +-- DSU UART + constant CFG_AHB_UART : integer := 1; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 0; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := 0 + 0; + constant CFG_ETH_BUF : integer := 1; + constant CFG_ETH_IPM : integer := 16#C0A8#; + constant CFG_ETH_IPL : integer := 16#0033#; + constant CFG_ETH_ENM : integer := 16#00007A#; + constant CFG_ETH_ENL : integer := 16#CC0001#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM16BIT : integer := 0; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; + +-- SSRAM controller + constant CFG_SSCTRL : integer := 0; + constant CFG_SSCTRLP16 : integer := 0; + +-- AHB ROM + constant CFG_AHBROMEN : integer := 0; + constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBRODDR : integer := 16#000#; + constant CFG_ROMADDR : integer := 16#000#; + constant CFG_ROMMASK : integer := 16#E00# + 16#000#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := 0; + constant CFG_AHBRSZ : integer := 1; + constant CFG_AHBRADDR : integer := 16#A00#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + constant CFG_GRETH1G : integer := 0; + constant CFG_ETH_FIFO : integer := 8; + +-- CAN 2.0 interface + constant CFG_CAN : integer := 0; + constant CFG_CANIO : integer := 16#0#; + constant CFG_CANIRQ : integer := 0; + constant CFG_CANLOOP : integer := 0; + constant CFG_CAN_SYNCRST : integer := 0; + constant CFG_CANFT : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 1; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := 1; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := 1; + constant CFG_GPT_NTIM : integer := (3); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := 1; + constant CFG_GRGPIO_IMASK : integer := 16#0000#; + constant CFG_GRGPIO_WIDTH : integer := (7); + +-- GRLIB debugging + constant CFG_DUART : integer := 0; + + +end; diff --git a/designs/LFR-em/leon3mp.vhd b/designs/LFR-em/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR-em/leon3mp.vhd @@ -0,0 +1,553 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +use lpp.lpp_cna.all; + + +ENTITY leon3mp IS + GENERIC ( + fabtech : INTEGER := CFG_FABTECH; + memtech : INTEGER := CFG_MEMTECH; + padtech : INTEGER := CFG_PADTECH; + clktech : INTEGER := CFG_CLKTECH; + disas : INTEGER := CFG_DISAS; -- Enable disassembly to console + dbguart : INTEGER := CFG_DUART; -- Print UART on console + pclow : INTEGER := CFG_PCLOW + ); + PORT ( + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- SPW -------------------------------------------------------------------- + spw1_din : IN STD_LOGIC; -- PLE + spw1_sin : IN STD_LOGIC; -- PLE + spw1_dout : OUT STD_LOGIC; -- PLE + spw1_sout : OUT STD_LOGIC; -- PLE + + spw2_din : IN STD_LOGIC; -- JCPE --TODO + spw2_sin : IN STD_LOGIC; -- JCPE --TODO + spw2_dout : OUT STD_LOGIC; -- JCPE --TODO + spw2_sout : OUT STD_LOGIC; -- JCPE --TODO + + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + + -- SCM CALIBRATION -------------------------------------------------------- + SCM_CAL_EN : OUT STD_LOGIC; -- TODO A6 + SCM_CAL_DIN : OUT STD_LOGIC; -- TODO A4 + SCM_CAL_SCLK : OUT STD_LOGIC; -- TODO A5 + SCM_CAL_nSYNC : OUT STD_LOGIC; -- TODO B6 + + --------------------------------------------------------------------------- + led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF leon3mp IS + +--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ +-- CFG_GRETH+CFG_AHB_JTAG; + CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ + CFG_AHB_UART + +2; + -- 1 is for the SpaceWire module grspw, which is a master + -- 1 is for the LFR + + CONSTANT maxahbm : INTEGER := maxahbmsp; + +--Clk & Rst g�n� + SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL resetnl : STD_ULOGIC; + SIGNAL clk2x : STD_ULOGIC; + SIGNAL lclk2x : STD_ULOGIC; + SIGNAL lclk25MHz : STD_ULOGIC; + SIGNAL lclk50MHz : STD_ULOGIC; + SIGNAL lclk100MHz : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; +--- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); +--UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; +--MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + SIGNAL ramcs : STD_ULOGIC; +--IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); +--Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; +--DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- + CONSTANT IOAEN : INTEGER := CFG_CAN; + CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz + +-- time management signal + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; -- PLE + SIGNAL swno : grspw_out_type; -- PLE + SIGNAL clkmn : STD_ULOGIC; -- PLE + SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 + +-- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + + PROCESS(lclk100MHz) + BEGIN + IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN + lclk50MHz <= NOT lclk50MHz; + END IF; + END PROCESS; + + PROCESS(lclk50MHz) + BEGIN + IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN + lclk25MHz <= NOT lclk25MHz; + END IF; + END PROCESS; + + lclk2x <= lclk50MHz; + spw_clk <= lclk50MHz; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + led(2) <= dsuo.active; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + led(0) <= NOT ahbuarti.rxd; + led(1) <= NOT ahbuarto.txd; + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- APB_DAC -------------------------------------------------------------------- +------------------------------------------------------------------------------- + APB_DAC_1: APB_DAC + GENERIC MAP ( + pindex => 14, + paddr => 14, + pmask => 16#fff#, + pirq => 13, + abits => 8) + PORT MAP ( + clk => clk, + rst => rst, + apbi => apbi, + apbo => apbo(14), + + Cal_EN => SCM_CAL_EN, + SYNC => SCM_CAL_nSYNC, + SCLK => SCM_CAL_SCLK, + DATA => SCM_CAL_DIN); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1: apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + pirq => 12) + PORT MAP ( + clk25MHz => clkm, + clk49_152MHz => clk49_152MHz, + resetn => rstn, + grspw_tick => swno.tickout, + apbi => apbi, + apbo => apbo(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sin, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sin, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => fabtech, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm + GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn, clkm, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbmi, ahbmo(1), apbi, apbo(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR +------------------------------------------------------------------------------- + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"00000005") + PORT MAP ( + clk => clkm, + rstn => rstn, + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi, + apbo => apbo(15), + ahbi => ahbmi, + ahbo => ahbmo(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw); + + top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk49_152MHz, + cnv_rstn => rstn, + cnv => ADC_smpclk, + clk => clkm, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -24,58 +24,58 @@ USE GRLIB.DMA2AHB_Package.ALL; ENTITY lpp_lfr IS GENERIC ( - Mem_use : INTEGER := use_RAM; + Mem_use : INTEGER := use_RAM; nb_data_by_buffer_size : INTEGER := 11; nb_word_by_buffer_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 7; + nb_snapshot_param_size : INTEGER := 11; + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 7; - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#; - pirq_ms : INTEGER := 0; - pirq_wfp : INTEGER := 1; + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq_ms : INTEGER := 0; + pirq_wfp : INTEGER := 1; hindex : INTEGER := 2; top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) - + ); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; -- SAMPLE - sample_B : IN Samples14v(2 DOWNTO 0); - sample_E : IN Samples14v(4 DOWNTO 0); + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); sample_val : IN STD_LOGIC; -- APB apbi : IN apb_slv_in_type; apbo : OUT apb_slv_out_type; -- AHB - ahbi : IN AHB_Mst_In_Type; - ahbo : OUT AHB_Mst_Out_Type; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; -- TIME - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo -- data_shaping_BW : OUT STD_LOGIC; --debug - debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f0_data_valid : OUT STD_LOGIC; - debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f1_data_valid : OUT STD_LOGIC; - debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f2_data_valid : OUT STD_LOGIC; - debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC + debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC ); END lpp_lfr; ARCHITECTURE beh OF lpp_lfr IS - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); -- SIGNAL data_shaping_SP0 : STD_LOGIC; SIGNAL data_shaping_SP1 : STD_LOGIC; @@ -91,10 +91,10 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL sample_f2_val : STD_LOGIC; SIGNAL sample_f3_val : STD_LOGIC; -- - SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); -- SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); @@ -122,77 +122,77 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- WFP - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - SIGNAL enable_f0 : STD_LOGIC; - SIGNAL enable_f1 : STD_LOGIC; - SIGNAL enable_f2 : STD_LOGIC; - SIGNAL enable_f3 : STD_LOGIC; - SIGNAL burst_f0 : STD_LOGIC; - SIGNAL burst_f1 : STD_LOGIC; - SIGNAL burst_f2 : STD_LOGIC; - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL run : STD_LOGIC; + SIGNAL run : STD_LOGIC; SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); - SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f0_data_out_valid : STD_LOGIC; - SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f0_data_out_ren : STD_LOGIC; - --f1 - SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f1_data_out_valid : STD_LOGIC; - SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f1_data_out_ren : STD_LOGIC; - --f2 - SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f2_data_out_valid : STD_LOGIC; - SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f2_data_out_ren : STD_LOGIC; - --f3 - SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f3_data_out_valid : STD_LOGIC; - SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; - SIGNAL data_f3_data_out_ren : STD_LOGIC; + SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out_valid : STD_LOGIC; + SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f0_data_out_ren : STD_LOGIC; + --f1 + SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out_valid : STD_LOGIC; + SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f1_data_out_ren : STD_LOGIC; + --f2 + SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out_valid : STD_LOGIC; + SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f2_data_out_ren : STD_LOGIC; + --f3 + SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out_valid : STD_LOGIC; + SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f3_data_out_ren : STD_LOGIC; ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- - SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f0_data_out_valid_s : STD_LOGIC; - SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; - --f1 - SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f1_data_out_valid_s : STD_LOGIC; - SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; - --f2 - SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f2_data_out_valid_s : STD_LOGIC; - SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; - --f3 - SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_f3_data_out_valid_s : STD_LOGIC; - SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; - + SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out_valid_s : STD_LOGIC; + SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; + --f1 + SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out_valid_s : STD_LOGIC; + SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; + --f2 + SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out_valid_s : STD_LOGIC; + SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; + --f3 + SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out_valid_s : STD_LOGIC; + SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; + ----------------------------------------------------------------------------- -- DMA RR ----------------------------------------------------------------------------- @@ -210,28 +210,46 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - + ----------------------------------------------------------------------------- -- DMA ----------------------------------------------------------------------------- SIGNAL dma_send : STD_LOGIC; - SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) SIGNAL dma_done : STD_LOGIC; SIGNAL dma_ren : STD_LOGIC; SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- DEBUG + ----------------------------------------------------------------------------- + -- + SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); - all_channel: FOR i IN 7 DOWNTO 0 GENERATE + all_channel : FOR i IN 7 DOWNTO 0 GENERATE sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); END GENERATE all_channel; - + ----------------------------------------------------------------------------- lpp_lfr_filter_1 : lpp_lfr_filter GENERIC MAP ( @@ -255,7 +273,7 @@ BEGIN sample_f3_wdata => sample_f3_data); ----------------------------------------------------------------------------- - lpp_lfr_apbreg_1: lpp_lfr_apbreg + lpp_lfr_apbreg_1 : lpp_lfr_apbreg GENERIC MAP ( nb_data_by_buffer_size => nb_data_by_buffer_size, nb_word_by_buffer_size => nb_word_by_buffer_size, @@ -321,66 +339,85 @@ BEGIN addr_data_f1 => addr_data_f1, addr_data_f2 => addr_data_f2, addr_data_f3 => addr_data_f3, - start_date => start_date); + start_date => start_date, + --------------------------------------------------------------------------- + debug_reg0 => debug_reg0, + debug_reg1 => debug_reg1, + debug_reg2 => debug_reg2, + debug_reg3 => debug_reg3, + debug_reg4 => debug_reg4, + debug_reg5 => debug_reg5, + debug_reg6 => debug_reg6, + debug_reg7 => debug_reg7); + + debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); + debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); + debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); + ----------------------------------------------------------------------------- + sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug + sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug + sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug + sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug + ----------------------------------------------------------------------------- - lpp_waveform_1: lpp_waveform + lpp_waveform_1 : lpp_waveform GENERIC MAP ( - tech => inferred, - data_size => 6*16, - nb_data_by_buffer_size => nb_data_by_buffer_size, - nb_word_by_buffer_size => nb_word_by_buffer_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_vector_size => delta_vector_size, - delta_vector_size_f0_2 => delta_vector_size_f0_2 + tech => inferred, + data_size => 6*16, + nb_data_by_buffer_size => nb_data_by_buffer_size, + nb_word_by_buffer_size => nb_word_by_buffer_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_vector_size => delta_vector_size, + delta_vector_size_f0_2 => delta_vector_size_f0_2 ) PORT MAP ( - clk => clk, - rstn => rstn, + clk => clk, + rstn => rstn, reg_run => run, - reg_start_date => start_date, + reg_start_date => start_date, reg_delta_snapshot => delta_snapshot, - reg_delta_f0 => delta_f0, + reg_delta_f0 => delta_f0, reg_delta_f0_2 => delta_f0_2, reg_delta_f1 => delta_f1, reg_delta_f2 => delta_f2, - - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - + + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_data_by_buffer => nb_data_by_buffer, nb_word_by_buffer => nb_word_by_buffer, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, - coarse_time => coarse_time, - fine_time => fine_time, + coarse_time => coarse_time, + fine_time => fine_time, --f0 - addr_data_f0 => addr_data_f0, - data_f0_in_valid => sample_f0_val, - data_f0_in => sample_f0_data, + addr_data_f0 => addr_data_f0, + data_f0_in_valid => sample_f0_val, + data_f0_in => sample_f0_data_debug, -- TODO : debug --f1 - addr_data_f1 => addr_data_f1, - data_f1_in_valid => sample_f1_val, - data_f1_in => sample_f1_data, + addr_data_f1 => addr_data_f1, + data_f1_in_valid => sample_f1_val, + data_f1_in => sample_f1_data_debug, -- TODO : debug, --f2 - addr_data_f2 => addr_data_f2, - data_f2_in_valid => sample_f2_val, - data_f2_in => sample_f2_data, + addr_data_f2 => addr_data_f2, + data_f2_in_valid => sample_f2_val, + data_f2_in => sample_f2_data_debug, -- TODO : debug, --f3 - addr_data_f3 => addr_data_f3, - data_f3_in_valid => sample_f3_val, - data_f3_in => sample_f3_data, + addr_data_f3 => addr_data_f3, + data_f3_in_valid => sample_f3_val, + data_f3_in => sample_f3_data_debug, -- TODO : debug, -- OUTPUT -- DMA interface --f0 data_f0_addr_out => data_f0_addr_out_s, @@ -407,16 +444,16 @@ BEGIN data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, data_f3_data_out_ren => data_f3_data_out_ren, - --debug - debug_f0_data => debug_f0_data, - debug_f0_data_valid => debug_f0_data_valid , - debug_f1_data => debug_f1_data , - debug_f1_data_valid => debug_f1_data_valid, - debug_f2_data => debug_f2_data , - debug_f2_data_valid => debug_f2_data_valid , - debug_f3_data => debug_f3_data , - debug_f3_data_valid => debug_f3_data_valid - + --debug + debug_f0_data => debug_f0_data, + debug_f0_data_valid => debug_f0_data_valid , + debug_f1_data => debug_f1_data , + debug_f1_data_valid => debug_f1_data_valid, + debug_f2_data => debug_f2_data , + debug_f2_data_valid => debug_f2_data_valid , + debug_f3_data => debug_f3_data , + debug_f3_data_valid => debug_f3_data_valid + ); @@ -435,23 +472,23 @@ BEGIN data_f2_data_out_valid_burst <= '0'; data_f3_data_out_valid <= '0'; data_f3_data_out_valid_burst <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - data_f0_data_out_valid <= data_f0_data_out_valid_s; - data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; - data_f1_data_out_valid <= data_f1_data_out_valid_s; - data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; - data_f2_data_out_valid <= data_f2_data_out_valid_s; - data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; - data_f3_data_out_valid <= data_f3_data_out_valid_s; - data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + data_f0_data_out_valid <= data_f0_data_out_valid_s; + data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; + data_f1_data_out_valid <= data_f1_data_out_valid_s; + data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; + data_f2_data_out_valid <= data_f2_data_out_valid_s; + data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; + data_f3_data_out_valid <= data_f3_data_out_valid_s; + data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; END IF; END PROCESS; - - data_f0_addr_out <= data_f0_addr_out_s; - data_f1_addr_out <= data_f1_addr_out_s; - data_f2_addr_out <= data_f2_addr_out_s; - data_f3_addr_out <= data_f3_addr_out_s; - + + data_f0_addr_out <= data_f0_addr_out_s; + data_f1_addr_out <= data_f1_addr_out_s; + data_f2_addr_out <= data_f2_addr_out_s; + data_f3_addr_out <= data_f3_addr_out_s; + ----------------------------------------------------------------------------- -- RoundRobin Selection For DMA ----------------------------------------------------------------------------- @@ -461,7 +498,7 @@ BEGIN dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; - RR_Arbiter_4_1: RR_Arbiter_4 + RR_Arbiter_4_1 : RR_Arbiter_4 PORT MAP ( clk => clk, rstn => rstn, @@ -478,11 +515,11 @@ BEGIN ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - dma_sel <= (OTHERS => '0'); + IF rstn = '0' THEN -- asynchronous reset (active low) + dma_sel <= (OTHERS => '0'); dma_send <= '0'; dma_valid_burst <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge -- IF dma_sel = "0000" OR dma_send = '1' THEN IF dma_sel = "0000" OR dma_done = '1' THEN dma_sel <= dma_rr_grant; @@ -500,33 +537,33 @@ BEGIN dma_sel_valid <= data_f2_data_out_valid; ELSIF dma_rr_grant(3) = '1' THEN dma_send <= '1'; - dma_valid_burst <= data_f3_data_out_valid_burst; - dma_sel_valid <= data_f3_data_out_valid; + dma_valid_burst <= data_f3_data_out_valid_burst; + dma_sel_valid <= data_f3_data_out_valid; END IF; ELSE - dma_sel <= dma_sel; - dma_send <= '0'; - END IF; + dma_sel <= dma_sel; + dma_send <= '0'; + END IF; END IF; END PROCESS; - + dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE data_f1_addr_out WHEN dma_sel(1) = '1' ELSE data_f2_addr_out WHEN dma_sel(2) = '1' ELSE - data_f3_addr_out ; + data_f3_addr_out; dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE data_f1_data_out WHEN dma_sel(1) = '1' ELSE data_f2_data_out WHEN dma_sel(2) = '1' ELSE - data_f3_data_out ; + data_f3_data_out; --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE -- '0'; - + --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE @@ -535,18 +572,18 @@ BEGIN -- TODO --dma_send <= dma_sel_valid OR dma_valid_burst; - + --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1'; --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1'; --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1'; --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1'; - + data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; - - + + --PROCESS (clk, rstn) --BEGIN -- PROCESS -- IF rstn = '0' THEN -- asynchronous reset (active low) @@ -579,15 +616,15 @@ BEGIN -- dma_data_2 <= (OTHERS => '0'); -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge -- dma_data_2 <= dma_data; - + -- END IF; --END PROCESS; - + ----------------------------------------------------------------------------- -- DMA ----------------------------------------------------------------------------- - lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst + lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst GENERIC MAP ( tech => inferred, hindex => hindex) @@ -597,14 +634,14 @@ BEGIN run => run, AHB_Master_In => ahbi, AHB_Master_Out => ahbo, - - send => dma_send,--_reg, - valid_burst => dma_valid_burst,--_reg, - done => dma_done, - ren => dma_ren, - address => dma_address,--_reg, - data => dma_data_2);--_reg); - + + send => dma_send, --_reg, + valid_burst => dma_valid_burst, --_reg, + done => dma_done, + ren => dma_ren, + address => dma_address, --_reg, + data => dma_data_2); --_reg); + ----------------------------------------------------------------------------- -- Matrix Spectral - TODO ----------------------------------------------------------------------------- @@ -634,7 +671,7 @@ BEGIN -- sample_f3_wdata => sample_f3_wdata, -- AHB_Master_In => ahbi_ms, -- AHB_Master_Out => ahbo_ms, - + -- ready_matrix_f0_0 => ready_matrix_f0_0, -- ready_matrix_f0_1 => ready_matrix_f0_1, -- ready_matrix_f1 => ready_matrix_f1, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -121,7 +121,16 @@ ENTITY lpp_lfr_apbreg IS addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + --------------------------------------------------------------------------- + debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) --------------------------------------------------------------------------- ); @@ -368,6 +377,15 @@ BEGIN -- beh WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; ---------------------------------------------------- + WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0); + WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0); + WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0); + WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0); + WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0); + WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0); + WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0); + WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0); + ---------------------------------------------------- WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0); WHEN OTHERS => NULL; END CASE; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -178,7 +178,16 @@ PACKAGE lpp_lfr_pkg IS addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)); + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + --------------------------------------------------------------------------- + debug_reg0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; COMPONENT lpp_top_ms diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -183,6 +183,7 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); + SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); @@ -322,9 +323,22 @@ BEGIN -- beh data_out(3,I) <= data_f3_out(I); END GENERATE all_bit_of_data_out; + ----------------------------------------------------------------------------- + -- TODO : debug + ----------------------------------------------------------------------------- + --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE + -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE + -- time_out_2(J,I) <= time_out(J)(I); + -- END GENERATE all_sample_of_time_out; + --END GENERATE all_bit_of_time_out; + time_out_debug(0) <= x"0A0A" & x"0A0A0A0A"; + time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; + time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; + time_out_debug(3) <= x"3D3D" & x"3D3D3D3D"; + all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE - time_out_2(J,I) <= time_out(J)(I); + time_out_2(J,I) <= time_out_debug(J)(I); END GENERATE all_sample_of_time_out; END GENERATE all_bit_of_time_out;