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Correction du bugs 266 (a confirmer) :...
pellion -
r465:8e656681264f (MINI-LFR) WFP_MS-0-1-35 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
192 BEGIN -- beh
196 BEGIN -- beh
193
197
194 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
195 -- CLK
199 -- CLK
196 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
197
201
198 --PROCESS(clk_50)
202 --PROCESS(clk_50)
199 --BEGIN
203 --BEGIN
200 -- IF clk_50'EVENT AND clk_50 = '1' THEN
204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
201 -- clk_50_s <= NOT clk_50_s;
205 -- clk_50_s <= NOT clk_50_s;
202 -- END IF;
206 -- END IF;
203 --END PROCESS;
207 --END PROCESS;
204
208
205 --PROCESS(clk_50_s)
209 --PROCESS(clk_50_s)
206 --BEGIN
210 --BEGIN
207 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
208 -- clk_25 <= NOT clk_25;
212 -- clk_25 <= NOT clk_25;
209 -- END IF;
213 -- END IF;
210 --END PROCESS;
214 --END PROCESS;
211
215
212 --PROCESS(clk_49)
216 --PROCESS(clk_49)
213 --BEGIN
217 --BEGIN
214 -- IF clk_49'EVENT AND clk_49 = '1' THEN
218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
215 -- clk_24 <= NOT clk_24;
219 -- clk_24 <= NOT clk_24;
216 -- END IF;
220 -- END IF;
217 --END PROCESS;
221 --END PROCESS;
218
222
219 --PROCESS(clk_25)
223 --PROCESS(clk_25)
220 --BEGIN
224 --BEGIN
221 -- IF clk_25'EVENT AND clk_25 = '1' THEN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
222 -- rstn_25 <= reset;
226 -- rstn_25 <= reset;
223 -- END IF;
227 -- END IF;
224 --END PROCESS;
228 --END PROCESS;
225
229
226 PROCESS (clk_50, reset)
230 PROCESS (clk_50, reset)
227 BEGIN -- PROCESS
231 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
232 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_50_s <= '0';
233 clk_50_s <= '0';
230 rstn_50 <= '0';
234 rstn_50 <= '0';
231 rstn_50_d1 <= '0';
235 rstn_50_d1 <= '0';
232 rstn_50_d2 <= '0';
236 rstn_50_d2 <= '0';
233 rstn_50_d3 <= '0';
237 rstn_50_d3 <= '0';
234
238
235 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
236 clk_50_s <= NOT clk_50_s;
240 clk_50_s <= NOT clk_50_s;
237 rstn_50_d1 <= '1';
241 rstn_50_d1 <= '1';
238 rstn_50_d2 <= rstn_50_d1;
242 rstn_50_d2 <= rstn_50_d1;
239 rstn_50_d3 <= rstn_50_d2;
243 rstn_50_d3 <= rstn_50_d2;
240 rstn_50 <= rstn_50_d3;
244 rstn_50 <= rstn_50_d3;
241 END IF;
245 END IF;
242 END PROCESS;
246 END PROCESS;
243
247
244 PROCESS (clk_50_s, rstn_50)
248 PROCESS (clk_50_s, rstn_50)
245 BEGIN -- PROCESS
249 BEGIN -- PROCESS
246 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
247 clk_25 <= '0';
251 clk_25 <= '0';
248 rstn_25 <= '0';
252 rstn_25 <= '0';
249 rstn_25_d1 <= '0';
253 rstn_25_d1 <= '0';
250 rstn_25_d2 <= '0';
254 rstn_25_d2 <= '0';
251 rstn_25_d3 <= '0';
255 rstn_25_d3 <= '0';
252 ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
253 clk_25 <= NOT clk_25;
257 clk_25 <= NOT clk_25;
254 rstn_25_d1 <= '1';
258 rstn_25_d1 <= '1';
255 rstn_25_d2 <= rstn_25_d1;
259 rstn_25_d2 <= rstn_25_d1;
256 rstn_25_d3 <= rstn_25_d2;
260 rstn_25_d3 <= rstn_25_d2;
257 rstn_25 <= rstn_25_d3;
261 rstn_25 <= rstn_25_d3;
258 END IF;
262 END IF;
259 END PROCESS;
263 END PROCESS;
260
264
261 PROCESS (clk_49, reset)
265 PROCESS (clk_49, reset)
262 BEGIN -- PROCESS
266 BEGIN -- PROCESS
263 IF reset = '0' THEN -- asynchronous reset (active low)
267 IF reset = '0' THEN -- asynchronous reset (active low)
264 clk_24 <= '0';
268 clk_24 <= '0';
265 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
266 clk_24 <= NOT clk_24;
270 clk_24 <= NOT clk_24;
267 END IF;
271 END IF;
268 END PROCESS;
272 END PROCESS;
269
273
270 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
271
275
272 PROCESS (clk_25, rstn_25)
276 PROCESS (clk_25, rstn_25)
273 BEGIN -- PROCESS
277 BEGIN -- PROCESS
274 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
275 LED0 <= '0';
279 LED0 <= '0';
276 LED1 <= '0';
280 LED1 <= '0';
277 LED2 <= '0';
281 LED2 <= '0';
278 --IO1 <= '0';
282 --IO1 <= '0';
279 --IO2 <= '1';
283 --IO2 <= '1';
280 --IO3 <= '0';
284 --IO3 <= '0';
281 --IO4 <= '0';
285 --IO4 <= '0';
282 --IO5 <= '0';
286 --IO5 <= '0';
283 --IO6 <= '0';
287 --IO6 <= '0';
284 --IO7 <= '0';
288 --IO7 <= '0';
285 --IO8 <= '0';
289 --IO8 <= '0';
286 --IO9 <= '0';
290 --IO9 <= '0';
287 --IO10 <= '0';
291 --IO10 <= '0';
288 --IO11 <= '0';
292 --IO11 <= '0';
289 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
290 LED0 <= '0';
294 LED0 <= '0';
291 LED1 <= '1';
295 LED1 <= '1';
292 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
293 --IO1 <= '1';
297 --IO1 <= '1';
294 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
295 --IO3 <= ADC_SDO(0);
299 --IO3 <= ADC_SDO(0);
296 --IO4 <= ADC_SDO(1);
300 --IO4 <= ADC_SDO(1);
297 --IO5 <= ADC_SDO(2);
301 --IO5 <= ADC_SDO(2);
298 --IO6 <= ADC_SDO(3);
302 --IO6 <= ADC_SDO(3);
299 --IO7 <= ADC_SDO(4);
303 --IO7 <= ADC_SDO(4);
300 --IO8 <= ADC_SDO(5);
304 --IO8 <= ADC_SDO(5);
301 --IO9 <= ADC_SDO(6);
305 --IO9 <= ADC_SDO(6);
302 --IO10 <= ADC_SDO(7);
306 --IO10 <= ADC_SDO(7);
303 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 END IF;
308 END IF;
305 END PROCESS;
309 END PROCESS;
306
310
307 PROCESS (clk_24, rstn_25)
311 PROCESS (clk_24, rstn_25)
308 BEGIN -- PROCESS
312 BEGIN -- PROCESS
309 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
310 I00_s <= '0';
314 I00_s <= '0';
311 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
312 I00_s <= NOT I00_s ;
316 I00_s <= NOT I00_s;
313 END IF;
317 END IF;
314 END PROCESS;
318 END PROCESS;
315 -- IO0 <= I00_s;
319 -- IO0 <= I00_s;
316
320
317 --UARTs
321 --UARTs
318 nCTS1 <= '1';
322 nCTS1 <= '1';
319 nCTS2 <= '1';
323 nCTS2 <= '1';
320 nDCD2 <= '1';
324 nDCD2 <= '1';
321
325
322 --EXT CONNECTOR
326 --EXT CONNECTOR
323
327
324 --SPACE WIRE
328 --SPACE WIRE
325
329
326 leon3_soc_1 : leon3_soc
330 leon3_soc_1 : leon3_soc
327 GENERIC MAP (
331 GENERIC MAP (
328 fabtech => apa3e,
332 fabtech => apa3e,
329 memtech => apa3e,
333 memtech => apa3e,
330 padtech => inferred,
334 padtech => inferred,
331 clktech => inferred,
335 clktech => inferred,
332 disas => 0,
336 disas => 0,
333 dbguart => 0,
337 dbguart => 0,
334 pclow => 2,
338 pclow => 2,
335 clk_freq => 25000,
339 clk_freq => 25000,
336 NB_CPU => 1,
340 NB_CPU => 1,
337 ENABLE_FPU => 1,
341 ENABLE_FPU => 1,
338 FPU_NETLIST => 0,
342 FPU_NETLIST => 0,
339 ENABLE_DSU => 1,
343 ENABLE_DSU => 1,
340 ENABLE_AHB_UART => 1,
344 ENABLE_AHB_UART => 1,
341 ENABLE_APB_UART => 1,
345 ENABLE_APB_UART => 1,
342 ENABLE_IRQMP => 1,
346 ENABLE_IRQMP => 1,
343 ENABLE_GPT => 1,
347 ENABLE_GPT => 1,
344 NB_AHB_MASTER => NB_AHB_MASTER,
348 NB_AHB_MASTER => NB_AHB_MASTER,
345 NB_AHB_SLAVE => NB_AHB_SLAVE,
349 NB_AHB_SLAVE => NB_AHB_SLAVE,
346 NB_APB_SLAVE => NB_APB_SLAVE,
350 NB_APB_SLAVE => NB_APB_SLAVE,
347 ADDRESS_SIZE => 20)
351 ADDRESS_SIZE => 20)
348 PORT MAP (
352 PORT MAP (
349 clk => clk_25,
353 clk => clk_25,
350 reset => rstn_25,
354 reset => rstn_25,
351 errorn => errorn,
355 errorn => errorn,
352 ahbrxd => TXD1,
356 ahbrxd => TXD1,
353 ahbtxd => RXD1,
357 ahbtxd => RXD1,
354 urxd1 => TXD2,
358 urxd1 => TXD2,
355 utxd1 => RXD2,
359 utxd1 => RXD2,
356 address => SRAM_A,
360 address => SRAM_A,
357 data => SRAM_DQ,
361 data => SRAM_DQ,
358 nSRAM_BE0 => SRAM_nBE(0),
362 nSRAM_BE0 => SRAM_nBE(0),
359 nSRAM_BE1 => SRAM_nBE(1),
363 nSRAM_BE1 => SRAM_nBE(1),
360 nSRAM_BE2 => SRAM_nBE(2),
364 nSRAM_BE2 => SRAM_nBE(2),
361 nSRAM_BE3 => SRAM_nBE(3),
365 nSRAM_BE3 => SRAM_nBE(3),
362 nSRAM_WE => SRAM_nWE,
366 nSRAM_WE => SRAM_nWE,
363 nSRAM_CE => SRAM_CE,
367 nSRAM_CE => SRAM_CE,
364 nSRAM_OE => SRAM_nOE,
368 nSRAM_OE => SRAM_nOE,
365
369
366 apbi_ext => apbi_ext,
370 apbi_ext => apbi_ext,
367 apbo_ext => apbo_ext,
371 apbo_ext => apbo_ext,
368 ahbi_s_ext => ahbi_s_ext,
372 ahbi_s_ext => ahbi_s_ext,
369 ahbo_s_ext => ahbo_s_ext,
373 ahbo_s_ext => ahbo_s_ext,
370 ahbi_m_ext => ahbi_m_ext,
374 ahbi_m_ext => ahbi_m_ext,
371 ahbo_m_ext => ahbo_m_ext);
375 ahbo_m_ext => ahbo_m_ext);
372
376
373 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1 : apb_lfr_time_management
380 apb_lfr_time_management_1 : apb_lfr_time_management
377 GENERIC MAP (
381 GENERIC MAP (
378 pindex => 6,
382 pindex => 6,
379 paddr => 6,
383 paddr => 6,
380 pmask => 16#fff#,
384 pmask => 16#fff#,
381 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
382 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
383 PORT MAP (
387 PORT MAP (
384 clk25MHz => clk_25,
388 clk25MHz => clk_25,
385 clk24_576MHz => clk_24, -- 49.152MHz/2
389 clk24_576MHz => clk_24, -- 49.152MHz/2
386 resetn => rstn_25,
390 resetn => rstn_25,
387 grspw_tick => swno.tickout,
391 grspw_tick => swno.tickout,
388 apbi => apbi_ext,
392 apbi => apbi_ext,
389 apbo => apbo_ext(6),
393 apbo => apbo_ext(6),
390 coarse_time => coarse_time,
394 coarse_time => coarse_time,
391 fine_time => fine_time,
395 fine_time => fine_time,
392 LFR_soft_rstn => LFR_soft_rstn
396 LFR_soft_rstn => LFR_soft_rstn
393 );
397 );
394
398
395 -----------------------------------------------------------------------
399 -----------------------------------------------------------------------
396 --- SpaceWire --------------------------------------------------------
400 --- SpaceWire --------------------------------------------------------
397 -----------------------------------------------------------------------
401 -----------------------------------------------------------------------
398
402
399 SPW_EN <= '1';
403 SPW_EN <= '1';
400
404
401 spw_clk <= clk_50_s;
405 spw_clk <= clk_50_s;
402 spw_rxtxclk <= spw_clk;
406 spw_rxtxclk <= spw_clk;
403 spw_rxclkn <= NOT spw_rxtxclk;
407 spw_rxclkn <= NOT spw_rxtxclk;
404
408
405 -- PADS for SPW1
409 -- PADS for SPW1
406 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
407 PORT MAP (SPW_NOM_DIN, dtmp(0));
411 PORT MAP (SPW_NOM_DIN, dtmp(0));
408 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
409 PORT MAP (SPW_NOM_SIN, stmp(0));
413 PORT MAP (SPW_NOM_SIN, stmp(0));
410 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
411 PORT MAP (SPW_NOM_DOUT, swno.d(0));
415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
412 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
413 PORT MAP (SPW_NOM_SOUT, swno.s(0));
417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
414 -- PADS FOR SPW2
418 -- PADS FOR SPW2
415 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
416 PORT MAP (SPW_RED_SIN, dtmp(1));
420 PORT MAP (SPW_RED_SIN, dtmp(1));
417 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
418 PORT MAP (SPW_RED_DIN, stmp(1));
422 PORT MAP (SPW_RED_DIN, stmp(1));
419 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
420 PORT MAP (SPW_RED_DOUT, swno.d(1));
424 PORT MAP (SPW_RED_DOUT, swno.d(1));
421 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
422 PORT MAP (SPW_RED_SOUT, swno.s(1));
426 PORT MAP (SPW_RED_SOUT, swno.s(1));
423
427
424 -- GRSPW PHY
428 -- GRSPW PHY
425 --spw1_input: if CFG_SPW_GRSPW = 1 generate
429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
426 spw_inputloop : FOR j IN 0 TO 1 GENERATE
430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
427 spw_phy0 : grspw_phy
431 spw_phy0 : grspw_phy
428 GENERIC MAP(
432 GENERIC MAP(
429 tech => apa3e,
433 tech => apa3e,
430 rxclkbuftype => 1,
434 rxclkbuftype => 1,
431 scantest => 0)
435 scantest => 0)
432 PORT MAP(
436 PORT MAP(
433 rxrst => swno.rxrst,
437 rxrst => swno.rxrst,
434 di => dtmp(j),
438 di => dtmp(j),
435 si => stmp(j),
439 si => stmp(j),
436 rxclko => spw_rxclk(j),
440 rxclko => spw_rxclk(j),
437 do => swni.d(j),
441 do => swni.d(j),
438 ndo => swni.nd(j*5+4 DOWNTO j*5),
442 ndo => swni.nd(j*5+4 DOWNTO j*5),
439 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
440 END GENERATE spw_inputloop;
444 END GENERATE spw_inputloop;
441
445
442 swni.rmapnodeaddr <= (others => '0');
446 swni.rmapnodeaddr <= (OTHERS => '0');
443
447
444 -- SPW core
448 -- SPW core
445 sw0 : grspwm GENERIC MAP(
449 sw0 : grspwm GENERIC MAP(
446 tech => apa3e,
450 tech => apa3e,
447 hindex => 1,
451 hindex => 1,
448 pindex => 5,
452 pindex => 5,
449 paddr => 5,
453 paddr => 5,
450 pirq => 11,
454 pirq => 11,
451 sysfreq => 25000, -- CPU_FREQ
455 sysfreq => 25000, -- CPU_FREQ
452 rmap => 1,
456 rmap => 1,
453 rmapcrc => 1,
457 rmapcrc => 1,
454 fifosize1 => 16,
458 fifosize1 => 16,
455 fifosize2 => 16,
459 fifosize2 => 16,
456 rxclkbuftype => 1,
460 rxclkbuftype => 1,
457 rxunaligned => 0,
461 rxunaligned => 0,
458 rmapbufs => 4,
462 rmapbufs => 4,
459 ft => 0,
463 ft => 0,
460 netlist => 0,
464 netlist => 0,
461 ports => 2,
465 ports => 2,
462 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
463 memtech => apa3e,
467 memtech => apa3e,
464 destkey => 2,
468 destkey => 2,
465 spwcore => 1
469 spwcore => 1
466 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
467 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
468 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
469 )
473 )
470 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
471 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
472 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
473 swni, swno);
477 swni, swno);
474
478
475 swni.tickin <= '0';
479 swni.tickin <= '0';
476 swni.rmapen <= '1';
480 swni.rmapen <= '1';
477 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
478 swni.tickinraw <= '0';
482 swni.tickinraw <= '0';
479 swni.timein <= (OTHERS => '0');
483 swni.timein <= (OTHERS => '0');
480 swni.dcrstval <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
481 swni.timerrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
482
486
483 -------------------------------------------------------------------------------
487 -------------------------------------------------------------------------------
484 -- LFR ------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
485 -------------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
486
490
487
491
488 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
489 LFR_rstn <= rstn_25;
493 --LFR_rstn <= rstn_25;
490
494
491 lpp_lfr_1 : lpp_lfr
495 lpp_lfr_1 : lpp_lfr
492 GENERIC MAP (
496 GENERIC MAP (
493 Mem_use => use_RAM,
497 Mem_use => use_RAM,
494 nb_data_by_buffer_size => 32,
498 nb_data_by_buffer_size => 32,
495 nb_snapshot_param_size => 32,
499 nb_snapshot_param_size => 32,
496 delta_vector_size => 32,
500 delta_vector_size => 32,
497 delta_vector_size_f0_2 => 7, -- log2(96)
501 delta_vector_size_f0_2 => 7, -- log2(96)
498 pindex => 15,
502 pindex => 15,
499 paddr => 15,
503 paddr => 15,
500 pmask => 16#fff#,
504 pmask => 16#fff#,
501 pirq_ms => 6,
505 pirq_ms => 6,
502 pirq_wfp => 14,
506 pirq_wfp => 14,
503 hindex => 2,
507 hindex => 2,
504 top_lfr_version => X"000122") -- aa.bb.cc version
508 top_lfr_version => X"000123") -- aa.bb.cc version
505 PORT MAP (
509 PORT MAP (
506 clk => clk_25,
510 clk => clk_25,
507 rstn => LFR_rstn,
511 rstn => LFR_rstn,
508 sample_B => sample_s(2 DOWNTO 0),
512 sample_B => sample_s(2 DOWNTO 0),
509 sample_E => sample_s(7 DOWNTO 3),
513 sample_E => sample_s(7 DOWNTO 3),
510 sample_val => sample_val,
514 sample_val => sample_val,
511 apbi => apbi_ext,
515 apbi => apbi_ext,
512 apbo => apbo_ext(15),
516 apbo => apbo_ext(15),
513 ahbi => ahbi_m_ext,
517 ahbi => ahbi_m_ext,
514 ahbo => ahbo_m_ext(2),
518 ahbo => ahbo_m_ext(2),
515 coarse_time => coarse_time,
519 coarse_time => coarse_time,
516 fine_time => fine_time,
520 fine_time => fine_time,
517 data_shaping_BW => bias_fail_sw_sig);
521 data_shaping_BW => bias_fail_sw_sig,
522 debug_vector => lfr_debug_vector,
523 debug_vector_ms => lfr_debug_vector_ms
524 );
518
525
519 observation_reg <= (others => '0');
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
520 observation_vector_0 <= (others => '0');
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
521 observation_vector_1 <= (others => '0');
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 IO0 <= rstn_25;
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
522
538
523 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
524 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
525 END GENERATE all_sample;
541 END GENERATE all_sample;
526
542
527 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
528 GENERIC MAP(
544 GENERIC MAP(
529 ChannelCount => 8,
545 ChannelCount => 8,
530 SampleNbBits => 14,
546 SampleNbBits => 14,
531 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
532 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
533 PORT MAP (
549 PORT MAP (
534 -- CONV
550 -- CONV
535 cnv_clk => clk_24,
551 cnv_clk => clk_24,
536 cnv_rstn => rstn_25,
552 cnv_rstn => rstn_25,
537 cnv => ADC_nCS_sig,
553 cnv => ADC_nCS_sig,
538 -- DATA
554 -- DATA
539 clk => clk_25,
555 clk => clk_25,
540 rstn => rstn_25,
556 rstn => rstn_25,
541 sck => ADC_CLK_sig,
557 sck => ADC_CLK_sig,
542 sdo => ADC_SDO_sig,
558 sdo => ADC_SDO_sig,
543 -- SAMPLE
559 -- SAMPLE
544 sample => sample,
560 sample => sample,
545 sample_val => sample_val);
561 sample_val => sample_val);
546
562
547 --IO10 <= ADC_SDO_sig(5);
563 --IO10 <= ADC_SDO_sig(5);
548 --IO9 <= ADC_SDO_sig(4);
564 --IO9 <= ADC_SDO_sig(4);
549 --IO8 <= ADC_SDO_sig(3);
565 --IO8 <= ADC_SDO_sig(3);
550
566
551 ADC_nCS <= ADC_nCS_sig;
567 ADC_nCS <= ADC_nCS_sig;
552 ADC_CLK <= ADC_CLK_sig;
568 ADC_CLK <= ADC_CLK_sig;
553 ADC_SDO_sig <= ADC_SDO;
569 ADC_SDO_sig <= ADC_SDO;
554
570
555 ----------------------------------------------------------------------
571 ----------------------------------------------------------------------
556 --- GPIO -----------------------------------------------------------
572 --- GPIO -----------------------------------------------------------
557 ----------------------------------------------------------------------
573 ----------------------------------------------------------------------
558
574
559 grgpio0 : grgpio
575 grgpio0 : grgpio
560 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
561 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
562
578
563 gpioi.sig_en <= (others => '0');
579 gpioi.sig_en <= (OTHERS => '0');
564 gpioi.sig_in <= (others => '0');
580 gpioi.sig_in <= (OTHERS => '0');
565 gpioi.din <= (others => '0');
581 gpioi.din <= (OTHERS => '0');
566 --pio_pad_0 : iopad
582 --pio_pad_0 : iopad
567 -- GENERIC MAP (tech => CFG_PADTECH)
583 -- GENERIC MAP (tech => CFG_PADTECH)
568 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
569 --pio_pad_1 : iopad
585 --pio_pad_1 : iopad
570 -- GENERIC MAP (tech => CFG_PADTECH)
586 -- GENERIC MAP (tech => CFG_PADTECH)
571 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
572 --pio_pad_2 : iopad
588 --pio_pad_2 : iopad
573 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
574 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
575 --pio_pad_3 : iopad
591 --pio_pad_3 : iopad
576 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
577 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
578 --pio_pad_4 : iopad
594 --pio_pad_4 : iopad
579 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
580 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
581 --pio_pad_5 : iopad
597 --pio_pad_5 : iopad
582 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
583 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
584 --pio_pad_6 : iopad
600 --pio_pad_6 : iopad
585 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
586 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
587 --pio_pad_7 : iopad
603 --pio_pad_7 : iopad
588 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
590
606
591 PROCESS (clk_25, rstn_25)
607 PROCESS (clk_25, rstn_25)
592 BEGIN -- PROCESS
608 BEGIN -- PROCESS
593 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
594 IO0 <= '0';
610 -- --IO0 <= '0';
595 IO1 <= '0';
611 -- IO1 <= '0';
596 IO2 <= '0';
612 -- IO2 <= '0';
597 IO3 <= '0';
613 -- IO3 <= '0';
598 IO4 <= '0';
614 -- IO4 <= '0';
599 IO5 <= '0';
615 -- IO5 <= '0';
600 IO6 <= '0';
616 -- IO6 <= '0';
601 IO7 <= '0';
617 -- IO7 <= '0';
602 IO8 <= '0';
618 IO8 <= '0';
603 IO9 <= '0';
619 IO9 <= '0';
604 IO10 <= '0';
620 IO10 <= '0';
605 IO11 <= '0';
621 IO11 <= '0';
606 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
607 CASE gpioo.dout(2 DOWNTO 0) IS
623 CASE gpioo.dout(2 DOWNTO 0) IS
608 WHEN "011" =>
624 WHEN "011" =>
609 IO0 <= observation_reg(0 );
625 -- --IO0 <= observation_reg(0 );
610 IO1 <= observation_reg(1 );
626 -- IO1 <= observation_reg(1 );
611 IO2 <= observation_reg(2 );
627 -- IO2 <= observation_reg(2 );
612 IO3 <= observation_reg(3 );
628 -- IO3 <= observation_reg(3 );
613 IO4 <= observation_reg(4 );
629 -- IO4 <= observation_reg(4 );
614 IO5 <= observation_reg(5 );
630 -- IO5 <= observation_reg(5 );
615 IO6 <= observation_reg(6 );
631 -- IO6 <= observation_reg(6 );
616 IO7 <= observation_reg(7 );
632 -- IO7 <= observation_reg(7 );
617 IO8 <= observation_reg(8 );
633 IO8 <= observation_reg(8);
618 IO9 <= observation_reg(9 );
634 IO9 <= observation_reg(9);
619 IO10 <= observation_reg(10);
635 IO10 <= observation_reg(10);
620 IO11 <= observation_reg(11);
636 IO11 <= observation_reg(11);
621 WHEN "001" =>
637 WHEN "001" =>
622 IO0 <= observation_reg(0 + 12);
638 -- --IO0 <= observation_reg(0 + 12);
623 IO1 <= observation_reg(1 + 12);
639 -- IO1 <= observation_reg(1 + 12);
624 IO2 <= observation_reg(2 + 12);
640 -- IO2 <= observation_reg(2 + 12);
625 IO3 <= observation_reg(3 + 12);
641 -- IO3 <= observation_reg(3 + 12);
626 IO4 <= observation_reg(4 + 12);
642 -- IO4 <= observation_reg(4 + 12);
627 IO5 <= observation_reg(5 + 12);
643 -- IO5 <= observation_reg(5 + 12);
628 IO6 <= observation_reg(6 + 12);
644 -- IO6 <= observation_reg(6 + 12);
629 IO7 <= observation_reg(7 + 12);
645 -- IO7 <= observation_reg(7 + 12);
630 IO8 <= observation_reg(8 + 12);
646 IO8 <= observation_reg(8 + 12);
631 IO9 <= observation_reg(9 + 12);
647 IO9 <= observation_reg(9 + 12);
632 IO10 <= observation_reg(10 + 12);
648 IO10 <= observation_reg(10 + 12);
633 IO11 <= observation_reg(11 + 12);
649 IO11 <= observation_reg(11 + 12);
634 WHEN "010" =>
650 WHEN "010" =>
635 IO0 <= observation_reg(0 + 12 + 12);
651 -- --IO0 <= observation_reg(0 + 12 + 12);
636 IO1 <= observation_reg(1 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
637 IO2 <= observation_reg(2 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
638 IO3 <= observation_reg(3 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
639 IO4 <= observation_reg(4 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
640 IO5 <= observation_reg(5 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
641 IO6 <= observation_reg(6 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
642 IO7 <= observation_reg(7 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
643 IO8 <= '0';
659 IO8 <= '0';
644 IO9 <= '0';
660 IO9 <= '0';
645 IO10 <= '0';
661 IO10 <= '0';
646 IO11 <= '0';
662 IO11 <= '0';
647 WHEN "000" =>
663 WHEN "000" =>
648 IO0 <= observation_vector_0(0 );
664 -- --IO0 <= observation_vector_0(0 );
649 IO1 <= observation_vector_0(1 );
665 -- IO1 <= observation_vector_0(1 );
650 IO2 <= observation_vector_0(2 );
666 -- IO2 <= observation_vector_0(2 );
651 IO3 <= observation_vector_0(3 );
667 -- IO3 <= observation_vector_0(3 );
652 IO4 <= observation_vector_0(4 );
668 -- IO4 <= observation_vector_0(4 );
653 IO5 <= observation_vector_0(5 );
669 -- IO5 <= observation_vector_0(5 );
654 IO6 <= observation_vector_0(6 );
670 -- IO6 <= observation_vector_0(6 );
655 IO7 <= observation_vector_0(7 );
671 -- IO7 <= observation_vector_0(7 );
656 IO8 <= observation_vector_0(8 );
672 IO8 <= observation_vector_0(8);
657 IO9 <= observation_vector_0(9 );
673 IO9 <= observation_vector_0(9);
658 IO10 <= observation_vector_0(10);
674 IO10 <= observation_vector_0(10);
659 IO11 <= observation_vector_0(11);
675 IO11 <= observation_vector_0(11);
660 WHEN "100" =>
676 WHEN "100" =>
661 IO0 <= observation_vector_1(0 );
677 -- --IO0 <= observation_vector_1(0 );
662 IO1 <= observation_vector_1(1 );
678 -- IO1 <= observation_vector_1(1 );
663 IO2 <= observation_vector_1(2 );
679 -- IO2 <= observation_vector_1(2 );
664 IO3 <= observation_vector_1(3 );
680 -- IO3 <= observation_vector_1(3 );
665 IO4 <= observation_vector_1(4 );
681 -- IO4 <= observation_vector_1(4 );
666 IO5 <= observation_vector_1(5 );
682 -- IO5 <= observation_vector_1(5 );
667 IO6 <= observation_vector_1(6 );
683 -- IO6 <= observation_vector_1(6 );
668 IO7 <= observation_vector_1(7 );
684 -- IO7 <= observation_vector_1(7 );
669 IO8 <= observation_vector_1(8 );
685 IO8 <= observation_vector_1(8);
670 IO9 <= observation_vector_1(9 );
686 IO9 <= observation_vector_1(9);
671 IO10 <= observation_vector_1(10);
687 IO10 <= observation_vector_1(10);
672 IO11 <= observation_vector_1(11);
688 IO11 <= observation_vector_1(11);
673 WHEN OTHERS => NULL;
689 WHEN OTHERS => NULL;
674 END CASE;
690 END CASE;
675
691
676 END IF;
692 END IF;
677 END PROCESS;
693 END PROCESS;
678 -----------------------------------------------------------------------------
694 -----------------------------------------------------------------------------
679 --
695 --
680 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
681 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
682 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
683 apbo_ext(I) <= apb_none;
699 apbo_ext(I) <= apb_none;
684 END GENERATE apbo_ext_not_used;
700 END GENERATE apbo_ext_not_used;
685 END GENERATE all_apbo_ext;
701 END GENERATE all_apbo_ext;
686
702
687
703
688 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
689 ahbo_s_ext(I) <= ahbs_none;
705 ahbo_s_ext(I) <= ahbs_none;
690 END GENERATE all_ahbo_ext;
706 END GENERATE all_ahbo_ext;
691
707
692 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
693 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
694 ahbo_m_ext(I) <= ahbm_none;
710 ahbo_m_ext(I) <= ahbm_none;
695 END GENERATE ahbo_m_ext_not_used;
711 END GENERATE ahbo_m_ext_not_used;
696 END GENERATE all_ahbo_m_ext;
712 END GENERATE all_ahbo_m_ext;
697
713
698 END beh; No newline at end of file
714 END beh;
Show file before | Show file after | Hide comments
@@ -1,273 +1,271
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
21
22 LIBRARY postlayout;
23 USE postlayout.ALL;
24
22
25 ENTITY testbench IS
23 ENTITY testbench IS
26 END;
24 END;
27
25
28 ARCHITECTURE behav OF testbench IS
26 ARCHITECTURE behav OF testbench IS
29
27
30 COMPONENT MINI_LFR_top
28 COMPONENT MINI_LFR_top
31 PORT (
29 PORT (
32 clk_50 : IN STD_LOGIC;
30 clk_50 : IN STD_LOGIC;
33 clk_49 : IN STD_LOGIC;
31 clk_49 : IN STD_LOGIC;
34 reset : IN STD_LOGIC;
32 reset : IN STD_LOGIC;
35 BP0 : IN STD_LOGIC;
33 BP0 : IN STD_LOGIC;
36 BP1 : IN STD_LOGIC;
34 BP1 : IN STD_LOGIC;
37 LED0 : OUT STD_LOGIC;
35 LED0 : OUT STD_LOGIC;
38 LED1 : OUT STD_LOGIC;
36 LED1 : OUT STD_LOGIC;
39 LED2 : OUT STD_LOGIC;
37 LED2 : OUT STD_LOGIC;
40 TXD1 : IN STD_LOGIC;
38 TXD1 : IN STD_LOGIC;
41 RXD1 : OUT STD_LOGIC;
39 RXD1 : OUT STD_LOGIC;
42 nCTS1 : OUT STD_LOGIC;
40 nCTS1 : OUT STD_LOGIC;
43 nRTS1 : IN STD_LOGIC;
41 nRTS1 : IN STD_LOGIC;
44 TXD2 : IN STD_LOGIC;
42 TXD2 : IN STD_LOGIC;
45 RXD2 : OUT STD_LOGIC;
43 RXD2 : OUT STD_LOGIC;
46 nCTS2 : OUT STD_LOGIC;
44 nCTS2 : OUT STD_LOGIC;
47 nDTR2 : IN STD_LOGIC;
45 nDTR2 : IN STD_LOGIC;
48 nRTS2 : IN STD_LOGIC;
46 nRTS2 : IN STD_LOGIC;
49 nDCD2 : OUT STD_LOGIC;
47 nDCD2 : OUT STD_LOGIC;
50 IO0 : INOUT STD_LOGIC;
48 IO0 : INOUT STD_LOGIC;
51 IO1 : INOUT STD_LOGIC;
49 IO1 : INOUT STD_LOGIC;
52 IO2 : INOUT STD_LOGIC;
50 IO2 : INOUT STD_LOGIC;
53 IO3 : INOUT STD_LOGIC;
51 IO3 : INOUT STD_LOGIC;
54 IO4 : INOUT STD_LOGIC;
52 IO4 : INOUT STD_LOGIC;
55 IO5 : INOUT STD_LOGIC;
53 IO5 : INOUT STD_LOGIC;
56 IO6 : INOUT STD_LOGIC;
54 IO6 : INOUT STD_LOGIC;
57 IO7 : INOUT STD_LOGIC;
55 IO7 : INOUT STD_LOGIC;
58 IO8 : INOUT STD_LOGIC;
56 IO8 : INOUT STD_LOGIC;
59 IO9 : INOUT STD_LOGIC;
57 IO9 : INOUT STD_LOGIC;
60 IO10 : INOUT STD_LOGIC;
58 IO10 : INOUT STD_LOGIC;
61 IO11 : INOUT STD_LOGIC;
59 IO11 : INOUT STD_LOGIC;
62 SPW_EN : OUT STD_LOGIC;
60 SPW_EN : OUT STD_LOGIC;
63 SPW_NOM_DIN : IN STD_LOGIC;
61 SPW_NOM_DIN : IN STD_LOGIC;
64 SPW_NOM_SIN : IN STD_LOGIC;
62 SPW_NOM_SIN : IN STD_LOGIC;
65 SPW_NOM_DOUT : OUT STD_LOGIC;
63 SPW_NOM_DOUT : OUT STD_LOGIC;
66 SPW_NOM_SOUT : OUT STD_LOGIC;
64 SPW_NOM_SOUT : OUT STD_LOGIC;
67 SPW_RED_DIN : IN STD_LOGIC;
65 SPW_RED_DIN : IN STD_LOGIC;
68 SPW_RED_SIN : IN STD_LOGIC;
66 SPW_RED_SIN : IN STD_LOGIC;
69 SPW_RED_DOUT : OUT STD_LOGIC;
67 SPW_RED_DOUT : OUT STD_LOGIC;
70 SPW_RED_SOUT : OUT STD_LOGIC;
68 SPW_RED_SOUT : OUT STD_LOGIC;
71 ADC_nCS : OUT STD_LOGIC;
69 ADC_nCS : OUT STD_LOGIC;
72 ADC_CLK : OUT STD_LOGIC;
70 ADC_CLK : OUT STD_LOGIC;
73 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
71 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
74 SRAM_nWE : OUT STD_LOGIC;
72 SRAM_nWE : OUT STD_LOGIC;
75 SRAM_CE : OUT STD_LOGIC;
73 SRAM_CE : OUT STD_LOGIC;
76 SRAM_nOE : OUT STD_LOGIC;
74 SRAM_nOE : OUT STD_LOGIC;
77 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
76 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
79 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
77 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
80 END COMPONENT;
78 END COMPONENT;
81
79
82 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
83 SIGNAL clk_50 : STD_LOGIC := '0';
81 SIGNAL clk_50 : STD_LOGIC := '0';
84 SIGNAL clk_49 : STD_LOGIC := '0';
82 SIGNAL clk_49 : STD_LOGIC := '0';
85 SIGNAL reset : STD_LOGIC;
83 SIGNAL reset : STD_LOGIC;
86 SIGNAL BP0 : STD_LOGIC;
84 SIGNAL BP0 : STD_LOGIC;
87 SIGNAL BP1 : STD_LOGIC;
85 SIGNAL BP1 : STD_LOGIC;
88 SIGNAL LED0 : STD_LOGIC;
86 SIGNAL LED0 : STD_LOGIC;
89 SIGNAL LED1 : STD_LOGIC;
87 SIGNAL LED1 : STD_LOGIC;
90 SIGNAL LED2 : STD_LOGIC;
88 SIGNAL LED2 : STD_LOGIC;
91 SIGNAL TXD1 : STD_LOGIC;
89 SIGNAL TXD1 : STD_LOGIC;
92 SIGNAL RXD1 : STD_LOGIC;
90 SIGNAL RXD1 : STD_LOGIC;
93 SIGNAL nCTS1 : STD_LOGIC;
91 SIGNAL nCTS1 : STD_LOGIC;
94 SIGNAL nRTS1 : STD_LOGIC;
92 SIGNAL nRTS1 : STD_LOGIC;
95 SIGNAL TXD2 : STD_LOGIC;
93 SIGNAL TXD2 : STD_LOGIC;
96 SIGNAL RXD2 : STD_LOGIC;
94 SIGNAL RXD2 : STD_LOGIC;
97 SIGNAL nCTS2 : STD_LOGIC;
95 SIGNAL nCTS2 : STD_LOGIC;
98 SIGNAL nDTR2 : STD_LOGIC;
96 SIGNAL nDTR2 : STD_LOGIC;
99 SIGNAL nRTS2 : STD_LOGIC;
97 SIGNAL nRTS2 : STD_LOGIC;
100 SIGNAL nDCD2 : STD_LOGIC;
98 SIGNAL nDCD2 : STD_LOGIC;
101 SIGNAL IO0 : STD_LOGIC;
99 SIGNAL IO0 : STD_LOGIC;
102 SIGNAL IO1 : STD_LOGIC;
100 SIGNAL IO1 : STD_LOGIC;
103 SIGNAL IO2 : STD_LOGIC;
101 SIGNAL IO2 : STD_LOGIC;
104 SIGNAL IO3 : STD_LOGIC;
102 SIGNAL IO3 : STD_LOGIC;
105 SIGNAL IO4 : STD_LOGIC;
103 SIGNAL IO4 : STD_LOGIC;
106 SIGNAL IO5 : STD_LOGIC;
104 SIGNAL IO5 : STD_LOGIC;
107 SIGNAL IO6 : STD_LOGIC;
105 SIGNAL IO6 : STD_LOGIC;
108 SIGNAL IO7 : STD_LOGIC;
106 SIGNAL IO7 : STD_LOGIC;
109 SIGNAL IO8 : STD_LOGIC;
107 SIGNAL IO8 : STD_LOGIC;
110 SIGNAL IO9 : STD_LOGIC;
108 SIGNAL IO9 : STD_LOGIC;
111 SIGNAL IO10 : STD_LOGIC;
109 SIGNAL IO10 : STD_LOGIC;
112 SIGNAL IO11 : STD_LOGIC;
110 SIGNAL IO11 : STD_LOGIC;
113 SIGNAL SPW_EN : STD_LOGIC;
111 SIGNAL SPW_EN : STD_LOGIC;
114 SIGNAL SPW_NOM_DIN : STD_LOGIC;
112 SIGNAL SPW_NOM_DIN : STD_LOGIC;
115 SIGNAL SPW_NOM_SIN : STD_LOGIC;
113 SIGNAL SPW_NOM_SIN : STD_LOGIC;
116 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
114 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
117 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
115 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
118 SIGNAL SPW_RED_DIN : STD_LOGIC;
116 SIGNAL SPW_RED_DIN : STD_LOGIC;
119 SIGNAL SPW_RED_SIN : STD_LOGIC;
117 SIGNAL SPW_RED_SIN : STD_LOGIC;
120 SIGNAL SPW_RED_DOUT : STD_LOGIC;
118 SIGNAL SPW_RED_DOUT : STD_LOGIC;
121 SIGNAL SPW_RED_SOUT : STD_LOGIC;
119 SIGNAL SPW_RED_SOUT : STD_LOGIC;
122 SIGNAL ADC_nCS : STD_LOGIC;
120 SIGNAL ADC_nCS : STD_LOGIC;
123 SIGNAL ADC_CLK : STD_LOGIC;
121 SIGNAL ADC_CLK : STD_LOGIC;
124 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
122 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
125 SIGNAL SRAM_nWE : STD_LOGIC;
123 SIGNAL SRAM_nWE : STD_LOGIC;
126 SIGNAL SRAM_CE : STD_LOGIC;
124 SIGNAL SRAM_CE : STD_LOGIC;
127 SIGNAL SRAM_nOE : STD_LOGIC;
125 SIGNAL SRAM_nOE : STD_LOGIC;
128 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
127 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
130 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
132
130
133 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
131 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
134 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
132 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
135 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
133 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
136
134
137
135
138 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
136 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
139
137
140 BEGIN
138 BEGIN
141
139
142 -----------------------------------------------------------------------------
140 -----------------------------------------------------------------------------
143 -- TB
141 -- TB
144 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
145 PROCESS
143 PROCESS
146 CONSTANT txp : TIME := 320 ns;
144 CONSTANT txp : TIME := 320 ns;
147 BEGIN -- PROCESS
145 BEGIN -- PROCESS
148 TXD1 <= '1';
146 TXD1 <= '1';
149 reset <= '0';
147 reset <= '0';
150 WAIT FOR 500 ns;
148 WAIT FOR 500 ns;
151 reset <= '1';
149 reset <= '1';
152 WAIT FOR 10000 ns;
150 WAIT FOR 10000 ns;
153 message_simu <= "0 - UART init ";
151 message_simu <= "0 - UART init ";
154 UART_INIT(TXD1,txp);
152 UART_INIT(TXD1,txp);
155
153
156 message_simu <= "1 - UART test ";
154 message_simu <= "1 - UART test ";
157 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
158 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
157 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
160
158
161 -- UNSET the LFR reset
159 -- UNSET the LFR reset
162 message_simu <= "2 - LFR UNRESET";
160 message_simu <= "2 - LFR UNRESET";
163 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
164 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
162 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
165 --
163 --
166 message_simu <= "3 - LFR CONFIG ";
164 message_simu <= "3 - LFR CONFIG ";
167 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
165 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
168
166
169 WAIT;
167 WAIT;
170 END PROCESS;
168 END PROCESS;
171
169
172 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
173 -- CLOCK
171 -- CLOCK
174 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
175 clk_50 <= NOT clk_50 AFTER 5 ns;
173 clk_50 <= NOT clk_50 AFTER 5 ns;
176 clk_49 <= NOT clk_49 AFTER 10172 ps;
174 clk_49 <= NOT clk_49 AFTER 10172 ps;
177
175
178 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
179 -- DON'T CARE
177 -- DON'T CARE
180 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
181 BP0 <= '0';
179 BP0 <= '0';
182 BP1 <= '0';
180 BP1 <= '0';
183 nRTS1 <= '0' ;
181 nRTS1 <= '0' ;
184
182
185 TXD2 <= '1';
183 TXD2 <= '1';
186 nRTS2 <= '1';
184 nRTS2 <= '1';
187 nDTR2 <= '1';
185 nDTR2 <= '1';
188
186
189 SPW_NOM_DIN <= '1';
187 SPW_NOM_DIN <= '1';
190 SPW_NOM_SIN <= '1';
188 SPW_NOM_SIN <= '1';
191 SPW_RED_DIN <= '1';
189 SPW_RED_DIN <= '1';
192 SPW_RED_SIN <= '1';
190 SPW_RED_SIN <= '1';
193
191
194 ADC_SDO <= x"AA";
192 ADC_SDO <= x"AA";
195
193
196 SRAM_DQ <= (OTHERS => 'Z');
194 SRAM_DQ <= (OTHERS => 'Z');
197 IO0 <= 'Z';
195 --IO0 <= 'Z';
198 IO1 <= 'Z';
196 --IO1 <= 'Z';
199 IO2 <= 'Z';
197 --IO2 <= 'Z';
200 IO3 <= 'Z';
198 --IO3 <= 'Z';
201 IO4 <= 'Z';
199 --IO4 <= 'Z';
202 IO5 <= 'Z';
200 --IO5 <= 'Z';
203 IO6 <= 'Z';
201 --IO6 <= 'Z';
204 IO7 <= 'Z';
202 --IO7 <= 'Z';
205 IO8 <= 'Z';
203 --IO8 <= 'Z';
206 IO9 <= 'Z';
204 --IO9 <= 'Z';
207 IO10 <= 'Z';
205 --IO10 <= 'Z';
208 IO11 <= 'Z';
206 --IO11 <= 'Z';
209
207
210 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
211 -- DUT
209 -- DUT
212 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
213 MINI_LFR_top_1: MINI_LFR_top
211 MINI_LFR_top_1: MINI_LFR_top
214 PORT MAP (
212 PORT MAP (
215 clk_50 => clk_50,
213 clk_50 => clk_50,
216 clk_49 => clk_49,
214 clk_49 => clk_49,
217 reset => reset,
215 reset => reset,
218
216
219 BP0 => BP0,
217 BP0 => BP0,
220 BP1 => BP1,
218 BP1 => BP1,
221
219
222 LED0 => LED0,
220 LED0 => LED0,
223 LED1 => LED1,
221 LED1 => LED1,
224 LED2 => LED2,
222 LED2 => LED2,
225
223
226 TXD1 => TXD1,
224 TXD1 => TXD1,
227 RXD1 => RXD1,
225 RXD1 => RXD1,
228 nCTS1 => nCTS1,
226 nCTS1 => nCTS1,
229 nRTS1 => nRTS1,
227 nRTS1 => nRTS1,
230
228
231 TXD2 => TXD2,
229 TXD2 => TXD2,
232 RXD2 => RXD2,
230 RXD2 => RXD2,
233 nCTS2 => nCTS2,
231 nCTS2 => nCTS2,
234 nDTR2 => nDTR2,
232 nDTR2 => nDTR2,
235 nRTS2 => nRTS2,
233 nRTS2 => nRTS2,
236 nDCD2 => nDCD2,
234 nDCD2 => nDCD2,
237
235
238 IO0 => IO0,
236 IO0 => IO0,
239 IO1 => IO1,
237 IO1 => IO1,
240 IO2 => IO2,
238 IO2 => IO2,
241 IO3 => IO3,
239 IO3 => IO3,
242 IO4 => IO4,
240 IO4 => IO4,
243 IO5 => IO5,
241 IO5 => IO5,
244 IO6 => IO6,
242 IO6 => IO6,
245 IO7 => IO7,
243 IO7 => IO7,
246 IO8 => IO8,
244 IO8 => IO8,
247 IO9 => IO9,
245 IO9 => IO9,
248 IO10 => IO10,
246 IO10 => IO10,
249 IO11 => IO11,
247 IO11 => IO11,
250
248
251 SPW_EN => SPW_EN,
249 SPW_EN => SPW_EN,
252 SPW_NOM_DIN => SPW_NOM_DIN,
250 SPW_NOM_DIN => SPW_NOM_DIN,
253 SPW_NOM_SIN => SPW_NOM_SIN,
251 SPW_NOM_SIN => SPW_NOM_SIN,
254 SPW_NOM_DOUT => SPW_NOM_DOUT,
252 SPW_NOM_DOUT => SPW_NOM_DOUT,
255 SPW_NOM_SOUT => SPW_NOM_SOUT,
253 SPW_NOM_SOUT => SPW_NOM_SOUT,
256 SPW_RED_DIN => SPW_RED_DIN,
254 SPW_RED_DIN => SPW_RED_DIN,
257 SPW_RED_SIN => SPW_RED_SIN,
255 SPW_RED_SIN => SPW_RED_SIN,
258 SPW_RED_DOUT => SPW_RED_DOUT,
256 SPW_RED_DOUT => SPW_RED_DOUT,
259 SPW_RED_SOUT => SPW_RED_SOUT,
257 SPW_RED_SOUT => SPW_RED_SOUT,
260
258
261 ADC_nCS => ADC_nCS,
259 ADC_nCS => ADC_nCS,
262 ADC_CLK => ADC_CLK,
260 ADC_CLK => ADC_CLK,
263 ADC_SDO => ADC_SDO,
261 ADC_SDO => ADC_SDO,
264
262
265 SRAM_nWE => SRAM_nWE,
263 SRAM_nWE => SRAM_nWE,
266 SRAM_CE => SRAM_CE,
264 SRAM_CE => SRAM_CE,
267 SRAM_nOE => SRAM_nOE,
265 SRAM_nOE => SRAM_nOE,
268 SRAM_nBE => SRAM_nBE,
266 SRAM_nBE => SRAM_nBE,
269 SRAM_A => SRAM_A,
267 SRAM_A => SRAM_A,
270 SRAM_DQ => SRAM_DQ);
268 SRAM_DQ => SRAM_DQ);
271
269
272
270
273 END;
271 END;
Show file before | Show file after | Hide comments
@@ -1,509 +1,519
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
30 delta_vector_size : INTEGER := 20;
30 delta_vector_size : INTEGER := 20;
31 delta_vector_size_f0_2 : INTEGER := 7;
31 delta_vector_size_f0_2 : INTEGER := 7;
32
32
33 pindex : INTEGER := 4;
33 pindex : INTEGER := 4;
34 paddr : INTEGER := 4;
34 paddr : INTEGER := 4;
35 pmask : INTEGER := 16#fff#;
35 pmask : INTEGER := 16#fff#;
36 pirq_ms : INTEGER := 0;
36 pirq_ms : INTEGER := 0;
37 pirq_wfp : INTEGER := 1;
37 pirq_wfp : INTEGER := 1;
38
38
39 hindex : INTEGER := 2;
39 hindex : INTEGER := 2;
40
40
41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42
42
43 );
43 );
44 PORT (
44 PORT (
45 clk : IN STD_LOGIC;
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 -- SAMPLE
47 -- SAMPLE
48 sample_B : IN Samples(2 DOWNTO 0);
48 sample_B : IN Samples(2 DOWNTO 0);
49 sample_E : IN Samples(4 DOWNTO 0);
49 sample_E : IN Samples(4 DOWNTO 0);
50 sample_val : IN STD_LOGIC;
50 sample_val : IN STD_LOGIC;
51 -- APB
51 -- APB
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 -- AHB
54 -- AHB
55 ahbi : IN AHB_Mst_In_Type;
55 ahbi : IN AHB_Mst_In_Type;
56 ahbo : OUT AHB_Mst_Out_Type;
56 ahbo : OUT AHB_Mst_Out_Type;
57 -- TIME
57 -- TIME
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 --
60 --
61 data_shaping_BW : OUT STD_LOGIC
61 data_shaping_BW : OUT STD_LOGIC;
62 --
63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
62 );
65 );
63 END lpp_lfr;
66 END lpp_lfr;
64
67
65 ARCHITECTURE beh OF lpp_lfr IS
68 ARCHITECTURE beh OF lpp_lfr IS
66 SIGNAL sample_s : Samples(7 DOWNTO 0);
69 SIGNAL sample_s : Samples(7 DOWNTO 0);
67 --
70 --
68 SIGNAL data_shaping_SP0 : STD_LOGIC;
71 SIGNAL data_shaping_SP0 : STD_LOGIC;
69 SIGNAL data_shaping_SP1 : STD_LOGIC;
72 SIGNAL data_shaping_SP1 : STD_LOGIC;
70 SIGNAL data_shaping_R0 : STD_LOGIC;
73 SIGNAL data_shaping_R0 : STD_LOGIC;
71 SIGNAL data_shaping_R1 : STD_LOGIC;
74 SIGNAL data_shaping_R1 : STD_LOGIC;
72 SIGNAL data_shaping_R2 : STD_LOGIC;
75 SIGNAL data_shaping_R2 : STD_LOGIC;
73 --
76 --
74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 --
80 --
78 SIGNAL sample_f0_val : STD_LOGIC;
81 SIGNAL sample_f0_val : STD_LOGIC;
79 SIGNAL sample_f1_val : STD_LOGIC;
82 SIGNAL sample_f1_val : STD_LOGIC;
80 SIGNAL sample_f2_val : STD_LOGIC;
83 SIGNAL sample_f2_val : STD_LOGIC;
81 SIGNAL sample_f3_val : STD_LOGIC;
84 SIGNAL sample_f3_val : STD_LOGIC;
82 --
85 --
83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 --
90 --
88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91
94
92 -- SM
95 -- SM
93 SIGNAL ready_matrix_f0 : STD_LOGIC;
96 SIGNAL ready_matrix_f0 : STD_LOGIC;
94 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
97 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 SIGNAL ready_matrix_f1 : STD_LOGIC;
98 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 SIGNAL ready_matrix_f2 : STD_LOGIC;
99 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
98 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
101 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
99 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
101 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
104 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
107 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
105 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
108 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
106 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
109 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
107
110
108 -- WFP
111 -- WFP
109 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
112 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
110 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115
118
116 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
120 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 SIGNAL enable_f0 : STD_LOGIC;
121 SIGNAL enable_f0 : STD_LOGIC;
119 SIGNAL enable_f1 : STD_LOGIC;
122 SIGNAL enable_f1 : STD_LOGIC;
120 SIGNAL enable_f2 : STD_LOGIC;
123 SIGNAL enable_f2 : STD_LOGIC;
121 SIGNAL enable_f3 : STD_LOGIC;
124 SIGNAL enable_f3 : STD_LOGIC;
122 SIGNAL burst_f0 : STD_LOGIC;
125 SIGNAL burst_f0 : STD_LOGIC;
123 SIGNAL burst_f1 : STD_LOGIC;
126 SIGNAL burst_f1 : STD_LOGIC;
124 SIGNAL burst_f2 : STD_LOGIC;
127 SIGNAL burst_f2 : STD_LOGIC;
125
128
126 --SIGNAL run : STD_LOGIC;
129 --SIGNAL run : STD_LOGIC;
127 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
130 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
128
131
129 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
130 --
133 --
131 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
132 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
136 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
134 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
137 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
135 --f1
138 --f1
136 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
140 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
138 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
141 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
139 --f2
142 --f2
140 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
144 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
142 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
145 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
143 --f3
146 --f3
144 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
148 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
146 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
149 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
147
150
148 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
152 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
150 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
153 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
151 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
155 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
153 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
155 -- DMA RR
158 -- DMA RR
156 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
157 -- SIGNAL dma_sel_valid : STD_LOGIC;
160 -- SIGNAL dma_sel_valid : STD_LOGIC;
158 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
162
165
163 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
165
168
166 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
167 -- DMA_REG
170 -- DMA_REG
168 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
169 -- SIGNAL ongoing_reg : STD_LOGIC;
172 -- SIGNAL ongoing_reg : STD_LOGIC;
170 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 -- SIGNAL dma_send_reg : STD_LOGIC;
174 -- SIGNAL dma_send_reg : STD_LOGIC;
172 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
175 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
173 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175
178
176
179
177 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
178 -- DMA
181 -- DMA
179 -----------------------------------------------------------------------------
182 -----------------------------------------------------------------------------
180 -- SIGNAL dma_send : STD_LOGIC;
183 -- SIGNAL dma_send : STD_LOGIC;
181 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
184 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 -- SIGNAL dma_done : STD_LOGIC;
185 -- SIGNAL dma_done : STD_LOGIC;
183 -- SIGNAL dma_ren : STD_LOGIC;
186 -- SIGNAL dma_ren : STD_LOGIC;
184 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187
190
188 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
189 -- MS
192 -- MS
190 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
191
194
192 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 -- SIGNAL data_ms_valid : STD_LOGIC;
197 -- SIGNAL data_ms_valid : STD_LOGIC;
195 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
198 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
196 -- SIGNAL data_ms_ren : STD_LOGIC;
199 -- SIGNAL data_ms_ren : STD_LOGIC;
197 -- SIGNAL data_ms_done : STD_LOGIC;
200 -- SIGNAL data_ms_done : STD_LOGIC;
198 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
201 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
199
202
200 -- SIGNAL run_ms : STD_LOGIC;
203 -- SIGNAL run_ms : STD_LOGIC;
201 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
204 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
202
205
203 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
206 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
208 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
206 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207
210
208
211
209 SIGNAL error_buffer_full : STD_LOGIC;
212 SIGNAL error_buffer_full : STD_LOGIC;
210 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
213 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
211
214
212 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
214
217
215 -----------------------------------------------------------------------------
218 -----------------------------------------------------------------------------
216 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
217 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
220 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
218 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
221 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
223 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
221 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
224 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
222 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
224 SIGNAL dma_grant_error : STD_LOGIC;
227 SIGNAL dma_grant_error : STD_LOGIC;
225
228
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
226 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
227 -- SIGNAL run_dma : STD_LOGIC;
231 -- SIGNAL run_dma : STD_LOGIC;
228 BEGIN
232 BEGIN
233
234 debug_vector <= apb_reg_debug_vector;
235 -----------------------------------------------------------------------------
229
236
230 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
237 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
231 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
238 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
232
239
233 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
240 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
234 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
241 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
235 --END GENERATE all_channel;
242 --END GENERATE all_channel;
236
243
237 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
238 lpp_lfr_filter_1 : lpp_lfr_filter
245 lpp_lfr_filter_1 : lpp_lfr_filter
239 GENERIC MAP (
246 GENERIC MAP (
240 Mem_use => Mem_use)
247 Mem_use => Mem_use)
241 PORT MAP (
248 PORT MAP (
242 sample => sample_s,
249 sample => sample_s,
243 sample_val => sample_val,
250 sample_val => sample_val,
244 clk => clk,
251 clk => clk,
245 rstn => rstn,
252 rstn => rstn,
246 data_shaping_SP0 => data_shaping_SP0,
253 data_shaping_SP0 => data_shaping_SP0,
247 data_shaping_SP1 => data_shaping_SP1,
254 data_shaping_SP1 => data_shaping_SP1,
248 data_shaping_R0 => data_shaping_R0,
255 data_shaping_R0 => data_shaping_R0,
249 data_shaping_R1 => data_shaping_R1,
256 data_shaping_R1 => data_shaping_R1,
250 data_shaping_R2 => data_shaping_R2,
257 data_shaping_R2 => data_shaping_R2,
251 sample_f0_val => sample_f0_val,
258 sample_f0_val => sample_f0_val,
252 sample_f1_val => sample_f1_val,
259 sample_f1_val => sample_f1_val,
253 sample_f2_val => sample_f2_val,
260 sample_f2_val => sample_f2_val,
254 sample_f3_val => sample_f3_val,
261 sample_f3_val => sample_f3_val,
255 sample_f0_wdata => sample_f0_data,
262 sample_f0_wdata => sample_f0_data,
256 sample_f1_wdata => sample_f1_data,
263 sample_f1_wdata => sample_f1_data,
257 sample_f2_wdata => sample_f2_data,
264 sample_f2_wdata => sample_f2_data,
258 sample_f3_wdata => sample_f3_data);
265 sample_f3_wdata => sample_f3_data);
259
266
260 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
261 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
268 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
262 GENERIC MAP (
269 GENERIC MAP (
263 nb_data_by_buffer_size => nb_data_by_buffer_size,
270 nb_data_by_buffer_size => nb_data_by_buffer_size,
264 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
271 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
265 nb_snapshot_param_size => nb_snapshot_param_size,
272 nb_snapshot_param_size => nb_snapshot_param_size,
266 delta_vector_size => delta_vector_size,
273 delta_vector_size => delta_vector_size,
267 delta_vector_size_f0_2 => delta_vector_size_f0_2,
274 delta_vector_size_f0_2 => delta_vector_size_f0_2,
268 pindex => pindex,
275 pindex => pindex,
269 paddr => paddr,
276 paddr => paddr,
270 pmask => pmask,
277 pmask => pmask,
271 pirq_ms => pirq_ms,
278 pirq_ms => pirq_ms,
272 pirq_wfp => pirq_wfp,
279 pirq_wfp => pirq_wfp,
273 top_lfr_version => top_lfr_version)
280 top_lfr_version => top_lfr_version)
274 PORT MAP (
281 PORT MAP (
275 HCLK => clk,
282 HCLK => clk,
276 HRESETn => rstn,
283 HRESETn => rstn,
277 apbi => apbi,
284 apbi => apbi,
278 apbo => apbo,
285 apbo => apbo,
279
286
280 run_ms => OPEN,--run_ms,
287 run_ms => OPEN,--run_ms,
281
288
282 ready_matrix_f0 => ready_matrix_f0,
289 ready_matrix_f0 => ready_matrix_f0,
283 ready_matrix_f1 => ready_matrix_f1,
290 ready_matrix_f1 => ready_matrix_f1,
284 ready_matrix_f2 => ready_matrix_f2,
291 ready_matrix_f2 => ready_matrix_f2,
285 error_buffer_full => error_buffer_full, -- TODO
292 error_buffer_full => error_buffer_full, -- TODO
286 error_input_fifo_write => error_input_fifo_write, -- TODO
293 error_input_fifo_write => error_input_fifo_write, -- TODO
287 status_ready_matrix_f0 => status_ready_matrix_f0,
294 status_ready_matrix_f0 => status_ready_matrix_f0,
288 status_ready_matrix_f1 => status_ready_matrix_f1,
295 status_ready_matrix_f1 => status_ready_matrix_f1,
289 status_ready_matrix_f2 => status_ready_matrix_f2,
296 status_ready_matrix_f2 => status_ready_matrix_f2,
290
297
291 matrix_time_f0 => matrix_time_f0,
298 matrix_time_f0 => matrix_time_f0,
292 matrix_time_f1 => matrix_time_f1,
299 matrix_time_f1 => matrix_time_f1,
293 matrix_time_f2 => matrix_time_f2,
300 matrix_time_f2 => matrix_time_f2,
294
301
295 addr_matrix_f0 => addr_matrix_f0,
302 addr_matrix_f0 => addr_matrix_f0,
296 addr_matrix_f1 => addr_matrix_f1,
303 addr_matrix_f1 => addr_matrix_f1,
297 addr_matrix_f2 => addr_matrix_f2,
304 addr_matrix_f2 => addr_matrix_f2,
298
305
299 length_matrix_f0 => length_matrix_f0,
306 length_matrix_f0 => length_matrix_f0,
300 length_matrix_f1 => length_matrix_f1,
307 length_matrix_f1 => length_matrix_f1,
301 length_matrix_f2 => length_matrix_f2,
308 length_matrix_f2 => length_matrix_f2,
302 -------------------------------------------------------------------------
309 -------------------------------------------------------------------------
303 --status_full => status_full, -- TODo
310 --status_full => status_full, -- TODo
304 --status_full_ack => status_full_ack, -- TODo
311 --status_full_ack => status_full_ack, -- TODo
305 --status_full_err => status_full_err, -- TODo
312 --status_full_err => status_full_err, -- TODo
306 status_new_err => status_new_err,
313 status_new_err => status_new_err,
307 data_shaping_BW => data_shaping_BW,
314 data_shaping_BW => data_shaping_BW,
308 data_shaping_SP0 => data_shaping_SP0,
315 data_shaping_SP0 => data_shaping_SP0,
309 data_shaping_SP1 => data_shaping_SP1,
316 data_shaping_SP1 => data_shaping_SP1,
310 data_shaping_R0 => data_shaping_R0,
317 data_shaping_R0 => data_shaping_R0,
311 data_shaping_R1 => data_shaping_R1,
318 data_shaping_R1 => data_shaping_R1,
312 data_shaping_R2 => data_shaping_R2,
319 data_shaping_R2 => data_shaping_R2,
313 delta_snapshot => delta_snapshot,
320 delta_snapshot => delta_snapshot,
314 delta_f0 => delta_f0,
321 delta_f0 => delta_f0,
315 delta_f0_2 => delta_f0_2,
322 delta_f0_2 => delta_f0_2,
316 delta_f1 => delta_f1,
323 delta_f1 => delta_f1,
317 delta_f2 => delta_f2,
324 delta_f2 => delta_f2,
318 nb_data_by_buffer => nb_data_by_buffer,
325 nb_data_by_buffer => nb_data_by_buffer,
319 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
326 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
320 nb_snapshot_param => nb_snapshot_param,
327 nb_snapshot_param => nb_snapshot_param,
321 enable_f0 => enable_f0,
328 enable_f0 => enable_f0,
322 enable_f1 => enable_f1,
329 enable_f1 => enable_f1,
323 enable_f2 => enable_f2,
330 enable_f2 => enable_f2,
324 enable_f3 => enable_f3,
331 enable_f3 => enable_f3,
325 burst_f0 => burst_f0,
332 burst_f0 => burst_f0,
326 burst_f1 => burst_f1,
333 burst_f1 => burst_f1,
327 burst_f2 => burst_f2,
334 burst_f2 => burst_f2,
328 run => OPEN, --run,
335 run => OPEN, --run,
329 start_date => start_date,
336 start_date => start_date,
330 -- debug_signal => debug_signal,
337 -- debug_signal => debug_signal,
331 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
338 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
332 wfp_addr_buffer => wfp_addr_buffer,-- TODO
339 wfp_addr_buffer => wfp_addr_buffer,-- TODO
333 wfp_length_buffer => wfp_length_buffer,-- TODO
340 wfp_length_buffer => wfp_length_buffer,-- TODO
334
341
335 wfp_ready_buffer => wfp_ready_buffer,-- TODO
342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
336 wfp_buffer_time => wfp_buffer_time,-- TODO
343 wfp_buffer_time => wfp_buffer_time,-- TODO
337 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
345 debug_vector => apb_reg_debug_vector
338 );
346 );
339
347
340 -----------------------------------------------------------------------------
348 -----------------------------------------------------------------------------
341 -----------------------------------------------------------------------------
349 -----------------------------------------------------------------------------
342 lpp_waveform_1 : lpp_waveform
350 lpp_waveform_1 : lpp_waveform
343 GENERIC MAP (
351 GENERIC MAP (
344 tech => inferred,
352 tech => inferred,
345 data_size => 6*16,
353 data_size => 6*16,
346 nb_data_by_buffer_size => nb_data_by_buffer_size,
354 nb_data_by_buffer_size => nb_data_by_buffer_size,
347 nb_snapshot_param_size => nb_snapshot_param_size,
355 nb_snapshot_param_size => nb_snapshot_param_size,
348 delta_vector_size => delta_vector_size,
356 delta_vector_size => delta_vector_size,
349 delta_vector_size_f0_2 => delta_vector_size_f0_2
357 delta_vector_size_f0_2 => delta_vector_size_f0_2
350 )
358 )
351 PORT MAP (
359 PORT MAP (
352 clk => clk,
360 clk => clk,
353 rstn => rstn,
361 rstn => rstn,
354
362
355 reg_run => '1',--run,
363 reg_run => '1',--run,
356 reg_start_date => start_date,
364 reg_start_date => start_date,
357 reg_delta_snapshot => delta_snapshot,
365 reg_delta_snapshot => delta_snapshot,
358 reg_delta_f0 => delta_f0,
366 reg_delta_f0 => delta_f0,
359 reg_delta_f0_2 => delta_f0_2,
367 reg_delta_f0_2 => delta_f0_2,
360 reg_delta_f1 => delta_f1,
368 reg_delta_f1 => delta_f1,
361 reg_delta_f2 => delta_f2,
369 reg_delta_f2 => delta_f2,
362
370
363 enable_f0 => enable_f0,
371 enable_f0 => enable_f0,
364 enable_f1 => enable_f1,
372 enable_f1 => enable_f1,
365 enable_f2 => enable_f2,
373 enable_f2 => enable_f2,
366 enable_f3 => enable_f3,
374 enable_f3 => enable_f3,
367 burst_f0 => burst_f0,
375 burst_f0 => burst_f0,
368 burst_f1 => burst_f1,
376 burst_f1 => burst_f1,
369 burst_f2 => burst_f2,
377 burst_f2 => burst_f2,
370
378
371 nb_data_by_buffer => nb_data_by_buffer,
379 nb_data_by_buffer => nb_data_by_buffer,
372 nb_snapshot_param => nb_snapshot_param,
380 nb_snapshot_param => nb_snapshot_param,
373 status_new_err => status_new_err,
381 status_new_err => status_new_err,
374
382
375 status_buffer_ready => wfp_status_buffer_ready,
383 status_buffer_ready => wfp_status_buffer_ready,
376 addr_buffer => wfp_addr_buffer,
384 addr_buffer => wfp_addr_buffer,
377 length_buffer => wfp_length_buffer,
385 length_buffer => wfp_length_buffer,
378 ready_buffer => wfp_ready_buffer,
386 ready_buffer => wfp_ready_buffer,
379 buffer_time => wfp_buffer_time,
387 buffer_time => wfp_buffer_time,
380 error_buffer_full => wfp_error_buffer_full,
388 error_buffer_full => wfp_error_buffer_full,
381
389
382 coarse_time => coarse_time,
390 coarse_time => coarse_time,
383 fine_time => fine_time,
391 fine_time => fine_time,
384
392
385 --f0
393 --f0
386 data_f0_in_valid => sample_f0_val,
394 data_f0_in_valid => sample_f0_val,
387 data_f0_in => sample_f0_data,
395 data_f0_in => sample_f0_data,
388 --f1
396 --f1
389 data_f1_in_valid => sample_f1_val,
397 data_f1_in_valid => sample_f1_val,
390 data_f1_in => sample_f1_data,
398 data_f1_in => sample_f1_data,
391 --f2
399 --f2
392 data_f2_in_valid => sample_f2_val,
400 data_f2_in_valid => sample_f2_val,
393 data_f2_in => sample_f2_data,
401 data_f2_in => sample_f2_data,
394 --f3
402 --f3
395 data_f3_in_valid => sample_f3_val,
403 data_f3_in_valid => sample_f3_val,
396 data_f3_in => sample_f3_data,
404 data_f3_in => sample_f3_data,
397 -- OUTPUT -- DMA interface
405 -- OUTPUT -- DMA interface
398
406
399 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
407 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
400 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
408 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
401 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
409 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
402 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
410 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
403 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
411 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
404 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
412 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
405 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
413 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
406 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
414 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
407
415
408 );
416 );
409
417
410 -----------------------------------------------------------------------------
418 -----------------------------------------------------------------------------
411 -- Matrix Spectral
419 -- Matrix Spectral
412 -----------------------------------------------------------------------------
420 -----------------------------------------------------------------------------
413 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
421 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
414 NOT(sample_f0_val) & NOT(sample_f0_val);
422 NOT(sample_f0_val) & NOT(sample_f0_val);
415 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
423 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
416 NOT(sample_f1_val) & NOT(sample_f1_val);
424 NOT(sample_f1_val) & NOT(sample_f1_val);
417 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
425 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
418 NOT(sample_f2_val) & NOT(sample_f2_val);
426 NOT(sample_f2_val) & NOT(sample_f2_val);
419
427
420 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
428 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
421 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
429 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
422 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
430 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
423
431
424 -------------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
425
433
426 --ms_softandhard_rstn <= rstn AND run_ms AND run;
434 --ms_softandhard_rstn <= rstn AND run_ms AND run;
427
435
428 -----------------------------------------------------------------------------
436 -----------------------------------------------------------------------------
429 lpp_lfr_ms_1 : lpp_lfr_ms
437 lpp_lfr_ms_1 : lpp_lfr_ms
430 GENERIC MAP (
438 GENERIC MAP (
431 Mem_use => Mem_use)
439 Mem_use => Mem_use)
432 PORT MAP (
440 PORT MAP (
433 clk => clk,
441 clk => clk,
434 --rstn => ms_softandhard_rstn, --rstn,
442 --rstn => ms_softandhard_rstn, --rstn,
435 rstn => rstn,
443 rstn => rstn,
436
444
437 run => '1',--run_ms,
445 run => '1',--run_ms,
438
446
439 start_date => start_date,
447 start_date => start_date,
440
448
441 coarse_time => coarse_time,
449 coarse_time => coarse_time,
442 fine_time => fine_time,
450 fine_time => fine_time,
443
451
444 sample_f0_wen => sample_f0_wen,
452 sample_f0_wen => sample_f0_wen,
445 sample_f0_wdata => sample_f0_wdata,
453 sample_f0_wdata => sample_f0_wdata,
446 sample_f1_wen => sample_f1_wen,
454 sample_f1_wen => sample_f1_wen,
447 sample_f1_wdata => sample_f1_wdata,
455 sample_f1_wdata => sample_f1_wdata,
448 sample_f2_wen => sample_f2_wen,
456 sample_f2_wen => sample_f2_wen,
449 sample_f2_wdata => sample_f2_wdata,
457 sample_f2_wdata => sample_f2_wdata,
450
458
451 --DMA
459 --DMA
452 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
460 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
453 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
461 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
454 dma_fifo_ren => dma_fifo_ren(4), -- IN
462 dma_fifo_ren => dma_fifo_ren(4), -- IN
455 dma_buffer_new => dma_buffer_new(4), -- OUT
463 dma_buffer_new => dma_buffer_new(4), -- OUT
456 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
464 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
457 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
465 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
458 dma_buffer_full => dma_buffer_full(4), -- IN
466 dma_buffer_full => dma_buffer_full(4), -- IN
459 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
467 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
460
468
461
469
462
470
463 --REG
471 --REG
464 ready_matrix_f0 => ready_matrix_f0,
472 ready_matrix_f0 => ready_matrix_f0,
465 ready_matrix_f1 => ready_matrix_f1,
473 ready_matrix_f1 => ready_matrix_f1,
466 ready_matrix_f2 => ready_matrix_f2,
474 ready_matrix_f2 => ready_matrix_f2,
467 error_buffer_full => error_buffer_full,
475 error_buffer_full => error_buffer_full,
468 error_input_fifo_write => error_input_fifo_write,
476 error_input_fifo_write => error_input_fifo_write,
469
477
470 status_ready_matrix_f0 => status_ready_matrix_f0,
478 status_ready_matrix_f0 => status_ready_matrix_f0,
471 status_ready_matrix_f1 => status_ready_matrix_f1,
479 status_ready_matrix_f1 => status_ready_matrix_f1,
472 status_ready_matrix_f2 => status_ready_matrix_f2,
480 status_ready_matrix_f2 => status_ready_matrix_f2,
473 addr_matrix_f0 => addr_matrix_f0,
481 addr_matrix_f0 => addr_matrix_f0,
474 addr_matrix_f1 => addr_matrix_f1,
482 addr_matrix_f1 => addr_matrix_f1,
475 addr_matrix_f2 => addr_matrix_f2,
483 addr_matrix_f2 => addr_matrix_f2,
476
484
477 length_matrix_f0 => length_matrix_f0,
485 length_matrix_f0 => length_matrix_f0,
478 length_matrix_f1 => length_matrix_f1,
486 length_matrix_f1 => length_matrix_f1,
479 length_matrix_f2 => length_matrix_f2,
487 length_matrix_f2 => length_matrix_f2,
480
488
481 matrix_time_f0 => matrix_time_f0,
489 matrix_time_f0 => matrix_time_f0,
482 matrix_time_f1 => matrix_time_f1,
490 matrix_time_f1 => matrix_time_f1,
483 matrix_time_f2 => matrix_time_f2);
491 matrix_time_f2 => matrix_time_f2,
492
493 debug_vector => debug_vector_ms);
484
494
485 -----------------------------------------------------------------------------
495 -----------------------------------------------------------------------------
486 --run_dma <= run_ms OR run;
496 --run_dma <= run_ms OR run;
487
497
488 DMA_SubSystem_1 : DMA_SubSystem
498 DMA_SubSystem_1 : DMA_SubSystem
489 GENERIC MAP (
499 GENERIC MAP (
490 hindex => hindex)
500 hindex => hindex)
491 PORT MAP (
501 PORT MAP (
492 clk => clk,
502 clk => clk,
493 rstn => rstn,
503 rstn => rstn,
494 run => '1',--run_dma,
504 run => '1',--run_dma,
495 ahbi => ahbi,
505 ahbi => ahbi,
496 ahbo => ahbo,
506 ahbo => ahbo,
497
507
498 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
508 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
499 fifo_data => dma_fifo_data, --fifo_data,
509 fifo_data => dma_fifo_data, --fifo_data,
500 fifo_ren => dma_fifo_ren, --fifo_ren,
510 fifo_ren => dma_fifo_ren, --fifo_ren,
501
511
502 buffer_new => dma_buffer_new, --buffer_new,
512 buffer_new => dma_buffer_new, --buffer_new,
503 buffer_addr => dma_buffer_addr, --buffer_addr,
513 buffer_addr => dma_buffer_addr, --buffer_addr,
504 buffer_length => dma_buffer_length, --buffer_length,
514 buffer_length => dma_buffer_length, --buffer_length,
505 buffer_full => dma_buffer_full, --buffer_full,
515 buffer_full => dma_buffer_full, --buffer_full,
506 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
516 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
507 grant_error => dma_grant_error); --grant_error);
517 grant_error => dma_grant_error); --grant_error);
508
518
509 END beh;
519 END beh;
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@@ -1,781 +1,792
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31
31
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_pkg.ALL;
33 USE lpp.lpp_lfr_pkg.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_lfr_apbreg IS
41 ENTITY lpp_lfr_apbreg IS
42 GENERIC (
42 GENERIC (
43 nb_data_by_buffer_size : INTEGER := 11;
43 nb_data_by_buffer_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
45 delta_vector_size : INTEGER := 20;
45 delta_vector_size : INTEGER := 20;
46 delta_vector_size_f0_2 : INTEGER := 3;
46 delta_vector_size_f0_2 : INTEGER := 3;
47
47
48 pindex : INTEGER := 4;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
49 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
50 pmask : INTEGER := 16#fff#;
51 pirq_ms : INTEGER := 0;
51 pirq_ms : INTEGER := 0;
52 pirq_wfp : INTEGER := 1;
52 pirq_wfp : INTEGER := 1;
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 PORT (
54 PORT (
55 -- AMBA AHB system signals
55 -- AMBA AHB system signals
56 HCLK : IN STD_ULOGIC;
56 HCLK : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
58
58
59 -- AMBA APB Slave Interface
59 -- AMBA APB Slave Interface
60 apbi : IN apb_slv_in_type;
60 apbi : IN apb_slv_in_type;
61 apbo : OUT apb_slv_out_type;
61 apbo : OUT apb_slv_out_type;
62
62
63 ---------------------------------------------------------------------------
63 ---------------------------------------------------------------------------
64 -- Spectral Matrix Reg
64 -- Spectral Matrix Reg
65 run_ms : OUT STD_LOGIC;
65 run_ms : OUT STD_LOGIC;
66 -- IN
66 -- IN
67 ready_matrix_f0 : IN STD_LOGIC;
67 ready_matrix_f0 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
70
70
71 -- error_bad_component_error : IN STD_LOGIC;
71 -- error_bad_component_error : IN STD_LOGIC;
72 error_buffer_full : IN STD_LOGIC; -- TODO
72 error_buffer_full : IN STD_LOGIC; -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74
74
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76
76
77 -- OUT
77 -- OUT
78 status_ready_matrix_f0 : OUT STD_LOGIC;
78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
81
81
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
84
84
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88
88
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92
92
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96
96
97 ---------------------------------------------------------------------------
97 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 -- WaveForm picker Reg
99 -- WaveForm picker Reg
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104
104
105 -- OUT
105 -- OUT
106 data_shaping_BW : OUT STD_LOGIC;
106 data_shaping_BW : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
112
112
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121
121
122 enable_f0 : OUT STD_LOGIC;
122 enable_f0 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
126
126
127 burst_f0 : OUT STD_LOGIC;
127 burst_f0 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
130
130
131 run : OUT STD_LOGIC;
131 run : OUT STD_LOGIC;
132
132
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134
134
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
142 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
141
143
142 );
144 );
143
145
144 END lpp_lfr_apbreg;
146 END lpp_lfr_apbreg;
145
147
146 ARCHITECTURE beh OF lpp_lfr_apbreg IS
148 ARCHITECTURE beh OF lpp_lfr_apbreg IS
147
149
148 CONSTANT REVISION : INTEGER := 1;
150 CONSTANT REVISION : INTEGER := 1;
149
151
150 CONSTANT pconfig : apb_config_type := (
152 CONSTANT pconfig : apb_config_type := (
151 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
153 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
152 1 => apb_iobar(paddr, pmask));
154 1 => apb_iobar(paddr, pmask));
153
155
154 --CONSTANT pconfig : apb_config_type := (
156 --CONSTANT pconfig : apb_config_type := (
155 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
157 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
156 -- 1 => apb_iobar(paddr, pmask));
158 -- 1 => apb_iobar(paddr, pmask));
157
159
158 TYPE lpp_SpectralMatrix_regs IS RECORD
160 TYPE lpp_SpectralMatrix_regs IS RECORD
159 config_active_interruption_onNewMatrix : STD_LOGIC;
161 config_active_interruption_onNewMatrix : STD_LOGIC;
160 config_active_interruption_onError : STD_LOGIC;
162 config_active_interruption_onError : STD_LOGIC;
161 config_ms_run : STD_LOGIC;
163 config_ms_run : STD_LOGIC;
162 status_ready_matrix_f0_0 : STD_LOGIC;
164 status_ready_matrix_f0_0 : STD_LOGIC;
163 status_ready_matrix_f1_0 : STD_LOGIC;
165 status_ready_matrix_f1_0 : STD_LOGIC;
164 status_ready_matrix_f2_0 : STD_LOGIC;
166 status_ready_matrix_f2_0 : STD_LOGIC;
165 status_ready_matrix_f0_1 : STD_LOGIC;
167 status_ready_matrix_f0_1 : STD_LOGIC;
166 status_ready_matrix_f1_1 : STD_LOGIC;
168 status_ready_matrix_f1_1 : STD_LOGIC;
167 status_ready_matrix_f2_1 : STD_LOGIC;
169 status_ready_matrix_f2_1 : STD_LOGIC;
168 -- status_error_bad_component_error : STD_LOGIC;
170 -- status_error_bad_component_error : STD_LOGIC;
169 status_error_buffer_full : STD_LOGIC;
171 status_error_buffer_full : STD_LOGIC;
170 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
172 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
171
173
172 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178
180
179 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
181 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
180
182
181 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
183 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
182 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
183 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
185 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
185 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 END RECORD;
189 END RECORD;
188 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
190 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
189
191
190 TYPE lpp_WaveformPicker_regs IS RECORD
192 TYPE lpp_WaveformPicker_regs IS RECORD
191 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 data_shaping_BW : STD_LOGIC;
196 data_shaping_BW : STD_LOGIC;
195 data_shaping_SP0 : STD_LOGIC;
197 data_shaping_SP0 : STD_LOGIC;
196 data_shaping_SP1 : STD_LOGIC;
198 data_shaping_SP1 : STD_LOGIC;
197 data_shaping_R0 : STD_LOGIC;
199 data_shaping_R0 : STD_LOGIC;
198 data_shaping_R1 : STD_LOGIC;
200 data_shaping_R1 : STD_LOGIC;
199 data_shaping_R2 : STD_LOGIC;
201 data_shaping_R2 : STD_LOGIC;
200 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
202 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
201 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
203 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
202 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
204 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
203 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
205 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
204 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
206 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
205 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
207 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
206 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
208 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
207 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
209 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
208 enable_f0 : STD_LOGIC;
210 enable_f0 : STD_LOGIC;
209 enable_f1 : STD_LOGIC;
211 enable_f1 : STD_LOGIC;
210 enable_f2 : STD_LOGIC;
212 enable_f2 : STD_LOGIC;
211 enable_f3 : STD_LOGIC;
213 enable_f3 : STD_LOGIC;
212 burst_f0 : STD_LOGIC;
214 burst_f0 : STD_LOGIC;
213 burst_f1 : STD_LOGIC;
215 burst_f1 : STD_LOGIC;
214 burst_f2 : STD_LOGIC;
216 burst_f2 : STD_LOGIC;
215 run : STD_LOGIC;
217 run : STD_LOGIC;
216 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
218 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
217 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
219 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
218 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
220 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
219 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
221 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
220 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
222 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
221 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
223 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
222 END RECORD;
224 END RECORD;
223 SIGNAL reg_wp : lpp_WaveformPicker_regs;
225 SIGNAL reg_wp : lpp_WaveformPicker_regs;
224
226
225 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
227 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
226
228
227 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
228 -- IRQ
230 -- IRQ
229 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
230 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
232 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
231 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
233 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
232 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
234 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
233 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
235 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
234 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
236 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
235 SIGNAL ored_irq_wfp : STD_LOGIC;
237 SIGNAL ored_irq_wfp : STD_LOGIC;
236
238
237 -----------------------------------------------------------------------------
239 -----------------------------------------------------------------------------
238 --
240 --
239 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
240 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
242 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
241 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243
245
244 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
246 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
245 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
248 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247
249
248 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
250 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
249 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
252 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
251
253
252 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
254 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
253 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
256 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
255
257
256 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
258 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
257 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
260 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
259
261
260 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
262 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
261 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
264 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 SIGNAL apbo_irq_ms : STD_LOGIC;
265 SIGNAL apbo_irq_ms : STD_LOGIC;
264 SIGNAL apbo_irq_wfp : STD_LOGIC;
266 SIGNAL apbo_irq_wfp : STD_LOGIC;
265 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
266 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
268 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
267
269
268 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
269
271
270 BEGIN -- beh
272 BEGIN -- beh
271
273
274 debug_vector(0) <= error_buffer_full;
275 debug_vector(1) <= reg_sp.status_error_buffer_full;
276 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
277 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
278 debug_vector(8) <= ready_matrix_f2;
279 debug_vector(9) <= reg0_ready_matrix_f2;
280 debug_vector(10) <= reg1_ready_matrix_f2;
281 debug_vector(11) <= HRESETn;
282
272 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
283 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
273 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
284 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
274 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
285 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
275
286
276 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
287 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
277 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
288 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
278
289
279
290
280 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
291 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
281 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
292 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
282 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
293 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
283
294
284
295
285 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
296 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
286 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
297 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
287 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
298 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
288 data_shaping_R0 <= reg_wp.data_shaping_R0;
299 data_shaping_R0 <= reg_wp.data_shaping_R0;
289 data_shaping_R1 <= reg_wp.data_shaping_R1;
300 data_shaping_R1 <= reg_wp.data_shaping_R1;
290 data_shaping_R2 <= reg_wp.data_shaping_R2;
301 data_shaping_R2 <= reg_wp.data_shaping_R2;
291
302
292 delta_snapshot <= reg_wp.delta_snapshot;
303 delta_snapshot <= reg_wp.delta_snapshot;
293 delta_f0 <= reg_wp.delta_f0;
304 delta_f0 <= reg_wp.delta_f0;
294 delta_f0_2 <= reg_wp.delta_f0_2;
305 delta_f0_2 <= reg_wp.delta_f0_2;
295 delta_f1 <= reg_wp.delta_f1;
306 delta_f1 <= reg_wp.delta_f1;
296 delta_f2 <= reg_wp.delta_f2;
307 delta_f2 <= reg_wp.delta_f2;
297 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
308 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
298 nb_snapshot_param <= reg_wp.nb_snapshot_param;
309 nb_snapshot_param <= reg_wp.nb_snapshot_param;
299
310
300 enable_f0 <= reg_wp.enable_f0;
311 enable_f0 <= reg_wp.enable_f0;
301 enable_f1 <= reg_wp.enable_f1;
312 enable_f1 <= reg_wp.enable_f1;
302 enable_f2 <= reg_wp.enable_f2;
313 enable_f2 <= reg_wp.enable_f2;
303 enable_f3 <= reg_wp.enable_f3;
314 enable_f3 <= reg_wp.enable_f3;
304
315
305 burst_f0 <= reg_wp.burst_f0;
316 burst_f0 <= reg_wp.burst_f0;
306 burst_f1 <= reg_wp.burst_f1;
317 burst_f1 <= reg_wp.burst_f1;
307 burst_f2 <= reg_wp.burst_f2;
318 burst_f2 <= reg_wp.burst_f2;
308
319
309 run <= reg_wp.run;
320 run <= reg_wp.run;
310
321
311 --addr_data_f0 <= reg_wp.addr_data_f0;
322 --addr_data_f0 <= reg_wp.addr_data_f0;
312 --addr_data_f1 <= reg_wp.addr_data_f1;
323 --addr_data_f1 <= reg_wp.addr_data_f1;
313 --addr_data_f2 <= reg_wp.addr_data_f2;
324 --addr_data_f2 <= reg_wp.addr_data_f2;
314 --addr_data_f3 <= reg_wp.addr_data_f3;
325 --addr_data_f3 <= reg_wp.addr_data_f3;
315
326
316 start_date <= reg_wp.start_date;
327 start_date <= reg_wp.start_date;
317
328
318 length_matrix_f0 <= reg_sp.length_matrix;
329 length_matrix_f0 <= reg_sp.length_matrix;
319 length_matrix_f1 <= reg_sp.length_matrix;
330 length_matrix_f1 <= reg_sp.length_matrix;
320 length_matrix_f2 <= reg_sp.length_matrix;
331 length_matrix_f2 <= reg_sp.length_matrix;
321 wfp_length_buffer <= reg_wp.length_buffer;
332 wfp_length_buffer <= reg_wp.length_buffer;
322
333
323
334
324 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
335 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
325 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
336 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
326 BEGIN -- PROCESS lpp_dma_top
337 BEGIN -- PROCESS lpp_dma_top
327 IF HRESETn = '0' THEN -- asynchronous reset (active low)
338 IF HRESETn = '0' THEN -- asynchronous reset (active low)
328 reg_sp.config_active_interruption_onNewMatrix <= '0';
339 reg_sp.config_active_interruption_onNewMatrix <= '0';
329 reg_sp.config_active_interruption_onError <= '0';
340 reg_sp.config_active_interruption_onError <= '0';
330 reg_sp.config_ms_run <= '0';
341 reg_sp.config_ms_run <= '0';
331 reg_sp.status_ready_matrix_f0_0 <= '0';
342 reg_sp.status_ready_matrix_f0_0 <= '0';
332 reg_sp.status_ready_matrix_f1_0 <= '0';
343 reg_sp.status_ready_matrix_f1_0 <= '0';
333 reg_sp.status_ready_matrix_f2_0 <= '0';
344 reg_sp.status_ready_matrix_f2_0 <= '0';
334 reg_sp.status_ready_matrix_f0_1 <= '0';
345 reg_sp.status_ready_matrix_f0_1 <= '0';
335 reg_sp.status_ready_matrix_f1_1 <= '0';
346 reg_sp.status_ready_matrix_f1_1 <= '0';
336 reg_sp.status_ready_matrix_f2_1 <= '0';
347 reg_sp.status_ready_matrix_f2_1 <= '0';
337 reg_sp.status_error_buffer_full <= '0';
348 reg_sp.status_error_buffer_full <= '0';
338 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
349 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
339
350
340 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
351 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
341 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
352 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
342 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
353 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
343
354
344 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
355 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
345 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
356 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
346 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
357 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
347
358
348 reg_sp.length_matrix <= (OTHERS => '0');
359 reg_sp.length_matrix <= (OTHERS => '0');
349
360
350 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
361 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
351 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
362 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
352 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
363 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
353
364
354 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
365 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
355 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
366 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
356 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
367 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
357
368
358 prdata <= (OTHERS => '0');
369 prdata <= (OTHERS => '0');
359
370
360
371
361 apbo_irq_ms <= '0';
372 apbo_irq_ms <= '0';
362 apbo_irq_wfp <= '0';
373 apbo_irq_wfp <= '0';
363
374
364
375
365 -- status_full_ack <= (OTHERS => '0');
376 -- status_full_ack <= (OTHERS => '0');
366
377
367 reg_wp.data_shaping_BW <= '0';
378 reg_wp.data_shaping_BW <= '0';
368 reg_wp.data_shaping_SP0 <= '0';
379 reg_wp.data_shaping_SP0 <= '0';
369 reg_wp.data_shaping_SP1 <= '0';
380 reg_wp.data_shaping_SP1 <= '0';
370 reg_wp.data_shaping_R0 <= '0';
381 reg_wp.data_shaping_R0 <= '0';
371 reg_wp.data_shaping_R1 <= '0';
382 reg_wp.data_shaping_R1 <= '0';
372 reg_wp.data_shaping_R2 <= '0';
383 reg_wp.data_shaping_R2 <= '0';
373 reg_wp.enable_f0 <= '0';
384 reg_wp.enable_f0 <= '0';
374 reg_wp.enable_f1 <= '0';
385 reg_wp.enable_f1 <= '0';
375 reg_wp.enable_f2 <= '0';
386 reg_wp.enable_f2 <= '0';
376 reg_wp.enable_f3 <= '0';
387 reg_wp.enable_f3 <= '0';
377 reg_wp.burst_f0 <= '0';
388 reg_wp.burst_f0 <= '0';
378 reg_wp.burst_f1 <= '0';
389 reg_wp.burst_f1 <= '0';
379 reg_wp.burst_f2 <= '0';
390 reg_wp.burst_f2 <= '0';
380 reg_wp.run <= '0';
391 reg_wp.run <= '0';
381 -- reg_wp.status_full <= (OTHERS => '0');
392 -- reg_wp.status_full <= (OTHERS => '0');
382 -- reg_wp.status_full_err <= (OTHERS => '0');
393 -- reg_wp.status_full_err <= (OTHERS => '0');
383 reg_wp.status_new_err <= (OTHERS => '0');
394 reg_wp.status_new_err <= (OTHERS => '0');
384 reg_wp.error_buffer_full <= (OTHERS => '0');
395 reg_wp.error_buffer_full <= (OTHERS => '0');
385 reg_wp.delta_snapshot <= (OTHERS => '0');
396 reg_wp.delta_snapshot <= (OTHERS => '0');
386 reg_wp.delta_f0 <= (OTHERS => '0');
397 reg_wp.delta_f0 <= (OTHERS => '0');
387 reg_wp.delta_f0_2 <= (OTHERS => '0');
398 reg_wp.delta_f0_2 <= (OTHERS => '0');
388 reg_wp.delta_f1 <= (OTHERS => '0');
399 reg_wp.delta_f1 <= (OTHERS => '0');
389 reg_wp.delta_f2 <= (OTHERS => '0');
400 reg_wp.delta_f2 <= (OTHERS => '0');
390 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
401 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
391 reg_wp.nb_snapshot_param <= (OTHERS => '0');
402 reg_wp.nb_snapshot_param <= (OTHERS => '0');
392 reg_wp.start_date <= (OTHERS => '1');
403 reg_wp.start_date <= (OTHERS => '1');
393
404
394 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
405 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
395 reg_wp.length_buffer <= (OTHERS => '0');
406 reg_wp.length_buffer <= (OTHERS => '0');
396
407
397 pirq_temp <= (OTHERS => '0');
408 pirq_temp <= (OTHERS => '0');
398
409
399 reg_wp.addr_buffer_f <= (OTHERS => '0');
410 reg_wp.addr_buffer_f <= (OTHERS => '0');
400
411
401 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
412 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
402
413
403 -- status_full_ack <= (OTHERS => '0');
414 -- status_full_ack <= (OTHERS => '0');
404
415
405 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
416 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
406 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
417 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
407 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
418 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
408
419
409 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
420 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
410 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
421 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
411 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
422 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
412
423
413 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
424 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
414 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
425 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
415 END LOOP all_status_ready_buffer_bit;
426 END LOOP all_status_ready_buffer_bit;
416
427
417
428
418 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
429 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
419 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
430 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
420 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
431 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
421 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
432 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
422
433
423
434
424
435
425 all_status : FOR I IN 3 DOWNTO 0 LOOP
436 all_status : FOR I IN 3 DOWNTO 0 LOOP
426 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
437 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
427 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
438 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
428 END LOOP all_status;
439 END LOOP all_status;
429
440
430 paddr := "000000";
441 paddr := "000000";
431 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
442 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
432 prdata <= (OTHERS => '0');
443 prdata <= (OTHERS => '0');
433 IF apbi.psel(pindex) = '1' THEN
444 IF apbi.psel(pindex) = '1' THEN
434 -- APB DMA READ --
445 -- APB DMA READ --
435 CASE paddr(7 DOWNTO 2) IS
446 CASE paddr(7 DOWNTO 2) IS
436
447
437 WHEN ADDR_LFR_SM_CONFIG =>
448 WHEN ADDR_LFR_SM_CONFIG =>
438 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
449 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
439 prdata(1) <= reg_sp.config_active_interruption_onError;
450 prdata(1) <= reg_sp.config_active_interruption_onError;
440 prdata(2) <= reg_sp.config_ms_run;
451 prdata(2) <= reg_sp.config_ms_run;
441
452
442 WHEN ADDR_LFR_SM_STATUS =>
453 WHEN ADDR_LFR_SM_STATUS =>
443 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
454 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
444 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
455 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
445 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
456 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
446 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
457 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
447 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
458 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
448 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
459 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
449 -- prdata(6) <= reg_sp.status_error_bad_component_error;
460 -- prdata(6) <= reg_sp.status_error_bad_component_error;
450 prdata(7) <= reg_sp.status_error_buffer_full;
461 prdata(7) <= reg_sp.status_error_buffer_full;
451 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
462 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
452 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
463 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
453 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
464 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
454
465
455 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
466 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
456 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
467 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
457 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
468 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
458 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
469 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
459 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
470 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
460 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
471 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
461 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
472 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
462 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
473 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
463 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
474 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
464 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
475 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
465 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
476 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
466 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
477 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
467 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
478 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
468 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
479 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
469 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
480 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
470 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
481 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
482 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
472 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
483 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
473 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
484 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
474 ---------------------------------------------------------------------
485 ---------------------------------------------------------------------
475 WHEN ADDR_LFR_WP_DATASHAPING =>
486 WHEN ADDR_LFR_WP_DATASHAPING =>
476 prdata(0) <= reg_wp.data_shaping_BW;
487 prdata(0) <= reg_wp.data_shaping_BW;
477 prdata(1) <= reg_wp.data_shaping_SP0;
488 prdata(1) <= reg_wp.data_shaping_SP0;
478 prdata(2) <= reg_wp.data_shaping_SP1;
489 prdata(2) <= reg_wp.data_shaping_SP1;
479 prdata(3) <= reg_wp.data_shaping_R0;
490 prdata(3) <= reg_wp.data_shaping_R0;
480 prdata(4) <= reg_wp.data_shaping_R1;
491 prdata(4) <= reg_wp.data_shaping_R1;
481 prdata(5) <= reg_wp.data_shaping_R2;
492 prdata(5) <= reg_wp.data_shaping_R2;
482 WHEN ADDR_LFR_WP_CONTROL =>
493 WHEN ADDR_LFR_WP_CONTROL =>
483 prdata(0) <= reg_wp.enable_f0;
494 prdata(0) <= reg_wp.enable_f0;
484 prdata(1) <= reg_wp.enable_f1;
495 prdata(1) <= reg_wp.enable_f1;
485 prdata(2) <= reg_wp.enable_f2;
496 prdata(2) <= reg_wp.enable_f2;
486 prdata(3) <= reg_wp.enable_f3;
497 prdata(3) <= reg_wp.enable_f3;
487 prdata(4) <= reg_wp.burst_f0;
498 prdata(4) <= reg_wp.burst_f0;
488 prdata(5) <= reg_wp.burst_f1;
499 prdata(5) <= reg_wp.burst_f1;
489 prdata(6) <= reg_wp.burst_f2;
500 prdata(6) <= reg_wp.burst_f2;
490 prdata(7) <= reg_wp.run;
501 prdata(7) <= reg_wp.run;
491 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
502 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
492 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
503 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
493 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
504 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
494 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
505 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
495 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
506 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
496 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
507 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
497 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
508 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
498 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
509 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
499
510
500 WHEN ADDR_LFR_WP_STATUS =>
511 WHEN ADDR_LFR_WP_STATUS =>
501 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
512 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
502 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
513 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
503 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
514 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
504
515
505 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
516 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
506 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
517 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
507 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
518 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
508 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
519 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
509 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
520 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
510 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
521 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
511 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
522 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
512 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
523 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
513
524
514 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
525 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
515 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
526 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
516 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
527 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
517 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
528 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
518
529
519 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
530 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
520 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
531 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
521 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
532 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
522 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
533 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
523
534
524 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
535 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
525 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
536 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
526 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
537 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
527 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
538 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
528
539
529 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
540 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
530 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
541 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
531 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
542 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
532 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
543 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
533
544
534 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
545 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
535 ---------------------------------------------------------------------
546 ---------------------------------------------------------------------
536 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
547 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
537 WHEN OTHERS => NULL;
548 WHEN OTHERS => NULL;
538
549
539 END CASE;
550 END CASE;
540 IF (apbi.pwrite AND apbi.penable) = '1' THEN
551 IF (apbi.pwrite AND apbi.penable) = '1' THEN
541 -- APB DMA WRITE --
552 -- APB DMA WRITE --
542 CASE paddr(7 DOWNTO 2) IS
553 CASE paddr(7 DOWNTO 2) IS
543 --
554 --
544 WHEN ADDR_LFR_SM_CONFIG =>
555 WHEN ADDR_LFR_SM_CONFIG =>
545 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
556 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
546 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
557 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
547 reg_sp.config_ms_run <= apbi.pwdata(2);
558 reg_sp.config_ms_run <= apbi.pwdata(2);
548
559
549 WHEN ADDR_LFR_SM_STATUS =>
560 WHEN ADDR_LFR_SM_STATUS =>
550 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
561 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
551 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
562 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
552 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
563 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
553 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
564 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
554 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
565 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
555 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
566 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
556 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
567 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
557 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
568 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
558 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
569 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
559 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
570 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
560 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
571 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
561 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
572 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
562 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
573 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
563 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
574 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
564 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
575 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
565 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
576 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
566
577
567 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
578 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
568 ---------------------------------------------------------------------
579 ---------------------------------------------------------------------
569 WHEN ADDR_LFR_WP_DATASHAPING =>
580 WHEN ADDR_LFR_WP_DATASHAPING =>
570 reg_wp.data_shaping_BW <= apbi.pwdata(0);
581 reg_wp.data_shaping_BW <= apbi.pwdata(0);
571 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
582 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
572 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
583 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
573 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
584 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
574 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
585 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
575 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
586 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
576 WHEN ADDR_LFR_WP_CONTROL =>
587 WHEN ADDR_LFR_WP_CONTROL =>
577 reg_wp.enable_f0 <= apbi.pwdata(0);
588 reg_wp.enable_f0 <= apbi.pwdata(0);
578 reg_wp.enable_f1 <= apbi.pwdata(1);
589 reg_wp.enable_f1 <= apbi.pwdata(1);
579 reg_wp.enable_f2 <= apbi.pwdata(2);
590 reg_wp.enable_f2 <= apbi.pwdata(2);
580 reg_wp.enable_f3 <= apbi.pwdata(3);
591 reg_wp.enable_f3 <= apbi.pwdata(3);
581 reg_wp.burst_f0 <= apbi.pwdata(4);
592 reg_wp.burst_f0 <= apbi.pwdata(4);
582 reg_wp.burst_f1 <= apbi.pwdata(5);
593 reg_wp.burst_f1 <= apbi.pwdata(5);
583 reg_wp.burst_f2 <= apbi.pwdata(6);
594 reg_wp.burst_f2 <= apbi.pwdata(6);
584 reg_wp.run <= apbi.pwdata(7);
595 reg_wp.run <= apbi.pwdata(7);
585 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
596 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
586 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
597 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
587 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
598 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
588 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
599 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
589 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
600 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
590 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
601 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
591 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
602 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
592 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
603 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
593 WHEN ADDR_LFR_WP_STATUS =>
604 WHEN ADDR_LFR_WP_STATUS =>
594 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
605 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
595 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
606 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
596 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
607 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
597 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
608 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
598 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
609 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
599 END LOOP all_reg_wp_status_bit;
610 END LOOP all_reg_wp_status_bit;
600
611
601 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
612 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
602 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
613 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
603 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
614 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
604 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
615 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
605 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
616 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
606 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
617 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
607 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
618 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
608 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
619 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
609
620
610 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
621 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
611
622
612 WHEN OTHERS => NULL;
623 WHEN OTHERS => NULL;
613 END CASE;
624 END CASE;
614 END IF;
625 END IF;
615 END IF;
626 END IF;
616 --apbo.pirq(pirq_ms) <=
627 --apbo.pirq(pirq_ms) <=
617 pirq_temp( pirq_ms) <= apbo_irq_ms;
628 pirq_temp( pirq_ms) <= apbo_irq_ms;
618 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
629 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
619 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
630 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
620 ready_matrix_f1 OR
631 ready_matrix_f1 OR
621 ready_matrix_f2)
632 ready_matrix_f2)
622 )
633 )
623 OR
634 OR
624 (reg_sp.config_active_interruption_onError AND (
635 (reg_sp.config_active_interruption_onError AND (
625 -- error_bad_component_error OR
636 -- error_bad_component_error OR
626 error_buffer_full
637 error_buffer_full
627 OR error_input_fifo_write(0)
638 OR error_input_fifo_write(0)
628 OR error_input_fifo_write(1)
639 OR error_input_fifo_write(1)
629 OR error_input_fifo_write(2))
640 OR error_input_fifo_write(2))
630 ));
641 ));
631 -- apbo.pirq(pirq_wfp)
642 -- apbo.pirq(pirq_wfp)
632 apbo_irq_wfp<= ored_irq_wfp;
643 apbo_irq_wfp<= ored_irq_wfp;
633
644
634 END IF;
645 END IF;
635 END PROCESS lpp_lfr_apbreg;
646 END PROCESS lpp_lfr_apbreg;
636
647
637 apbo.pirq <= pirq_temp;
648 apbo.pirq <= pirq_temp;
638
649
639
650
640 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
651 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
641 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
652 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
642 -- apbo.pirq(I) <= apbo_irq_ms;
653 -- apbo.pirq(I) <= apbo_irq_ms;
643 -- END GENERATE IRQ_is_PIRQ_MS;
654 -- END GENERATE IRQ_is_PIRQ_MS;
644 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
655 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
645 -- apbo.pirq(I) <= apbo_irq_wfp;
656 -- apbo.pirq(I) <= apbo_irq_wfp;
646 -- END GENERATE IRQ_is_PIRQ_WFP;
657 -- END GENERATE IRQ_is_PIRQ_WFP;
647 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
658 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
648 -- apbo.pirq(I) <= '0';
659 -- apbo.pirq(I) <= '0';
649 -- END GENERATE IRQ_OTHERS;
660 -- END GENERATE IRQ_OTHERS;
650
661
651 --END GENERATE all_irq;
662 --END GENERATE all_irq;
652
663
653
664
654
665
655 apbo.pindex <= pindex;
666 apbo.pindex <= pindex;
656 apbo.pconfig <= pconfig;
667 apbo.pconfig <= pconfig;
657 apbo.prdata <= prdata;
668 apbo.prdata <= prdata;
658
669
659 -----------------------------------------------------------------------------
670 -----------------------------------------------------------------------------
660 -- IRQ
671 -- IRQ
661 -----------------------------------------------------------------------------
672 -----------------------------------------------------------------------------
662 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
673 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
663
674
664 PROCESS (HCLK, HRESETn)
675 PROCESS (HCLK, HRESETn)
665 BEGIN -- PROCESS
676 BEGIN -- PROCESS
666 IF HRESETn = '0' THEN -- asynchronous reset (active low)
677 IF HRESETn = '0' THEN -- asynchronous reset (active low)
667 irq_wfp_reg <= (OTHERS => '0');
678 irq_wfp_reg <= (OTHERS => '0');
668 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
679 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
669 irq_wfp_reg <= irq_wfp_reg_s;
680 irq_wfp_reg <= irq_wfp_reg_s;
670 END IF;
681 END IF;
671 END PROCESS;
682 END PROCESS;
672
683
673 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
684 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
674 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
685 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
675 END GENERATE all_irq_wfp;
686 END GENERATE all_irq_wfp;
676
687
677 irq_wfp_ZERO <= (OTHERS => '0');
688 irq_wfp_ZERO <= (OTHERS => '0');
678 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
689 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
679
690
680 run_ms <= reg_sp.config_ms_run;
691 run_ms <= reg_sp.config_ms_run;
681
692
682 -----------------------------------------------------------------------------
693 -----------------------------------------------------------------------------
683 --
694 --
684 -----------------------------------------------------------------------------
695 -----------------------------------------------------------------------------
685 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
696 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
686 PORT MAP (
697 PORT MAP (
687 clk => HCLK,
698 clk => HCLK,
688 rstn => HRESETn,
699 rstn => HRESETn,
689
700
690 run => '1',--reg_sp.config_ms_run,
701 run => '1',--reg_sp.config_ms_run,
691
702
692 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
703 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
693 reg0_ready_matrix => reg0_ready_matrix_f0,
704 reg0_ready_matrix => reg0_ready_matrix_f0,
694 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
705 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
695 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
706 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
696
707
697 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
708 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
698 reg1_ready_matrix => reg1_ready_matrix_f0,
709 reg1_ready_matrix => reg1_ready_matrix_f0,
699 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
710 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
700 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
711 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
701
712
702 ready_matrix => ready_matrix_f0,
713 ready_matrix => ready_matrix_f0,
703 status_ready_matrix => status_ready_matrix_f0,
714 status_ready_matrix => status_ready_matrix_f0,
704 addr_matrix => addr_matrix_f0,
715 addr_matrix => addr_matrix_f0,
705 matrix_time => matrix_time_f0);
716 matrix_time => matrix_time_f0);
706
717
707 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
718 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
708 PORT MAP (
719 PORT MAP (
709 clk => HCLK,
720 clk => HCLK,
710 rstn => HRESETn,
721 rstn => HRESETn,
711
722
712 run => '1',--reg_sp.config_ms_run,
723 run => '1',--reg_sp.config_ms_run,
713
724
714 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
725 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
715 reg0_ready_matrix => reg0_ready_matrix_f1,
726 reg0_ready_matrix => reg0_ready_matrix_f1,
716 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
727 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
717 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
728 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
718
729
719 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
730 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
720 reg1_ready_matrix => reg1_ready_matrix_f1,
731 reg1_ready_matrix => reg1_ready_matrix_f1,
721 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
732 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
722 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
733 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
723
734
724 ready_matrix => ready_matrix_f1,
735 ready_matrix => ready_matrix_f1,
725 status_ready_matrix => status_ready_matrix_f1,
736 status_ready_matrix => status_ready_matrix_f1,
726 addr_matrix => addr_matrix_f1,
737 addr_matrix => addr_matrix_f1,
727 matrix_time => matrix_time_f1);
738 matrix_time => matrix_time_f1);
728
739
729 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
740 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
730 PORT MAP (
741 PORT MAP (
731 clk => HCLK,
742 clk => HCLK,
732 rstn => HRESETn,
743 rstn => HRESETn,
733
744
734 run => '1',--reg_sp.config_ms_run,
745 run => '1',--reg_sp.config_ms_run,
735
746
736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
747 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
737 reg0_ready_matrix => reg0_ready_matrix_f2,
748 reg0_ready_matrix => reg0_ready_matrix_f2,
738 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
749 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
739 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
750 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
740
751
741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
752 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
742 reg1_ready_matrix => reg1_ready_matrix_f2,
753 reg1_ready_matrix => reg1_ready_matrix_f2,
743 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
754 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
744 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
755 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
745
756
746 ready_matrix => ready_matrix_f2,
757 ready_matrix => ready_matrix_f2,
747 status_ready_matrix => status_ready_matrix_f2,
758 status_ready_matrix => status_ready_matrix_f2,
748 addr_matrix => addr_matrix_f2,
759 addr_matrix => addr_matrix_f2,
749 matrix_time => matrix_time_f2);
760 matrix_time => matrix_time_f2);
750
761
751 -----------------------------------------------------------------------------
762 -----------------------------------------------------------------------------
752 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
763 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
753 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
764 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
754 PORT MAP (
765 PORT MAP (
755 clk => HCLK,
766 clk => HCLK,
756 rstn => HRESETn,
767 rstn => HRESETn,
757
768
758 run => '1',--reg_wp.run,
769 run => '1',--reg_wp.run,
759
770
760 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
771 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
761 reg0_ready_matrix => reg_ready_buffer_f(2*I),
772 reg0_ready_matrix => reg_ready_buffer_f(2*I),
762 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
773 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
763 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
774 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
764
775
765 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
776 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
766 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
777 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
767 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
778 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
768 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
779 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
769
780
770 ready_matrix => wfp_ready_buffer(I),
781 ready_matrix => wfp_ready_buffer(I),
771 status_ready_matrix => wfp_status_buffer_ready(I),
782 status_ready_matrix => wfp_status_buffer_ready(I),
772 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
783 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
773 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
784 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
774 );
785 );
775
786
776 END GENERATE all_wfp_pointer;
787 END GENERATE all_wfp_pointer;
777 -----------------------------------------------------------------------------
788 -----------------------------------------------------------------------------
778
789
779 END beh;
790 END beh;
780
791
781 ------------------------------------------------------------------------------- No newline at end of file
792 ------------------------------------------------------------------------------
Show file before | Show file after | Hide comments
@@ -1,1207 +1,1213
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5
5
6 LIBRARY lpp;
6 LIBRARY lpp;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.spectral_matrix_package.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_Header.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
15 USE lpp.lpp_fft.ALL;
15 USE lpp.lpp_fft.ALL;
16 USE lpp.fft_components.ALL;
16 USE lpp.fft_components.ALL;
17
17
18 ENTITY lpp_lfr_ms IS
18 ENTITY lpp_lfr_ms IS
19 GENERIC (
19 GENERIC (
20 Mem_use : INTEGER := use_RAM
20 Mem_use : INTEGER := use_RAM
21 );
21 );
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25 run : IN STD_LOGIC;
25 run : IN STD_LOGIC;
26
26
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- DATA INPUT
28 -- DATA INPUT
29 ---------------------------------------------------------------------------
29 ---------------------------------------------------------------------------
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 -- TIME
31 -- TIME
32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
34 --
34 --
35 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 --
40 --
41 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43
43
44 ---------------------------------------------------------------------------
44 ---------------------------------------------------------------------------
45 -- DMA
45 -- DMA
46 ---------------------------------------------------------------------------
46 ---------------------------------------------------------------------------
47 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
47 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
48 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
48 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
49 dma_fifo_ren : IN STD_LOGIC; --TODO
49 dma_fifo_ren : IN STD_LOGIC; --TODO
50 dma_buffer_new : OUT STD_LOGIC; --TODOx
50 dma_buffer_new : OUT STD_LOGIC; --TODOx
51 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
52 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
52 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
53 dma_buffer_full : IN STD_LOGIC; --TODO
53 dma_buffer_full : IN STD_LOGIC; --TODO
54 dma_buffer_full_err : IN STD_LOGIC; --TODO
54 dma_buffer_full_err : IN STD_LOGIC; --TODO
55
55
56 -- Reg out
56 -- Reg out
57 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
57 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
58 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
58 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
59 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
59 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
60 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
60 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
61 error_buffer_full : OUT STD_LOGIC; -- TODO
61 error_buffer_full : OUT STD_LOGIC; -- TODO
62 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
62 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
63
63
64 -- Reg In
64 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
65 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
66 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
66 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
67 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
67 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
68
68
69 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
69 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72
72
73 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
73 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76
76
77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80
80 ---------------------------------------------------------------------------
81 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
81 );
82 );
82 END;
83 END;
83
84
84 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
85 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
85
86
86 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
91
92
92 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97
98
98 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
103
103 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104
105
105 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
106 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
109 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
109
110
110 SIGNAL error_wen_f0 : STD_LOGIC;
111 SIGNAL error_wen_f0 : STD_LOGIC;
111 SIGNAL error_wen_f1 : STD_LOGIC;
112 SIGNAL error_wen_f1 : STD_LOGIC;
112 SIGNAL error_wen_f2 : STD_LOGIC;
113 SIGNAL error_wen_f2 : STD_LOGIC;
113
114
114 SIGNAL one_sample_f1_full : STD_LOGIC;
115 SIGNAL one_sample_f1_full : STD_LOGIC;
115 SIGNAL one_sample_f1_wen : STD_LOGIC;
116 SIGNAL one_sample_f1_wen : STD_LOGIC;
116 SIGNAL one_sample_f2_full : STD_LOGIC;
117 SIGNAL one_sample_f2_full : STD_LOGIC;
117 SIGNAL one_sample_f2_wen : STD_LOGIC;
118 SIGNAL one_sample_f2_wen : STD_LOGIC;
118
119
119 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
120 -- FSM / SWITCH SELECT CHANNEL
121 -- FSM / SWITCH SELECT CHANNEL
121 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
122 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
123 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
123 SIGNAL state_fsm_select_channel : fsm_select_channel;
124 SIGNAL state_fsm_select_channel : fsm_select_channel;
124 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
127
128
128 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
130 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
130 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
132 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
132
133
133 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
134 -- FSM LOAD FFT
135 -- FSM LOAD FFT
135 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
136 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
137 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
137 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
138 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
138 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
139 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
139 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
140 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
140 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
141 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
141
142
142 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 SIGNAL sample_load : STD_LOGIC;
144 SIGNAL sample_load : STD_LOGIC;
144 SIGNAL sample_valid : STD_LOGIC;
145 SIGNAL sample_valid : STD_LOGIC;
145 SIGNAL sample_valid_r : STD_LOGIC;
146 SIGNAL sample_valid_r : STD_LOGIC;
146 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
147 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
147
148
148
149
149 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
150 -- FFT
151 -- FFT
151 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
152 SIGNAL fft_read : STD_LOGIC;
153 SIGNAL fft_read : STD_LOGIC;
153 SIGNAL fft_pong : STD_LOGIC;
154 SIGNAL fft_pong : STD_LOGIC;
154 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
155 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
155 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
156 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
156 SIGNAL fft_data_valid : STD_LOGIC;
157 SIGNAL fft_data_valid : STD_LOGIC;
157 SIGNAL fft_ready : STD_LOGIC;
158 SIGNAL fft_ready : STD_LOGIC;
158 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
159 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
160 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
160 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
161 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
162 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
162 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
163 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
163 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL current_fifo_empty : STD_LOGIC;
165 SIGNAL current_fifo_empty : STD_LOGIC;
165 SIGNAL current_fifo_locked : STD_LOGIC;
166 SIGNAL current_fifo_locked : STD_LOGIC;
166 SIGNAL current_fifo_full : STD_LOGIC;
167 SIGNAL current_fifo_full : STD_LOGIC;
167 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
168
169
169 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
170 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
174 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
175 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
175 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
176 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
176 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
178 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
178 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
179 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
180 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
180 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
182 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
182
183
183 SIGNAL SM_correlation_start : STD_LOGIC;
184 SIGNAL SM_correlation_start : STD_LOGIC;
184 SIGNAL SM_correlation_auto : STD_LOGIC;
185 SIGNAL SM_correlation_auto : STD_LOGIC;
185 SIGNAL SM_correlation_done : STD_LOGIC;
186 SIGNAL SM_correlation_done : STD_LOGIC;
186 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
187 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
187 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
188 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
188 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
189 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
189 SIGNAL SM_correlation_begin : STD_LOGIC;
190 SIGNAL SM_correlation_begin : STD_LOGIC;
190
191
191 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
192 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
192 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
194 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
194
195
195 SIGNAL current_matrix_write : STD_LOGIC;
196 SIGNAL current_matrix_write : STD_LOGIC;
196 SIGNAL current_matrix_wait_empty : STD_LOGIC;
197 SIGNAL current_matrix_wait_empty : STD_LOGIC;
197 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
198 SIGNAL fifo_0_ready : STD_LOGIC;
199 SIGNAL fifo_0_ready : STD_LOGIC;
199 SIGNAL fifo_1_ready : STD_LOGIC;
200 SIGNAL fifo_1_ready : STD_LOGIC;
200 SIGNAL fifo_ongoing : STD_LOGIC;
201 SIGNAL fifo_ongoing : STD_LOGIC;
201
202
202 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
203 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
203 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
204 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
204 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
205 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
205 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
207 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
207 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
208 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
209 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
209 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
210 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
210 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
211 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
211 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
212 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
212 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
215 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
215
216
216 -----------------------------------------------------------------------------
217 -----------------------------------------------------------------------------
217 -- TIME REG & INFOs
218 -- TIME REG & INFOs
218 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
219 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
220
221
221 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
222 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
222 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
224 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
224 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
225 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
225
226
226 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
227 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
227 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
230
231
231 --SIGNAL time_update_f0_A : STD_LOGIC;
232 --SIGNAL time_update_f0_A : STD_LOGIC;
232 --SIGNAL time_update_f0_B : STD_LOGIC;
233 --SIGNAL time_update_f0_B : STD_LOGIC;
233 --SIGNAL time_update_f1 : STD_LOGIC;
234 --SIGNAL time_update_f1 : STD_LOGIC;
234 --SIGNAL time_update_f2 : STD_LOGIC;
235 --SIGNAL time_update_f2 : STD_LOGIC;
235 --
236 --
236 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
237 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
237 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
238 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
238 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
239 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
239
240
240 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
241 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
241 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
242 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
242 SIGNAL status_component_fifo_0_end : STD_LOGIC;
243 SIGNAL status_component_fifo_0_end : STD_LOGIC;
243 SIGNAL status_component_fifo_1_end : STD_LOGIC;
244 SIGNAL status_component_fifo_1_end : STD_LOGIC;
244 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
245 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
246 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
246
247
247 SIGNAL fft_ready_reg : STD_LOGIC;
248 SIGNAL fft_ready_reg : STD_LOGIC;
248 SIGNAL fft_ready_rising_down : STD_LOGIC;
249 SIGNAL fft_ready_rising_down : STD_LOGIC;
249
250
250 SIGNAL sample_load_reg : STD_LOGIC;
251 SIGNAL sample_load_reg : STD_LOGIC;
251 SIGNAL sample_load_rising_down : STD_LOGIC;
252 SIGNAL sample_load_rising_down : STD_LOGIC;
252
253
253 -----------------------------------------------------------------------------
254 -----------------------------------------------------------------------------
254 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
255 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
255 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
256 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
256 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
257 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
257 SIGNAL sample_f1_full_head_in : STD_LOGIC;
258 SIGNAL sample_f1_full_head_in : STD_LOGIC;
258 SIGNAL sample_f1_full_head_out : STD_LOGIC;
259 SIGNAL sample_f1_full_head_out : STD_LOGIC;
259 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
260 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
260
261
261 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
262 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
262 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
263 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
264 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
264 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
265 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
265 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
266 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
266 SIGNAL ongoing : STD_LOGIC;
267 SIGNAL ongoing : STD_LOGIC;
267
268
268 BEGIN
269 BEGIN
269
270
270 PROCESS (clk, rstn)
271 PROCESS (clk, rstn)
271 BEGIN -- PROCESS
272 BEGIN -- PROCESS
272 IF rstn = '0' THEN -- asynchronous reset (active low)
273 IF rstn = '0' THEN -- asynchronous reset (active low)
273 sample_f0_wen_s <= (OTHERS => '1');
274 sample_f0_wen_s <= (OTHERS => '1');
274 sample_f1_wen_s <= (OTHERS => '1');
275 sample_f1_wen_s <= (OTHERS => '1');
275 sample_f2_wen_s <= (OTHERS => '1');
276 sample_f2_wen_s <= (OTHERS => '1');
276 ongoing <= '0';
277 ongoing <= '0';
277 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
278 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
278 IF ongoing = '1' THEN
279 IF ongoing = '1' THEN
279 sample_f0_wen_s <= sample_f0_wen;
280 sample_f0_wen_s <= sample_f0_wen;
280 sample_f1_wen_s <= sample_f1_wen;
281 sample_f1_wen_s <= sample_f1_wen;
281 sample_f2_wen_s <= sample_f2_wen;
282 sample_f2_wen_s <= sample_f2_wen;
282 ELSE
283 ELSE
283 IF start_date = coarse_time(30 DOWNTO 0) THEN
284 IF start_date = coarse_time(30 DOWNTO 0) THEN
284 ongoing <= '1';
285 ongoing <= '1';
285 END IF;
286 END IF;
286 sample_f0_wen_s <= (OTHERS => '1');
287 sample_f0_wen_s <= (OTHERS => '1');
287 sample_f1_wen_s <= (OTHERS => '1');
288 sample_f1_wen_s <= (OTHERS => '1');
288 sample_f2_wen_s <= (OTHERS => '1');
289 sample_f2_wen_s <= (OTHERS => '1');
289 END IF;
290 END IF;
290 END IF;
291 END IF;
291 END PROCESS;
292 END PROCESS;
292
293
293
294
294 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
295 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
295
296
296
297
297 switch_f0_inst : spectral_matrix_switch_f0
298 switch_f0_inst : spectral_matrix_switch_f0
298 PORT MAP (
299 PORT MAP (
299 clk => clk,
300 clk => clk,
300 rstn => rstn,
301 rstn => rstn,
301
302
302 sample_wen => sample_f0_wen_s,
303 sample_wen => sample_f0_wen_s,
303
304
304 fifo_A_empty => sample_f0_A_empty,
305 fifo_A_empty => sample_f0_A_empty,
305 fifo_A_full => sample_f0_A_full,
306 fifo_A_full => sample_f0_A_full,
306 fifo_A_wen => sample_f0_A_wen,
307 fifo_A_wen => sample_f0_A_wen,
307
308
308 fifo_B_empty => sample_f0_B_empty,
309 fifo_B_empty => sample_f0_B_empty,
309 fifo_B_full => sample_f0_B_full,
310 fifo_B_full => sample_f0_B_full,
310 fifo_B_wen => sample_f0_B_wen,
311 fifo_B_wen => sample_f0_B_wen,
311
312
312 error_wen => error_wen_f0); -- TODO
313 error_wen => error_wen_f0); -- TODO
313
314
314 -----------------------------------------------------------------------------
315 -----------------------------------------------------------------------------
315 -- FIFO IN
316 -- FIFO IN
316 -----------------------------------------------------------------------------
317 -----------------------------------------------------------------------------
317 lppFIFOxN_f0_a : lppFIFOxN
318 lppFIFOxN_f0_a : lppFIFOxN
318 GENERIC MAP (
319 GENERIC MAP (
319 tech => 0,
320 tech => 0,
320 Mem_use => Mem_use,
321 Mem_use => Mem_use,
321 Data_sz => 16,
322 Data_sz => 16,
322 Addr_sz => 8,
323 Addr_sz => 8,
323 FifoCnt => 5)
324 FifoCnt => 5)
324 PORT MAP (
325 PORT MAP (
325 clk => clk,
326 clk => clk,
326 rstn => rstn,
327 rstn => rstn,
327
328
328 ReUse => (OTHERS => '0'),
329 ReUse => (OTHERS => '0'),
329
330
330 run => (OTHERS => '1'),
331 run => (OTHERS => '1'),
331
332
332 wen => sample_f0_A_wen,
333 wen => sample_f0_A_wen,
333 wdata => sample_f0_wdata,
334 wdata => sample_f0_wdata,
334
335
335 ren => sample_f0_A_ren,
336 ren => sample_f0_A_ren,
336 rdata => sample_f0_A_rdata,
337 rdata => sample_f0_A_rdata,
337
338
338 empty => sample_f0_A_empty,
339 empty => sample_f0_A_empty,
339 full => sample_f0_A_full,
340 full => sample_f0_A_full,
340 almost_full => OPEN);
341 almost_full => OPEN);
341
342
342 lppFIFOxN_f0_b : lppFIFOxN
343 lppFIFOxN_f0_b : lppFIFOxN
343 GENERIC MAP (
344 GENERIC MAP (
344 tech => 0,
345 tech => 0,
345 Mem_use => Mem_use,
346 Mem_use => Mem_use,
346 Data_sz => 16,
347 Data_sz => 16,
347 Addr_sz => 8,
348 Addr_sz => 8,
348 FifoCnt => 5)
349 FifoCnt => 5)
349 PORT MAP (
350 PORT MAP (
350 clk => clk,
351 clk => clk,
351 rstn => rstn,
352 rstn => rstn,
352
353
353 ReUse => (OTHERS => '0'),
354 ReUse => (OTHERS => '0'),
354 run => (OTHERS => '1'),
355 run => (OTHERS => '1'),
355
356
356 wen => sample_f0_B_wen,
357 wen => sample_f0_B_wen,
357 wdata => sample_f0_wdata,
358 wdata => sample_f0_wdata,
358 ren => sample_f0_B_ren,
359 ren => sample_f0_B_ren,
359 rdata => sample_f0_B_rdata,
360 rdata => sample_f0_B_rdata,
360 empty => sample_f0_B_empty,
361 empty => sample_f0_B_empty,
361 full => sample_f0_B_full,
362 full => sample_f0_B_full,
362 almost_full => OPEN);
363 almost_full => OPEN);
363
364
364 -----------------------------------------------------------------------------
365 -----------------------------------------------------------------------------
365 -- sample_f1_wen in
366 -- sample_f1_wen in
366 -- sample_f1_wdata in
367 -- sample_f1_wdata in
367 -- sample_f1_full OUT
368 -- sample_f1_full OUT
368
369
369 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
370 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
370 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
371 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
371 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
372 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
372
373
373 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
374 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
374 PORT MAP (
375 PORT MAP (
375 clk => clk,
376 clk => clk,
376 rstn => rstn,
377 rstn => rstn,
377 in_wen => sample_f1_wen_head_in,
378 in_wen => sample_f1_wen_head_in,
378 in_data => sample_f1_wdata,
379 in_data => sample_f1_wdata,
379 in_full => sample_f1_full_head_in,
380 in_full => sample_f1_full_head_in,
380 in_empty => sample_f1_empty_head_in,
381 in_empty => sample_f1_empty_head_in,
381 out_wen => sample_f1_wen_head_out,
382 out_wen => sample_f1_wen_head_out,
382 out_data => sample_f1_wdata_head,
383 out_data => sample_f1_wdata_head,
383 out_full => sample_f1_full_head_out);
384 out_full => sample_f1_full_head_out);
384
385
385 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
386 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
386
387
387
388
388 lppFIFOxN_f1 : lppFIFOxN
389 lppFIFOxN_f1 : lppFIFOxN
389 GENERIC MAP (
390 GENERIC MAP (
390 tech => 0,
391 tech => 0,
391 Mem_use => Mem_use,
392 Mem_use => Mem_use,
392 Data_sz => 16,
393 Data_sz => 16,
393 Addr_sz => 8,
394 Addr_sz => 8,
394 FifoCnt => 5)
395 FifoCnt => 5)
395 PORT MAP (
396 PORT MAP (
396 clk => clk,
397 clk => clk,
397 rstn => rstn,
398 rstn => rstn,
398
399
399 ReUse => (OTHERS => '0'),
400 ReUse => (OTHERS => '0'),
400 run => (OTHERS => '1'),
401 run => (OTHERS => '1'),
401
402
402 wen => sample_f1_wen_head,
403 wen => sample_f1_wen_head,
403 wdata => sample_f1_wdata_head,
404 wdata => sample_f1_wdata_head,
404 ren => sample_f1_ren,
405 ren => sample_f1_ren,
405 rdata => sample_f1_rdata,
406 rdata => sample_f1_rdata,
406 empty => sample_f1_empty,
407 empty => sample_f1_empty,
407 full => sample_f1_full,
408 full => sample_f1_full,
408 almost_full => sample_f1_almost_full);
409 almost_full => sample_f1_almost_full);
409
410
410
411
411 one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
412 one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
412
413
413 PROCESS (clk, rstn)
414 PROCESS (clk, rstn)
414 BEGIN -- PROCESS
415 BEGIN -- PROCESS
415 IF rstn = '0' THEN -- asynchronous reset (active low)
416 IF rstn = '0' THEN -- asynchronous reset (active low)
416 one_sample_f1_full <= '0';
417 one_sample_f1_full <= '0';
417 error_wen_f1 <= '0';
418 error_wen_f1 <= '0';
418 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
419 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
419 IF sample_f1_full_head_out = '0' THEN
420 IF sample_f1_full_head_out = '0' THEN
420 one_sample_f1_full <= '0';
421 one_sample_f1_full <= '0';
421 ELSE
422 ELSE
422 one_sample_f1_full <= '1';
423 one_sample_f1_full <= '1';
423 END IF;
424 END IF;
424 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
425 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
425 END IF;
426 END IF;
426 END PROCESS;
427 END PROCESS;
427
428
428 -----------------------------------------------------------------------------
429 -----------------------------------------------------------------------------
429
430
430
431
431 lppFIFOxN_f2 : lppFIFOxN
432 lppFIFOxN_f2 : lppFIFOxN
432 GENERIC MAP (
433 GENERIC MAP (
433 tech => 0,
434 tech => 0,
434 Mem_use => Mem_use,
435 Mem_use => Mem_use,
435 Data_sz => 16,
436 Data_sz => 16,
436 Addr_sz => 8,
437 Addr_sz => 8,
437 FifoCnt => 5)
438 FifoCnt => 5)
438 PORT MAP (
439 PORT MAP (
439 clk => clk,
440 clk => clk,
440 rstn => rstn,
441 rstn => rstn,
441
442
442 ReUse => (OTHERS => '0'),
443 ReUse => (OTHERS => '0'),
443 run => (OTHERS => '1'),
444 run => (OTHERS => '1'),
444
445
445 wen => sample_f2_wen,
446 wen => sample_f2_wen_s,
446 wdata => sample_f2_wdata,
447 wdata => sample_f2_wdata,
447 ren => sample_f2_ren,
448 ren => sample_f2_ren,
448 rdata => sample_f2_rdata,
449 rdata => sample_f2_rdata,
449 empty => sample_f2_empty,
450 empty => sample_f2_empty,
450 full => sample_f2_full,
451 full => sample_f2_full,
451 almost_full => OPEN);
452 almost_full => OPEN);
452
453
453
454
454 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
455 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
455
456
456 PROCESS (clk, rstn)
457 PROCESS (clk, rstn)
457 BEGIN -- PROCESS
458 BEGIN -- PROCESS
458 IF rstn = '0' THEN -- asynchronous reset (active low)
459 IF rstn = '0' THEN -- asynchronous reset (active low)
459 one_sample_f2_full <= '0';
460 one_sample_f2_full <= '0';
460 error_wen_f2 <= '0';
461 error_wen_f2 <= '0';
461 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
462 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
462 IF sample_f2_full = "00000" THEN
463 IF sample_f2_full = "00000" THEN
463 one_sample_f2_full <= '0';
464 one_sample_f2_full <= '0';
464 ELSE
465 ELSE
465 one_sample_f2_full <= '1';
466 one_sample_f2_full <= '1';
466 END IF;
467 END IF;
467 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
468 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
468 END IF;
469 END IF;
469 END PROCESS;
470 END PROCESS;
470
471
471 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
472 -- FSM SELECT CHANNEL
473 -- FSM SELECT CHANNEL
473 -----------------------------------------------------------------------------
474 -----------------------------------------------------------------------------
474 PROCESS (clk, rstn)
475 PROCESS (clk, rstn)
475 BEGIN
476 BEGIN
476 IF rstn = '0' THEN
477 IF rstn = '0' THEN
477 state_fsm_select_channel <= IDLE;
478 state_fsm_select_channel <= IDLE;
478 select_channel <= (OTHERS => '0');
479 select_channel <= (OTHERS => '0');
479 ELSIF clk'EVENT AND clk = '1' THEN
480 ELSIF clk'EVENT AND clk = '1' THEN
480 CASE state_fsm_select_channel IS
481 CASE state_fsm_select_channel IS
481 WHEN IDLE =>
482 WHEN IDLE =>
482 IF sample_f1_full = "11111" THEN
483 IF sample_f1_full = "11111" THEN
483 state_fsm_select_channel <= SWITCH_F1;
484 state_fsm_select_channel <= SWITCH_F1;
484 select_channel <= "10";
485 select_channel <= "10";
485 ELSIF sample_f1_almost_full = "00000" THEN
486 ELSIF sample_f1_almost_full = "00000" THEN
486 IF sample_f0_A_full = "11111" THEN
487 IF sample_f0_A_full = "11111" THEN
487 state_fsm_select_channel <= SWITCH_F0_A;
488 state_fsm_select_channel <= SWITCH_F0_A;
488 select_channel <= "00";
489 select_channel <= "00";
489 ELSIF sample_f0_B_full = "11111" THEN
490 ELSIF sample_f0_B_full = "11111" THEN
490 state_fsm_select_channel <= SWITCH_F0_B;
491 state_fsm_select_channel <= SWITCH_F0_B;
491 select_channel <= "01";
492 select_channel <= "01";
492 ELSIF sample_f2_full = "11111" THEN
493 ELSIF sample_f2_full = "11111" THEN
493 state_fsm_select_channel <= SWITCH_F2;
494 state_fsm_select_channel <= SWITCH_F2;
494 select_channel <= "11";
495 select_channel <= "11";
495 END IF;
496 END IF;
496 END IF;
497 END IF;
497
498
498 WHEN SWITCH_F0_A =>
499 WHEN SWITCH_F0_A =>
499 IF sample_f0_A_empty = "11111" THEN
500 IF sample_f0_A_empty = "11111" THEN
500 state_fsm_select_channel <= IDLE;
501 state_fsm_select_channel <= IDLE;
501 select_channel <= (OTHERS => '0');
502 select_channel <= (OTHERS => '0');
502 END IF;
503 END IF;
503 WHEN SWITCH_F0_B =>
504 WHEN SWITCH_F0_B =>
504 IF sample_f0_B_empty = "11111" THEN
505 IF sample_f0_B_empty = "11111" THEN
505 state_fsm_select_channel <= IDLE;
506 state_fsm_select_channel <= IDLE;
506 select_channel <= (OTHERS => '0');
507 select_channel <= (OTHERS => '0');
507 END IF;
508 END IF;
508 WHEN SWITCH_F1 =>
509 WHEN SWITCH_F1 =>
509 IF sample_f1_empty = "11111" THEN
510 IF sample_f1_empty = "11111" THEN
510 state_fsm_select_channel <= IDLE;
511 state_fsm_select_channel <= IDLE;
511 select_channel <= (OTHERS => '0');
512 select_channel <= (OTHERS => '0');
512 END IF;
513 END IF;
513 WHEN SWITCH_F2 =>
514 WHEN SWITCH_F2 =>
514 IF sample_f2_empty = "11111" THEN
515 IF sample_f2_empty = "11111" THEN
515 state_fsm_select_channel <= IDLE;
516 state_fsm_select_channel <= IDLE;
516 select_channel <= (OTHERS => '0');
517 select_channel <= (OTHERS => '0');
517 END IF;
518 END IF;
518 WHEN OTHERS => NULL;
519 WHEN OTHERS => NULL;
519 END CASE;
520 END CASE;
520
521
521 END IF;
522 END IF;
522 END PROCESS;
523 END PROCESS;
523
524
524 PROCESS (clk, rstn)
525 PROCESS (clk, rstn)
525 BEGIN
526 BEGIN
526 IF rstn = '0' THEN
527 IF rstn = '0' THEN
527 select_channel_reg <= (OTHERS => '0');
528 select_channel_reg <= (OTHERS => '0');
528 --pre_state_fsm_select_channel <= IDLE;
529 --pre_state_fsm_select_channel <= IDLE;
529 ELSIF clk'EVENT AND clk = '1' THEN
530 ELSIF clk'EVENT AND clk = '1' THEN
530 select_channel_reg <= select_channel;
531 select_channel_reg <= select_channel;
531 --pre_state_fsm_select_channel <= state_fsm_select_channel;
532 --pre_state_fsm_select_channel <= state_fsm_select_channel;
532 END IF;
533 END IF;
533 END PROCESS;
534 END PROCESS;
534
535
535
536
536 -----------------------------------------------------------------------------
537 -----------------------------------------------------------------------------
537 -- SWITCH SELECT CHANNEL
538 -- SWITCH SELECT CHANNEL
538 -----------------------------------------------------------------------------
539 -----------------------------------------------------------------------------
539 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
540 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
540 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
541 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
541 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
542 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
542 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
543 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
543 (OTHERS => '1');
544 (OTHERS => '1');
544
545
545 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
546 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
546 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
547 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
547 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
548 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
548 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
549 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
549 (OTHERS => '0');
550 (OTHERS => '0');
550
551
551 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
552 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
552 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
553 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
553 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
554 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
554 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
555 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
555 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
556 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
556 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
557 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
557 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
558 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
558 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
559 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
559
560
560
561
561 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
562 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
562 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
563 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
563 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
564 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
564 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
565 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
565
566
566
567
567 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
568 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
568 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
569 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
569 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
570 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
570 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
571 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
571
572
572 -----------------------------------------------------------------------------
573 -----------------------------------------------------------------------------
573 -- FSM LOAD FFT
574 -- FSM LOAD FFT
574 -----------------------------------------------------------------------------
575 -----------------------------------------------------------------------------
575
576
576 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
577 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
577 sample_ren_s WHEN sample_load = '1' ELSE
578 sample_ren_s WHEN sample_load = '1' ELSE
578 (OTHERS => '1');
579 (OTHERS => '1');
579
580
580 PROCESS (clk, rstn)
581 PROCESS (clk, rstn)
581 BEGIN
582 BEGIN
582 IF rstn = '0' THEN
583 IF rstn = '0' THEN
583 sample_ren_s <= (OTHERS => '1');
584 sample_ren_s <= (OTHERS => '1');
584 state_fsm_load_FFT <= IDLE;
585 state_fsm_load_FFT <= IDLE;
585 status_MS_input <= (OTHERS => '0');
586 status_MS_input <= (OTHERS => '0');
586 select_fifo <= "000";
587 select_fifo <= "000";
587 --next_state_fsm_load_FFT <= IDLE;
588 --next_state_fsm_load_FFT <= IDLE;
588 --sample_valid <= '0';
589 --sample_valid <= '0';
589 ELSIF clk'EVENT AND clk = '1' THEN
590 ELSIF clk'EVENT AND clk = '1' THEN
590 CASE state_fsm_load_FFT IS
591 CASE state_fsm_load_FFT IS
591 WHEN IDLE =>
592 WHEN IDLE =>
592 --sample_valid <= '0';
593 --sample_valid <= '0';
593 sample_ren_s <= (OTHERS => '1');
594 sample_ren_s <= (OTHERS => '1');
594 IF sample_full = "11111" AND sample_load = '1' THEN
595 IF sample_full = "11111" AND sample_load = '1' THEN
595 state_fsm_load_FFT <= FIFO_1;
596 state_fsm_load_FFT <= FIFO_1;
596 status_MS_input <= status_channel;
597 status_MS_input <= status_channel;
597 select_fifo <= "000";
598 select_fifo <= "000";
598 END IF;
599 END IF;
599
600
600 WHEN FIFO_1 =>
601 WHEN FIFO_1 =>
601 sample_ren_s <= "1111" & NOT(sample_load);
602 sample_ren_s <= "1111" & NOT(sample_load);
602 IF sample_empty(0) = '1' THEN
603 IF sample_empty(0) = '1' THEN
603 sample_ren_s <= (OTHERS => '1');
604 sample_ren_s <= (OTHERS => '1');
604 state_fsm_load_FFT <= FIFO_2;
605 state_fsm_load_FFT <= FIFO_2;
605 select_fifo <= "001";
606 select_fifo <= "001";
606 END IF;
607 END IF;
607
608
608 WHEN FIFO_2 =>
609 WHEN FIFO_2 =>
609 sample_ren_s <= "111" & NOT(sample_load) & '1';
610 sample_ren_s <= "111" & NOT(sample_load) & '1';
610 IF sample_empty(1) = '1' THEN
611 IF sample_empty(1) = '1' THEN
611 sample_ren_s <= (OTHERS => '1');
612 sample_ren_s <= (OTHERS => '1');
612 state_fsm_load_FFT <= FIFO_3;
613 state_fsm_load_FFT <= FIFO_3;
613 select_fifo <= "010";
614 select_fifo <= "010";
614 END IF;
615 END IF;
615
616
616 WHEN FIFO_3 =>
617 WHEN FIFO_3 =>
617 sample_ren_s <= "11" & NOT(sample_load) & "11";
618 sample_ren_s <= "11" & NOT(sample_load) & "11";
618 IF sample_empty(2) = '1' THEN
619 IF sample_empty(2) = '1' THEN
619 sample_ren_s <= (OTHERS => '1');
620 sample_ren_s <= (OTHERS => '1');
620 state_fsm_load_FFT <= FIFO_4;
621 state_fsm_load_FFT <= FIFO_4;
621 select_fifo <= "011";
622 select_fifo <= "011";
622 END IF;
623 END IF;
623
624
624 WHEN FIFO_4 =>
625 WHEN FIFO_4 =>
625 sample_ren_s <= '1' & NOT(sample_load) & "111";
626 sample_ren_s <= '1' & NOT(sample_load) & "111";
626 IF sample_empty(3) = '1' THEN
627 IF sample_empty(3) = '1' THEN
627 sample_ren_s <= (OTHERS => '1');
628 sample_ren_s <= (OTHERS => '1');
628 state_fsm_load_FFT <= FIFO_5;
629 state_fsm_load_FFT <= FIFO_5;
629 select_fifo <= "100";
630 select_fifo <= "100";
630 END IF;
631 END IF;
631
632
632 WHEN FIFO_5 =>
633 WHEN FIFO_5 =>
633 sample_ren_s <= NOT(sample_load) & "1111";
634 sample_ren_s <= NOT(sample_load) & "1111";
634 IF sample_empty(4) = '1' THEN
635 IF sample_empty(4) = '1' THEN
635 sample_ren_s <= (OTHERS => '1');
636 sample_ren_s <= (OTHERS => '1');
636 state_fsm_load_FFT <= IDLE;
637 state_fsm_load_FFT <= IDLE;
637 select_fifo <= "000";
638 select_fifo <= "000";
638 END IF;
639 END IF;
639 WHEN OTHERS => NULL;
640 WHEN OTHERS => NULL;
640 END CASE;
641 END CASE;
641 END IF;
642 END IF;
642 END PROCESS;
643 END PROCESS;
643
644
644 PROCESS (clk, rstn)
645 PROCESS (clk, rstn)
645 BEGIN
646 BEGIN
646 IF rstn = '0' THEN
647 IF rstn = '0' THEN
647 sample_valid_r <= '0';
648 sample_valid_r <= '0';
648 select_fifo_reg <= (OTHERS => '0');
649 select_fifo_reg <= (OTHERS => '0');
649 --next_state_fsm_load_FFT <= IDLE;
650 --next_state_fsm_load_FFT <= IDLE;
650 ELSIF clk'EVENT AND clk = '1' THEN
651 ELSIF clk'EVENT AND clk = '1' THEN
651 select_fifo_reg <= select_fifo;
652 select_fifo_reg <= select_fifo;
652 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
653 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
653 IF sample_ren_s = "11111" THEN
654 IF sample_ren_s = "11111" THEN
654 sample_valid_r <= '0';
655 sample_valid_r <= '0';
655 ELSE
656 ELSE
656 sample_valid_r <= '1';
657 sample_valid_r <= '1';
657 END IF;
658 END IF;
658 END IF;
659 END IF;
659 END PROCESS;
660 END PROCESS;
660
661
661 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
662 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
662
663
663 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
664 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
664 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
665 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
665 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
666 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
666 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
667 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
667 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
668 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
668 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
669 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
669 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
670 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
670 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
671 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
671 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
672 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
672 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
673 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
673
674
674 -----------------------------------------------------------------------------
675 -----------------------------------------------------------------------------
675 -- FFT
676 -- FFT
676 -----------------------------------------------------------------------------
677 -----------------------------------------------------------------------------
677 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
678 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
678 PORT MAP (
679 PORT MAP (
679 clk => clk,
680 clk => clk,
680 rstn => rstn,
681 rstn => rstn,
681 sample_valid => sample_valid,
682 sample_valid => sample_valid,
682 fft_read => fft_read,
683 fft_read => fft_read,
683 sample_data => sample_data,
684 sample_data => sample_data,
684 sample_load => sample_load,
685 sample_load => sample_load,
685 fft_pong => fft_pong,
686 fft_pong => fft_pong,
686 fft_data_im => fft_data_im,
687 fft_data_im => fft_data_im,
687 fft_data_re => fft_data_re,
688 fft_data_re => fft_data_re,
688 fft_data_valid => fft_data_valid,
689 fft_data_valid => fft_data_valid,
689 fft_ready => fft_ready);
690 fft_ready => fft_ready);
691
692 debug_vector(0) <= fft_data_valid;
693 debug_vector(1) <= fft_ready;
694 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
690
695
696
691 -----------------------------------------------------------------------------
697 -----------------------------------------------------------------------------
692 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
698 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
693 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
699 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
694
700
695 PROCESS (clk, rstn)
701 PROCESS (clk, rstn)
696 BEGIN
702 BEGIN
697 IF rstn = '0' THEN
703 IF rstn = '0' THEN
698 fft_ready_reg <= '0';
704 fft_ready_reg <= '0';
699 sample_load_reg <= '0';
705 sample_load_reg <= '0';
700
706
701 fft_ongoing_counter <= '0';
707 fft_ongoing_counter <= '0';
702 ELSIF clk'event AND clk = '1' THEN
708 ELSIF clk'event AND clk = '1' THEN
703 fft_ready_reg <= fft_ready;
709 fft_ready_reg <= fft_ready;
704 sample_load_reg <= sample_load;
710 sample_load_reg <= sample_load;
705
711
706 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
712 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
707 fft_ongoing_counter <= '0';
713 fft_ongoing_counter <= '0';
708
714
709 -- CASE fft_ongoing_counter IS
715 -- CASE fft_ongoing_counter IS
710 -- WHEN "01" => fft_ongoing_counter <= "00";
716 -- WHEN "01" => fft_ongoing_counter <= "00";
711 ---- WHEN "10" => fft_ongoing_counter <= "01";
717 ---- WHEN "10" => fft_ongoing_counter <= "01";
712 -- WHEN OTHERS => NULL;
718 -- WHEN OTHERS => NULL;
713 -- END CASE;
719 -- END CASE;
714 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
720 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
715 fft_ongoing_counter <= '1';
721 fft_ongoing_counter <= '1';
716 -- CASE fft_ongoing_counter IS
722 -- CASE fft_ongoing_counter IS
717 -- WHEN "00" => fft_ongoing_counter <= "01";
723 -- WHEN "00" => fft_ongoing_counter <= "01";
718 ---- WHEN "01" => fft_ongoing_counter <= "10";
724 ---- WHEN "01" => fft_ongoing_counter <= "10";
719 -- WHEN OTHERS => NULL;
725 -- WHEN OTHERS => NULL;
720 -- END CASE;
726 -- END CASE;
721 END IF;
727 END IF;
722
728
723 END IF;
729 END IF;
724 END PROCESS;
730 END PROCESS;
725
731
726 -----------------------------------------------------------------------------
732 -----------------------------------------------------------------------------
727 PROCESS (clk, rstn)
733 PROCESS (clk, rstn)
728 BEGIN
734 BEGIN
729 IF rstn = '0' THEN
735 IF rstn = '0' THEN
730 state_fsm_load_MS_memory <= IDLE;
736 state_fsm_load_MS_memory <= IDLE;
731 current_fifo_load <= "00001";
737 current_fifo_load <= "00001";
732 ELSIF clk'EVENT AND clk = '1' THEN
738 ELSIF clk'EVENT AND clk = '1' THEN
733 CASE state_fsm_load_MS_memory IS
739 CASE state_fsm_load_MS_memory IS
734 WHEN IDLE =>
740 WHEN IDLE =>
735 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
741 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
736 state_fsm_load_MS_memory <= LOAD_FIFO;
742 state_fsm_load_MS_memory <= LOAD_FIFO;
737 END IF;
743 END IF;
738 WHEN LOAD_FIFO =>
744 WHEN LOAD_FIFO =>
739 IF current_fifo_full = '1' THEN
745 IF current_fifo_full = '1' THEN
740 state_fsm_load_MS_memory <= TRASH_FFT;
746 state_fsm_load_MS_memory <= TRASH_FFT;
741 END IF;
747 END IF;
742 WHEN TRASH_FFT =>
748 WHEN TRASH_FFT =>
743 IF fft_ready = '0' THEN
749 IF fft_ready = '0' THEN
744 state_fsm_load_MS_memory <= IDLE;
750 state_fsm_load_MS_memory <= IDLE;
745 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
751 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
746 END IF;
752 END IF;
747 WHEN OTHERS => NULL;
753 WHEN OTHERS => NULL;
748 END CASE;
754 END CASE;
749
755
750 END IF;
756 END IF;
751 END PROCESS;
757 END PROCESS;
752
758
753 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
759 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
754 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
760 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
755 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
761 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
756 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
762 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
757 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
763 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
758
764
759 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
765 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
760 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
766 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
761 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
767 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
762 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
768 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
763 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
769 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
764
770
765 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
771 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
766 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
772 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
767 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
773 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
768 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
774 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
769 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
775 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
770
776
771 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
777 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
772
778
773 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
779 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
774 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
780 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
775 AND state_fsm_load_MS_memory = LOAD_FIFO
781 AND state_fsm_load_MS_memory = LOAD_FIFO
776 AND current_fifo_load(I) = '1'
782 AND current_fifo_load(I) = '1'
777 ELSE '1';
783 ELSE '1';
778 END GENERATE all_fifo;
784 END GENERATE all_fifo;
779
785
780 PROCESS (clk, rstn)
786 PROCESS (clk, rstn)
781 BEGIN
787 BEGIN
782 IF rstn = '0' THEN
788 IF rstn = '0' THEN
783 MEM_IN_SM_wen <= (OTHERS => '1');
789 MEM_IN_SM_wen <= (OTHERS => '1');
784 ELSIF clk'EVENT AND clk = '1' THEN
790 ELSIF clk'EVENT AND clk = '1' THEN
785 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
791 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
786 END IF;
792 END IF;
787 END PROCESS;
793 END PROCESS;
788
794
789 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
795 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
790 (fft_data_im & fft_data_re) &
796 (fft_data_im & fft_data_re) &
791 (fft_data_im & fft_data_re) &
797 (fft_data_im & fft_data_re) &
792 (fft_data_im & fft_data_re) &
798 (fft_data_im & fft_data_re) &
793 (fft_data_im & fft_data_re);
799 (fft_data_im & fft_data_re);
794 -----------------------------------------------------------------------------
800 -----------------------------------------------------------------------------
795
801
796
802
797 -----------------------------------------------------------------------------
803 -----------------------------------------------------------------------------
798 Mem_In_SpectralMatrix : lppFIFOxN
804 Mem_In_SpectralMatrix : lppFIFOxN
799 GENERIC MAP (
805 GENERIC MAP (
800 tech => 0,
806 tech => 0,
801 Mem_use => Mem_use,
807 Mem_use => Mem_use,
802 Data_sz => 32, --16,
808 Data_sz => 32, --16,
803 Addr_sz => 7, --8
809 Addr_sz => 7, --8
804 FifoCnt => 5)
810 FifoCnt => 5)
805 PORT MAP (
811 PORT MAP (
806 clk => clk,
812 clk => clk,
807 rstn => rstn,
813 rstn => rstn,
808
814
809 ReUse => MEM_IN_SM_ReUse,
815 ReUse => MEM_IN_SM_ReUse,
810 run => (OTHERS => '1'),
816 run => (OTHERS => '1'),
811
817
812 wen => MEM_IN_SM_wen,
818 wen => MEM_IN_SM_wen,
813 wdata => MEM_IN_SM_wData,
819 wdata => MEM_IN_SM_wData,
814
820
815 ren => MEM_IN_SM_ren,
821 ren => MEM_IN_SM_ren,
816 rdata => MEM_IN_SM_rData,
822 rdata => MEM_IN_SM_rData,
817 full => MEM_IN_SM_Full,
823 full => MEM_IN_SM_Full,
818 empty => MEM_IN_SM_Empty,
824 empty => MEM_IN_SM_Empty,
819 almost_full => OPEN);
825 almost_full => OPEN);
820
826
821
827
822 -----------------------------------------------------------------------------
828 -----------------------------------------------------------------------------
823 MS_control_1 : MS_control
829 MS_control_1 : MS_control
824 PORT MAP (
830 PORT MAP (
825 clk => clk,
831 clk => clk,
826 rstn => rstn,
832 rstn => rstn,
827
833
828 current_status_ms => status_MS_input,
834 current_status_ms => status_MS_input,
829
835
830 fifo_in_lock => MEM_IN_SM_locked,
836 fifo_in_lock => MEM_IN_SM_locked,
831 fifo_in_data => MEM_IN_SM_rdata,
837 fifo_in_data => MEM_IN_SM_rdata,
832 fifo_in_full => MEM_IN_SM_Full,
838 fifo_in_full => MEM_IN_SM_Full,
833 fifo_in_empty => MEM_IN_SM_Empty,
839 fifo_in_empty => MEM_IN_SM_Empty,
834 fifo_in_ren => MEM_IN_SM_ren,
840 fifo_in_ren => MEM_IN_SM_ren,
835 fifo_in_reuse => MEM_IN_SM_ReUse,
841 fifo_in_reuse => MEM_IN_SM_ReUse,
836
842
837 fifo_out_data => SM_in_data,
843 fifo_out_data => SM_in_data,
838 fifo_out_ren => SM_in_ren,
844 fifo_out_ren => SM_in_ren,
839 fifo_out_empty => SM_in_empty,
845 fifo_out_empty => SM_in_empty,
840
846
841 current_status_component => status_component,
847 current_status_component => status_component,
842
848
843 correlation_start => SM_correlation_start,
849 correlation_start => SM_correlation_start,
844 correlation_auto => SM_correlation_auto,
850 correlation_auto => SM_correlation_auto,
845 correlation_done => SM_correlation_done);
851 correlation_done => SM_correlation_done);
846
852
847
853
848 MS_calculation_1 : MS_calculation
854 MS_calculation_1 : MS_calculation
849 PORT MAP (
855 PORT MAP (
850 clk => clk,
856 clk => clk,
851 rstn => rstn,
857 rstn => rstn,
852
858
853 fifo_in_data => SM_in_data,
859 fifo_in_data => SM_in_data,
854 fifo_in_ren => SM_in_ren,
860 fifo_in_ren => SM_in_ren,
855 fifo_in_empty => SM_in_empty,
861 fifo_in_empty => SM_in_empty,
856
862
857 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
863 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
858 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
864 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
859 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
865 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
860
866
861 correlation_start => SM_correlation_start,
867 correlation_start => SM_correlation_start,
862 correlation_auto => SM_correlation_auto,
868 correlation_auto => SM_correlation_auto,
863 correlation_begin => SM_correlation_begin,
869 correlation_begin => SM_correlation_begin,
864 correlation_done => SM_correlation_done);
870 correlation_done => SM_correlation_done);
865
871
866 -----------------------------------------------------------------------------
872 -----------------------------------------------------------------------------
867 PROCESS (clk, rstn)
873 PROCESS (clk, rstn)
868 BEGIN -- PROCESS
874 BEGIN -- PROCESS
869 IF rstn = '0' THEN -- asynchronous reset (active low)
875 IF rstn = '0' THEN -- asynchronous reset (active low)
870 current_matrix_write <= '0';
876 current_matrix_write <= '0';
871 current_matrix_wait_empty <= '1';
877 current_matrix_wait_empty <= '1';
872 status_component_fifo_0 <= (OTHERS => '0');
878 status_component_fifo_0 <= (OTHERS => '0');
873 status_component_fifo_1 <= (OTHERS => '0');
879 status_component_fifo_1 <= (OTHERS => '0');
874 status_component_fifo_0_end <= '0';
880 status_component_fifo_0_end <= '0';
875 status_component_fifo_1_end <= '0';
881 status_component_fifo_1_end <= '0';
876 SM_correlation_done_reg1 <= '0';
882 SM_correlation_done_reg1 <= '0';
877 SM_correlation_done_reg2 <= '0';
883 SM_correlation_done_reg2 <= '0';
878 SM_correlation_done_reg3 <= '0';
884 SM_correlation_done_reg3 <= '0';
879
885
880 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
886 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
881 SM_correlation_done_reg1 <= SM_correlation_done;
887 SM_correlation_done_reg1 <= SM_correlation_done;
882 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
888 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
883 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
889 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
884 status_component_fifo_0_end <= '0';
890 status_component_fifo_0_end <= '0';
885 status_component_fifo_1_end <= '0';
891 status_component_fifo_1_end <= '0';
886 IF SM_correlation_begin = '1' THEN
892 IF SM_correlation_begin = '1' THEN
887 IF current_matrix_write = '0' THEN
893 IF current_matrix_write = '0' THEN
888 status_component_fifo_0 <= status_component(53 DOWNTO 4);
894 status_component_fifo_0 <= status_component(53 DOWNTO 4);
889 ELSE
895 ELSE
890 status_component_fifo_1 <= status_component(53 DOWNTO 4);
896 status_component_fifo_1 <= status_component(53 DOWNTO 4);
891 END IF;
897 END IF;
892 END IF;
898 END IF;
893
899
894 IF SM_correlation_done_reg3 = '1' THEN
900 IF SM_correlation_done_reg3 = '1' THEN
895 IF current_matrix_write = '0' THEN
901 IF current_matrix_write = '0' THEN
896 status_component_fifo_0_end <= '1';
902 status_component_fifo_0_end <= '1';
897 ELSE
903 ELSE
898 status_component_fifo_1_end <= '1';
904 status_component_fifo_1_end <= '1';
899 END IF;
905 END IF;
900 current_matrix_wait_empty <= '1';
906 current_matrix_wait_empty <= '1';
901 current_matrix_write <= NOT current_matrix_write;
907 current_matrix_write <= NOT current_matrix_write;
902 END IF;
908 END IF;
903
909
904 IF current_matrix_wait_empty <= '1' THEN
910 IF current_matrix_wait_empty <= '1' THEN
905 IF current_matrix_write = '0' THEN
911 IF current_matrix_write = '0' THEN
906 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
912 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
907 ELSE
913 ELSE
908 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
914 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
909 END IF;
915 END IF;
910 END IF;
916 END IF;
911
917
912 END IF;
918 END IF;
913 END PROCESS;
919 END PROCESS;
914
920
915 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
921 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
916 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
922 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
917 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
923 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
918 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
924 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
919 '1' WHEN current_matrix_wait_empty = '1' ELSE
925 '1' WHEN current_matrix_wait_empty = '1' ELSE
920 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
926 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
921 MEM_OUT_SM_Full(1);
927 MEM_OUT_SM_Full(1);
922
928
923 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
929 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
924 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
930 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
925
931
926 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
932 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
927 -----------------------------------------------------------------------------
933 -----------------------------------------------------------------------------
928
934
929 --Mem_Out_SpectralMatrix : lppFIFOxN
935 --Mem_Out_SpectralMatrix : lppFIFOxN
930 -- GENERIC MAP (
936 -- GENERIC MAP (
931 -- tech => 0,
937 -- tech => 0,
932 -- Mem_use => Mem_use,
938 -- Mem_use => Mem_use,
933 -- Data_sz => 32,
939 -- Data_sz => 32,
934 -- Addr_sz => 8,
940 -- Addr_sz => 8,
935 -- FifoCnt => 2)
941 -- FifoCnt => 2)
936 -- PORT MAP (
942 -- PORT MAP (
937 -- clk => clk,
943 -- clk => clk,
938 -- rstn => rstn,
944 -- rstn => rstn,
939
945
940 -- ReUse => (OTHERS => '0'),
946 -- ReUse => (OTHERS => '0'),
941 -- run => (OTHERS => '1'),
947 -- run => (OTHERS => '1'),
942
948
943 -- wen => MEM_OUT_SM_Write,
949 -- wen => MEM_OUT_SM_Write,
944 -- wdata => MEM_OUT_SM_Data_in,
950 -- wdata => MEM_OUT_SM_Data_in,
945
951
946 -- ren => MEM_OUT_SM_Read,
952 -- ren => MEM_OUT_SM_Read,
947 -- rdata => MEM_OUT_SM_Data_out,
953 -- rdata => MEM_OUT_SM_Data_out,
948
954
949 -- full => MEM_OUT_SM_Full,
955 -- full => MEM_OUT_SM_Full,
950 -- empty => MEM_OUT_SM_Empty,
956 -- empty => MEM_OUT_SM_Empty,
951 -- almost_full => OPEN);
957 -- almost_full => OPEN);
952
958
953
959
954 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
960 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
955 Mem_Out_SpectralMatrix_I: lpp_fifo
961 Mem_Out_SpectralMatrix_I: lpp_fifo
956 GENERIC MAP (
962 GENERIC MAP (
957 tech => 0,
963 tech => 0,
958 Mem_use => Mem_use,
964 Mem_use => Mem_use,
959 EMPTY_THRESHOLD_LIMIT => 15,
965 EMPTY_THRESHOLD_LIMIT => 15,
960 FULL_THRESHOLD_LIMIT => 1,
966 FULL_THRESHOLD_LIMIT => 1,
961 DataSz => 32,
967 DataSz => 32,
962 AddrSz => 8)
968 AddrSz => 8)
963 PORT MAP (
969 PORT MAP (
964 clk => clk,
970 clk => clk,
965 rstn => rstn,
971 rstn => rstn,
966 reUse => '0',
972 reUse => '0',
967 run => run,
973 run => run,
968
974
969 ren => MEM_OUT_SM_Read(I),
975 ren => MEM_OUT_SM_Read(I),
970 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
976 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
971
977
972 wen => MEM_OUT_SM_Write(I),
978 wen => MEM_OUT_SM_Write(I),
973 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
979 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
974
980
975 empty => MEM_OUT_SM_Empty(I),
981 empty => MEM_OUT_SM_Empty(I),
976 full => MEM_OUT_SM_Full(I),
982 full => MEM_OUT_SM_Full(I),
977 full_almost => OPEN,
983 full_almost => OPEN,
978 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
984 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
979
985
980 full_threshold => OPEN);
986 full_threshold => OPEN);
981
987
982 END GENERATE all_Mem_Out_SpectralMatrix;
988 END GENERATE all_Mem_Out_SpectralMatrix;
983
989
984 -----------------------------------------------------------------------------
990 -----------------------------------------------------------------------------
985 -- MEM_OUT_SM_Read <= "00";
991 -- MEM_OUT_SM_Read <= "00";
986 PROCESS (clk, rstn)
992 PROCESS (clk, rstn)
987 BEGIN
993 BEGIN
988 IF rstn = '0' THEN
994 IF rstn = '0' THEN
989 fifo_0_ready <= '0';
995 fifo_0_ready <= '0';
990 fifo_1_ready <= '0';
996 fifo_1_ready <= '0';
991 fifo_ongoing <= '0';
997 fifo_ongoing <= '0';
992 ELSIF clk'EVENT AND clk = '1' THEN
998 ELSIF clk'EVENT AND clk = '1' THEN
993 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
999 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
994 fifo_ongoing <= '1';
1000 fifo_ongoing <= '1';
995 fifo_0_ready <= '0';
1001 fifo_0_ready <= '0';
996 ELSIF status_component_fifo_0_end = '1' THEN
1002 ELSIF status_component_fifo_0_end = '1' THEN
997 fifo_0_ready <= '1';
1003 fifo_0_ready <= '1';
998 END IF;
1004 END IF;
999
1005
1000 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1006 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1001 fifo_ongoing <= '0';
1007 fifo_ongoing <= '0';
1002 fifo_1_ready <= '0';
1008 fifo_1_ready <= '0';
1003 ELSIF status_component_fifo_1_end = '1' THEN
1009 ELSIF status_component_fifo_1_end = '1' THEN
1004 fifo_1_ready <= '1';
1010 fifo_1_ready <= '1';
1005 END IF;
1011 END IF;
1006
1012
1007 END IF;
1013 END IF;
1008 END PROCESS;
1014 END PROCESS;
1009
1015
1010 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1016 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1011 '1' WHEN fifo_0_ready = '0' ELSE
1017 '1' WHEN fifo_0_ready = '0' ELSE
1012 FSM_DMA_fifo_ren;
1018 FSM_DMA_fifo_ren;
1013
1019
1014 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1020 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1015 '1' WHEN fifo_1_ready = '0' ELSE
1021 '1' WHEN fifo_1_ready = '0' ELSE
1016 FSM_DMA_fifo_ren;
1022 FSM_DMA_fifo_ren;
1017
1023
1018 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1024 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1019 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1025 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1020 '1';
1026 '1';
1021
1027
1022 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1028 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1023 status_component_fifo_1;
1029 status_component_fifo_1;
1024
1030
1025 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
1031 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
1026 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1032 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1027
1033
1028
1034
1029 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1035 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1030 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1036 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1031 '1';
1037 '1';
1032
1038
1033 -----------------------------------------------------------------------------
1039 -----------------------------------------------------------------------------
1034 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1040 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1035 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1041 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1036 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1042 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1037 -- fifo_data => FSM_DMA_fifo_data, --IN
1043 -- fifo_data => FSM_DMA_fifo_data, --IN
1038 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1044 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1039 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1045 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1040 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1046 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1041
1047
1042
1048
1043 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1049 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1044 PORT MAP (
1050 PORT MAP (
1045 clk => clk,
1051 clk => clk,
1046 rstn => rstn,
1052 rstn => rstn,
1047 run => run,
1053 run => run,
1048
1054
1049 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1055 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1050 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1056 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1051 fifo_data => FSM_DMA_fifo_data,
1057 fifo_data => FSM_DMA_fifo_data,
1052 fifo_empty => FSM_DMA_fifo_empty,
1058 fifo_empty => FSM_DMA_fifo_empty,
1053 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1059 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1054 fifo_ren => FSM_DMA_fifo_ren,
1060 fifo_ren => FSM_DMA_fifo_ren,
1055
1061
1056 dma_fifo_valid_burst => dma_fifo_burst_valid,
1062 dma_fifo_valid_burst => dma_fifo_burst_valid,
1057 dma_fifo_data => dma_fifo_data,
1063 dma_fifo_data => dma_fifo_data,
1058 dma_fifo_ren => dma_fifo_ren,
1064 dma_fifo_ren => dma_fifo_ren,
1059 dma_buffer_new => dma_buffer_new,
1065 dma_buffer_new => dma_buffer_new,
1060 dma_buffer_addr => dma_buffer_addr,
1066 dma_buffer_addr => dma_buffer_addr,
1061 dma_buffer_length => dma_buffer_length,
1067 dma_buffer_length => dma_buffer_length,
1062 dma_buffer_full => dma_buffer_full,
1068 dma_buffer_full => dma_buffer_full,
1063 dma_buffer_full_err => dma_buffer_full_err,
1069 dma_buffer_full_err => dma_buffer_full_err,
1064
1070
1065 status_ready_matrix_f0 => status_ready_matrix_f0,
1071 status_ready_matrix_f0 => status_ready_matrix_f0,
1066 status_ready_matrix_f1 => status_ready_matrix_f1,
1072 status_ready_matrix_f1 => status_ready_matrix_f1,
1067 status_ready_matrix_f2 => status_ready_matrix_f2,
1073 status_ready_matrix_f2 => status_ready_matrix_f2,
1068 addr_matrix_f0 => addr_matrix_f0,
1074 addr_matrix_f0 => addr_matrix_f0,
1069 addr_matrix_f1 => addr_matrix_f1,
1075 addr_matrix_f1 => addr_matrix_f1,
1070 addr_matrix_f2 => addr_matrix_f2,
1076 addr_matrix_f2 => addr_matrix_f2,
1071 length_matrix_f0 => length_matrix_f0,
1077 length_matrix_f0 => length_matrix_f0,
1072 length_matrix_f1 => length_matrix_f1,
1078 length_matrix_f1 => length_matrix_f1,
1073 length_matrix_f2 => length_matrix_f2,
1079 length_matrix_f2 => length_matrix_f2,
1074 ready_matrix_f0 => ready_matrix_f0,
1080 ready_matrix_f0 => ready_matrix_f0,
1075 ready_matrix_f1 => ready_matrix_f1,
1081 ready_matrix_f1 => ready_matrix_f1,
1076 ready_matrix_f2 => ready_matrix_f2,
1082 ready_matrix_f2 => ready_matrix_f2,
1077 matrix_time_f0 => matrix_time_f0,
1083 matrix_time_f0 => matrix_time_f0,
1078 matrix_time_f1 => matrix_time_f1,
1084 matrix_time_f1 => matrix_time_f1,
1079 matrix_time_f2 => matrix_time_f2,
1085 matrix_time_f2 => matrix_time_f2,
1080 error_buffer_full => error_buffer_full);
1086 error_buffer_full => error_buffer_full);
1081
1087
1082
1088
1083
1089
1084
1090
1085
1091
1086 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1092 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1087 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1093 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1088 --dma_fifo_ren : IN STD_LOGIC; --TODO
1094 --dma_fifo_ren : IN STD_LOGIC; --TODO
1089 --dma_buffer_new : OUT STD_LOGIC; --TODO
1095 --dma_buffer_new : OUT STD_LOGIC; --TODO
1090 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1096 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1091 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1097 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1092 --dma_buffer_full : IN STD_LOGIC; --TODO
1098 --dma_buffer_full : IN STD_LOGIC; --TODO
1093 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1099 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1094
1100
1095 ---- Reg out
1101 ---- Reg out
1096 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1102 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1097 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1103 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1098 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1104 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1099 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1105 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1100 --error_buffer_full : OUT STD_LOGIC; -- TODO
1106 --error_buffer_full : OUT STD_LOGIC; -- TODO
1101
1107
1102 ---- Reg In
1108 ---- Reg In
1103 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1109 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1104 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1110 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1105 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1111 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1106
1112
1107 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1113 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1108 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1114 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1109 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1115 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1110
1116
1111 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1117 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1112 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1118 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1113 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1119 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1114 -----------------------------------------------------------------------------
1120 -----------------------------------------------------------------------------
1115
1121
1116 -----------------------------------------------------------------------------
1122 -----------------------------------------------------------------------------
1117 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1123 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1118 -- PORT MAP (
1124 -- PORT MAP (
1119 -- HCLK => clk,
1125 -- HCLK => clk,
1120 -- HRESETn => rstn,
1126 -- HRESETn => rstn,
1121
1127
1122 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1128 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1123 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1129 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1124 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1130 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1125 -- fifo_data => FSM_DMA_fifo_data,
1131 -- fifo_data => FSM_DMA_fifo_data,
1126 -- fifo_empty => FSM_DMA_fifo_empty,
1132 -- fifo_empty => FSM_DMA_fifo_empty,
1127 -- fifo_ren => FSM_DMA_fifo_ren,
1133 -- fifo_ren => FSM_DMA_fifo_ren,
1128
1134
1129 -- dma_addr => dma_addr,
1135 -- dma_addr => dma_addr,
1130 -- dma_data => dma_data,
1136 -- dma_data => dma_data,
1131 -- dma_valid => dma_valid,
1137 -- dma_valid => dma_valid,
1132 -- dma_valid_burst => dma_valid_burst,
1138 -- dma_valid_burst => dma_valid_burst,
1133 -- dma_ren => dma_ren,
1139 -- dma_ren => dma_ren,
1134 -- dma_done => dma_done,
1140 -- dma_done => dma_done,
1135
1141
1136 -- ready_matrix_f0 => ready_matrix_f0,
1142 -- ready_matrix_f0 => ready_matrix_f0,
1137 -- ready_matrix_f1 => ready_matrix_f1,
1143 -- ready_matrix_f1 => ready_matrix_f1,
1138 -- ready_matrix_f2 => ready_matrix_f2,
1144 -- ready_matrix_f2 => ready_matrix_f2,
1139
1145
1140 -- error_bad_component_error => error_bad_component_error,
1146 -- error_bad_component_error => error_bad_component_error,
1141 -- error_buffer_full => error_buffer_full,
1147 -- error_buffer_full => error_buffer_full,
1142
1148
1143 -- debug_reg => debug_reg,
1149 -- debug_reg => debug_reg,
1144 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1150 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1145 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1151 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1146 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1152 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1147
1153
1148 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1154 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1149 -- config_active_interruption_onError => config_active_interruption_onError,
1155 -- config_active_interruption_onError => config_active_interruption_onError,
1150
1156
1151 -- addr_matrix_f0 => addr_matrix_f0,
1157 -- addr_matrix_f0 => addr_matrix_f0,
1152 -- addr_matrix_f1 => addr_matrix_f1,
1158 -- addr_matrix_f1 => addr_matrix_f1,
1153 -- addr_matrix_f2 => addr_matrix_f2,
1159 -- addr_matrix_f2 => addr_matrix_f2,
1154
1160
1155 -- matrix_time_f0 => matrix_time_f0,
1161 -- matrix_time_f0 => matrix_time_f0,
1156 -- matrix_time_f1 => matrix_time_f1,
1162 -- matrix_time_f1 => matrix_time_f1,
1157 -- matrix_time_f2 => matrix_time_f2
1163 -- matrix_time_f2 => matrix_time_f2
1158 -- );
1164 -- );
1159 -----------------------------------------------------------------------------
1165 -----------------------------------------------------------------------------
1160
1166
1161
1167
1162
1168
1163
1169
1164
1170
1165
1171
1166 -----------------------------------------------------------------------------
1172 -----------------------------------------------------------------------------
1167 -- TIME MANAGMENT
1173 -- TIME MANAGMENT
1168 -----------------------------------------------------------------------------
1174 -----------------------------------------------------------------------------
1169 all_time <= coarse_time & fine_time;
1175 all_time <= coarse_time & fine_time;
1170 --
1176 --
1171 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1177 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1172 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1178 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1173 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1179 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1174 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1180 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1175
1181
1176 all_time_reg: FOR I IN 0 TO 3 GENERATE
1182 all_time_reg: FOR I IN 0 TO 3 GENERATE
1177
1183
1178 PROCESS (clk, rstn)
1184 PROCESS (clk, rstn)
1179 BEGIN
1185 BEGIN
1180 IF rstn = '0' THEN
1186 IF rstn = '0' THEN
1181 f_empty_reg(I) <= '1';
1187 f_empty_reg(I) <= '1';
1182 ELSIF clk'event AND clk = '1' THEN
1188 ELSIF clk'event AND clk = '1' THEN
1183 f_empty_reg(I) <= f_empty(I);
1189 f_empty_reg(I) <= f_empty(I);
1184 END IF;
1190 END IF;
1185 END PROCESS;
1191 END PROCESS;
1186
1192
1187 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1193 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1188
1194
1189 s_m_t_m_f0_A : spectral_matrix_time_managment
1195 s_m_t_m_f0_A : spectral_matrix_time_managment
1190 PORT MAP (
1196 PORT MAP (
1191 clk => clk,
1197 clk => clk,
1192 rstn => rstn,
1198 rstn => rstn,
1193 time_in => all_time,
1199 time_in => all_time,
1194 update_1 => time_update_f(I),
1200 update_1 => time_update_f(I),
1195 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1201 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1196 );
1202 );
1197
1203
1198 END GENERATE all_time_reg;
1204 END GENERATE all_time_reg;
1199
1205
1200 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1206 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1201 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1207 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1202 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1208 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1203 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1209 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1204
1210
1205 -----------------------------------------------------------------------------
1211 -----------------------------------------------------------------------------
1206
1212
1207 END Behavioral;
1213 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,386 +1,390
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER);
72 Mem_use : INTEGER);
73 PORT (
73 PORT (
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 dma_fifo_burst_valid : OUT STD_LOGIC;
86 dma_fifo_burst_valid : OUT STD_LOGIC;
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 dma_fifo_ren : IN STD_LOGIC;
88 dma_fifo_ren : IN STD_LOGIC;
89 dma_buffer_new : OUT STD_LOGIC;
89 dma_buffer_new : OUT STD_LOGIC;
90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 dma_buffer_full : IN STD_LOGIC;
92 dma_buffer_full : IN STD_LOGIC;
93 dma_buffer_full_err : IN STD_LOGIC;
93 dma_buffer_full_err : IN STD_LOGIC;
94 ready_matrix_f0 : OUT STD_LOGIC;
94 ready_matrix_f0 : OUT STD_LOGIC;
95 ready_matrix_f1 : OUT STD_LOGIC;
95 ready_matrix_f1 : OUT STD_LOGIC;
96 ready_matrix_f2 : OUT STD_LOGIC;
96 ready_matrix_f2 : OUT STD_LOGIC;
97 error_buffer_full : OUT STD_LOGIC;
97 error_buffer_full : OUT STD_LOGIC;
98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
99 status_ready_matrix_f0 : IN STD_LOGIC;
99 status_ready_matrix_f0 : IN STD_LOGIC;
100 status_ready_matrix_f1 : IN STD_LOGIC;
100 status_ready_matrix_f1 : IN STD_LOGIC;
101 status_ready_matrix_f2 : IN STD_LOGIC;
101 status_ready_matrix_f2 : IN STD_LOGIC;
102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
111 END COMPONENT;
112 END COMPONENT;
112
113
113 COMPONENT lpp_lfr_ms_fsmdma
114 COMPONENT lpp_lfr_ms_fsmdma
114 PORT (
115 PORT (
115 clk : IN STD_ULOGIC;
116 clk : IN STD_ULOGIC;
116 rstn : IN STD_ULOGIC;
117 rstn : IN STD_ULOGIC;
117 run : IN STD_LOGIC;
118 run : IN STD_LOGIC;
118 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
119 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
119 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
120 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
120 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 fifo_empty : IN STD_LOGIC;
122 fifo_empty : IN STD_LOGIC;
122 fifo_empty_threshold : IN STD_LOGIC;
123 fifo_empty_threshold : IN STD_LOGIC;
123 fifo_ren : OUT STD_LOGIC;
124 fifo_ren : OUT STD_LOGIC;
124 dma_fifo_valid_burst : OUT STD_LOGIC;
125 dma_fifo_valid_burst : OUT STD_LOGIC;
125 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 dma_fifo_ren : IN STD_LOGIC;
127 dma_fifo_ren : IN STD_LOGIC;
127 dma_buffer_new : OUT STD_LOGIC;
128 dma_buffer_new : OUT STD_LOGIC;
128 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
130 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
130 dma_buffer_full : IN STD_LOGIC;
131 dma_buffer_full : IN STD_LOGIC;
131 dma_buffer_full_err : IN STD_LOGIC;
132 dma_buffer_full_err : IN STD_LOGIC;
132 status_ready_matrix_f0 : IN STD_LOGIC;
133 status_ready_matrix_f0 : IN STD_LOGIC;
133 status_ready_matrix_f1 : IN STD_LOGIC;
134 status_ready_matrix_f1 : IN STD_LOGIC;
134 status_ready_matrix_f2 : IN STD_LOGIC;
135 status_ready_matrix_f2 : IN STD_LOGIC;
135 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 ready_matrix_f0 : OUT STD_LOGIC;
142 ready_matrix_f0 : OUT STD_LOGIC;
142 ready_matrix_f1 : OUT STD_LOGIC;
143 ready_matrix_f1 : OUT STD_LOGIC;
143 ready_matrix_f2 : OUT STD_LOGIC;
144 ready_matrix_f2 : OUT STD_LOGIC;
144 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 error_buffer_full : OUT STD_LOGIC);
148 error_buffer_full : OUT STD_LOGIC);
148 END COMPONENT;
149 END COMPONENT;
149
150
150 COMPONENT lpp_lfr_ms_FFT
151 COMPONENT lpp_lfr_ms_FFT
151 PORT (
152 PORT (
152 clk : IN STD_LOGIC;
153 clk : IN STD_LOGIC;
153 rstn : IN STD_LOGIC;
154 rstn : IN STD_LOGIC;
154 sample_valid : IN STD_LOGIC;
155 sample_valid : IN STD_LOGIC;
155 fft_read : IN STD_LOGIC;
156 fft_read : IN STD_LOGIC;
156 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
157 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
157 sample_load : OUT STD_LOGIC;
158 sample_load : OUT STD_LOGIC;
158 fft_pong : OUT STD_LOGIC;
159 fft_pong : OUT STD_LOGIC;
159 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
161 fft_data_valid : OUT STD_LOGIC;
162 fft_data_valid : OUT STD_LOGIC;
162 fft_ready : OUT STD_LOGIC);
163 fft_ready : OUT STD_LOGIC);
163 END COMPONENT;
164 END COMPONENT;
164
165
165 COMPONENT lpp_lfr_filter
166 COMPONENT lpp_lfr_filter
166 GENERIC (
167 GENERIC (
167 Mem_use : INTEGER);
168 Mem_use : INTEGER);
168 PORT (
169 PORT (
169 sample : IN Samples(7 DOWNTO 0);
170 sample : IN Samples(7 DOWNTO 0);
170 sample_val : IN STD_LOGIC;
171 sample_val : IN STD_LOGIC;
171 clk : IN STD_LOGIC;
172 clk : IN STD_LOGIC;
172 rstn : IN STD_LOGIC;
173 rstn : IN STD_LOGIC;
173 data_shaping_SP0 : IN STD_LOGIC;
174 data_shaping_SP0 : IN STD_LOGIC;
174 data_shaping_SP1 : IN STD_LOGIC;
175 data_shaping_SP1 : IN STD_LOGIC;
175 data_shaping_R0 : IN STD_LOGIC;
176 data_shaping_R0 : IN STD_LOGIC;
176 data_shaping_R1 : IN STD_LOGIC;
177 data_shaping_R1 : IN STD_LOGIC;
177 data_shaping_R2 : IN STD_LOGIC;
178 data_shaping_R2 : IN STD_LOGIC;
178 sample_f0_val : OUT STD_LOGIC;
179 sample_f0_val : OUT STD_LOGIC;
179 sample_f1_val : OUT STD_LOGIC;
180 sample_f1_val : OUT STD_LOGIC;
180 sample_f2_val : OUT STD_LOGIC;
181 sample_f2_val : OUT STD_LOGIC;
181 sample_f3_val : OUT STD_LOGIC;
182 sample_f3_val : OUT STD_LOGIC;
182 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
185 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
186 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
186 END COMPONENT;
187 END COMPONENT;
187
188
188 COMPONENT lpp_lfr
189 COMPONENT lpp_lfr
189 GENERIC (
190 GENERIC (
190 Mem_use : INTEGER;
191 Mem_use : INTEGER;
191 nb_data_by_buffer_size : INTEGER;
192 nb_data_by_buffer_size : INTEGER;
192 -- nb_word_by_buffer_size : INTEGER;
193 -- nb_word_by_buffer_size : INTEGER;
193 nb_snapshot_param_size : INTEGER;
194 nb_snapshot_param_size : INTEGER;
194 delta_vector_size : INTEGER;
195 delta_vector_size : INTEGER;
195 delta_vector_size_f0_2 : INTEGER;
196 delta_vector_size_f0_2 : INTEGER;
196 pindex : INTEGER;
197 pindex : INTEGER;
197 paddr : INTEGER;
198 paddr : INTEGER;
198 pmask : INTEGER;
199 pmask : INTEGER;
199 pirq_ms : INTEGER;
200 pirq_ms : INTEGER;
200 pirq_wfp : INTEGER;
201 pirq_wfp : INTEGER;
201 hindex : INTEGER;
202 hindex : INTEGER;
202 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
203 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
203 );
204 );
204 PORT (
205 PORT (
205 clk : IN STD_LOGIC;
206 clk : IN STD_LOGIC;
206 rstn : IN STD_LOGIC;
207 rstn : IN STD_LOGIC;
207 sample_B : IN Samples(2 DOWNTO 0);
208 sample_B : IN Samples(2 DOWNTO 0);
208 sample_E : IN Samples(4 DOWNTO 0);
209 sample_E : IN Samples(4 DOWNTO 0);
209 sample_val : IN STD_LOGIC;
210 sample_val : IN STD_LOGIC;
210 apbi : IN apb_slv_in_type;
211 apbi : IN apb_slv_in_type;
211 apbo : OUT apb_slv_out_type;
212 apbo : OUT apb_slv_out_type;
212 ahbi : IN AHB_Mst_In_Type;
213 ahbi : IN AHB_Mst_In_Type;
213 ahbo : OUT AHB_Mst_Out_Type;
214 ahbo : OUT AHB_Mst_Out_Type;
214 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 data_shaping_BW : OUT STD_LOGIC
217 data_shaping_BW : OUT STD_LOGIC ;
218 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
217 );
220 );
218 END COMPONENT;
221 END COMPONENT;
219
222
220 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
221 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
224 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
222 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
223 COMPONENT lpp_lfr_WFP_nMS
226 COMPONENT lpp_lfr_WFP_nMS
224 GENERIC (
227 GENERIC (
225 Mem_use : INTEGER;
228 Mem_use : INTEGER;
226 nb_data_by_buffer_size : INTEGER;
229 nb_data_by_buffer_size : INTEGER;
227 nb_word_by_buffer_size : INTEGER;
230 nb_word_by_buffer_size : INTEGER;
228 nb_snapshot_param_size : INTEGER;
231 nb_snapshot_param_size : INTEGER;
229 delta_vector_size : INTEGER;
232 delta_vector_size : INTEGER;
230 delta_vector_size_f0_2 : INTEGER;
233 delta_vector_size_f0_2 : INTEGER;
231 pindex : INTEGER;
234 pindex : INTEGER;
232 paddr : INTEGER;
235 paddr : INTEGER;
233 pmask : INTEGER;
236 pmask : INTEGER;
234 pirq_ms : INTEGER;
237 pirq_ms : INTEGER;
235 pirq_wfp : INTEGER;
238 pirq_wfp : INTEGER;
236 hindex : INTEGER;
239 hindex : INTEGER;
237 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
240 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
238 PORT (
241 PORT (
239 clk : IN STD_LOGIC;
242 clk : IN STD_LOGIC;
240 rstn : IN STD_LOGIC;
243 rstn : IN STD_LOGIC;
241 sample_B : IN Samples(2 DOWNTO 0);
244 sample_B : IN Samples(2 DOWNTO 0);
242 sample_E : IN Samples(4 DOWNTO 0);
245 sample_E : IN Samples(4 DOWNTO 0);
243 sample_val : IN STD_LOGIC;
246 sample_val : IN STD_LOGIC;
244 apbi : IN apb_slv_in_type;
247 apbi : IN apb_slv_in_type;
245 apbo : OUT apb_slv_out_type;
248 apbo : OUT apb_slv_out_type;
246 ahbi : IN AHB_Mst_In_Type;
249 ahbi : IN AHB_Mst_In_Type;
247 ahbo : OUT AHB_Mst_Out_Type;
250 ahbo : OUT AHB_Mst_Out_Type;
248 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
252 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
250 data_shaping_BW : OUT STD_LOGIC;
253 data_shaping_BW : OUT STD_LOGIC;
251 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
254 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
252 END COMPONENT;
255 END COMPONENT;
253 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
254
257
255 COMPONENT lpp_lfr_apbreg
258 COMPONENT lpp_lfr_apbreg
256 GENERIC (
259 GENERIC (
257 nb_data_by_buffer_size : INTEGER;
260 nb_data_by_buffer_size : INTEGER;
258 nb_snapshot_param_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
259 delta_vector_size : INTEGER;
262 delta_vector_size : INTEGER;
260 delta_vector_size_f0_2 : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
261 pindex : INTEGER;
264 pindex : INTEGER;
262 paddr : INTEGER;
265 paddr : INTEGER;
263 pmask : INTEGER;
266 pmask : INTEGER;
264 pirq_ms : INTEGER;
267 pirq_ms : INTEGER;
265 pirq_wfp : INTEGER;
268 pirq_wfp : INTEGER;
266 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
269 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
267 PORT (
270 PORT (
268 HCLK : IN STD_ULOGIC;
271 HCLK : IN STD_ULOGIC;
269 HRESETn : IN STD_ULOGIC;
272 HRESETn : IN STD_ULOGIC;
270 apbi : IN apb_slv_in_type;
273 apbi : IN apb_slv_in_type;
271 apbo : OUT apb_slv_out_type;
274 apbo : OUT apb_slv_out_type;
272 run_ms : OUT STD_LOGIC;
275 run_ms : OUT STD_LOGIC;
273 ready_matrix_f0 : IN STD_LOGIC;
276 ready_matrix_f0 : IN STD_LOGIC;
274 ready_matrix_f1 : IN STD_LOGIC;
277 ready_matrix_f1 : IN STD_LOGIC;
275 ready_matrix_f2 : IN STD_LOGIC;
278 ready_matrix_f2 : IN STD_LOGIC;
276 error_buffer_full : IN STD_LOGIC;
279 error_buffer_full : IN STD_LOGIC;
277 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
280 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
278 status_ready_matrix_f0 : OUT STD_LOGIC;
281 status_ready_matrix_f0 : OUT STD_LOGIC;
279 status_ready_matrix_f1 : OUT STD_LOGIC;
282 status_ready_matrix_f1 : OUT STD_LOGIC;
280 status_ready_matrix_f2 : OUT STD_LOGIC;
283 status_ready_matrix_f2 : OUT STD_LOGIC;
281 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
287 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
285 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
288 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
286 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
289 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
287 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
290 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
288 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
291 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
289 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
292 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
290 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
293 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
291 data_shaping_BW : OUT STD_LOGIC;
294 data_shaping_BW : OUT STD_LOGIC;
292 data_shaping_SP0 : OUT STD_LOGIC;
295 data_shaping_SP0 : OUT STD_LOGIC;
293 data_shaping_SP1 : OUT STD_LOGIC;
296 data_shaping_SP1 : OUT STD_LOGIC;
294 data_shaping_R0 : OUT STD_LOGIC;
297 data_shaping_R0 : OUT STD_LOGIC;
295 data_shaping_R1 : OUT STD_LOGIC;
298 data_shaping_R1 : OUT STD_LOGIC;
296 data_shaping_R2 : OUT STD_LOGIC;
299 data_shaping_R2 : OUT STD_LOGIC;
297 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
300 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
298 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
299 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
302 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
300 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
303 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
304 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
302 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
305 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
303 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
306 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
304 enable_f0 : OUT STD_LOGIC;
307 enable_f0 : OUT STD_LOGIC;
305 enable_f1 : OUT STD_LOGIC;
308 enable_f1 : OUT STD_LOGIC;
306 enable_f2 : OUT STD_LOGIC;
309 enable_f2 : OUT STD_LOGIC;
307 enable_f3 : OUT STD_LOGIC;
310 enable_f3 : OUT STD_LOGIC;
308 burst_f0 : OUT STD_LOGIC;
311 burst_f0 : OUT STD_LOGIC;
309 burst_f1 : OUT STD_LOGIC;
312 burst_f1 : OUT STD_LOGIC;
310 burst_f2 : OUT STD_LOGIC;
313 burst_f2 : OUT STD_LOGIC;
311 run : OUT STD_LOGIC;
314 run : OUT STD_LOGIC;
312 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
315 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
313 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
316 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
314 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
317 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
315 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
316 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
317 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
318 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
319 END COMPONENT;
323 END COMPONENT;
320
324
321 COMPONENT lpp_top_ms
325 COMPONENT lpp_top_ms
322 GENERIC (
326 GENERIC (
323 Mem_use : INTEGER;
327 Mem_use : INTEGER;
324 nb_burst_available_size : INTEGER;
328 nb_burst_available_size : INTEGER;
325 nb_snapshot_param_size : INTEGER;
329 nb_snapshot_param_size : INTEGER;
326 delta_snapshot_size : INTEGER;
330 delta_snapshot_size : INTEGER;
327 delta_f2_f0_size : INTEGER;
331 delta_f2_f0_size : INTEGER;
328 delta_f2_f1_size : INTEGER;
332 delta_f2_f1_size : INTEGER;
329 pindex : INTEGER;
333 pindex : INTEGER;
330 paddr : INTEGER;
334 paddr : INTEGER;
331 pmask : INTEGER;
335 pmask : INTEGER;
332 pirq_ms : INTEGER;
336 pirq_ms : INTEGER;
333 pirq_wfp : INTEGER;
337 pirq_wfp : INTEGER;
334 hindex_wfp : INTEGER;
338 hindex_wfp : INTEGER;
335 hindex_ms : INTEGER);
339 hindex_ms : INTEGER);
336 PORT (
340 PORT (
337 clk : IN STD_LOGIC;
341 clk : IN STD_LOGIC;
338 rstn : IN STD_LOGIC;
342 rstn : IN STD_LOGIC;
339 sample_B : IN Samples14v(2 DOWNTO 0);
343 sample_B : IN Samples14v(2 DOWNTO 0);
340 sample_E : IN Samples14v(4 DOWNTO 0);
344 sample_E : IN Samples14v(4 DOWNTO 0);
341 sample_val : IN STD_LOGIC;
345 sample_val : IN STD_LOGIC;
342 apbi : IN apb_slv_in_type;
346 apbi : IN apb_slv_in_type;
343 apbo : OUT apb_slv_out_type;
347 apbo : OUT apb_slv_out_type;
344 ahbi_ms : IN AHB_Mst_In_Type;
348 ahbi_ms : IN AHB_Mst_In_Type;
345 ahbo_ms : OUT AHB_Mst_Out_Type;
349 ahbo_ms : OUT AHB_Mst_Out_Type;
346 data_shaping_BW : OUT STD_LOGIC;
350 data_shaping_BW : OUT STD_LOGIC;
347 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
351 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
352 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
353 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
350 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
354 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
351 );
355 );
352 END COMPONENT;
356 END COMPONENT;
353
357
354 COMPONENT lpp_apbreg_ms_pointer
358 COMPONENT lpp_apbreg_ms_pointer
355 PORT (
359 PORT (
356 clk : IN STD_LOGIC;
360 clk : IN STD_LOGIC;
357 rstn : IN STD_LOGIC;
361 rstn : IN STD_LOGIC;
358 run : IN STD_LOGIC;
362 run : IN STD_LOGIC;
359 reg0_status_ready_matrix : IN STD_LOGIC;
363 reg0_status_ready_matrix : IN STD_LOGIC;
360 reg0_ready_matrix : OUT STD_LOGIC;
364 reg0_ready_matrix : OUT STD_LOGIC;
361 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
362 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
366 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
363 reg1_status_ready_matrix : IN STD_LOGIC;
367 reg1_status_ready_matrix : IN STD_LOGIC;
364 reg1_ready_matrix : OUT STD_LOGIC;
368 reg1_ready_matrix : OUT STD_LOGIC;
365 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
369 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
370 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
367 ready_matrix : IN STD_LOGIC;
371 ready_matrix : IN STD_LOGIC;
368 status_ready_matrix : OUT STD_LOGIC;
372 status_ready_matrix : OUT STD_LOGIC;
369 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
373 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
370 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
374 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
371 END COMPONENT;
375 END COMPONENT;
372
376
373 COMPONENT lpp_lfr_ms_reg_head
377 COMPONENT lpp_lfr_ms_reg_head
374 PORT (
378 PORT (
375 clk : IN STD_LOGIC;
379 clk : IN STD_LOGIC;
376 rstn : IN STD_LOGIC;
380 rstn : IN STD_LOGIC;
377 in_wen : IN STD_LOGIC;
381 in_wen : IN STD_LOGIC;
378 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
382 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
379 in_full : IN STD_LOGIC;
383 in_full : IN STD_LOGIC;
380 in_empty : IN STD_LOGIC;
384 in_empty : IN STD_LOGIC;
381 out_wen : OUT STD_LOGIC;
385 out_wen : OUT STD_LOGIC;
382 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
386 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
383 out_full : OUT STD_LOGIC);
387 out_full : OUT STD_LOGIC);
384 END COMPONENT;
388 END COMPONENT;
385
389
386 END lpp_lfr_pkg;
390 END lpp_lfr_pkg;
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