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Correction du bugs 266 (a confirmer) :...
pellion -
r465:8e656681264f (MINI-LFR) WFP_MS-0-1-35 JC
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@@ -38,7 +38,7 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
@@ -128,7 +128,7 ARCHITECTURE beh OF MINI_LFR_top IS
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
@@ -139,11 +139,11 ARCHITECTURE beh OF MINI_LFR_top IS
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -171,24 +171,28 ARCHITECTURE beh OF MINI_LFR_top IS
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
192 BEGIN -- beh
196 BEGIN -- beh
193
197
194 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
@@ -215,7 +219,7 BEGIN -- beh
215 -- clk_24 <= NOT clk_24;
219 -- clk_24 <= NOT clk_24;
216 -- END IF;
220 -- END IF;
217 --END PROCESS;
221 --END PROCESS;
218
222
219 --PROCESS(clk_25)
223 --PROCESS(clk_25)
220 --BEGIN
224 --BEGIN
221 -- IF clk_25'EVENT AND clk_25 = '1' THEN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
@@ -232,8 +236,8 BEGIN -- beh
232 rstn_50_d2 <= '0';
236 rstn_50_d2 <= '0';
233 rstn_50_d3 <= '0';
237 rstn_50_d3 <= '0';
234
238
235 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
236 clk_50_s <= NOT clk_50_s;
240 clk_50_s <= NOT clk_50_s;
237 rstn_50_d1 <= '1';
241 rstn_50_d1 <= '1';
238 rstn_50_d2 <= rstn_50_d1;
242 rstn_50_d2 <= rstn_50_d1;
239 rstn_50_d3 <= rstn_50_d2;
243 rstn_50_d3 <= rstn_50_d2;
@@ -244,12 +248,12 BEGIN -- beh
244 PROCESS (clk_50_s, rstn_50)
248 PROCESS (clk_50_s, rstn_50)
245 BEGIN -- PROCESS
249 BEGIN -- PROCESS
246 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
247 clk_25 <= '0';
251 clk_25 <= '0';
248 rstn_25 <= '0';
252 rstn_25 <= '0';
249 rstn_25_d1 <= '0';
253 rstn_25_d1 <= '0';
250 rstn_25_d2 <= '0';
254 rstn_25_d2 <= '0';
251 rstn_25_d3 <= '0';
255 rstn_25_d3 <= '0';
252 ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
253 clk_25 <= NOT clk_25;
257 clk_25 <= NOT clk_25;
254 rstn_25_d1 <= '1';
258 rstn_25_d1 <= '1';
255 rstn_25_d2 <= rstn_25_d1;
259 rstn_25_d2 <= rstn_25_d1;
@@ -262,16 +266,16 BEGIN -- beh
262 BEGIN -- PROCESS
266 BEGIN -- PROCESS
263 IF reset = '0' THEN -- asynchronous reset (active low)
267 IF reset = '0' THEN -- asynchronous reset (active low)
264 clk_24 <= '0';
268 clk_24 <= '0';
265 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
266 clk_24 <= NOT clk_24;
270 clk_24 <= NOT clk_24;
267 END IF;
271 END IF;
268 END PROCESS;
272 END PROCESS;
269
273
270 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
271
275
272 PROCESS (clk_25, rstn_25)
276 PROCESS (clk_25, rstn_25)
273 BEGIN -- PROCESS
277 BEGIN -- PROCESS
274 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
275 LED0 <= '0';
279 LED0 <= '0';
276 LED1 <= '0';
280 LED1 <= '0';
277 LED2 <= '0';
281 LED2 <= '0';
@@ -306,10 +310,10 BEGIN -- beh
306
310
307 PROCESS (clk_24, rstn_25)
311 PROCESS (clk_24, rstn_25)
308 BEGIN -- PROCESS
312 BEGIN -- PROCESS
309 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
310 I00_s <= '0';
314 I00_s <= '0';
311 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
312 I00_s <= NOT I00_s ;
316 I00_s <= NOT I00_s;
313 END IF;
317 END IF;
314 END PROCESS;
318 END PROCESS;
315 -- IO0 <= I00_s;
319 -- IO0 <= I00_s;
@@ -375,20 +379,20 BEGIN -- beh
375 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1 : apb_lfr_time_management
380 apb_lfr_time_management_1 : apb_lfr_time_management
377 GENERIC MAP (
381 GENERIC MAP (
378 pindex => 6,
382 pindex => 6,
379 paddr => 6,
383 paddr => 6,
380 pmask => 16#fff#,
384 pmask => 16#fff#,
381 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
382 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
383 PORT MAP (
387 PORT MAP (
384 clk25MHz => clk_25,
388 clk25MHz => clk_25,
385 clk24_576MHz => clk_24, -- 49.152MHz/2
389 clk24_576MHz => clk_24, -- 49.152MHz/2
386 resetn => rstn_25,
390 resetn => rstn_25,
387 grspw_tick => swno.tickout,
391 grspw_tick => swno.tickout,
388 apbi => apbi_ext,
392 apbi => apbi_ext,
389 apbo => apbo_ext(6),
393 apbo => apbo_ext(6),
390 coarse_time => coarse_time,
394 coarse_time => coarse_time,
391 fine_time => fine_time,
395 fine_time => fine_time,
392 LFR_soft_rstn => LFR_soft_rstn
396 LFR_soft_rstn => LFR_soft_rstn
393 );
397 );
394
398
@@ -439,7 +443,7 BEGIN -- beh
439 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
440 END GENERATE spw_inputloop;
444 END GENERATE spw_inputloop;
441
445
442 swni.rmapnodeaddr <= (others => '0');
446 swni.rmapnodeaddr <= (OTHERS => '0');
443
447
444 -- SPW core
448 -- SPW core
445 sw0 : grspwm GENERIC MAP(
449 sw0 : grspwm GENERIC MAP(
@@ -485,23 +489,23 BEGIN -- beh
485 -------------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
486
490
487
491
488 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
489 LFR_rstn <= rstn_25;
493 --LFR_rstn <= rstn_25;
490
494
491 lpp_lfr_1 : lpp_lfr
495 lpp_lfr_1 : lpp_lfr
492 GENERIC MAP (
496 GENERIC MAP (
493 Mem_use => use_RAM,
497 Mem_use => use_RAM,
494 nb_data_by_buffer_size => 32,
498 nb_data_by_buffer_size => 32,
495 nb_snapshot_param_size => 32,
499 nb_snapshot_param_size => 32,
496 delta_vector_size => 32,
500 delta_vector_size => 32,
497 delta_vector_size_f0_2 => 7, -- log2(96)
501 delta_vector_size_f0_2 => 7, -- log2(96)
498 pindex => 15,
502 pindex => 15,
499 paddr => 15,
503 paddr => 15,
500 pmask => 16#fff#,
504 pmask => 16#fff#,
501 pirq_ms => 6,
505 pirq_ms => 6,
502 pirq_wfp => 14,
506 pirq_wfp => 14,
503 hindex => 2,
507 hindex => 2,
504 top_lfr_version => X"000122") -- aa.bb.cc version
508 top_lfr_version => X"000123") -- aa.bb.cc version
505 PORT MAP (
509 PORT MAP (
506 clk => clk_25,
510 clk => clk_25,
507 rstn => LFR_rstn,
511 rstn => LFR_rstn,
@@ -514,13 +518,25 BEGIN -- beh
514 ahbo => ahbo_m_ext(2),
518 ahbo => ahbo_m_ext(2),
515 coarse_time => coarse_time,
519 coarse_time => coarse_time,
516 fine_time => fine_time,
520 fine_time => fine_time,
517 data_shaping_BW => bias_fail_sw_sig);
521 data_shaping_BW => bias_fail_sw_sig,
522 debug_vector => lfr_debug_vector,
523 debug_vector_ms => lfr_debug_vector_ms
524 );
518
525
519 observation_reg <= (others => '0');
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
520 observation_vector_0 <= (others => '0');
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
521 observation_vector_1 <= (others => '0');
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 IO0 <= rstn_25;
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
522
538
523 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
524 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
525 END GENERATE all_sample;
541 END GENERATE all_sample;
526
542
@@ -529,7 +545,7 BEGIN -- beh
529 ChannelCount => 8,
545 ChannelCount => 8,
530 SampleNbBits => 14,
546 SampleNbBits => 14,
531 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
532 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
533 PORT MAP (
549 PORT MAP (
534 -- CONV
550 -- CONV
535 cnv_clk => clk_24,
551 cnv_clk => clk_24,
@@ -560,9 +576,9 BEGIN -- beh
560 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
561 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
562
578
563 gpioi.sig_en <= (others => '0');
579 gpioi.sig_en <= (OTHERS => '0');
564 gpioi.sig_in <= (others => '0');
580 gpioi.sig_in <= (OTHERS => '0');
565 gpioi.din <= (others => '0');
581 gpioi.din <= (OTHERS => '0');
566 --pio_pad_0 : iopad
582 --pio_pad_0 : iopad
567 -- GENERIC MAP (tech => CFG_PADTECH)
583 -- GENERIC MAP (tech => CFG_PADTECH)
568 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
@@ -590,84 +606,84 BEGIN -- beh
590
606
591 PROCESS (clk_25, rstn_25)
607 PROCESS (clk_25, rstn_25)
592 BEGIN -- PROCESS
608 BEGIN -- PROCESS
593 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
594 IO0 <= '0';
610 -- --IO0 <= '0';
595 IO1 <= '0';
611 -- IO1 <= '0';
596 IO2 <= '0';
612 -- IO2 <= '0';
597 IO3 <= '0';
613 -- IO3 <= '0';
598 IO4 <= '0';
614 -- IO4 <= '0';
599 IO5 <= '0';
615 -- IO5 <= '0';
600 IO6 <= '0';
616 -- IO6 <= '0';
601 IO7 <= '0';
617 -- IO7 <= '0';
602 IO8 <= '0';
618 IO8 <= '0';
603 IO9 <= '0';
619 IO9 <= '0';
604 IO10 <= '0';
620 IO10 <= '0';
605 IO11 <= '0';
621 IO11 <= '0';
606 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
607 CASE gpioo.dout(2 DOWNTO 0) IS
623 CASE gpioo.dout(2 DOWNTO 0) IS
608 WHEN "011" =>
624 WHEN "011" =>
609 IO0 <= observation_reg(0 );
625 -- --IO0 <= observation_reg(0 );
610 IO1 <= observation_reg(1 );
626 -- IO1 <= observation_reg(1 );
611 IO2 <= observation_reg(2 );
627 -- IO2 <= observation_reg(2 );
612 IO3 <= observation_reg(3 );
628 -- IO3 <= observation_reg(3 );
613 IO4 <= observation_reg(4 );
629 -- IO4 <= observation_reg(4 );
614 IO5 <= observation_reg(5 );
630 -- IO5 <= observation_reg(5 );
615 IO6 <= observation_reg(6 );
631 -- IO6 <= observation_reg(6 );
616 IO7 <= observation_reg(7 );
632 -- IO7 <= observation_reg(7 );
617 IO8 <= observation_reg(8 );
633 IO8 <= observation_reg(8);
618 IO9 <= observation_reg(9 );
634 IO9 <= observation_reg(9);
619 IO10 <= observation_reg(10);
635 IO10 <= observation_reg(10);
620 IO11 <= observation_reg(11);
636 IO11 <= observation_reg(11);
621 WHEN "001" =>
637 WHEN "001" =>
622 IO0 <= observation_reg(0 + 12);
638 -- --IO0 <= observation_reg(0 + 12);
623 IO1 <= observation_reg(1 + 12);
639 -- IO1 <= observation_reg(1 + 12);
624 IO2 <= observation_reg(2 + 12);
640 -- IO2 <= observation_reg(2 + 12);
625 IO3 <= observation_reg(3 + 12);
641 -- IO3 <= observation_reg(3 + 12);
626 IO4 <= observation_reg(4 + 12);
642 -- IO4 <= observation_reg(4 + 12);
627 IO5 <= observation_reg(5 + 12);
643 -- IO5 <= observation_reg(5 + 12);
628 IO6 <= observation_reg(6 + 12);
644 -- IO6 <= observation_reg(6 + 12);
629 IO7 <= observation_reg(7 + 12);
645 -- IO7 <= observation_reg(7 + 12);
630 IO8 <= observation_reg(8 + 12);
646 IO8 <= observation_reg(8 + 12);
631 IO9 <= observation_reg(9 + 12);
647 IO9 <= observation_reg(9 + 12);
632 IO10 <= observation_reg(10 + 12);
648 IO10 <= observation_reg(10 + 12);
633 IO11 <= observation_reg(11 + 12);
649 IO11 <= observation_reg(11 + 12);
634 WHEN "010" =>
650 WHEN "010" =>
635 IO0 <= observation_reg(0 + 12 + 12);
651 -- --IO0 <= observation_reg(0 + 12 + 12);
636 IO1 <= observation_reg(1 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
637 IO2 <= observation_reg(2 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
638 IO3 <= observation_reg(3 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
639 IO4 <= observation_reg(4 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
640 IO5 <= observation_reg(5 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
641 IO6 <= observation_reg(6 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
642 IO7 <= observation_reg(7 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
643 IO8 <= '0';
659 IO8 <= '0';
644 IO9 <= '0';
660 IO9 <= '0';
645 IO10 <= '0';
661 IO10 <= '0';
646 IO11 <= '0';
662 IO11 <= '0';
647 WHEN "000" =>
663 WHEN "000" =>
648 IO0 <= observation_vector_0(0 );
664 -- --IO0 <= observation_vector_0(0 );
649 IO1 <= observation_vector_0(1 );
665 -- IO1 <= observation_vector_0(1 );
650 IO2 <= observation_vector_0(2 );
666 -- IO2 <= observation_vector_0(2 );
651 IO3 <= observation_vector_0(3 );
667 -- IO3 <= observation_vector_0(3 );
652 IO4 <= observation_vector_0(4 );
668 -- IO4 <= observation_vector_0(4 );
653 IO5 <= observation_vector_0(5 );
669 -- IO5 <= observation_vector_0(5 );
654 IO6 <= observation_vector_0(6 );
670 -- IO6 <= observation_vector_0(6 );
655 IO7 <= observation_vector_0(7 );
671 -- IO7 <= observation_vector_0(7 );
656 IO8 <= observation_vector_0(8 );
672 IO8 <= observation_vector_0(8);
657 IO9 <= observation_vector_0(9 );
673 IO9 <= observation_vector_0(9);
658 IO10 <= observation_vector_0(10);
674 IO10 <= observation_vector_0(10);
659 IO11 <= observation_vector_0(11);
675 IO11 <= observation_vector_0(11);
660 WHEN "100" =>
676 WHEN "100" =>
661 IO0 <= observation_vector_1(0 );
677 -- --IO0 <= observation_vector_1(0 );
662 IO1 <= observation_vector_1(1 );
678 -- IO1 <= observation_vector_1(1 );
663 IO2 <= observation_vector_1(2 );
679 -- IO2 <= observation_vector_1(2 );
664 IO3 <= observation_vector_1(3 );
680 -- IO3 <= observation_vector_1(3 );
665 IO4 <= observation_vector_1(4 );
681 -- IO4 <= observation_vector_1(4 );
666 IO5 <= observation_vector_1(5 );
682 -- IO5 <= observation_vector_1(5 );
667 IO6 <= observation_vector_1(6 );
683 -- IO6 <= observation_vector_1(6 );
668 IO7 <= observation_vector_1(7 );
684 -- IO7 <= observation_vector_1(7 );
669 IO8 <= observation_vector_1(8 );
685 IO8 <= observation_vector_1(8);
670 IO9 <= observation_vector_1(9 );
686 IO9 <= observation_vector_1(9);
671 IO10 <= observation_vector_1(10);
687 IO10 <= observation_vector_1(10);
672 IO11 <= observation_vector_1(11);
688 IO11 <= observation_vector_1(11);
673 WHEN OTHERS => NULL;
689 WHEN OTHERS => NULL;
@@ -678,21 +694,21 BEGIN -- beh
678 -----------------------------------------------------------------------------
694 -----------------------------------------------------------------------------
679 --
695 --
680 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
681 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
682 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
683 apbo_ext(I) <= apb_none;
699 apbo_ext(I) <= apb_none;
684 END GENERATE apbo_ext_not_used;
700 END GENERATE apbo_ext_not_used;
685 END GENERATE all_apbo_ext;
701 END GENERATE all_apbo_ext;
686
702
687
703
688 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
689 ahbo_s_ext(I) <= ahbs_none;
705 ahbo_s_ext(I) <= ahbs_none;
690 END GENERATE all_ahbo_ext;
706 END GENERATE all_ahbo_ext;
691
707
692 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
693 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
694 ahbo_m_ext(I) <= ahbm_none;
710 ahbo_m_ext(I) <= ahbm_none;
695 END GENERATE ahbo_m_ext_not_used;
711 END GENERATE ahbo_m_ext_not_used;
696 END GENERATE all_ahbo_m_ext;
712 END GENERATE all_ahbo_m_ext;
697
713
698 END beh; No newline at end of file
714 END beh;
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@@ -19,8 +19,6 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
21
22 LIBRARY postlayout;
23 USE postlayout.ALL;
24
22
25 ENTITY testbench IS
23 ENTITY testbench IS
26 END;
24 END;
@@ -194,18 +192,18 BEGIN
194 ADC_SDO <= x"AA";
192 ADC_SDO <= x"AA";
195
193
196 SRAM_DQ <= (OTHERS => 'Z');
194 SRAM_DQ <= (OTHERS => 'Z');
197 IO0 <= 'Z';
195 --IO0 <= 'Z';
198 IO1 <= 'Z';
196 --IO1 <= 'Z';
199 IO2 <= 'Z';
197 --IO2 <= 'Z';
200 IO3 <= 'Z';
198 --IO3 <= 'Z';
201 IO4 <= 'Z';
199 --IO4 <= 'Z';
202 IO5 <= 'Z';
200 --IO5 <= 'Z';
203 IO6 <= 'Z';
201 --IO6 <= 'Z';
204 IO7 <= 'Z';
202 --IO7 <= 'Z';
205 IO8 <= 'Z';
203 --IO8 <= 'Z';
206 IO9 <= 'Z';
204 --IO9 <= 'Z';
207 IO10 <= 'Z';
205 --IO10 <= 'Z';
208 IO11 <= 'Z';
206 --IO11 <= 'Z';
209
207
210 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
211 -- DUT
209 -- DUT
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@@ -58,7 +58,10 ENTITY lpp_lfr IS
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 --
60 --
61 data_shaping_BW : OUT STD_LOGIC
61 data_shaping_BW : OUT STD_LOGIC;
62 --
63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
62 );
65 );
63 END lpp_lfr;
66 END lpp_lfr;
64
67
@@ -223,9 +226,13 ARCHITECTURE beh OF lpp_lfr IS
223 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
224 SIGNAL dma_grant_error : STD_LOGIC;
227 SIGNAL dma_grant_error : STD_LOGIC;
225
228
229 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
226 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
227 -- SIGNAL run_dma : STD_LOGIC;
231 -- SIGNAL run_dma : STD_LOGIC;
228 BEGIN
232 BEGIN
233
234 debug_vector <= apb_reg_debug_vector;
235 -----------------------------------------------------------------------------
229
236
230 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
237 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
231 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
238 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
@@ -334,7 +341,8 BEGIN
334
341
335 wfp_ready_buffer => wfp_ready_buffer,-- TODO
342 wfp_ready_buffer => wfp_ready_buffer,-- TODO
336 wfp_buffer_time => wfp_buffer_time,-- TODO
343 wfp_buffer_time => wfp_buffer_time,-- TODO
337 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
344 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
345 debug_vector => apb_reg_debug_vector
338 );
346 );
339
347
340 -----------------------------------------------------------------------------
348 -----------------------------------------------------------------------------
@@ -480,7 +488,9 BEGIN
480
488
481 matrix_time_f0 => matrix_time_f0,
489 matrix_time_f0 => matrix_time_f0,
482 matrix_time_f1 => matrix_time_f1,
490 matrix_time_f1 => matrix_time_f1,
483 matrix_time_f2 => matrix_time_f2);
491 matrix_time_f2 => matrix_time_f2,
492
493 debug_vector => debug_vector_ms);
484
494
485 -----------------------------------------------------------------------------
495 -----------------------------------------------------------------------------
486 --run_dma <= run_ms OR run;
496 --run_dma <= run_ms OR run;
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@@ -137,7 +137,9 ENTITY lpp_lfr_apbreg IS
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
142 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
141
143
142 );
144 );
143
145
@@ -269,6 +271,15 ARCHITECTURE beh OF lpp_lfr_apbreg IS
269
271
270 BEGIN -- beh
272 BEGIN -- beh
271
273
274 debug_vector(0) <= error_buffer_full;
275 debug_vector(1) <= reg_sp.status_error_buffer_full;
276 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
277 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
278 debug_vector(8) <= ready_matrix_f2;
279 debug_vector(9) <= reg0_ready_matrix_f2;
280 debug_vector(10) <= reg1_ready_matrix_f2;
281 debug_vector(11) <= HRESETn;
282
272 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
283 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
273 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
284 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
274 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
285 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
@@ -778,4 +789,4 BEGIN -- beh
778
789
779 END beh;
790 END beh;
780
791
781 ------------------------------------------------------------------------------- No newline at end of file
792 ------------------------------------------------------------------------------
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@@ -76,8 +76,9 ENTITY lpp_lfr_ms IS
76
76
77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80
80 ---------------------------------------------------------------------------
81 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
81 );
82 );
82 END;
83 END;
83
84
@@ -442,7 +443,7 BEGIN
442 ReUse => (OTHERS => '0'),
443 ReUse => (OTHERS => '0'),
443 run => (OTHERS => '1'),
444 run => (OTHERS => '1'),
444
445
445 wen => sample_f2_wen,
446 wen => sample_f2_wen_s,
446 wdata => sample_f2_wdata,
447 wdata => sample_f2_wdata,
447 ren => sample_f2_ren,
448 ren => sample_f2_ren,
448 rdata => sample_f2_rdata,
449 rdata => sample_f2_rdata,
@@ -687,7 +688,12 BEGIN
687 fft_data_re => fft_data_re,
688 fft_data_re => fft_data_re,
688 fft_data_valid => fft_data_valid,
689 fft_data_valid => fft_data_valid,
689 fft_ready => fft_ready);
690 fft_ready => fft_ready);
691
692 debug_vector(0) <= fft_data_valid;
693 debug_vector(1) <= fft_ready;
694 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
690
695
696
691 -----------------------------------------------------------------------------
697 -----------------------------------------------------------------------------
692 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
698 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
693 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
699 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
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@@ -107,7 +107,8 PACKAGE lpp_lfr_pkg IS
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
111 END COMPONENT;
112 END COMPONENT;
112
113
113 COMPONENT lpp_lfr_ms_fsmdma
114 COMPONENT lpp_lfr_ms_fsmdma
@@ -213,7 +214,9 PACKAGE lpp_lfr_pkg IS
213 ahbo : OUT AHB_Mst_Out_Type;
214 ahbo : OUT AHB_Mst_Out_Type;
214 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
216 data_shaping_BW : OUT STD_LOGIC
217 data_shaping_BW : OUT STD_LOGIC ;
218 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
219 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
217 );
220 );
218 END COMPONENT;
221 END COMPONENT;
219
222
@@ -315,7 +318,8 PACKAGE lpp_lfr_pkg IS
315 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
318 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
316 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
319 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
317 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
320 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
318 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
321 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
319 END COMPONENT;
323 END COMPONENT;
320
324
321 COMPONENT lpp_top_ms
325 COMPONENT lpp_top_ms
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