@@ -38,7 +38,7 USE esa.memoryctrl.ALL; | |||
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 |
USE lpp.lpp_lfr_pkg.ALL; |
|
|
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
@@ -128,7 +128,7 ARCHITECTURE beh OF MINI_LFR_top IS | |||
|
128 | 128 | -- UART APB --------------------------------------------------------------- |
|
129 | 129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
130 | 130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
131 | -- | |
|
131 | -- | |
|
132 | 132 | SIGNAL I00_s : STD_LOGIC; |
|
133 | 133 | |
|
134 | 134 | -- CONSTANTS |
@@ -139,11 +139,11 ARCHITECTURE beh OF MINI_LFR_top IS | |||
|
139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
140 | 140 | |
|
141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none); | |
|
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); | |
|
143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none); | |
|
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); | |
|
145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none); | |
|
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); | |
|
147 | 147 | |
|
148 | 148 | -- Spacewire signals |
|
149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
@@ -171,24 +171,28 ARCHITECTURE beh OF MINI_LFR_top IS | |||
|
171 | 171 | |
|
172 | 172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
173 | 173 | |
|
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
175 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
176 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
177 | 177 | ----------------------------------------------------------------------------- |
|
178 | 178 | |
|
179 | 179 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
|
180 | SIGNAL LFR_rstn : STD_LOGIC; | |
|
180 | SIGNAL LFR_rstn : STD_LOGIC; | |
|
181 | 181 | |
|
182 | 182 | |
|
183 | 183 | SIGNAL rstn_25 : STD_LOGIC; |
|
184 | 184 | SIGNAL rstn_25_d1 : STD_LOGIC; |
|
185 | 185 | SIGNAL rstn_25_d2 : STD_LOGIC; |
|
186 | 186 | SIGNAL rstn_25_d3 : STD_LOGIC; |
|
187 | ||
|
187 | ||
|
188 | 188 | SIGNAL rstn_50 : STD_LOGIC; |
|
189 | 189 | SIGNAL rstn_50_d1 : STD_LOGIC; |
|
190 | 190 | SIGNAL rstn_50_d2 : STD_LOGIC; |
|
191 | 191 | SIGNAL rstn_50_d3 : STD_LOGIC; |
|
192 | ||
|
193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
195 | ||
|
192 | 196 | BEGIN -- beh |
|
193 | 197 | |
|
194 | 198 | ----------------------------------------------------------------------------- |
@@ -215,7 +219,7 BEGIN -- beh | |||
|
215 | 219 | -- clk_24 <= NOT clk_24; |
|
216 | 220 | -- END IF; |
|
217 | 221 | --END PROCESS; |
|
218 | ||
|
222 | ||
|
219 | 223 | --PROCESS(clk_25) |
|
220 | 224 | --BEGIN |
|
221 | 225 | -- IF clk_25'EVENT AND clk_25 = '1' THEN |
@@ -232,8 +236,8 BEGIN -- beh | |||
|
232 | 236 | rstn_50_d2 <= '0'; |
|
233 | 237 | rstn_50_d3 <= '0'; |
|
234 | 238 | |
|
235 |
ELSIF clk_50' |
|
|
236 | clk_50_s <= NOT clk_50_s; | |
|
239 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge | |
|
240 | clk_50_s <= NOT clk_50_s; | |
|
237 | 241 | rstn_50_d1 <= '1'; |
|
238 | 242 | rstn_50_d2 <= rstn_50_d1; |
|
239 | 243 | rstn_50_d3 <= rstn_50_d2; |
@@ -244,12 +248,12 BEGIN -- beh | |||
|
244 | 248 | PROCESS (clk_50_s, rstn_50) |
|
245 | 249 | BEGIN -- PROCESS |
|
246 | 250 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
247 | clk_25 <= '0'; | |
|
251 | clk_25 <= '0'; | |
|
248 | 252 | rstn_25 <= '0'; |
|
249 | 253 | rstn_25_d1 <= '0'; |
|
250 | 254 | rstn_25_d2 <= '0'; |
|
251 | 255 | rstn_25_d3 <= '0'; |
|
252 |
ELSIF clk_50_s' |
|
|
256 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
|
253 | 257 | clk_25 <= NOT clk_25; |
|
254 | 258 | rstn_25_d1 <= '1'; |
|
255 | 259 | rstn_25_d2 <= rstn_25_d1; |
@@ -262,16 +266,16 BEGIN -- beh | |||
|
262 | 266 | BEGIN -- PROCESS |
|
263 | 267 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
264 | 268 | clk_24 <= '0'; |
|
265 |
ELSIF clk_49' |
|
|
266 |
clk_24 <= NOT clk_24; |
|
|
269 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
|
270 | clk_24 <= NOT clk_24; | |
|
267 | 271 | END IF; |
|
268 | 272 | END PROCESS; |
|
269 | ||
|
273 | ||
|
270 | 274 | ----------------------------------------------------------------------------- |
|
271 | 275 | |
|
272 | 276 | PROCESS (clk_25, rstn_25) |
|
273 | 277 | BEGIN -- PROCESS |
|
274 |
IF rstn_25 = '0' THEN |
|
|
278 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
275 | 279 | LED0 <= '0'; |
|
276 | 280 | LED1 <= '0'; |
|
277 | 281 | LED2 <= '0'; |
@@ -306,10 +310,10 BEGIN -- beh | |||
|
306 | 310 | |
|
307 | 311 | PROCESS (clk_24, rstn_25) |
|
308 | 312 | BEGIN -- PROCESS |
|
309 |
IF rstn_25 = '0' THEN |
|
|
313 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
310 | 314 | I00_s <= '0'; |
|
311 | 315 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
312 |
I00_s <= NOT I00_s |
|
|
316 | I00_s <= NOT I00_s; | |
|
313 | 317 | END IF; |
|
314 | 318 | END PROCESS; |
|
315 | 319 | -- IO0 <= I00_s; |
@@ -375,20 +379,20 BEGIN -- beh | |||
|
375 | 379 | ------------------------------------------------------------------------------- |
|
376 | 380 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
377 | 381 | GENERIC MAP ( |
|
378 | pindex => 6, | |
|
379 | paddr => 6, | |
|
380 | pmask => 16#fff#, | |
|
381 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
|
382 | pindex => 6, | |
|
383 | paddr => 6, | |
|
384 | pmask => 16#fff#, | |
|
385 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
|
382 | 386 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
383 | 387 | PORT MAP ( |
|
384 | clk25MHz => clk_25, | |
|
385 |
clk24_576MHz => clk_24, |
|
|
386 | resetn => rstn_25, | |
|
387 | grspw_tick => swno.tickout, | |
|
388 | apbi => apbi_ext, | |
|
389 | apbo => apbo_ext(6), | |
|
390 | coarse_time => coarse_time, | |
|
391 | fine_time => fine_time, | |
|
388 | clk25MHz => clk_25, | |
|
389 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
|
390 | resetn => rstn_25, | |
|
391 | grspw_tick => swno.tickout, | |
|
392 | apbi => apbi_ext, | |
|
393 | apbo => apbo_ext(6), | |
|
394 | coarse_time => coarse_time, | |
|
395 | fine_time => fine_time, | |
|
392 | 396 | LFR_soft_rstn => LFR_soft_rstn |
|
393 | 397 | ); |
|
394 | 398 | |
@@ -439,7 +443,7 BEGIN -- beh | |||
|
439 | 443 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
440 | 444 | END GENERATE spw_inputloop; |
|
441 | 445 | |
|
442 |
swni.rmapnodeaddr <= ( |
|
|
446 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
|
443 | 447 | |
|
444 | 448 | -- SPW core |
|
445 | 449 | sw0 : grspwm GENERIC MAP( |
@@ -485,23 +489,23 BEGIN -- beh | |||
|
485 | 489 | ------------------------------------------------------------------------------- |
|
486 | 490 | |
|
487 | 491 | |
|
488 |
|
|
|
489 | LFR_rstn <= rstn_25; | |
|
490 | ||
|
492 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
|
493 | --LFR_rstn <= rstn_25; | |
|
494 | ||
|
491 | 495 | lpp_lfr_1 : lpp_lfr |
|
492 | 496 | GENERIC MAP ( |
|
493 | 497 | Mem_use => use_RAM, |
|
494 | 498 | nb_data_by_buffer_size => 32, |
|
495 | 499 | nb_snapshot_param_size => 32, |
|
496 | 500 | delta_vector_size => 32, |
|
497 | delta_vector_size_f0_2 => 7, -- log2(96) | |
|
501 | delta_vector_size_f0_2 => 7, -- log2(96) | |
|
498 | 502 | pindex => 15, |
|
499 | 503 | paddr => 15, |
|
500 | 504 | pmask => 16#fff#, |
|
501 | 505 | pirq_ms => 6, |
|
502 | 506 | pirq_wfp => 14, |
|
503 | 507 | hindex => 2, |
|
504 |
top_lfr_version => X"00012 |
|
|
508 | top_lfr_version => X"000123") -- aa.bb.cc version | |
|
505 | 509 | PORT MAP ( |
|
506 | 510 | clk => clk_25, |
|
507 | 511 | rstn => LFR_rstn, |
@@ -514,13 +518,25 BEGIN -- beh | |||
|
514 | 518 | ahbo => ahbo_m_ext(2), |
|
515 | 519 | coarse_time => coarse_time, |
|
516 | 520 | fine_time => fine_time, |
|
517 |
data_shaping_BW => bias_fail_sw_sig |
|
|
521 | data_shaping_BW => bias_fail_sw_sig, | |
|
522 | debug_vector => lfr_debug_vector, | |
|
523 | debug_vector_ms => lfr_debug_vector_ms | |
|
524 | ); | |
|
518 | 525 | |
|
519 | observation_reg <= (others => '0'); | |
|
520 | observation_vector_0 <= (others => '0'); | |
|
521 | observation_vector_1 <= (others => '0'); | |
|
526 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
|
527 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
|
528 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
|
529 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |
|
530 | IO0 <= rstn_25; | |
|
531 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |
|
532 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |
|
533 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |
|
534 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |
|
535 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |
|
536 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |
|
537 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |
|
522 | 538 | |
|
523 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE | |
|
539 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
|
524 | 540 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
525 | 541 | END GENERATE all_sample; |
|
526 | 542 | |
@@ -529,7 +545,7 BEGIN -- beh | |||
|
529 | 545 | ChannelCount => 8, |
|
530 | 546 | SampleNbBits => 14, |
|
531 | 547 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
532 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
|
548 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
|
533 | 549 | PORT MAP ( |
|
534 | 550 | -- CONV |
|
535 | 551 | cnv_clk => clk_24, |
@@ -560,9 +576,9 BEGIN -- beh | |||
|
560 | 576 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
561 | 577 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
562 | 578 | |
|
563 |
gpioi.sig_en <= ( |
|
|
564 |
gpioi.sig_in <= ( |
|
|
565 |
gpioi.din <= ( |
|
|
579 | gpioi.sig_en <= (OTHERS => '0'); | |
|
580 | gpioi.sig_in <= (OTHERS => '0'); | |
|
581 | gpioi.din <= (OTHERS => '0'); | |
|
566 | 582 | --pio_pad_0 : iopad |
|
567 | 583 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
568 | 584 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
@@ -590,84 +606,84 BEGIN -- beh | |||
|
590 | 606 | |
|
591 | 607 | PROCESS (clk_25, rstn_25) |
|
592 | 608 | BEGIN -- PROCESS |
|
593 |
IF rstn_25 = '0' THEN |
|
|
594 | IO0 <= '0'; | |
|
595 | IO1 <= '0'; | |
|
596 | IO2 <= '0'; | |
|
597 | IO3 <= '0'; | |
|
598 | IO4 <= '0'; | |
|
599 | IO5 <= '0'; | |
|
600 | IO6 <= '0'; | |
|
601 | IO7 <= '0'; | |
|
609 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
610 | -- --IO0 <= '0'; | |
|
611 | -- IO1 <= '0'; | |
|
612 | -- IO2 <= '0'; | |
|
613 | -- IO3 <= '0'; | |
|
614 | -- IO4 <= '0'; | |
|
615 | -- IO5 <= '0'; | |
|
616 | -- IO6 <= '0'; | |
|
617 | -- IO7 <= '0'; | |
|
602 | 618 | IO8 <= '0'; |
|
603 | 619 | IO9 <= '0'; |
|
604 | 620 | IO10 <= '0'; |
|
605 | 621 | IO11 <= '0'; |
|
606 |
ELSIF clk_25' |
|
|
622 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
|
607 | 623 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
608 |
WHEN "011" => |
|
|
609 | IO0 <= observation_reg(0 ); | |
|
610 | IO1 <= observation_reg(1 ); | |
|
611 | IO2 <= observation_reg(2 ); | |
|
612 | IO3 <= observation_reg(3 ); | |
|
613 | IO4 <= observation_reg(4 ); | |
|
614 | IO5 <= observation_reg(5 ); | |
|
615 | IO6 <= observation_reg(6 ); | |
|
616 | IO7 <= observation_reg(7 ); | |
|
617 |
IO8 <= observation_reg(8 |
|
|
618 |
IO9 <= observation_reg(9 |
|
|
624 | WHEN "011" => | |
|
625 | -- --IO0 <= observation_reg(0 ); | |
|
626 | -- IO1 <= observation_reg(1 ); | |
|
627 | -- IO2 <= observation_reg(2 ); | |
|
628 | -- IO3 <= observation_reg(3 ); | |
|
629 | -- IO4 <= observation_reg(4 ); | |
|
630 | -- IO5 <= observation_reg(5 ); | |
|
631 | -- IO6 <= observation_reg(6 ); | |
|
632 | -- IO7 <= observation_reg(7 ); | |
|
633 | IO8 <= observation_reg(8); | |
|
634 | IO9 <= observation_reg(9); | |
|
619 | 635 | IO10 <= observation_reg(10); |
|
620 | 636 | IO11 <= observation_reg(11); |
|
621 |
WHEN "001" => |
|
|
622 | IO0 <= observation_reg(0 + 12); | |
|
623 | IO1 <= observation_reg(1 + 12); | |
|
624 | IO2 <= observation_reg(2 + 12); | |
|
625 | IO3 <= observation_reg(3 + 12); | |
|
626 | IO4 <= observation_reg(4 + 12); | |
|
627 | IO5 <= observation_reg(5 + 12); | |
|
628 | IO6 <= observation_reg(6 + 12); | |
|
629 | IO7 <= observation_reg(7 + 12); | |
|
630 |
IO8 <= observation_reg(8 |
|
|
631 |
IO9 <= observation_reg(9 |
|
|
637 | WHEN "001" => | |
|
638 | -- --IO0 <= observation_reg(0 + 12); | |
|
639 | -- IO1 <= observation_reg(1 + 12); | |
|
640 | -- IO2 <= observation_reg(2 + 12); | |
|
641 | -- IO3 <= observation_reg(3 + 12); | |
|
642 | -- IO4 <= observation_reg(4 + 12); | |
|
643 | -- IO5 <= observation_reg(5 + 12); | |
|
644 | -- IO6 <= observation_reg(6 + 12); | |
|
645 | -- IO7 <= observation_reg(7 + 12); | |
|
646 | IO8 <= observation_reg(8 + 12); | |
|
647 | IO9 <= observation_reg(9 + 12); | |
|
632 | 648 | IO10 <= observation_reg(10 + 12); |
|
633 | 649 | IO11 <= observation_reg(11 + 12); |
|
634 |
WHEN "010" => |
|
|
635 | IO0 <= observation_reg(0 + 12 + 12); | |
|
636 | IO1 <= observation_reg(1 + 12 + 12); | |
|
637 | IO2 <= observation_reg(2 + 12 + 12); | |
|
638 | IO3 <= observation_reg(3 + 12 + 12); | |
|
639 | IO4 <= observation_reg(4 + 12 + 12); | |
|
640 | IO5 <= observation_reg(5 + 12 + 12); | |
|
641 | IO6 <= observation_reg(6 + 12 + 12); | |
|
642 | IO7 <= observation_reg(7 + 12 + 12); | |
|
650 | WHEN "010" => | |
|
651 | -- --IO0 <= observation_reg(0 + 12 + 12); | |
|
652 | -- IO1 <= observation_reg(1 + 12 + 12); | |
|
653 | -- IO2 <= observation_reg(2 + 12 + 12); | |
|
654 | -- IO3 <= observation_reg(3 + 12 + 12); | |
|
655 | -- IO4 <= observation_reg(4 + 12 + 12); | |
|
656 | -- IO5 <= observation_reg(5 + 12 + 12); | |
|
657 | -- IO6 <= observation_reg(6 + 12 + 12); | |
|
658 | -- IO7 <= observation_reg(7 + 12 + 12); | |
|
643 | 659 | IO8 <= '0'; |
|
644 | 660 | IO9 <= '0'; |
|
645 | 661 | IO10 <= '0'; |
|
646 | 662 | IO11 <= '0'; |
|
647 |
WHEN "000" => |
|
|
648 | IO0 <= observation_vector_0(0 ); | |
|
649 | IO1 <= observation_vector_0(1 ); | |
|
650 | IO2 <= observation_vector_0(2 ); | |
|
651 | IO3 <= observation_vector_0(3 ); | |
|
652 | IO4 <= observation_vector_0(4 ); | |
|
653 | IO5 <= observation_vector_0(5 ); | |
|
654 | IO6 <= observation_vector_0(6 ); | |
|
655 | IO7 <= observation_vector_0(7 ); | |
|
656 |
IO8 <= observation_vector_0(8 |
|
|
657 |
IO9 <= observation_vector_0(9 |
|
|
663 | WHEN "000" => | |
|
664 | -- --IO0 <= observation_vector_0(0 ); | |
|
665 | -- IO1 <= observation_vector_0(1 ); | |
|
666 | -- IO2 <= observation_vector_0(2 ); | |
|
667 | -- IO3 <= observation_vector_0(3 ); | |
|
668 | -- IO4 <= observation_vector_0(4 ); | |
|
669 | -- IO5 <= observation_vector_0(5 ); | |
|
670 | -- IO6 <= observation_vector_0(6 ); | |
|
671 | -- IO7 <= observation_vector_0(7 ); | |
|
672 | IO8 <= observation_vector_0(8); | |
|
673 | IO9 <= observation_vector_0(9); | |
|
658 | 674 | IO10 <= observation_vector_0(10); |
|
659 | 675 | IO11 <= observation_vector_0(11); |
|
660 |
WHEN "100" => |
|
|
661 | IO0 <= observation_vector_1(0 ); | |
|
662 | IO1 <= observation_vector_1(1 ); | |
|
663 | IO2 <= observation_vector_1(2 ); | |
|
664 | IO3 <= observation_vector_1(3 ); | |
|
665 | IO4 <= observation_vector_1(4 ); | |
|
666 | IO5 <= observation_vector_1(5 ); | |
|
667 | IO6 <= observation_vector_1(6 ); | |
|
668 | IO7 <= observation_vector_1(7 ); | |
|
669 |
IO8 <= observation_vector_1(8 |
|
|
670 |
IO9 <= observation_vector_1(9 |
|
|
676 | WHEN "100" => | |
|
677 | -- --IO0 <= observation_vector_1(0 ); | |
|
678 | -- IO1 <= observation_vector_1(1 ); | |
|
679 | -- IO2 <= observation_vector_1(2 ); | |
|
680 | -- IO3 <= observation_vector_1(3 ); | |
|
681 | -- IO4 <= observation_vector_1(4 ); | |
|
682 | -- IO5 <= observation_vector_1(5 ); | |
|
683 | -- IO6 <= observation_vector_1(6 ); | |
|
684 | -- IO7 <= observation_vector_1(7 ); | |
|
685 | IO8 <= observation_vector_1(8); | |
|
686 | IO9 <= observation_vector_1(9); | |
|
671 | 687 | IO10 <= observation_vector_1(10); |
|
672 | 688 | IO11 <= observation_vector_1(11); |
|
673 | 689 | WHEN OTHERS => NULL; |
@@ -678,21 +694,21 BEGIN -- beh | |||
|
678 | 694 | ----------------------------------------------------------------------------- |
|
679 | 695 | -- |
|
680 | 696 | ----------------------------------------------------------------------------- |
|
681 | all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
|
682 | apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
|
697 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
|
698 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
|
683 | 699 | apbo_ext(I) <= apb_none; |
|
684 | 700 | END GENERATE apbo_ext_not_used; |
|
685 | 701 | END GENERATE all_apbo_ext; |
|
686 | ||
|
702 | ||
|
687 | 703 | |
|
688 | all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
|
704 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
|
689 | 705 | ahbo_s_ext(I) <= ahbs_none; |
|
690 | 706 | END GENERATE all_ahbo_ext; |
|
691 | ||
|
692 | all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
|
693 | ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE | |
|
707 | ||
|
708 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
|
709 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE | |
|
694 | 710 | ahbo_m_ext(I) <= ahbm_none; |
|
695 | 711 | END GENERATE ahbo_m_ext_not_used; |
|
696 | 712 | END GENERATE all_ahbo_m_ext; |
|
697 | 713 | |
|
698 | END beh; No newline at end of file | |
|
714 | END beh; |
@@ -19,8 +19,6 USE lpp.lpp_sim_pkg.ALL; | |||
|
19 | 19 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
20 | 20 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; |
|
21 | 21 | |
|
22 | LIBRARY postlayout; | |
|
23 | USE postlayout.ALL; | |
|
24 | 22 | |
|
25 | 23 | ENTITY testbench IS |
|
26 | 24 | END; |
@@ -194,18 +192,18 BEGIN | |||
|
194 | 192 | ADC_SDO <= x"AA"; |
|
195 | 193 | |
|
196 | 194 | SRAM_DQ <= (OTHERS => 'Z'); |
|
197 | IO0 <= 'Z'; | |
|
198 | IO1 <= 'Z'; | |
|
199 | IO2 <= 'Z'; | |
|
200 | IO3 <= 'Z'; | |
|
201 | IO4 <= 'Z'; | |
|
202 | IO5 <= 'Z'; | |
|
203 | IO6 <= 'Z'; | |
|
204 | IO7 <= 'Z'; | |
|
205 | IO8 <= 'Z'; | |
|
206 | IO9 <= 'Z'; | |
|
207 | IO10 <= 'Z'; | |
|
208 | IO11 <= 'Z'; | |
|
195 | --IO0 <= 'Z'; | |
|
196 | --IO1 <= 'Z'; | |
|
197 | --IO2 <= 'Z'; | |
|
198 | --IO3 <= 'Z'; | |
|
199 | --IO4 <= 'Z'; | |
|
200 | --IO5 <= 'Z'; | |
|
201 | --IO6 <= 'Z'; | |
|
202 | --IO7 <= 'Z'; | |
|
203 | --IO8 <= 'Z'; | |
|
204 | --IO9 <= 'Z'; | |
|
205 | --IO10 <= 'Z'; | |
|
206 | --IO11 <= 'Z'; | |
|
209 | 207 | |
|
210 | 208 | ----------------------------------------------------------------------------- |
|
211 | 209 | -- DUT |
@@ -58,7 +58,10 ENTITY lpp_lfr IS | |||
|
58 | 58 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | 59 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | 60 | -- |
|
61 | data_shaping_BW : OUT STD_LOGIC | |
|
61 | data_shaping_BW : OUT STD_LOGIC; | |
|
62 | -- | |
|
63 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
64 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
|
62 | 65 |
|
|
63 | 66 | END lpp_lfr; |
|
64 | 67 | |
@@ -223,9 +226,13 ARCHITECTURE beh OF lpp_lfr IS | |||
|
223 | 226 | SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
224 | 227 | SIGNAL dma_grant_error : STD_LOGIC; |
|
225 | 228 | |
|
229 | SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
226 | 230 | ----------------------------------------------------------------------------- |
|
227 | 231 | -- SIGNAL run_dma : STD_LOGIC; |
|
228 | 232 | BEGIN |
|
233 | ||
|
234 | debug_vector <= apb_reg_debug_vector; | |
|
235 | ----------------------------------------------------------------------------- | |
|
229 | 236 | |
|
230 | 237 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
231 | 238 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
@@ -334,7 +341,8 BEGIN | |||
|
334 | 341 | |
|
335 | 342 | wfp_ready_buffer => wfp_ready_buffer,-- TODO |
|
336 | 343 | wfp_buffer_time => wfp_buffer_time,-- TODO |
|
337 | wfp_error_buffer_full => wfp_error_buffer_full -- TODO | |
|
344 | wfp_error_buffer_full => wfp_error_buffer_full, -- TODO | |
|
345 | debug_vector => apb_reg_debug_vector | |
|
338 | 346 | ); |
|
339 | 347 | |
|
340 | 348 | ----------------------------------------------------------------------------- |
@@ -480,7 +488,9 BEGIN | |||
|
480 | 488 | |
|
481 | 489 | matrix_time_f0 => matrix_time_f0, |
|
482 | 490 | matrix_time_f1 => matrix_time_f1, |
|
483 |
matrix_time_f2 => matrix_time_f2 |
|
|
491 | matrix_time_f2 => matrix_time_f2, | |
|
492 | ||
|
493 | debug_vector => debug_vector_ms); | |
|
484 | 494 | |
|
485 | 495 | ----------------------------------------------------------------------------- |
|
486 | 496 | --run_dma <= run_ms OR run; |
@@ -137,7 +137,9 ENTITY lpp_lfr_apbreg IS | |||
|
137 | 137 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
138 | 138 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
139 | 139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) | |
|
140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
141 | --------------------------------------------------------------------------- | |
|
142 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
|
141 | 143 | |
|
142 | 144 | ); |
|
143 | 145 | |
@@ -269,6 +271,15 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
269 | 271 | |
|
270 | 272 | BEGIN -- beh |
|
271 | 273 | |
|
274 | debug_vector(0) <= error_buffer_full; | |
|
275 | debug_vector(1) <= reg_sp.status_error_buffer_full; | |
|
276 | debug_vector(4 DOWNTO 2) <= error_input_fifo_write; | |
|
277 | debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write; | |
|
278 | debug_vector(8) <= ready_matrix_f2; | |
|
279 | debug_vector(9) <= reg0_ready_matrix_f2; | |
|
280 | debug_vector(10) <= reg1_ready_matrix_f2; | |
|
281 | debug_vector(11) <= HRESETn; | |
|
282 | ||
|
272 | 283 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; |
|
273 | 284 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
274 | 285 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
@@ -778,4 +789,4 BEGIN -- beh | |||
|
778 | 789 | |
|
779 | 790 | END beh; |
|
780 | 791 | |
|
781 |
------------------------------------------------------------------------------ |
|
|
792 | ------------------------------------------------------------------------------ |
@@ -76,8 +76,9 ENTITY lpp_lfr_ms IS | |||
|
76 | 76 | |
|
77 | 77 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
78 | 78 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
79 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO | |
|
80 | ||
|
79 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
|
80 | --------------------------------------------------------------------------- | |
|
81 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
|
81 | 82 | ); |
|
82 | 83 | END; |
|
83 | 84 | |
@@ -442,7 +443,7 BEGIN | |||
|
442 | 443 | ReUse => (OTHERS => '0'), |
|
443 | 444 | run => (OTHERS => '1'), |
|
444 | 445 | |
|
445 | wen => sample_f2_wen, | |
|
446 | wen => sample_f2_wen_s, | |
|
446 | 447 | wdata => sample_f2_wdata, |
|
447 | 448 | ren => sample_f2_ren, |
|
448 | 449 | rdata => sample_f2_rdata, |
@@ -687,7 +688,12 BEGIN | |||
|
687 | 688 | fft_data_re => fft_data_re, |
|
688 | 689 | fft_data_valid => fft_data_valid, |
|
689 | 690 | fft_ready => fft_ready); |
|
691 | ||
|
692 | debug_vector(0) <= fft_data_valid; | |
|
693 | debug_vector(1) <= fft_ready; | |
|
694 | debug_vector(11 DOWNTO 2) <= (OTHERS => '0'); | |
|
690 | 695 | |
|
696 | ||
|
691 | 697 |
|
|
692 | 698 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; |
|
693 | 699 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; |
@@ -107,7 +107,8 PACKAGE lpp_lfr_pkg IS | |||
|
107 | 107 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
108 | 108 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
109 | 109 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
110 |
matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
|
110 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
111 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); | |
|
111 | 112 | END COMPONENT; |
|
112 | 113 | |
|
113 | 114 | COMPONENT lpp_lfr_ms_fsmdma |
@@ -213,7 +214,9 PACKAGE lpp_lfr_pkg IS | |||
|
213 | 214 | ahbo : OUT AHB_Mst_Out_Type; |
|
214 | 215 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
215 | 216 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
216 | data_shaping_BW : OUT STD_LOGIC | |
|
217 | data_shaping_BW : OUT STD_LOGIC ; | |
|
218 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
219 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
|
217 | 220 | ); |
|
218 | 221 | END COMPONENT; |
|
219 | 222 | |
@@ -315,7 +318,8 PACKAGE lpp_lfr_pkg IS | |||
|
315 | 318 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
316 | 319 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
317 | 320 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
318 |
wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
|
|
321 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
322 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); | |
|
319 | 323 | END COMPONENT; |
|
320 | 324 | |
|
321 | 325 | COMPONENT lpp_top_ms |
General Comments 0
You need to be logged in to leave comments.
Login now