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MINI_LFR-WFP_MS-0.1.32.pdb :...
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r453:8e0c2cb85822 (MINI-LFR) WFP_MS-0-1-32 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
178
181
179 BEGIN -- beh
182 BEGIN -- beh
180
183
181 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
182 -- CLK
185 -- CLK
183 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
184
187
185 PROCESS(clk_50)
188 PROCESS(clk_50)
186 BEGIN
189 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
190 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
191 clk_50_s <= NOT clk_50_s;
189 END IF;
192 END IF;
190 END PROCESS;
193 END PROCESS;
191
194
192 PROCESS(clk_50_s)
195 PROCESS(clk_50_s)
193 BEGIN
196 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
197 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
198 clk_25 <= NOT clk_25;
196 END IF;
199 END IF;
197 END PROCESS;
200 END PROCESS;
198
201
199 PROCESS(clk_49)
202 PROCESS(clk_49)
200 BEGIN
203 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
204 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
205 clk_24 <= NOT clk_24;
203 END IF;
206 END IF;
204 END PROCESS;
207 END PROCESS;
205
208
206 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
207
210
208 PROCESS (clk_25, reset)
211 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
212 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
213 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
214 LED0 <= '0';
212 LED1 <= '0';
215 LED1 <= '0';
213 LED2 <= '0';
216 LED2 <= '0';
214 --IO1 <= '0';
217 --IO1 <= '0';
215 --IO2 <= '1';
218 --IO2 <= '1';
216 --IO3 <= '0';
219 --IO3 <= '0';
217 --IO4 <= '0';
220 --IO4 <= '0';
218 --IO5 <= '0';
221 --IO5 <= '0';
219 --IO6 <= '0';
222 --IO6 <= '0';
220 --IO7 <= '0';
223 --IO7 <= '0';
221 --IO8 <= '0';
224 --IO8 <= '0';
222 --IO9 <= '0';
225 --IO9 <= '0';
223 --IO10 <= '0';
226 --IO10 <= '0';
224 --IO11 <= '0';
227 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
228 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
229 LED0 <= '0';
227 LED1 <= '1';
230 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
231 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
232 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
233 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
234 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
235 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
236 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
237 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
238 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
239 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
240 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
241 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
242 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
243 END IF;
241 END PROCESS;
244 END PROCESS;
242
245
243 PROCESS (clk_24, reset)
246 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
247 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
248 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
249 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
250 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
251 I00_s <= NOT I00_s ;
249 END IF;
252 END IF;
250 END PROCESS;
253 END PROCESS;
251 -- IO0 <= I00_s;
254 -- IO0 <= I00_s;
252
255
253 --UARTs
256 --UARTs
254 nCTS1 <= '1';
257 nCTS1 <= '1';
255 nCTS2 <= '1';
258 nCTS2 <= '1';
256 nDCD2 <= '1';
259 nDCD2 <= '1';
257
260
258 --EXT CONNECTOR
261 --EXT CONNECTOR
259
262
260 --SPACE WIRE
263 --SPACE WIRE
261
264
262 leon3_soc_1 : leon3_soc
265 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
266 GENERIC MAP (
264 fabtech => apa3e,
267 fabtech => apa3e,
265 memtech => apa3e,
268 memtech => apa3e,
266 padtech => inferred,
269 padtech => inferred,
267 clktech => inferred,
270 clktech => inferred,
268 disas => 0,
271 disas => 0,
269 dbguart => 0,
272 dbguart => 0,
270 pclow => 2,
273 pclow => 2,
271 clk_freq => 25000,
274 clk_freq => 25000,
272 NB_CPU => 1,
275 NB_CPU => 1,
273 ENABLE_FPU => 1,
276 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
277 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
278 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
279 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
280 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
281 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
282 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
283 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
284 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
285 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
286 PORT MAP (
284 clk => clk_25,
287 clk => clk_25,
285 reset => reset,
288 reset => reset,
286 errorn => errorn,
289 errorn => errorn,
287 ahbrxd => TXD1,
290 ahbrxd => TXD1,
288 ahbtxd => RXD1,
291 ahbtxd => RXD1,
289 urxd1 => TXD2,
292 urxd1 => TXD2,
290 utxd1 => RXD2,
293 utxd1 => RXD2,
291 address => SRAM_A,
294 address => SRAM_A,
292 data => SRAM_DQ,
295 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
296 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
297 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
298 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
299 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
300 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
301 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
302 nSRAM_OE => SRAM_nOE,
300
303
301 apbi_ext => apbi_ext,
304 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
305 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
306 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
307 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
308 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
309 ahbo_m_ext => ahbo_m_ext);
307
310
308 -------------------------------------------------------------------------------
311 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
312 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
313 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
314 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
315 GENERIC MAP (
313 pindex => 6,
316 pindex => 6,
314 paddr => 6,
317 paddr => 6,
315 pmask => 16#fff#,
318 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
319 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
320 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
321 PORT MAP (
319 clk25MHz => clk_25,
322 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
323 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
324 resetn => reset,
322 grspw_tick => swno.tickout,
325 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
326 apbi => apbi_ext,
324 apbo => apbo_ext(6),
327 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
328 coarse_time => coarse_time,
326 fine_time => fine_time);
329 fine_time => fine_time,
330 LFR_soft_rstn => LFR_soft_rstn
331 );
327
332
328 -----------------------------------------------------------------------
333 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
334 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
335 -----------------------------------------------------------------------
331
336
332 SPW_EN <= '1';
337 SPW_EN <= '1';
333
338
334 spw_clk <= clk_50_s;
339 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
340 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
341 spw_rxclkn <= NOT spw_rxtxclk;
337
342
338 -- PADS for SPW1
343 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
344 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
345 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
346 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
347 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
348 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
349 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
350 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
351 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
352 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
353 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
354 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
355 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
356 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
357 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
358 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
359 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
360 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
361
357 -- GRSPW PHY
362 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
363 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
364 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
365 spw_phy0 : grspw_phy
361 GENERIC MAP(
366 GENERIC MAP(
362 tech => apa3e,
367 tech => apa3e,
363 rxclkbuftype => 1,
368 rxclkbuftype => 1,
364 scantest => 0)
369 scantest => 0)
365 PORT MAP(
370 PORT MAP(
366 rxrst => swno.rxrst,
371 rxrst => swno.rxrst,
367 di => dtmp(j),
372 di => dtmp(j),
368 si => stmp(j),
373 si => stmp(j),
369 rxclko => spw_rxclk(j),
374 rxclko => spw_rxclk(j),
370 do => swni.d(j),
375 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
376 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
377 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
378 END GENERATE spw_inputloop;
374
379
375 -- SPW core
380 -- SPW core
376 sw0 : grspwm GENERIC MAP(
381 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
382 tech => apa3e,
378 hindex => 1,
383 hindex => 1,
379 pindex => 5,
384 pindex => 5,
380 paddr => 5,
385 paddr => 5,
381 pirq => 11,
386 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
387 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
388 rmap => 1,
384 rmapcrc => 1,
389 rmapcrc => 1,
385 fifosize1 => 16,
390 fifosize1 => 16,
386 fifosize2 => 16,
391 fifosize2 => 16,
387 rxclkbuftype => 1,
392 rxclkbuftype => 1,
388 rxunaligned => 0,
393 rxunaligned => 0,
389 rmapbufs => 4,
394 rmapbufs => 4,
390 ft => 0,
395 ft => 0,
391 netlist => 0,
396 netlist => 0,
392 ports => 2,
397 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
398 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
399 memtech => apa3e,
395 destkey => 2,
400 destkey => 2,
396 spwcore => 1
401 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
402 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
403 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
404 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
405 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
406 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
407 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
408 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
409 swni, swno);
405
410
406 swni.tickin <= '0';
411 swni.tickin <= '0';
407 swni.rmapen <= '1';
412 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
413 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
414 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
415 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
416 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
417 swni.timerrstval <= (OTHERS => '0');
413
418
414 -------------------------------------------------------------------------------
419 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
420 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
421 -------------------------------------------------------------------------------
422
423
424 LFR_rstn <= LFR_soft_rstn AND reset;
425
417 lpp_lfr_1 : lpp_lfr
426 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
427 GENERIC MAP (
419 Mem_use => use_RAM,
428 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
429 nb_data_by_buffer_size => 32,
421 -- nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
430 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
431 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
432 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
433 pindex => 15,
426 paddr => 15,
434 paddr => 15,
427 pmask => 16#fff#,
435 pmask => 16#fff#,
428 pirq_ms => 6,
436 pirq_ms => 6,
429 pirq_wfp => 14,
437 pirq_wfp => 14,
430 hindex => 2,
438 hindex => 2,
431 top_lfr_version => X"00011F") -- aa.bb.cc version
439 top_lfr_version => X"000120") -- aa.bb.cc version
432 PORT MAP (
440 PORT MAP (
433 clk => clk_25,
441 clk => clk_25,
434 rstn => reset,
442 rstn => LFR_rstn,
435 sample_B => sample_s(2 DOWNTO 0),
443 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
444 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
445 sample_val => sample_val,
438 apbi => apbi_ext,
446 apbi => apbi_ext,
439 apbo => apbo_ext(15),
447 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
448 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
449 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
450 coarse_time => coarse_time,
443 fine_time => fine_time,
451 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig);
452 data_shaping_BW => bias_fail_sw_sig);
445
453
446 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
454 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
447 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
455 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
448 END GENERATE all_sample;
456 END GENERATE all_sample;
449
457
450
458
451
459
452 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
460 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
453 GENERIC MAP(
461 GENERIC MAP(
454 ChannelCount => 8,
462 ChannelCount => 8,
455 SampleNbBits => 14,
463 SampleNbBits => 14,
456 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
464 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
457 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
465 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
458 PORT MAP (
466 PORT MAP (
459 -- CONV
467 -- CONV
460 cnv_clk => clk_24,
468 cnv_clk => clk_24,
461 cnv_rstn => reset,
469 cnv_rstn => reset,
462 cnv => ADC_nCS_sig,
470 cnv => ADC_nCS_sig,
463 -- DATA
471 -- DATA
464 clk => clk_25,
472 clk => clk_25,
465 rstn => reset,
473 rstn => reset,
466 sck => ADC_CLK_sig,
474 sck => ADC_CLK_sig,
467 sdo => ADC_SDO_sig,
475 sdo => ADC_SDO_sig,
468 -- SAMPLE
476 -- SAMPLE
469 sample => sample,
477 sample => sample,
470 sample_val => sample_val);
478 sample_val => sample_val);
471
479
472 --IO10 <= ADC_SDO_sig(5);
480 --IO10 <= ADC_SDO_sig(5);
473 --IO9 <= ADC_SDO_sig(4);
481 --IO9 <= ADC_SDO_sig(4);
474 --IO8 <= ADC_SDO_sig(3);
482 --IO8 <= ADC_SDO_sig(3);
475
483
476 ADC_nCS <= ADC_nCS_sig;
484 ADC_nCS <= ADC_nCS_sig;
477 ADC_CLK <= ADC_CLK_sig;
485 ADC_CLK <= ADC_CLK_sig;
478 ADC_SDO_sig <= ADC_SDO;
486 ADC_SDO_sig <= ADC_SDO;
479
487
480 ----------------------------------------------------------------------
488 ----------------------------------------------------------------------
481 --- GPIO -----------------------------------------------------------
489 --- GPIO -----------------------------------------------------------
482 ----------------------------------------------------------------------
490 ----------------------------------------------------------------------
483
491
484 grgpio0 : grgpio
492 grgpio0 : grgpio
485 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
493 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
486 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
494 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
487
495
488 --pio_pad_0 : iopad
496 --pio_pad_0 : iopad
489 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
498 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
491 --pio_pad_1 : iopad
499 --pio_pad_1 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
501 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
494 --pio_pad_2 : iopad
502 --pio_pad_2 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
504 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
497 --pio_pad_3 : iopad
505 --pio_pad_3 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
506 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
507 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
500 --pio_pad_4 : iopad
508 --pio_pad_4 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
509 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
510 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
503 --pio_pad_5 : iopad
511 --pio_pad_5 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
512 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
513 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
506 --pio_pad_6 : iopad
514 --pio_pad_6 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
515 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
516 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
509 --pio_pad_7 : iopad
517 --pio_pad_7 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
518 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
519 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
512
520
513 PROCESS (clk_25, reset)
521 PROCESS (clk_25, reset)
514 BEGIN -- PROCESS
522 BEGIN -- PROCESS
515 IF reset = '0' THEN -- asynchronous reset (active low)
523 IF reset = '0' THEN -- asynchronous reset (active low)
516 IO0 <= '0';
524 IO0 <= '0';
517 IO1 <= '0';
525 IO1 <= '0';
518 IO2 <= '0';
526 IO2 <= '0';
519 IO3 <= '0';
527 IO3 <= '0';
520 IO4 <= '0';
528 IO4 <= '0';
521 IO5 <= '0';
529 IO5 <= '0';
522 IO6 <= '0';
530 IO6 <= '0';
523 IO7 <= '0';
531 IO7 <= '0';
524 IO8 <= '0';
532 IO8 <= '0';
525 IO9 <= '0';
533 IO9 <= '0';
526 IO10 <= '0';
534 IO10 <= '0';
527 IO11 <= '0';
535 IO11 <= '0';
528 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
536 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
529 CASE gpioo.dout(2 DOWNTO 0) IS
537 CASE gpioo.dout(2 DOWNTO 0) IS
530 WHEN "011" =>
538 WHEN "011" =>
531 IO0 <= observation_reg(0 );
539 IO0 <= observation_reg(0 );
532 IO1 <= observation_reg(1 );
540 IO1 <= observation_reg(1 );
533 IO2 <= observation_reg(2 );
541 IO2 <= observation_reg(2 );
534 IO3 <= observation_reg(3 );
542 IO3 <= observation_reg(3 );
535 IO4 <= observation_reg(4 );
543 IO4 <= observation_reg(4 );
536 IO5 <= observation_reg(5 );
544 IO5 <= observation_reg(5 );
537 IO6 <= observation_reg(6 );
545 IO6 <= observation_reg(6 );
538 IO7 <= observation_reg(7 );
546 IO7 <= observation_reg(7 );
539 IO8 <= observation_reg(8 );
547 IO8 <= observation_reg(8 );
540 IO9 <= observation_reg(9 );
548 IO9 <= observation_reg(9 );
541 IO10 <= observation_reg(10);
549 IO10 <= observation_reg(10);
542 IO11 <= observation_reg(11);
550 IO11 <= observation_reg(11);
543 WHEN "001" =>
551 WHEN "001" =>
544 IO0 <= observation_reg(0 + 12);
552 IO0 <= observation_reg(0 + 12);
545 IO1 <= observation_reg(1 + 12);
553 IO1 <= observation_reg(1 + 12);
546 IO2 <= observation_reg(2 + 12);
554 IO2 <= observation_reg(2 + 12);
547 IO3 <= observation_reg(3 + 12);
555 IO3 <= observation_reg(3 + 12);
548 IO4 <= observation_reg(4 + 12);
556 IO4 <= observation_reg(4 + 12);
549 IO5 <= observation_reg(5 + 12);
557 IO5 <= observation_reg(5 + 12);
550 IO6 <= observation_reg(6 + 12);
558 IO6 <= observation_reg(6 + 12);
551 IO7 <= observation_reg(7 + 12);
559 IO7 <= observation_reg(7 + 12);
552 IO8 <= observation_reg(8 + 12);
560 IO8 <= observation_reg(8 + 12);
553 IO9 <= observation_reg(9 + 12);
561 IO9 <= observation_reg(9 + 12);
554 IO10 <= observation_reg(10 + 12);
562 IO10 <= observation_reg(10 + 12);
555 IO11 <= observation_reg(11 + 12);
563 IO11 <= observation_reg(11 + 12);
556 WHEN "010" =>
564 WHEN "010" =>
557 IO0 <= observation_reg(0 + 12 + 12);
565 IO0 <= observation_reg(0 + 12 + 12);
558 IO1 <= observation_reg(1 + 12 + 12);
566 IO1 <= observation_reg(1 + 12 + 12);
559 IO2 <= observation_reg(2 + 12 + 12);
567 IO2 <= observation_reg(2 + 12 + 12);
560 IO3 <= observation_reg(3 + 12 + 12);
568 IO3 <= observation_reg(3 + 12 + 12);
561 IO4 <= observation_reg(4 + 12 + 12);
569 IO4 <= observation_reg(4 + 12 + 12);
562 IO5 <= observation_reg(5 + 12 + 12);
570 IO5 <= observation_reg(5 + 12 + 12);
563 IO6 <= observation_reg(6 + 12 + 12);
571 IO6 <= observation_reg(6 + 12 + 12);
564 IO7 <= observation_reg(7 + 12 + 12);
572 IO7 <= observation_reg(7 + 12 + 12);
565 IO8 <= '0';
573 IO8 <= '0';
566 IO9 <= '0';
574 IO9 <= '0';
567 IO10 <= '0';
575 IO10 <= '0';
568 IO11 <= '0';
576 IO11 <= '0';
569 WHEN "000" =>
577 WHEN "000" =>
570 IO0 <= observation_vector_0(0 );
578 IO0 <= observation_vector_0(0 );
571 IO1 <= observation_vector_0(1 );
579 IO1 <= observation_vector_0(1 );
572 IO2 <= observation_vector_0(2 );
580 IO2 <= observation_vector_0(2 );
573 IO3 <= observation_vector_0(3 );
581 IO3 <= observation_vector_0(3 );
574 IO4 <= observation_vector_0(4 );
582 IO4 <= observation_vector_0(4 );
575 IO5 <= observation_vector_0(5 );
583 IO5 <= observation_vector_0(5 );
576 IO6 <= observation_vector_0(6 );
584 IO6 <= observation_vector_0(6 );
577 IO7 <= observation_vector_0(7 );
585 IO7 <= observation_vector_0(7 );
578 IO8 <= observation_vector_0(8 );
586 IO8 <= observation_vector_0(8 );
579 IO9 <= observation_vector_0(9 );
587 IO9 <= observation_vector_0(9 );
580 IO10 <= observation_vector_0(10);
588 IO10 <= observation_vector_0(10);
581 IO11 <= observation_vector_0(11);
589 IO11 <= observation_vector_0(11);
582 WHEN "100" =>
590 WHEN "100" =>
583 IO0 <= observation_vector_1(0 );
591 IO0 <= observation_vector_1(0 );
584 IO1 <= observation_vector_1(1 );
592 IO1 <= observation_vector_1(1 );
585 IO2 <= observation_vector_1(2 );
593 IO2 <= observation_vector_1(2 );
586 IO3 <= observation_vector_1(3 );
594 IO3 <= observation_vector_1(3 );
587 IO4 <= observation_vector_1(4 );
595 IO4 <= observation_vector_1(4 );
588 IO5 <= observation_vector_1(5 );
596 IO5 <= observation_vector_1(5 );
589 IO6 <= observation_vector_1(6 );
597 IO6 <= observation_vector_1(6 );
590 IO7 <= observation_vector_1(7 );
598 IO7 <= observation_vector_1(7 );
591 IO8 <= observation_vector_1(8 );
599 IO8 <= observation_vector_1(8 );
592 IO9 <= observation_vector_1(9 );
600 IO9 <= observation_vector_1(9 );
593 IO10 <= observation_vector_1(10);
601 IO10 <= observation_vector_1(10);
594 IO11 <= observation_vector_1(11);
602 IO11 <= observation_vector_1(11);
595 WHEN OTHERS => NULL;
603 WHEN OTHERS => NULL;
596 END CASE;
604 END CASE;
597
605
598 END IF;
606 END IF;
599 END PROCESS;
607 END PROCESS;
600
608
601 END beh;
609 END beh;
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@@ -1,281 +1,281
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27
27
28
28
29 LIBRARY lpp;
29 LIBRARY lpp;
30 USE lpp.cic_pkg.ALL;
30 USE lpp.cic_pkg.ALL;
31 USE lpp.data_type_pkg.ALL;
31 USE lpp.data_type_pkg.ALL;
32
32
33 ENTITY cic_lfr_control IS
33 ENTITY cic_lfr_control IS
34 PORT (
34 PORT (
35 clk : IN STD_LOGIC;
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38 --
38 --
39 data_in_valid : IN STD_LOGIC;
39 data_in_valid : IN STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
40 data_out_16_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
41 data_out_256_valid : OUT STD_LOGIC;
42 -- dataflow
42 -- dataflow
43 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 sel_sample : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
44 --
44 --
45 op_valid : OUT STD_LOGIC;
45 op_valid : OUT STD_LOGIC;
46 op_ADD_SUBn : OUT STD_LOGIC;
46 op_ADD_SUBn : OUT STD_LOGIC;
47 --
47 --
48 r_addr_init : OUT STD_LOGIC;
48 r_addr_init : OUT STD_LOGIC;
49 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
49 r_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
50 r_addr_add1 : OUT STD_LOGIC;
50 r_addr_add1 : OUT STD_LOGIC;
51 --
51 --
52 w_en : OUT STD_LOGIC;
52 w_en : OUT STD_LOGIC;
53 w_addr_init : OUT STD_LOGIC;
53 w_addr_init : OUT STD_LOGIC;
54 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
54 w_addr_base : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
55 w_addr_add1 : OUT STD_LOGIC
55 w_addr_add1 : OUT STD_LOGIC
56 );
56 );
57
57
58 END cic_lfr_control;
58 END cic_lfr_control;
59
59
60 ARCHITECTURE beh OF cic_lfr_control IS
60 ARCHITECTURE beh OF cic_lfr_control IS
61
61
62 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
62 TYPE STATE_CIC_LFR_TYPE IS (IDLE,
63
63
64 INT_0_d0, INT_1_d0, INT_2_d0,
64 INT_0_d0, INT_1_d0, INT_2_d0,
65 INT_0_d1, INT_1_d1, INT_2_d1,
65 INT_0_d1, INT_1_d1, INT_2_d1,
66 INT_0_d2, INT_1_d2, INT_2_d2,
66 INT_0_d2, INT_1_d2, INT_2_d2,
67
67
68 WAIT_INT_to_COMB_16,
68 WAIT_INT_to_COMB_16,
69
69
70 COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
70 COMB_0_16_d0, COMB_1_16_d0, COMB_2_16_d0,
71 COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
71 COMB_0_16_d1, COMB_1_16_d1, COMB_2_16_d1,
72
72
73 COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
73 COMB_0_256_d0, COMB_1_256_d0, COMB_2_256_d0,
74 COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
74 COMB_0_256_d1, COMB_1_256_d1, COMB_2_256_d1,
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
75 COMB_0_256_d2, COMB_1_256_d2, COMB_2_256_d2,
76
76
77 READ_INT_2_d0,
77 READ_INT_2_d0,
78 READ_INT_2_d1,
78 READ_INT_2_d1,
79
79
80 Wait_step,
80 Wait_step,
81
82 INT_0, INT_1, INT_2
81 INT_0, INT_1, INT_2
83 );
82 );
83
84 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
84 SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
85 SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
85 SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE;
86
86
87 SIGNAL nb_data_receipt : INTEGER;
87 SIGNAL nb_data_receipt : INTEGER;
88 SIGNAL current_channel : INTEGER;
88 SIGNAL current_channel : INTEGER;
89
89
90 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
90 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
91
91
92 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
92 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
93 CONSTANT base_addr_delta : INTEGER := 40;
93 CONSTANT base_addr_delta : INTEGER := 40;
94
94
95 CONSTANT SEL_OUT : INTEGER := 6;
95 CONSTANT SEL_OUT : INTEGER := 6;
96
96
97 signal nb_cycle_wait : integer;
97 signal nb_cycle_wait : integer;
98 BEGIN
98 BEGIN
99
99
100 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
100 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
101 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
101 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
102 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
102 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
103 END GENERATE all_bit;
103 END GENERATE all_bit;
104 END GENERATE all_channel;
104 END GENERATE all_channel;
105
105
106 PROCESS (clk, rstn)
106 PROCESS (clk, rstn)
107 BEGIN -- PROCESS
107 BEGIN -- PROCESS
108 IF rstn = '0' THEN -- asynchronous reset (active low)
108 IF rstn = '0' THEN -- asynchronous reset (active low)
109 STATE_CIC_LFR <= IDLE;
109 STATE_CIC_LFR <= IDLE;
110 --
110 --
111 data_out_16_valid <= '0';
111 data_out_16_valid <= '0';
112 data_out_256_valid <= '0';
112 data_out_256_valid <= '0';
113 --
113 --
114 sel_sample <= (OTHERS => '0');
114 sel_sample <= (OTHERS => '0');
115 --
115 --
116 op_valid <= '0';
116 op_valid <= '0';
117 op_ADD_SUBn <= '0';
117 op_ADD_SUBn <= '0';
118 --
118 --
119 r_addr_init <= '0';
119 r_addr_init <= '0';
120 r_addr_base <= (OTHERS => '0');
120 r_addr_base <= (OTHERS => '0');
121 r_addr_add1 <= '0';
121 r_addr_add1 <= '0';
122 --
122 --
123 w_en <= '1';
123 w_en <= '1';
124 w_addr_init <= '0';
124 w_addr_init <= '0';
125 w_addr_base <= (OTHERS => '0');
125 w_addr_base <= (OTHERS => '0');
126 w_addr_add1 <= '0';
126 w_addr_add1 <= '0';
127 --
127 --
128 nb_data_receipt <= 0;
128 nb_data_receipt <= 0;
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 data_out_16_valid <= '0';
130 data_out_16_valid <= '0';
131 data_out_256_valid <= '0';
131 data_out_256_valid <= '0';
132 op_valid <= '0';
132 op_valid <= '0';
133 op_ADD_SUBn <= '0';
133 op_ADD_SUBn <= '0';
134 r_addr_init <= '0';
134 r_addr_init <= '0';
135 r_addr_base <= (OTHERS => '0');
135 r_addr_base <= (OTHERS => '0');
136 r_addr_add1 <= '0';
136 r_addr_add1 <= '0';
137 w_en <= '1';
137 w_en <= '1';
138 w_addr_init <= '0';
138 w_addr_init <= '0';
139 w_addr_base <= (OTHERS => '0');
139 w_addr_base <= (OTHERS => '0');
140 w_addr_add1 <= '0';
140 w_addr_add1 <= '0';
141
141
142 IF run = '0' THEN
142 IF run = '0' THEN
143 STATE_CIC_LFR <= IDLE;
143 STATE_CIC_LFR <= IDLE;
144 --
144 --
145 data_out_16_valid <= '0';
145 data_out_16_valid <= '0';
146 data_out_256_valid <= '0';
146 data_out_256_valid <= '0';
147 --
147 --
148 sel_sample <= (OTHERS => '0');
148 sel_sample <= (OTHERS => '0');
149 --
149 --
150 op_valid <= '0';
150 op_valid <= '0';
151 op_ADD_SUBn <= '0';
151 op_ADD_SUBn <= '0';
152 --
152 --
153 r_addr_init <= '0';
153 r_addr_init <= '0';
154 r_addr_base <= (OTHERS => '0');
154 r_addr_base <= (OTHERS => '0');
155 r_addr_add1 <= '0';
155 r_addr_add1 <= '0';
156 --
156 --
157 w_en <= '1';
157 w_en <= '1';
158 w_addr_init <= '0';
158 w_addr_init <= '0';
159 w_addr_base <= (OTHERS => '0');
159 w_addr_base <= (OTHERS => '0');
160 w_addr_add1 <= '0';
160 w_addr_add1 <= '0';
161 --
161 --
162 nb_data_receipt <= 0;
162 nb_data_receipt <= 0;
163 current_channel <= 0;
163 current_channel <= 0;
164 ELSE
164 ELSE
165 CASE STATE_CIC_LFR IS
165 CASE STATE_CIC_LFR IS
166 WHEN IDLE =>
166 WHEN IDLE =>
167 data_out_16_valid <= '0';
167 data_out_16_valid <= '0';
168 data_out_256_valid <= '0';
168 data_out_256_valid <= '0';
169 --
169 --
170 sel_sample <= (OTHERS => '0');
170 sel_sample <= (OTHERS => '0');
171 --
171 --
172 op_valid <= '0';
172 op_valid <= '0';
173 op_ADD_SUBn <= '0';
173 op_ADD_SUBn <= '0';
174 --
174 --
175 r_addr_init <= '0';
175 r_addr_init <= '0';
176 r_addr_base <= (OTHERS => '0');
176 r_addr_base <= (OTHERS => '0');
177 r_addr_add1 <= '0';
177 r_addr_add1 <= '0';
178 --
178 --
179 w_en <= '1';
179 w_en <= '1';
180 w_addr_init <= '0';
180 w_addr_init <= '0';
181 w_addr_base <= (OTHERS => '0');
181 w_addr_base <= (OTHERS => '0');
182 w_addr_add1 <= '0';
182 w_addr_add1 <= '0';
183 --
183 --
184 IF data_in_valid = '1' THEN
184 IF data_in_valid = '1' THEN
185 nb_data_receipt <= nb_data_receipt+1;
185 nb_data_receipt <= nb_data_receipt+1;
186 current_channel <= 0;
186 current_channel <= 0;
187 STATE_CIC_LFR <= INT_0_d0;
187 STATE_CIC_LFR <= INT_0_d0;
188 END IF;
188 END IF;
189
189
190
190
191 WHEN WAIT_step => ---------------------------------------------------
191 WHEN WAIT_step => ---------------------------------------------------
192 IF nb_cycle_wait > 0 THEN
192 IF nb_cycle_wait > 0 THEN
193 nb_cycle_wait <= nb_cycle_wait -1;
193 nb_cycle_wait <= nb_cycle_wait -1;
194 ELSE
194 ELSE
195 STATE_CIC_LFR <= STATE_CIC_LFR_pre;
195 STATE_CIC_LFR <= STATE_CIC_LFR_pre;
196 END IF;
196 END IF;
197
197
198
198
199 WHEN INT_0 => -------------------------------------------------------
199 WHEN INT_0 => -------------------------------------------------------
200 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
200 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
201 r_addr_init <= '1';
201 r_addr_init <= '1';
202 r_addr_base <= base_addr_INT(current_channel);
202 r_addr_base <= base_addr_INT(current_channel);
203 nb_cycle_wait <= 1;
203 nb_cycle_wait <= 1;
204 op_ADD_SUBn <= '1';
204 op_ADD_SUBn <= '1';
205 op_valid <= '1';
205 op_valid <= '1';
206 STATE_CIC_LFR <= WAIT_step;
206 STATE_CIC_LFR <= WAIT_step;
207 STATE_CIC_LFR_pre <= INT_1;
207 STATE_CIC_LFR_pre <= INT_1;
208
208
209 WHEN INT_1 =>
209 WHEN INT_1 =>
210 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
210 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
211 r_addr_add1 <= '1';
211 r_addr_add1 <= '1';
212 nb_cycle_wait <= 3;
212 nb_cycle_wait <= 3;
213 op_ADD_SUBn <= '1';
213 op_ADD_SUBn <= '1';
214 op_valid <= '1';
214 op_valid <= '1';
215 STATE_CIC_LFR <= INT_2;
215 STATE_CIC_LFR <= INT_2;
216
216
217 WHEN INT_2 =>
217 WHEN INT_2 =>
218 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
218 sel_sample <= STD_LOGIC_VECTOR(to_unsigned(SEL_OUT, 3));
219 r_addr_add1 <= '1';
219 r_addr_add1 <= '1';
220 nb_cycle_wait <= 3;
220 nb_cycle_wait <= 3;
221 op_ADD_SUBn <= '1';
221 op_ADD_SUBn <= '1';
222 op_valid <= '1';
222 op_valid <= '1';
223 IF nb_data_receipt = 256 THEN
223 IF nb_data_receipt = 256 THEN
224 STATE_CIC_LFR <= COMB_0_256_d0;
224 STATE_CIC_LFR <= COMB_0_256_d0;
225 ELSIF (nb_data_receipt mod 16) = 0 THEN
225 ELSIF (nb_data_receipt mod 16) = 0 THEN
226 STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
226 STATE_CIC_LFR <= WAIT_INT_to_COMB_16;
227 ELSE
227 ELSE
228 IF current_channel = 5 THEN
228 IF current_channel = 5 THEN
229 STATE_CIC_LFR <= IDLE;
229 STATE_CIC_LFR <= IDLE;
230 ELSE
230 ELSE
231 current_channel <= current_channel +1;
231 current_channel <= current_channel +1;
232 STATE_CIC_LFR <= INT_0;
232 STATE_CIC_LFR <= INT_0;
233 END IF;
233 END IF;
234 END IF;
234 END IF;
235
235
236 -------------------------------------------------------------------
236 -------------------------------------------------------------------
237 WHEN WAIT_INT_to_COMB_16 =>
237 WHEN WAIT_INT_to_COMB_16 =>
238 STATE_CIC_LFR <= COMB_0_16_d0;
238 STATE_CIC_LFR <= COMB_0_16_d0;
239
239
240 WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
240 WHEN COMB_0_16_d0 => STATE_CIC_LFR <= COMB_0_16_d1;
241 WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
241 WHEN COMB_0_16_d1 => STATE_CIC_LFR <= COMB_1_16_d0;
242
242
243 WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
243 WHEN COMB_1_16_d0 => STATE_CIC_LFR <= COMB_1_16_d1;
244 WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
244 WHEN COMB_1_16_d1 => STATE_CIC_LFR <= COMB_2_16_d0;
245
245
246 WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
246 WHEN COMB_2_16_d0 => STATE_CIC_LFR <= COMB_2_16_d1;
247 WHEN COMB_2_16_d1 =>
247 WHEN COMB_2_16_d1 =>
248 IF current_channel = 5 THEN
248 IF current_channel = 5 THEN
249 STATE_CIC_LFR <= IDLE;
249 STATE_CIC_LFR <= IDLE;
250 IF nb_data_receipt = 256 THEN
250 IF nb_data_receipt = 256 THEN
251 nb_data_receipt <= 0;
251 nb_data_receipt <= 0;
252 END IF;
252 END IF;
253 ELSE
253 ELSE
254 current_channel <= current_channel +1;
254 current_channel <= current_channel +1;
255 STATE_CIC_LFR <= INT_0_d0;
255 STATE_CIC_LFR <= INT_0_d0;
256 END IF;
256 END IF;
257
257
258 -------------------------------------------------------------------
258 -------------------------------------------------------------------
259 WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
259 WHEN COMB_0_256_d0 => STATE_CIC_LFR <= COMB_0_256_d1;
260 WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
260 WHEN COMB_0_256_d1 => STATE_CIC_LFR <= COMB_0_256_d2;
261 WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
261 WHEN COMB_0_256_d2 => STATE_CIC_LFR <= COMB_1_256_d0;
262
262
263 WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
263 WHEN COMB_1_256_d0 => STATE_CIC_LFR <= COMB_1_256_d1;
264 WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
264 WHEN COMB_1_256_d1 => STATE_CIC_LFR <= COMB_1_256_d2;
265 WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
265 WHEN COMB_1_256_d2 => STATE_CIC_LFR <= COMB_2_256_d0;
266
266
267 WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
267 WHEN COMB_2_256_d0 => STATE_CIC_LFR <= COMB_2_256_d1;
268 WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
268 WHEN COMB_2_256_d1 => STATE_CIC_LFR <= COMB_2_256_d2;
269 WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
269 WHEN COMB_2_256_d2 => STATE_CIC_LFR <= READ_INT_2_d0;
270
270
271 -------------------------------------------------------------------
271 -------------------------------------------------------------------
272 WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
272 WHEN READ_INT_2_d0 => STATE_CIC_LFR <= READ_INT_2_d1;
273 WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
273 WHEN READ_INT_2_d1 => STATE_CIC_LFR <= COMB_0_16_d0;
274
274
275 WHEN OTHERS => NULL;
275 WHEN OTHERS => NULL;
276 END CASE;
276 END CASE;
277 END IF;
277 END IF;
278 END IF;
278 END IF;
279 END PROCESS;
279 END PROCESS;
280
280
281 END beh;
281 END beh;
Show file before | Show file after | Hide comments
@@ -1,317 +1,326
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
31
31
32 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
33
33
34 GENERIC(
34 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 FIRST_DIVISION : INTEGER := 374;
38 FIRST_DIVISION : INTEGER := 374;
39 NB_SECOND_DESYNC : INTEGER := 60
39 NB_SECOND_DESYNC : INTEGER := 60
40 );
40 );
41
41
42 PORT (
42 PORT (
43 clk25MHz : IN STD_LOGIC; --! Clock
43 clk25MHz : IN STD_LOGIC; --! Clock
44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
45 resetn : IN STD_LOGIC; --! Reset
45 resetn : IN STD_LOGIC; --! Reset
46
46
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48
48
49 apbi : IN apb_slv_in_type; --! APB slave input signals
49 apbi : IN apb_slv_in_type; --! APB slave input signals
50 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 apbo : OUT apb_slv_out_type; --! APB slave output signals
51
51
52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
54 ---------------------------------------------------------------------------
55 LFR_soft_rstn : OUT STD_LOGIC
54 );
56 );
55
57
56 END apb_lfr_time_management;
58 END apb_lfr_time_management;
57
59
58 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
60 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
59
61
60 CONSTANT REVISION : INTEGER := 1;
62 CONSTANT REVISION : INTEGER := 1;
61 CONSTANT pconfig : apb_config_type := (
63 CONSTANT pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
64 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask)
65 1 => apb_iobar(paddr, pmask)
64 );
66 );
65
67
66 TYPE apb_lfr_time_management_Reg IS RECORD
68 TYPE apb_lfr_time_management_Reg IS RECORD
67 ctrl : STD_LOGIC;
69 ctrl : STD_LOGIC;
68 soft_reset : STD_LOGIC;
70 soft_reset : STD_LOGIC;
69 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
71 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
70 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
74 LFR_soft_reset : STD_LOGIC;
72 END RECORD;
75 END RECORD;
73 SIGNAL r : apb_lfr_time_management_Reg;
76 SIGNAL r : apb_lfr_time_management_Reg;
74
77
75 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
76 SIGNAL force_tick : STD_LOGIC;
79 SIGNAL force_tick : STD_LOGIC;
77 SIGNAL previous_force_tick : STD_LOGIC;
80 SIGNAL previous_force_tick : STD_LOGIC;
78 SIGNAL soft_tick : STD_LOGIC;
81 SIGNAL soft_tick : STD_LOGIC;
79
82
80 SIGNAL coarsetime_reg_updated : STD_LOGIC;
83 SIGNAL coarsetime_reg_updated : STD_LOGIC;
81 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
84 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
82
85
83 --SIGNAL coarse_time_new : STD_LOGIC;
86 --SIGNAL coarse_time_new : STD_LOGIC;
84 SIGNAL coarse_time_new_49 : STD_LOGIC;
87 SIGNAL coarse_time_new_49 : STD_LOGIC;
85 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
90
88 --SIGNAL fine_time_new : STD_LOGIC;
91 --SIGNAL fine_time_new : STD_LOGIC;
89 --SIGNAL fine_time_new_temp : STD_LOGIC;
92 --SIGNAL fine_time_new_temp : STD_LOGIC;
90 SIGNAL fine_time_new_49 : STD_LOGIC;
93 SIGNAL fine_time_new_49 : STD_LOGIC;
91 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
94 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
95 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 SIGNAL tick : STD_LOGIC;
96 SIGNAL tick : STD_LOGIC;
94 SIGNAL new_timecode : STD_LOGIC;
97 SIGNAL new_timecode : STD_LOGIC;
95 SIGNAL new_coarsetime : STD_LOGIC;
98 SIGNAL new_coarsetime : STD_LOGIC;
96
99
97 SIGNAL time_new_49 : STD_LOGIC;
100 SIGNAL time_new_49 : STD_LOGIC;
98 SIGNAL time_new : STD_LOGIC;
101 SIGNAL time_new : STD_LOGIC;
99
102
100 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
101 SIGNAL force_reset : STD_LOGIC;
104 SIGNAL force_reset : STD_LOGIC;
102 SIGNAL previous_force_reset : STD_LOGIC;
105 SIGNAL previous_force_reset : STD_LOGIC;
103 SIGNAL soft_reset : STD_LOGIC;
106 SIGNAL soft_reset : STD_LOGIC;
104 SIGNAL soft_reset_sync : STD_LOGIC;
107 SIGNAL soft_reset_sync : STD_LOGIC;
105 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
106
109
107 SIGNAL rstn_LFR_TM : STD_LOGIC;
110 SIGNAL rstn_LFR_TM : STD_LOGIC;
108
111
109 BEGIN
112 BEGIN
110
113
114 LFR_soft_rstn <= NOT r.LFR_soft_reset;
115
111 PROCESS(resetn, clk25MHz)
116 PROCESS(resetn, clk25MHz)
112 BEGIN
117 BEGIN
113
118
114 IF resetn = '0' THEN
119 IF resetn = '0' THEN
115 Rdata <= (OTHERS => '0');
120 Rdata <= (OTHERS => '0');
116 r.coarse_time_load <= (OTHERS => '0');
121 r.coarse_time_load <= (OTHERS => '0');
117 r.soft_reset <= '0';
122 r.soft_reset <= '0';
118 r.ctrl <= '0';
123 r.ctrl <= '0';
124 r.LFR_soft_reset <= '1';
125
119 force_tick <= '0';
126 force_tick <= '0';
120 previous_force_tick <= '0';
127 previous_force_tick <= '0';
121 soft_tick <= '0';
128 soft_tick <= '0';
122
129
123 coarsetime_reg_updated <= '0';
130 coarsetime_reg_updated <= '0';
124
131
125 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
132 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
126 coarsetime_reg_updated <= '0';
133 coarsetime_reg_updated <= '0';
127
134
128 force_tick <= r.ctrl;
135 force_tick <= r.ctrl;
129 previous_force_tick <= force_tick;
136 previous_force_tick <= force_tick;
130 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
137 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
131 soft_tick <= '1';
138 soft_tick <= '1';
132 ELSE
139 ELSE
133 soft_tick <= '0';
140 soft_tick <= '0';
134 END IF;
141 END IF;
135
142
136 force_reset <= r.soft_reset;
143 force_reset <= r.soft_reset;
137 previous_force_reset <= force_reset;
144 previous_force_reset <= force_reset;
138 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
145 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
139 soft_reset <= '1';
146 soft_reset <= '1';
140 ELSE
147 ELSE
141 soft_reset <= '0';
148 soft_reset <= '0';
142 END IF;
149 END IF;
143
150
144 --APB Write OP
151 --APB Write OP
145 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
152 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
146 CASE apbi.paddr(7 DOWNTO 2) IS
153 CASE apbi.paddr(7 DOWNTO 2) IS
147 WHEN "000000" =>
154 WHEN "000000" =>
148 r.ctrl <= apbi.pwdata(0);
155 r.ctrl <= apbi.pwdata(0);
149 r.soft_reset <= apbi.pwdata(1);
156 r.soft_reset <= apbi.pwdata(1);
157 r.LFR_soft_reset <= apbi.pwdata(2);
150 WHEN "000001" =>
158 WHEN "000001" =>
151 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
159 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
152 coarsetime_reg_updated <= '1';
160 coarsetime_reg_updated <= '1';
153 WHEN OTHERS =>
161 WHEN OTHERS =>
154 NULL;
162 NULL;
155 END CASE;
163 END CASE;
156 ELSE
164 ELSE
157 IF r.ctrl = '1' THEN
165 IF r.ctrl = '1' THEN
158 r.ctrl <= '0';
166 r.ctrl <= '0';
159 END if;
167 END if;
160 IF r.soft_reset = '1' THEN
168 IF r.soft_reset = '1' THEN
161 r.soft_reset <= '0';
169 r.soft_reset <= '0';
162 END if;
170 END if;
163 END IF;
171 END IF;
164
172
165 --APB READ OP
173 --APB READ OP
166 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
174 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
167 CASE apbi.paddr(7 DOWNTO 2) IS
175 CASE apbi.paddr(7 DOWNTO 2) IS
168 WHEN "000000" =>
176 WHEN "000000" =>
169 Rdata(0) <= r.ctrl;
177 Rdata(0) <= r.ctrl;
170 Rdata(1) <= r.soft_reset;
178 Rdata(1) <= r.soft_reset;
171 Rdata(31 DOWNTO 1) <= (others => '0');
179 Rdata(2) <= r.LFR_soft_reset;
180 Rdata(31 DOWNTO 3) <= (others => '0');
172 WHEN "000001" =>
181 WHEN "000001" =>
173 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
182 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
174 WHEN "000010" =>
183 WHEN "000010" =>
175 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
184 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
176 WHEN "000011" =>
185 WHEN "000011" =>
177 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
186 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
178 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
187 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
179 WHEN OTHERS =>
188 WHEN OTHERS =>
180 Rdata(31 DOWNTO 0) <= (others => '0');
189 Rdata(31 DOWNTO 0) <= (others => '0');
181 END CASE;
190 END CASE;
182 END IF;
191 END IF;
183
192
184 END IF;
193 END IF;
185 END PROCESS;
194 END PROCESS;
186
195
187 apbo.prdata <= Rdata;
196 apbo.prdata <= Rdata;
188 apbo.pconfig <= pconfig;
197 apbo.pconfig <= pconfig;
189 apbo.pindex <= pindex;
198 apbo.pindex <= pindex;
190
199
191 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
192 -- IN
201 -- IN
193 coarse_time <= r.coarse_time;
202 coarse_time <= r.coarse_time;
194 fine_time <= r.fine_time;
203 fine_time <= r.fine_time;
195 coarsetime_reg <= r.coarse_time_load;
204 coarsetime_reg <= r.coarse_time_load;
196 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
197
206
198 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
199 -- OUT
208 -- OUT
200 r.coarse_time <= coarse_time_s;
209 r.coarse_time <= coarse_time_s;
201 r.fine_time <= fine_time_s;
210 r.fine_time <= fine_time_s;
202 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
203
212
204 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
205 tick <= grspw_tick OR soft_tick;
214 tick <= grspw_tick OR soft_tick;
206
215
207 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
216 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
208 GENERIC MAP (
217 GENERIC MAP (
209 NB_FF_OF_SYNC => 2)
218 NB_FF_OF_SYNC => 2)
210 PORT MAP (
219 PORT MAP (
211 clk_in => clk25MHz,
220 clk_in => clk25MHz,
212 clk_out => clk24_576MHz,
221 clk_out => clk24_576MHz,
213 rstn => resetn,
222 rstn => resetn,
214 sin => tick,
223 sin => tick,
215 sout => new_timecode);
224 sout => new_timecode);
216
225
217 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
226 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
218 GENERIC MAP (
227 GENERIC MAP (
219 NB_FF_OF_SYNC => 2)
228 NB_FF_OF_SYNC => 2)
220 PORT MAP (
229 PORT MAP (
221 clk_in => clk25MHz,
230 clk_in => clk25MHz,
222 clk_out => clk24_576MHz,
231 clk_out => clk24_576MHz,
223 rstn => resetn,
232 rstn => resetn,
224 sin => coarsetime_reg_updated,
233 sin => coarsetime_reg_updated,
225 sout => new_coarsetime);
234 sout => new_coarsetime);
226
235
227 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
236 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
228 GENERIC MAP (
237 GENERIC MAP (
229 NB_FF_OF_SYNC => 2)
238 NB_FF_OF_SYNC => 2)
230 PORT MAP (
239 PORT MAP (
231 clk_in => clk25MHz,
240 clk_in => clk25MHz,
232 clk_out => clk24_576MHz,
241 clk_out => clk24_576MHz,
233 rstn => resetn,
242 rstn => resetn,
234 sin => soft_reset,
243 sin => soft_reset,
235 sout => soft_reset_sync);
244 sout => soft_reset_sync);
236
245
237 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
238 --SYNC_FF_1 : SYNC_FF
247 --SYNC_FF_1 : SYNC_FF
239 -- GENERIC MAP (
248 -- GENERIC MAP (
240 -- NB_FF_OF_SYNC => 2)
249 -- NB_FF_OF_SYNC => 2)
241 -- PORT MAP (
250 -- PORT MAP (
242 -- clk => clk25MHz,
251 -- clk => clk25MHz,
243 -- rstn => resetn,
252 -- rstn => resetn,
244 -- A => fine_time_new_49,
253 -- A => fine_time_new_49,
245 -- A_sync => fine_time_new_temp);
254 -- A_sync => fine_time_new_temp);
246
255
247 --lpp_front_detection_1 : lpp_front_detection
256 --lpp_front_detection_1 : lpp_front_detection
248 -- PORT MAP (
257 -- PORT MAP (
249 -- clk => clk25MHz,
258 -- clk => clk25MHz,
250 -- rstn => resetn,
259 -- rstn => resetn,
251 -- sin => fine_time_new_temp,
260 -- sin => fine_time_new_temp,
252 -- sout => fine_time_new);
261 -- sout => fine_time_new);
253
262
254 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
263 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
255 -- GENERIC MAP (
264 -- GENERIC MAP (
256 -- NB_FF_OF_SYNC => 2)
265 -- NB_FF_OF_SYNC => 2)
257 -- PORT MAP (
266 -- PORT MAP (
258 -- clk_in => clk24_576MHz,
267 -- clk_in => clk24_576MHz,
259 -- clk_out => clk25MHz,
268 -- clk_out => clk25MHz,
260 -- rstn => resetn,
269 -- rstn => resetn,
261 -- sin => coarse_time_new_49,
270 -- sin => coarse_time_new_49,
262 -- sout => coarse_time_new);
271 -- sout => coarse_time_new);
263
272
264 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
273 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
265
274
266 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
275 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
267 GENERIC MAP (
276 GENERIC MAP (
268 NB_FF_OF_SYNC => 2)
277 NB_FF_OF_SYNC => 2)
269 PORT MAP (
278 PORT MAP (
270 clk_in => clk24_576MHz,
279 clk_in => clk24_576MHz,
271 clk_out => clk25MHz,
280 clk_out => clk25MHz,
272 rstn => resetn,
281 rstn => resetn,
273 sin => time_new_49,
282 sin => time_new_49,
274 sout => time_new);
283 sout => time_new);
275
284
276
285
277
286
278 PROCESS (clk25MHz, resetn)
287 PROCESS (clk25MHz, resetn)
279 BEGIN -- PROCESS
288 BEGIN -- PROCESS
280 IF resetn = '0' THEN -- asynchronous reset (active low)
289 IF resetn = '0' THEN -- asynchronous reset (active low)
281 fine_time_s <= (OTHERS => '0');
290 fine_time_s <= (OTHERS => '0');
282 coarse_time_s <= (OTHERS => '0');
291 coarse_time_s <= (OTHERS => '0');
283 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
292 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
284 IF time_new = '1' THEN
293 IF time_new = '1' THEN
285 fine_time_s <= fine_time_49;
294 fine_time_s <= fine_time_49;
286 coarse_time_s <= coarse_time_49;
295 coarse_time_s <= coarse_time_49;
287 END IF;
296 END IF;
288 END IF;
297 END IF;
289 END PROCESS;
298 END PROCESS;
290
299
291
300
292 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
301 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
293 '0' WHEN soft_reset_sync = '1' ELSE
302 '0' WHEN soft_reset_sync = '1' ELSE
294 '1';
303 '1';
295
304
296
305
297 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
298 -- LFR_TIME_MANAGMENT
307 -- LFR_TIME_MANAGMENT
299 -----------------------------------------------------------------------------
308 -----------------------------------------------------------------------------
300 lfr_time_management_1 : lfr_time_management
309 lfr_time_management_1 : lfr_time_management
301 GENERIC MAP (
310 GENERIC MAP (
302 FIRST_DIVISION => FIRST_DIVISION,
311 FIRST_DIVISION => FIRST_DIVISION,
303 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
312 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
304 PORT MAP (
313 PORT MAP (
305 clk => clk24_576MHz,
314 clk => clk24_576MHz,
306 rstn => rstn_LFR_TM,
315 rstn => rstn_LFR_TM,
307
316
308 tick => new_timecode,
317 tick => new_timecode,
309 new_coarsetime => new_coarsetime,
318 new_coarsetime => new_coarsetime,
310 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
319 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
311
320
312 fine_time => fine_time_49,
321 fine_time => fine_time_49,
313 fine_time_new => fine_time_new_49,
322 fine_time_new => fine_time_new_49,
314 coarse_time => coarse_time_49,
323 coarse_time => coarse_time_49,
315 coarse_time_new => coarse_time_new_49);
324 coarse_time_new => coarse_time_new_49);
316
325
317 END Behavioral;
326 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,102 +1,103
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 13:04:01 07/02/2012
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26
26
27 PACKAGE lpp_lfr_time_management IS
27 PACKAGE lpp_lfr_time_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_TIME_MANAGEMENT
31
31
32 COMPONENT apb_lfr_time_management IS
32 COMPONENT apb_lfr_time_management IS
33 GENERIC(
33 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
34 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 FIRST_DIVISION : INTEGER;
37 FIRST_DIVISION : INTEGER;
38 NB_SECOND_DESYNC : INTEGER);
38 NB_SECOND_DESYNC : INTEGER);
39 PORT (
39 PORT (
40 clk25MHz : IN STD_LOGIC; --! Clock
40 clk25MHz : IN STD_LOGIC; --! Clock
41 clk24_576MHz : IN STD_LOGIC; --! secondary clock
41 clk24_576MHz : IN STD_LOGIC; --! secondary clock
42 resetn : IN STD_LOGIC; --! Reset
42 resetn : IN STD_LOGIC; --! Reset
43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
44 apbi : IN apb_slv_in_type; --! APB slave input signals
44 apbi : IN apb_slv_in_type; --! APB slave input signals
45 apbo : OUT apb_slv_out_type; --! APB slave output signals
45 apbo : OUT apb_slv_out_type; --! APB slave output signals
46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
48 LFR_soft_rstn : OUT STD_LOGIC
48 );
49 );
49 END COMPONENT;
50 END COMPONENT;
50
51
51 COMPONENT lfr_time_management
52 COMPONENT lfr_time_management
52 GENERIC (
53 GENERIC (
53 FIRST_DIVISION : INTEGER;
54 FIRST_DIVISION : INTEGER;
54 NB_SECOND_DESYNC : INTEGER);
55 NB_SECOND_DESYNC : INTEGER);
55 PORT (
56 PORT (
56 clk : IN STD_LOGIC;
57 clk : IN STD_LOGIC;
57 rstn : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
58 tick : IN STD_LOGIC;
59 tick : IN STD_LOGIC;
59 new_coarsetime : IN STD_LOGIC;
60 new_coarsetime : IN STD_LOGIC;
60 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 fine_time_new : OUT STD_LOGIC;
63 fine_time_new : OUT STD_LOGIC;
63 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 coarse_time_new : OUT STD_LOGIC);
65 coarse_time_new : OUT STD_LOGIC);
65 END COMPONENT;
66 END COMPONENT;
66
67
67 COMPONENT coarse_time_counter
68 COMPONENT coarse_time_counter
68 GENERIC (
69 GENERIC (
69 NB_SECOND_DESYNC : INTEGER );
70 NB_SECOND_DESYNC : INTEGER );
70 PORT (
71 PORT (
71 clk : IN STD_LOGIC;
72 clk : IN STD_LOGIC;
72 rstn : IN STD_LOGIC;
73 rstn : IN STD_LOGIC;
73 tick : IN STD_LOGIC;
74 tick : IN STD_LOGIC;
74 set_TCU : IN STD_LOGIC;
75 set_TCU : IN STD_LOGIC;
75 new_TCU : IN STD_LOGIC;
76 new_TCU : IN STD_LOGIC;
76 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 CT_add1 : IN STD_LOGIC;
78 CT_add1 : IN STD_LOGIC;
78 fsm_desync : IN STD_LOGIC;
79 fsm_desync : IN STD_LOGIC;
79 FT_max : IN STD_LOGIC;
80 FT_max : IN STD_LOGIC;
80 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 coarse_time_new : OUT STD_LOGIC);
82 coarse_time_new : OUT STD_LOGIC);
82 END COMPONENT;
83 END COMPONENT;
83
84
84 COMPONENT fine_time_counter
85 COMPONENT fine_time_counter
85 GENERIC (
86 GENERIC (
86 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
87 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
87 FIRST_DIVISION : INTEGER );
88 FIRST_DIVISION : INTEGER );
88 PORT (
89 PORT (
89 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
90 rstn : IN STD_LOGIC;
91 rstn : IN STD_LOGIC;
91 tick : IN STD_LOGIC;
92 tick : IN STD_LOGIC;
92 fsm_transition : IN STD_LOGIC;
93 fsm_transition : IN STD_LOGIC;
93 FT_max : OUT STD_LOGIC;
94 FT_max : OUT STD_LOGIC;
94 FT_half : OUT STD_LOGIC;
95 FT_half : OUT STD_LOGIC;
95 FT_wait : OUT STD_LOGIC;
96 FT_wait : OUT STD_LOGIC;
96 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
97 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
97 fine_time_new : OUT STD_LOGIC);
98 fine_time_new : OUT STD_LOGIC);
98 END COMPONENT;
99 END COMPONENT;
99
100
100
101
101 END lpp_lfr_time_management;
102 END lpp_lfr_time_management;
102
103
Show file before | Show file after | Hide comments
@@ -1,565 +1,567
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 -- nb_word_by_buffer_size : INTEGER := 11; -- TODO
29 -- nb_word_by_buffer_size : INTEGER := 11; -- TODO
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC
62 data_shaping_BW : OUT STD_LOGIC
63 --
63 --
64 --
64 --
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
67
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
69
70 --debug
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
79
80 ---- debug FIFO_IN
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
89
90 ----debug FIFO OUT
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
99
100 ----debug DMA IN
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 );
109 );
110 END lpp_lfr;
110 END lpp_lfr;
111
111
112 ARCHITECTURE beh OF lpp_lfr IS
112 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 --
115 --
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
121 --
121 --
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 --
125 --
126 SIGNAL sample_f0_val : STD_LOGIC;
126 SIGNAL sample_f0_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
130 --
130 --
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 --
135 --
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
139
139
140 -- SM
140 -- SM
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
162
162
163 -- WFP
163 -- WFP
164 --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173
173
174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
175 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
175 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
176 SIGNAL enable_f0 : STD_LOGIC;
176 SIGNAL enable_f0 : STD_LOGIC;
177 SIGNAL enable_f1 : STD_LOGIC;
177 SIGNAL enable_f1 : STD_LOGIC;
178 SIGNAL enable_f2 : STD_LOGIC;
178 SIGNAL enable_f2 : STD_LOGIC;
179 SIGNAL enable_f3 : STD_LOGIC;
179 SIGNAL enable_f3 : STD_LOGIC;
180 SIGNAL burst_f0 : STD_LOGIC;
180 SIGNAL burst_f0 : STD_LOGIC;
181 SIGNAL burst_f1 : STD_LOGIC;
181 SIGNAL burst_f1 : STD_LOGIC;
182 SIGNAL burst_f2 : STD_LOGIC;
182 SIGNAL burst_f2 : STD_LOGIC;
183
183
184 SIGNAL run : STD_LOGIC;
184 --SIGNAL run : STD_LOGIC;
185 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
185 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
186
186
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188 --
188 --
189 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
190 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
191 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
193 --f1
193 --f1
194 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
195 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
196 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
196 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
197 --f2
197 --f2
198 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
201 --f3
201 --f3
202 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
203 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
205
205
206 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
206 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
207 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
207 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
208 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
208 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
209 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
210 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
211 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
211 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
212 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
213 -- DMA RR
213 -- DMA RR
214 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
215 SIGNAL dma_sel_valid : STD_LOGIC;
215 SIGNAL dma_sel_valid : STD_LOGIC;
216 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
219 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
219 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
220
220
221 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
221 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
223
223
224 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
225 -- DMA_REG
225 -- DMA_REG
226 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
227 SIGNAL ongoing_reg : STD_LOGIC;
227 SIGNAL ongoing_reg : STD_LOGIC;
228 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
229 SIGNAL dma_send_reg : STD_LOGIC;
229 SIGNAL dma_send_reg : STD_LOGIC;
230 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
230 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
231 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
231 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
233
233
234
234
235 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
236 -- DMA
236 -- DMA
237 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
238 SIGNAL dma_send : STD_LOGIC;
238 SIGNAL dma_send : STD_LOGIC;
239 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
239 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
240 SIGNAL dma_done : STD_LOGIC;
240 SIGNAL dma_done : STD_LOGIC;
241 SIGNAL dma_ren : STD_LOGIC;
241 SIGNAL dma_ren : STD_LOGIC;
242 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
245
245
246 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
247 -- MS
247 -- MS
248 -----------------------------------------------------------------------------
248 -----------------------------------------------------------------------------
249
249
250 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL data_ms_valid : STD_LOGIC;
252 SIGNAL data_ms_valid : STD_LOGIC;
253 SIGNAL data_ms_valid_burst : STD_LOGIC;
253 SIGNAL data_ms_valid_burst : STD_LOGIC;
254 SIGNAL data_ms_ren : STD_LOGIC;
254 SIGNAL data_ms_ren : STD_LOGIC;
255 SIGNAL data_ms_done : STD_LOGIC;
255 SIGNAL data_ms_done : STD_LOGIC;
256 SIGNAL dma_ms_ongoing : STD_LOGIC;
256 SIGNAL dma_ms_ongoing : STD_LOGIC;
257
257
258 SIGNAL run_ms : STD_LOGIC;
258 -- SIGNAL run_ms : STD_LOGIC;
259 SIGNAL ms_softandhard_rstn : STD_LOGIC;
259 SIGNAL ms_softandhard_rstn : STD_LOGIC;
260
260
261 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
264 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
264 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
265
265
266
266
267 SIGNAL error_buffer_full : STD_LOGIC;
267 SIGNAL error_buffer_full : STD_LOGIC;
268 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
268 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
269
269
270 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
272
272
273 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
274 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
274 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
275 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
275 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
276 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
276 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
277 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
277 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
278 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
279 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
279 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
280 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
280 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
281 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
281 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
282 SIGNAL dma_grant_error : STD_LOGIC;
282 SIGNAL dma_grant_error : STD_LOGIC;
283
283
284 -----------------------------------------------------------------------------
284 -----------------------------------------------------------------------------
285 SIGNAL run_dma : STD_LOGIC;
285 -- SIGNAL run_dma : STD_LOGIC;
286 BEGIN
286 BEGIN
287
287
288 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
288 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
289 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
289 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
290
290
291 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
291 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
292 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
292 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
293 --END GENERATE all_channel;
293 --END GENERATE all_channel;
294
294
295 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
296 lpp_lfr_filter_1 : lpp_lfr_filter
296 lpp_lfr_filter_1 : lpp_lfr_filter
297 GENERIC MAP (
297 GENERIC MAP (
298 Mem_use => Mem_use)
298 Mem_use => Mem_use)
299 PORT MAP (
299 PORT MAP (
300 sample => sample_s,
300 sample => sample_s,
301 sample_val => sample_val,
301 sample_val => sample_val,
302 clk => clk,
302 clk => clk,
303 rstn => rstn,
303 rstn => rstn,
304 data_shaping_SP0 => data_shaping_SP0,
304 data_shaping_SP0 => data_shaping_SP0,
305 data_shaping_SP1 => data_shaping_SP1,
305 data_shaping_SP1 => data_shaping_SP1,
306 data_shaping_R0 => data_shaping_R0,
306 data_shaping_R0 => data_shaping_R0,
307 data_shaping_R1 => data_shaping_R1,
307 data_shaping_R1 => data_shaping_R1,
308 data_shaping_R2 => data_shaping_R2,
308 data_shaping_R2 => data_shaping_R2,
309 sample_f0_val => sample_f0_val,
309 sample_f0_val => sample_f0_val,
310 sample_f1_val => sample_f1_val,
310 sample_f1_val => sample_f1_val,
311 sample_f2_val => sample_f2_val,
311 sample_f2_val => sample_f2_val,
312 sample_f3_val => sample_f3_val,
312 sample_f3_val => sample_f3_val,
313 sample_f0_wdata => sample_f0_data,
313 sample_f0_wdata => sample_f0_data,
314 sample_f1_wdata => sample_f1_data,
314 sample_f1_wdata => sample_f1_data,
315 sample_f2_wdata => sample_f2_data,
315 sample_f2_wdata => sample_f2_data,
316 sample_f3_wdata => sample_f3_data);
316 sample_f3_wdata => sample_f3_data);
317
317
318 -----------------------------------------------------------------------------
318 -----------------------------------------------------------------------------
319 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
319 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
320 GENERIC MAP (
320 GENERIC MAP (
321 nb_data_by_buffer_size => nb_data_by_buffer_size,
321 nb_data_by_buffer_size => nb_data_by_buffer_size,
322 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
322 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
323 nb_snapshot_param_size => nb_snapshot_param_size,
323 nb_snapshot_param_size => nb_snapshot_param_size,
324 delta_vector_size => delta_vector_size,
324 delta_vector_size => delta_vector_size,
325 delta_vector_size_f0_2 => delta_vector_size_f0_2,
325 delta_vector_size_f0_2 => delta_vector_size_f0_2,
326 pindex => pindex,
326 pindex => pindex,
327 paddr => paddr,
327 paddr => paddr,
328 pmask => pmask,
328 pmask => pmask,
329 pirq_ms => pirq_ms,
329 pirq_ms => pirq_ms,
330 pirq_wfp => pirq_wfp,
330 pirq_wfp => pirq_wfp,
331 top_lfr_version => top_lfr_version)
331 top_lfr_version => top_lfr_version)
332 PORT MAP (
332 PORT MAP (
333 HCLK => clk,
333 HCLK => clk,
334 HRESETn => rstn,
334 HRESETn => rstn,
335 apbi => apbi,
335 apbi => apbi,
336 apbo => apbo,
336 apbo => apbo,
337
337
338 run_ms => run_ms,
338 run_ms => OPEN,--run_ms,
339
339
340 ready_matrix_f0 => ready_matrix_f0,
340 ready_matrix_f0 => ready_matrix_f0,
341 ready_matrix_f1 => ready_matrix_f1,
341 ready_matrix_f1 => ready_matrix_f1,
342 ready_matrix_f2 => ready_matrix_f2,
342 ready_matrix_f2 => ready_matrix_f2,
343 error_buffer_full => error_buffer_full, -- TODO
343 error_buffer_full => error_buffer_full, -- TODO
344 error_input_fifo_write => error_input_fifo_write, -- TODO
344 error_input_fifo_write => error_input_fifo_write, -- TODO
345 status_ready_matrix_f0 => status_ready_matrix_f0,
345 status_ready_matrix_f0 => status_ready_matrix_f0,
346 status_ready_matrix_f1 => status_ready_matrix_f1,
346 status_ready_matrix_f1 => status_ready_matrix_f1,
347 status_ready_matrix_f2 => status_ready_matrix_f2,
347 status_ready_matrix_f2 => status_ready_matrix_f2,
348
348
349 matrix_time_f0 => matrix_time_f0,
349 matrix_time_f0 => matrix_time_f0,
350 matrix_time_f1 => matrix_time_f1,
350 matrix_time_f1 => matrix_time_f1,
351 matrix_time_f2 => matrix_time_f2,
351 matrix_time_f2 => matrix_time_f2,
352
352
353 addr_matrix_f0 => addr_matrix_f0,
353 addr_matrix_f0 => addr_matrix_f0,
354 addr_matrix_f1 => addr_matrix_f1,
354 addr_matrix_f1 => addr_matrix_f1,
355 addr_matrix_f2 => addr_matrix_f2,
355 addr_matrix_f2 => addr_matrix_f2,
356
356
357 length_matrix_f0 => length_matrix_f0,
357 length_matrix_f0 => length_matrix_f0,
358 length_matrix_f1 => length_matrix_f1,
358 length_matrix_f1 => length_matrix_f1,
359 length_matrix_f2 => length_matrix_f2,
359 length_matrix_f2 => length_matrix_f2,
360 -------------------------------------------------------------------------
360 -------------------------------------------------------------------------
361 --status_full => status_full, -- TODo
361 --status_full => status_full, -- TODo
362 --status_full_ack => status_full_ack, -- TODo
362 --status_full_ack => status_full_ack, -- TODo
363 --status_full_err => status_full_err, -- TODo
363 --status_full_err => status_full_err, -- TODo
364 status_new_err => status_new_err,
364 status_new_err => status_new_err,
365 data_shaping_BW => data_shaping_BW,
365 data_shaping_BW => data_shaping_BW,
366 data_shaping_SP0 => data_shaping_SP0,
366 data_shaping_SP0 => data_shaping_SP0,
367 data_shaping_SP1 => data_shaping_SP1,
367 data_shaping_SP1 => data_shaping_SP1,
368 data_shaping_R0 => data_shaping_R0,
368 data_shaping_R0 => data_shaping_R0,
369 data_shaping_R1 => data_shaping_R1,
369 data_shaping_R1 => data_shaping_R1,
370 data_shaping_R2 => data_shaping_R2,
370 data_shaping_R2 => data_shaping_R2,
371 delta_snapshot => delta_snapshot,
371 delta_snapshot => delta_snapshot,
372 delta_f0 => delta_f0,
372 delta_f0 => delta_f0,
373 delta_f0_2 => delta_f0_2,
373 delta_f0_2 => delta_f0_2,
374 delta_f1 => delta_f1,
374 delta_f1 => delta_f1,
375 delta_f2 => delta_f2,
375 delta_f2 => delta_f2,
376 nb_data_by_buffer => nb_data_by_buffer,
376 nb_data_by_buffer => nb_data_by_buffer,
377 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
377 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
378 nb_snapshot_param => nb_snapshot_param,
378 nb_snapshot_param => nb_snapshot_param,
379 enable_f0 => enable_f0,
379 enable_f0 => enable_f0,
380 enable_f1 => enable_f1,
380 enable_f1 => enable_f1,
381 enable_f2 => enable_f2,
381 enable_f2 => enable_f2,
382 enable_f3 => enable_f3,
382 enable_f3 => enable_f3,
383 burst_f0 => burst_f0,
383 burst_f0 => burst_f0,
384 burst_f1 => burst_f1,
384 burst_f1 => burst_f1,
385 burst_f2 => burst_f2,
385 burst_f2 => burst_f2,
386 run => run,
386 run => OPEN, --run,
387 start_date => start_date,
387 start_date => start_date,
388 -- debug_signal => debug_signal,
388 -- debug_signal => debug_signal,
389 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
389 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
390 wfp_addr_buffer => wfp_addr_buffer,-- TODO
390 wfp_addr_buffer => wfp_addr_buffer,-- TODO
391 wfp_length_buffer => wfp_length_buffer,-- TODO
391 wfp_length_buffer => wfp_length_buffer,-- TODO
392
392
393 wfp_ready_buffer => wfp_ready_buffer,-- TODO
393 wfp_ready_buffer => wfp_ready_buffer,-- TODO
394 wfp_buffer_time => wfp_buffer_time,-- TODO
394 wfp_buffer_time => wfp_buffer_time,-- TODO
395 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
395 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
396 );
396 );
397
397
398 -----------------------------------------------------------------------------
398 -----------------------------------------------------------------------------
399 -----------------------------------------------------------------------------
399 -----------------------------------------------------------------------------
400 lpp_waveform_1 : lpp_waveform
400 lpp_waveform_1 : lpp_waveform
401 GENERIC MAP (
401 GENERIC MAP (
402 tech => inferred,
402 tech => inferred,
403 data_size => 6*16,
403 data_size => 6*16,
404 nb_data_by_buffer_size => nb_data_by_buffer_size,
404 nb_data_by_buffer_size => nb_data_by_buffer_size,
405 nb_snapshot_param_size => nb_snapshot_param_size,
405 nb_snapshot_param_size => nb_snapshot_param_size,
406 delta_vector_size => delta_vector_size,
406 delta_vector_size => delta_vector_size,
407 delta_vector_size_f0_2 => delta_vector_size_f0_2
407 delta_vector_size_f0_2 => delta_vector_size_f0_2
408 )
408 )
409 PORT MAP (
409 PORT MAP (
410 clk => clk,
410 clk => clk,
411 rstn => rstn,
411 rstn => rstn,
412
412
413 reg_run => run,
413 reg_run => '1',--run,
414 reg_start_date => start_date,
414 reg_start_date => start_date,
415 reg_delta_snapshot => delta_snapshot,
415 reg_delta_snapshot => delta_snapshot,
416 reg_delta_f0 => delta_f0,
416 reg_delta_f0 => delta_f0,
417 reg_delta_f0_2 => delta_f0_2,
417 reg_delta_f0_2 => delta_f0_2,
418 reg_delta_f1 => delta_f1,
418 reg_delta_f1 => delta_f1,
419 reg_delta_f2 => delta_f2,
419 reg_delta_f2 => delta_f2,
420
420
421 enable_f0 => enable_f0,
421 enable_f0 => enable_f0,
422 enable_f1 => enable_f1,
422 enable_f1 => enable_f1,
423 enable_f2 => enable_f2,
423 enable_f2 => enable_f2,
424 enable_f3 => enable_f3,
424 enable_f3 => enable_f3,
425 burst_f0 => burst_f0,
425 burst_f0 => burst_f0,
426 burst_f1 => burst_f1,
426 burst_f1 => burst_f1,
427 burst_f2 => burst_f2,
427 burst_f2 => burst_f2,
428
428
429 nb_data_by_buffer => nb_data_by_buffer,
429 nb_data_by_buffer => nb_data_by_buffer,
430 nb_snapshot_param => nb_snapshot_param,
430 nb_snapshot_param => nb_snapshot_param,
431 status_new_err => status_new_err,
431 status_new_err => status_new_err,
432
432
433 status_buffer_ready => wfp_status_buffer_ready,
433 status_buffer_ready => wfp_status_buffer_ready,
434 addr_buffer => wfp_addr_buffer,
434 addr_buffer => wfp_addr_buffer,
435 length_buffer => wfp_length_buffer,
435 length_buffer => wfp_length_buffer,
436 ready_buffer => wfp_ready_buffer,
436 ready_buffer => wfp_ready_buffer,
437 buffer_time => wfp_buffer_time,
437 buffer_time => wfp_buffer_time,
438 error_buffer_full => wfp_error_buffer_full,
438 error_buffer_full => wfp_error_buffer_full,
439
439
440 coarse_time => coarse_time,
440 coarse_time => coarse_time,
441 fine_time => fine_time,
441 fine_time => fine_time,
442
442
443 --f0
443 --f0
444 data_f0_in_valid => sample_f0_val,
444 data_f0_in_valid => sample_f0_val,
445 data_f0_in => sample_f0_data,
445 data_f0_in => sample_f0_data,
446 --f1
446 --f1
447 data_f1_in_valid => sample_f1_val,
447 data_f1_in_valid => sample_f1_val,
448 data_f1_in => sample_f1_data,
448 data_f1_in => sample_f1_data,
449 --f2
449 --f2
450 data_f2_in_valid => sample_f2_val,
450 data_f2_in_valid => sample_f2_val,
451 data_f2_in => sample_f2_data,
451 data_f2_in => sample_f2_data,
452 --f3
452 --f3
453 data_f3_in_valid => sample_f3_val,
453 data_f3_in_valid => sample_f3_val,
454 data_f3_in => sample_f3_data,
454 data_f3_in => sample_f3_data,
455 -- OUTPUT -- DMA interface
455 -- OUTPUT -- DMA interface
456
456
457 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
457 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
458 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
458 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
459 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
459 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
460 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
460 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
461 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
461 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
462 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
462 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
463 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
463 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
464 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
464 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
465
465
466 );
466 );
467
467
468 -----------------------------------------------------------------------------
468 -----------------------------------------------------------------------------
469 -- Matrix Spectral
469 -- Matrix Spectral
470 -----------------------------------------------------------------------------
470 -----------------------------------------------------------------------------
471 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
471 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
472 NOT(sample_f0_val) & NOT(sample_f0_val);
472 NOT(sample_f0_val) & NOT(sample_f0_val);
473 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
473 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
474 NOT(sample_f1_val) & NOT(sample_f1_val);
474 NOT(sample_f1_val) & NOT(sample_f1_val);
475 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
475 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
476 NOT(sample_f2_val) & NOT(sample_f2_val);
476 NOT(sample_f2_val) & NOT(sample_f2_val);
477
477
478 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
478 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
479 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
479 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
480 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
480 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
481
481
482 -------------------------------------------------------------------------------
482 -------------------------------------------------------------------------------
483
483
484 ms_softandhard_rstn <= rstn AND run_ms AND run;
484 --ms_softandhard_rstn <= rstn AND run_ms AND run;
485
485
486 -----------------------------------------------------------------------------
486 -----------------------------------------------------------------------------
487 lpp_lfr_ms_1 : lpp_lfr_ms
487 lpp_lfr_ms_1 : lpp_lfr_ms
488 GENERIC MAP (
488 GENERIC MAP (
489 Mem_use => Mem_use)
489 Mem_use => Mem_use)
490 PORT MAP (
490 PORT MAP (
491 clk => clk,
491 clk => clk,
492 --rstn => ms_softandhard_rstn, --rstn,
492 --rstn => ms_softandhard_rstn, --rstn,
493 rstn => rstn,
493 rstn => rstn,
494
494
495 run => run_ms,
495 run => '1',--run_ms,
496
496
497 start_date => start_date,
498
497 coarse_time => coarse_time,
499 coarse_time => coarse_time,
498 fine_time => fine_time,
500 fine_time => fine_time,
499
501
500 sample_f0_wen => sample_f0_wen,
502 sample_f0_wen => sample_f0_wen,
501 sample_f0_wdata => sample_f0_wdata,
503 sample_f0_wdata => sample_f0_wdata,
502 sample_f1_wen => sample_f1_wen,
504 sample_f1_wen => sample_f1_wen,
503 sample_f1_wdata => sample_f1_wdata,
505 sample_f1_wdata => sample_f1_wdata,
504 sample_f2_wen => sample_f2_wen,
506 sample_f2_wen => sample_f2_wen,
505 sample_f2_wdata => sample_f2_wdata,
507 sample_f2_wdata => sample_f2_wdata,
506
508
507 --DMA
509 --DMA
508 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
510 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
509 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
511 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
510 dma_fifo_ren => dma_fifo_ren(4), -- IN
512 dma_fifo_ren => dma_fifo_ren(4), -- IN
511 dma_buffer_new => dma_buffer_new(4), -- OUT
513 dma_buffer_new => dma_buffer_new(4), -- OUT
512 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
514 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
513 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
515 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
514 dma_buffer_full => dma_buffer_full(4), -- IN
516 dma_buffer_full => dma_buffer_full(4), -- IN
515 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
517 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
516
518
517
519
518
520
519 --REG
521 --REG
520 ready_matrix_f0 => ready_matrix_f0,
522 ready_matrix_f0 => ready_matrix_f0,
521 ready_matrix_f1 => ready_matrix_f1,
523 ready_matrix_f1 => ready_matrix_f1,
522 ready_matrix_f2 => ready_matrix_f2,
524 ready_matrix_f2 => ready_matrix_f2,
523 error_buffer_full => error_buffer_full,
525 error_buffer_full => error_buffer_full,
524 error_input_fifo_write => error_input_fifo_write,
526 error_input_fifo_write => error_input_fifo_write,
525
527
526 status_ready_matrix_f0 => status_ready_matrix_f0,
528 status_ready_matrix_f0 => status_ready_matrix_f0,
527 status_ready_matrix_f1 => status_ready_matrix_f1,
529 status_ready_matrix_f1 => status_ready_matrix_f1,
528 status_ready_matrix_f2 => status_ready_matrix_f2,
530 status_ready_matrix_f2 => status_ready_matrix_f2,
529 addr_matrix_f0 => addr_matrix_f0,
531 addr_matrix_f0 => addr_matrix_f0,
530 addr_matrix_f1 => addr_matrix_f1,
532 addr_matrix_f1 => addr_matrix_f1,
531 addr_matrix_f2 => addr_matrix_f2,
533 addr_matrix_f2 => addr_matrix_f2,
532
534
533 length_matrix_f0 => length_matrix_f0,
535 length_matrix_f0 => length_matrix_f0,
534 length_matrix_f1 => length_matrix_f1,
536 length_matrix_f1 => length_matrix_f1,
535 length_matrix_f2 => length_matrix_f2,
537 length_matrix_f2 => length_matrix_f2,
536
538
537 matrix_time_f0 => matrix_time_f0,
539 matrix_time_f0 => matrix_time_f0,
538 matrix_time_f1 => matrix_time_f1,
540 matrix_time_f1 => matrix_time_f1,
539 matrix_time_f2 => matrix_time_f2);
541 matrix_time_f2 => matrix_time_f2);
540
542
541 -----------------------------------------------------------------------------
543 -----------------------------------------------------------------------------
542 run_dma <= run_ms OR run;
544 --run_dma <= run_ms OR run;
543
545
544 DMA_SubSystem_1 : DMA_SubSystem
546 DMA_SubSystem_1 : DMA_SubSystem
545 GENERIC MAP (
547 GENERIC MAP (
546 hindex => hindex)
548 hindex => hindex)
547 PORT MAP (
549 PORT MAP (
548 clk => clk,
550 clk => clk,
549 rstn => rstn,
551 rstn => rstn,
550 run => run_dma,
552 run => '1',--run_dma,
551 ahbi => ahbi,
553 ahbi => ahbi,
552 ahbo => ahbo,
554 ahbo => ahbo,
553
555
554 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
556 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
555 fifo_data => dma_fifo_data, --fifo_data,
557 fifo_data => dma_fifo_data, --fifo_data,
556 fifo_ren => dma_fifo_ren, --fifo_ren,
558 fifo_ren => dma_fifo_ren, --fifo_ren,
557
559
558 buffer_new => dma_buffer_new, --buffer_new,
560 buffer_new => dma_buffer_new, --buffer_new,
559 buffer_addr => dma_buffer_addr, --buffer_addr,
561 buffer_addr => dma_buffer_addr, --buffer_addr,
560 buffer_length => dma_buffer_length, --buffer_length,
562 buffer_length => dma_buffer_length, --buffer_length,
561 buffer_full => dma_buffer_full, --buffer_full,
563 buffer_full => dma_buffer_full, --buffer_full,
562 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
564 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
563 grant_error => dma_grant_error); --grant_error);
565 grant_error => dma_grant_error); --grant_error);
564
566
565 END beh;
567 END beh;
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@@ -1,784 +1,784
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
36 USE techmap.gencomp.ALL;
37
37
38 ENTITY lpp_lfr_apbreg IS
38 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
39 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
40 nb_data_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
43 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
44 delta_vector_size_f0_2 : INTEGER := 3;
45
45
46 pindex : INTEGER := 4;
46 pindex : INTEGER := 4;
47 paddr : INTEGER := 4;
47 paddr : INTEGER := 4;
48 pmask : INTEGER := 16#fff#;
48 pmask : INTEGER := 16#fff#;
49 pirq_ms : INTEGER := 0;
49 pirq_ms : INTEGER := 0;
50 pirq_wfp : INTEGER := 1;
50 pirq_wfp : INTEGER := 1;
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 -- Spectral Matrix Reg
62 -- Spectral Matrix Reg
63 run_ms : OUT STD_LOGIC;
63 run_ms : OUT STD_LOGIC;
64 -- IN
64 -- IN
65 ready_matrix_f0 : IN STD_LOGIC;
65 ready_matrix_f0 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68
68
69 -- error_bad_component_error : IN STD_LOGIC;
69 -- error_bad_component_error : IN STD_LOGIC;
70 error_buffer_full : IN STD_LOGIC; -- TODO
70 error_buffer_full : IN STD_LOGIC; -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72
72
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- OUT
75 -- OUT
76 status_ready_matrix_f0 : OUT STD_LOGIC;
76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
79
79
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
81 --config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
87 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90
90
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94
94
95 ---------------------------------------------------------------------------
95 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
96 ---------------------------------------------------------------------------
97 -- WaveForm picker Reg
97 -- WaveForm picker Reg
98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102
102
103 -- OUT
103 -- OUT
104 data_shaping_BW : OUT STD_LOGIC;
104 data_shaping_BW : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
105 data_shaping_SP0 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
106 data_shaping_SP1 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
107 data_shaping_R0 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
108 data_shaping_R1 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
109 data_shaping_R2 : OUT STD_LOGIC;
110
110
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
113 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
116 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
117 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
118 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
119
119
120 enable_f0 : OUT STD_LOGIC;
120 enable_f0 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
121 enable_f1 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
122 enable_f2 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
123 enable_f3 : OUT STD_LOGIC;
124
124
125 burst_f0 : OUT STD_LOGIC;
125 burst_f0 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
126 burst_f1 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
127 burst_f2 : OUT STD_LOGIC;
128
128
129 run : OUT STD_LOGIC;
129 run : OUT STD_LOGIC;
130
130
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
132
132
133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
134 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
135 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
137 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
138 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
139
139
140 );
140 );
141
141
142 END lpp_lfr_apbreg;
142 END lpp_lfr_apbreg;
143
143
144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
144 ARCHITECTURE beh OF lpp_lfr_apbreg IS
145
145
146 CONSTANT REVISION : INTEGER := 1;
146 CONSTANT REVISION : INTEGER := 1;
147
147
148 CONSTANT pconfig : apb_config_type := (
148 CONSTANT pconfig : apb_config_type := (
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
150 1 => apb_iobar(paddr, pmask));
150 1 => apb_iobar(paddr, pmask));
151
151
152 TYPE lpp_SpectralMatrix_regs IS RECORD
152 TYPE lpp_SpectralMatrix_regs IS RECORD
153 config_active_interruption_onNewMatrix : STD_LOGIC;
153 config_active_interruption_onNewMatrix : STD_LOGIC;
154 config_active_interruption_onError : STD_LOGIC;
154 config_active_interruption_onError : STD_LOGIC;
155 config_ms_run : STD_LOGIC;
155 config_ms_run : STD_LOGIC;
156 status_ready_matrix_f0_0 : STD_LOGIC;
156 status_ready_matrix_f0_0 : STD_LOGIC;
157 status_ready_matrix_f1_0 : STD_LOGIC;
157 status_ready_matrix_f1_0 : STD_LOGIC;
158 status_ready_matrix_f2_0 : STD_LOGIC;
158 status_ready_matrix_f2_0 : STD_LOGIC;
159 status_ready_matrix_f0_1 : STD_LOGIC;
159 status_ready_matrix_f0_1 : STD_LOGIC;
160 status_ready_matrix_f1_1 : STD_LOGIC;
160 status_ready_matrix_f1_1 : STD_LOGIC;
161 status_ready_matrix_f2_1 : STD_LOGIC;
161 status_ready_matrix_f2_1 : STD_LOGIC;
162 -- status_error_bad_component_error : STD_LOGIC;
162 -- status_error_bad_component_error : STD_LOGIC;
163 status_error_buffer_full : STD_LOGIC;
163 status_error_buffer_full : STD_LOGIC;
164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
164 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
165
165
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172
172
173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
173 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
174
174
175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
175 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
181 END RECORD;
181 END RECORD;
182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
183
183
184 TYPE lpp_WaveformPicker_regs IS RECORD
184 TYPE lpp_WaveformPicker_regs IS RECORD
185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 data_shaping_BW : STD_LOGIC;
188 data_shaping_BW : STD_LOGIC;
189 data_shaping_SP0 : STD_LOGIC;
189 data_shaping_SP0 : STD_LOGIC;
190 data_shaping_SP1 : STD_LOGIC;
190 data_shaping_SP1 : STD_LOGIC;
191 data_shaping_R0 : STD_LOGIC;
191 data_shaping_R0 : STD_LOGIC;
192 data_shaping_R1 : STD_LOGIC;
192 data_shaping_R1 : STD_LOGIC;
193 data_shaping_R2 : STD_LOGIC;
193 data_shaping_R2 : STD_LOGIC;
194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
196 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
199 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
200 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
201 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
202 enable_f0 : STD_LOGIC;
202 enable_f0 : STD_LOGIC;
203 enable_f1 : STD_LOGIC;
203 enable_f1 : STD_LOGIC;
204 enable_f2 : STD_LOGIC;
204 enable_f2 : STD_LOGIC;
205 enable_f3 : STD_LOGIC;
205 enable_f3 : STD_LOGIC;
206 burst_f0 : STD_LOGIC;
206 burst_f0 : STD_LOGIC;
207 burst_f1 : STD_LOGIC;
207 burst_f1 : STD_LOGIC;
208 burst_f2 : STD_LOGIC;
208 burst_f2 : STD_LOGIC;
209 run : STD_LOGIC;
209 run : STD_LOGIC;
210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
210 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
211 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
212 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
213 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
215 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
216 END RECORD;
216 END RECORD;
217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
217 SIGNAL reg_wp : lpp_WaveformPicker_regs;
218
218
219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
220
220
221 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
222 -- IRQ
222 -- IRQ
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
224 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
225 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
229 SIGNAL ored_irq_wfp : STD_LOGIC;
229 SIGNAL ored_irq_wfp : STD_LOGIC;
230
230
231 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
232 --
232 --
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
234 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
235 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237
237
238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
238 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241
241
242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
242 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245
245
246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
246 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249
249
250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
250 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
252 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253
253
254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
254 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
256 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 SIGNAL apbo_irq_ms : STD_LOGIC;
257 SIGNAL apbo_irq_ms : STD_LOGIC;
258 SIGNAL apbo_irq_wfp : STD_LOGIC;
258 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
261
261
262 BEGIN -- beh
262 BEGIN -- beh
263
263
264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
264 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
265 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
266 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
267
267
268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
268 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
269 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
270
270
271
271
272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
272 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
273 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
274 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
275
275
276
276
277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
277 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
278 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
279 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
280 data_shaping_R0 <= reg_wp.data_shaping_R0;
280 data_shaping_R0 <= reg_wp.data_shaping_R0;
281 data_shaping_R1 <= reg_wp.data_shaping_R1;
281 data_shaping_R1 <= reg_wp.data_shaping_R1;
282 data_shaping_R2 <= reg_wp.data_shaping_R2;
282 data_shaping_R2 <= reg_wp.data_shaping_R2;
283
283
284 delta_snapshot <= reg_wp.delta_snapshot;
284 delta_snapshot <= reg_wp.delta_snapshot;
285 delta_f0 <= reg_wp.delta_f0;
285 delta_f0 <= reg_wp.delta_f0;
286 delta_f0_2 <= reg_wp.delta_f0_2;
286 delta_f0_2 <= reg_wp.delta_f0_2;
287 delta_f1 <= reg_wp.delta_f1;
287 delta_f1 <= reg_wp.delta_f1;
288 delta_f2 <= reg_wp.delta_f2;
288 delta_f2 <= reg_wp.delta_f2;
289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
289 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
290 nb_snapshot_param <= reg_wp.nb_snapshot_param;
291
291
292 enable_f0 <= reg_wp.enable_f0;
292 enable_f0 <= reg_wp.enable_f0;
293 enable_f1 <= reg_wp.enable_f1;
293 enable_f1 <= reg_wp.enable_f1;
294 enable_f2 <= reg_wp.enable_f2;
294 enable_f2 <= reg_wp.enable_f2;
295 enable_f3 <= reg_wp.enable_f3;
295 enable_f3 <= reg_wp.enable_f3;
296
296
297 burst_f0 <= reg_wp.burst_f0;
297 burst_f0 <= reg_wp.burst_f0;
298 burst_f1 <= reg_wp.burst_f1;
298 burst_f1 <= reg_wp.burst_f1;
299 burst_f2 <= reg_wp.burst_f2;
299 burst_f2 <= reg_wp.burst_f2;
300
300
301 run <= reg_wp.run;
301 run <= reg_wp.run;
302
302
303 --addr_data_f0 <= reg_wp.addr_data_f0;
303 --addr_data_f0 <= reg_wp.addr_data_f0;
304 --addr_data_f1 <= reg_wp.addr_data_f1;
304 --addr_data_f1 <= reg_wp.addr_data_f1;
305 --addr_data_f2 <= reg_wp.addr_data_f2;
305 --addr_data_f2 <= reg_wp.addr_data_f2;
306 --addr_data_f3 <= reg_wp.addr_data_f3;
306 --addr_data_f3 <= reg_wp.addr_data_f3;
307
307
308 start_date <= reg_wp.start_date;
308 start_date <= reg_wp.start_date;
309
309
310 length_matrix_f0 <= reg_sp.length_matrix;
310 length_matrix_f0 <= reg_sp.length_matrix;
311 length_matrix_f1 <= reg_sp.length_matrix;
311 length_matrix_f1 <= reg_sp.length_matrix;
312 length_matrix_f2 <= reg_sp.length_matrix;
312 length_matrix_f2 <= reg_sp.length_matrix;
313 wfp_length_buffer <= reg_wp.length_buffer;
313 wfp_length_buffer <= reg_wp.length_buffer;
314
314
315
315
316 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
316 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
317 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
317 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
318 BEGIN -- PROCESS lpp_dma_top
318 BEGIN -- PROCESS lpp_dma_top
319 IF HRESETn = '0' THEN -- asynchronous reset (active low)
319 IF HRESETn = '0' THEN -- asynchronous reset (active low)
320 reg_sp.config_active_interruption_onNewMatrix <= '0';
320 reg_sp.config_active_interruption_onNewMatrix <= '0';
321 reg_sp.config_active_interruption_onError <= '0';
321 reg_sp.config_active_interruption_onError <= '0';
322 reg_sp.config_ms_run <= '0';
322 reg_sp.config_ms_run <= '0';
323 reg_sp.status_ready_matrix_f0_0 <= '0';
323 reg_sp.status_ready_matrix_f0_0 <= '0';
324 reg_sp.status_ready_matrix_f1_0 <= '0';
324 reg_sp.status_ready_matrix_f1_0 <= '0';
325 reg_sp.status_ready_matrix_f2_0 <= '0';
325 reg_sp.status_ready_matrix_f2_0 <= '0';
326 reg_sp.status_ready_matrix_f0_1 <= '0';
326 reg_sp.status_ready_matrix_f0_1 <= '0';
327 reg_sp.status_ready_matrix_f1_1 <= '0';
327 reg_sp.status_ready_matrix_f1_1 <= '0';
328 reg_sp.status_ready_matrix_f2_1 <= '0';
328 reg_sp.status_ready_matrix_f2_1 <= '0';
329 reg_sp.status_error_buffer_full <= '0';
329 reg_sp.status_error_buffer_full <= '0';
330 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
330 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
331
331
332 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
332 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
333 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
333 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
334 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
334 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
335
335
336 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
336 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
337 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
337 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
338 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
338 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
339
339
340 reg_sp.length_matrix <= (OTHERS => '0');
340 reg_sp.length_matrix <= (OTHERS => '0');
341
341
342 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
342 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
343 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
343 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
344 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
344 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
345
345
346 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
346 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
347 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
347 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
348 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
348 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
349
349
350 prdata <= (OTHERS => '0');
350 prdata <= (OTHERS => '0');
351
351
352
352
353 apbo_irq_ms <= '0';
353 apbo_irq_ms <= '0';
354 apbo_irq_wfp <= '0';
354 apbo_irq_wfp <= '0';
355
355
356
356
357 -- status_full_ack <= (OTHERS => '0');
357 -- status_full_ack <= (OTHERS => '0');
358
358
359 reg_wp.data_shaping_BW <= '0';
359 reg_wp.data_shaping_BW <= '0';
360 reg_wp.data_shaping_SP0 <= '0';
360 reg_wp.data_shaping_SP0 <= '0';
361 reg_wp.data_shaping_SP1 <= '0';
361 reg_wp.data_shaping_SP1 <= '0';
362 reg_wp.data_shaping_R0 <= '0';
362 reg_wp.data_shaping_R0 <= '0';
363 reg_wp.data_shaping_R1 <= '0';
363 reg_wp.data_shaping_R1 <= '0';
364 reg_wp.data_shaping_R2 <= '0';
364 reg_wp.data_shaping_R2 <= '0';
365 reg_wp.enable_f0 <= '0';
365 reg_wp.enable_f0 <= '0';
366 reg_wp.enable_f1 <= '0';
366 reg_wp.enable_f1 <= '0';
367 reg_wp.enable_f2 <= '0';
367 reg_wp.enable_f2 <= '0';
368 reg_wp.enable_f3 <= '0';
368 reg_wp.enable_f3 <= '0';
369 reg_wp.burst_f0 <= '0';
369 reg_wp.burst_f0 <= '0';
370 reg_wp.burst_f1 <= '0';
370 reg_wp.burst_f1 <= '0';
371 reg_wp.burst_f2 <= '0';
371 reg_wp.burst_f2 <= '0';
372 reg_wp.run <= '0';
372 reg_wp.run <= '0';
373 -- reg_wp.status_full <= (OTHERS => '0');
373 -- reg_wp.status_full <= (OTHERS => '0');
374 -- reg_wp.status_full_err <= (OTHERS => '0');
374 -- reg_wp.status_full_err <= (OTHERS => '0');
375 reg_wp.status_new_err <= (OTHERS => '0');
375 reg_wp.status_new_err <= (OTHERS => '0');
376 reg_wp.error_buffer_full <= (OTHERS => '0');
376 reg_wp.error_buffer_full <= (OTHERS => '0');
377 reg_wp.delta_snapshot <= (OTHERS => '0');
377 reg_wp.delta_snapshot <= (OTHERS => '0');
378 reg_wp.delta_f0 <= (OTHERS => '0');
378 reg_wp.delta_f0 <= (OTHERS => '0');
379 reg_wp.delta_f0_2 <= (OTHERS => '0');
379 reg_wp.delta_f0_2 <= (OTHERS => '0');
380 reg_wp.delta_f1 <= (OTHERS => '0');
380 reg_wp.delta_f1 <= (OTHERS => '0');
381 reg_wp.delta_f2 <= (OTHERS => '0');
381 reg_wp.delta_f2 <= (OTHERS => '0');
382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
382 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
383 reg_wp.nb_snapshot_param <= (OTHERS => '0');
384 reg_wp.start_date <= (OTHERS => '0');
384 reg_wp.start_date <= (OTHERS => '1');
385
385
386 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
386 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
387 reg_wp.length_buffer <= (OTHERS => '0');
387 reg_wp.length_buffer <= (OTHERS => '0');
388 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
388 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
389
389
390 -- status_full_ack <= (OTHERS => '0');
390 -- status_full_ack <= (OTHERS => '0');
391
391
392 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
392 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
393 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
393 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
394 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
394 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
395
395
396 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
396 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
397 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
397 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
398 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
398 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
399
399
400 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
400 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
401 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
401 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
402 END LOOP all_status_ready_buffer_bit;
402 END LOOP all_status_ready_buffer_bit;
403
403
404
404
405 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
405 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
406 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
406 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
407 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
407 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
408 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
408 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
409
409
410
410
411
411
412 all_status : FOR I IN 3 DOWNTO 0 LOOP
412 all_status : FOR I IN 3 DOWNTO 0 LOOP
413 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
413 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
414 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
414 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
415 END LOOP all_status;
415 END LOOP all_status;
416
416
417 paddr := "000000";
417 paddr := "000000";
418 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
418 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
419 prdata <= (OTHERS => '0');
419 prdata <= (OTHERS => '0');
420 IF apbi.psel(pindex) = '1' THEN
420 IF apbi.psel(pindex) = '1' THEN
421 -- APB DMA READ --
421 -- APB DMA READ --
422 CASE paddr(7 DOWNTO 2) IS
422 CASE paddr(7 DOWNTO 2) IS
423 --0
423 --0
424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
425 prdata(1) <= reg_sp.config_active_interruption_onError;
425 prdata(1) <= reg_sp.config_active_interruption_onError;
426 prdata(2) <= reg_sp.config_ms_run;
426 prdata(2) <= reg_sp.config_ms_run;
427 --1
427 --1
428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
435 prdata(7) <= reg_sp.status_error_buffer_full;
435 prdata(7) <= reg_sp.status_error_buffer_full;
436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
439 --2
439 --2
440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
441 --3
441 --3
442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
443 --4
443 --4
444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
445 --5
445 --5
446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
447 --6
447 --6
448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
449 --7
449 --7
450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
451 --8
451 --8
452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
453 --9
453 --9
454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
455 --10
455 --10
456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
457 --11
457 --11
458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
459 --12
459 --12
460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
461 --13
461 --13
462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
463 --14
463 --14
464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
465 --15
465 --15
466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
467 --16
467 --16
468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
469 --17
469 --17
470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 --18
471 --18
472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
473 --19
473 --19
474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
475 --20
475 --20
476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
477 ---------------------------------------------------------------------
477 ---------------------------------------------------------------------
478 --20
478 --20
479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
480 prdata(1) <= reg_wp.data_shaping_SP0;
480 prdata(1) <= reg_wp.data_shaping_SP0;
481 prdata(2) <= reg_wp.data_shaping_SP1;
481 prdata(2) <= reg_wp.data_shaping_SP1;
482 prdata(3) <= reg_wp.data_shaping_R0;
482 prdata(3) <= reg_wp.data_shaping_R0;
483 prdata(4) <= reg_wp.data_shaping_R1;
483 prdata(4) <= reg_wp.data_shaping_R1;
484 prdata(5) <= reg_wp.data_shaping_R2;
484 prdata(5) <= reg_wp.data_shaping_R2;
485 --21
485 --21
486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
487 prdata(1) <= reg_wp.enable_f1;
487 prdata(1) <= reg_wp.enable_f1;
488 prdata(2) <= reg_wp.enable_f2;
488 prdata(2) <= reg_wp.enable_f2;
489 prdata(3) <= reg_wp.enable_f3;
489 prdata(3) <= reg_wp.enable_f3;
490 prdata(4) <= reg_wp.burst_f0;
490 prdata(4) <= reg_wp.burst_f0;
491 prdata(5) <= reg_wp.burst_f1;
491 prdata(5) <= reg_wp.burst_f1;
492 prdata(6) <= reg_wp.burst_f2;
492 prdata(6) <= reg_wp.burst_f2;
493 prdata(7) <= reg_wp.run;
493 prdata(7) <= reg_wp.run;
494 --22
494 --22
495 --ON GOING \/
495 --ON GOING \/
496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
504 --ON GOING /\
504 --ON GOING /\
505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
510 --27
510 --27
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
512 --28
512 --28
513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
514 --29
514 --29
515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
516 --30
516 --30
517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
518 --31
518 --31
519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
520 --32
520 --32
521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
522 --33
522 --33
523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
524 --34
524 --34
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
526 --35
526 --35
527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
531
531
532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
536
536
537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
541
541
542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
546
546
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
548
548
549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
550 ----------------------------------------------------
550 ----------------------------------------------------
551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
552 WHEN OTHERS => NULL;
552 WHEN OTHERS => NULL;
553
553
554 END CASE;
554 END CASE;
555 IF (apbi.pwrite AND apbi.penable) = '1' THEN
555 IF (apbi.pwrite AND apbi.penable) = '1' THEN
556 -- APB DMA WRITE --
556 -- APB DMA WRITE --
557 CASE paddr(7 DOWNTO 2) IS
557 CASE paddr(7 DOWNTO 2) IS
558 --
558 --
559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
561 reg_sp.config_ms_run <= apbi.pwdata(2);
561 reg_sp.config_ms_run <= apbi.pwdata(2);
562
562
563 WHEN "000001" =>
563 WHEN "000001" =>
564 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
564 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
565 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
565 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
566 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
566 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
567 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
567 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
568 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
568 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
569 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
569 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
570 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
570 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
571 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
571 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
572 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
572 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
573 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
573 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
574 --2
574 --2
575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
581 --8 to 19
581 --8 to 19
582 --20
582 --20
583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
584 --20
584 --20
585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
592 reg_wp.enable_f1 <= apbi.pwdata(1);
592 reg_wp.enable_f1 <= apbi.pwdata(1);
593 reg_wp.enable_f2 <= apbi.pwdata(2);
593 reg_wp.enable_f2 <= apbi.pwdata(2);
594 reg_wp.enable_f3 <= apbi.pwdata(3);
594 reg_wp.enable_f3 <= apbi.pwdata(3);
595 reg_wp.burst_f0 <= apbi.pwdata(4);
595 reg_wp.burst_f0 <= apbi.pwdata(4);
596 reg_wp.burst_f1 <= apbi.pwdata(5);
596 reg_wp.burst_f1 <= apbi.pwdata(5);
597 reg_wp.burst_f2 <= apbi.pwdata(6);
597 reg_wp.burst_f2 <= apbi.pwdata(6);
598 reg_wp.run <= apbi.pwdata(7);
598 reg_wp.run <= apbi.pwdata(7);
599 --22
599 --22
600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
608 --26
608 --26
609 WHEN "011111" =>
609 WHEN "011111" =>
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
613 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
615 END LOOP all_reg_wp_status_bit;
615 END LOOP all_reg_wp_status_bit;
616
616
617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
625
625
626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
627
627
628
628
629
629
630
630
631
631
632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
633 --
633 --
634 WHEN OTHERS => NULL;
634 WHEN OTHERS => NULL;
635 END CASE;
635 END CASE;
636 END IF;
636 END IF;
637 END IF;
637 END IF;
638 --apbo.pirq(pirq_ms) <=
638 --apbo.pirq(pirq_ms) <=
639 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
639 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
640 ready_matrix_f1 OR
640 ready_matrix_f1 OR
641 ready_matrix_f2)
641 ready_matrix_f2)
642 )
642 )
643 OR
643 OR
644 (reg_sp.config_active_interruption_onError AND (
644 (reg_sp.config_active_interruption_onError AND (
645 -- error_bad_component_error OR
645 -- error_bad_component_error OR
646 error_buffer_full
646 error_buffer_full
647 OR error_input_fifo_write(0)
647 OR error_input_fifo_write(0)
648 OR error_input_fifo_write(1)
648 OR error_input_fifo_write(1)
649 OR error_input_fifo_write(2))
649 OR error_input_fifo_write(2))
650 ));
650 ));
651 -- apbo.pirq(pirq_wfp)
651 -- apbo.pirq(pirq_wfp)
652 apbo_irq_wfp<= ored_irq_wfp;
652 apbo_irq_wfp<= ored_irq_wfp;
653
653
654 END IF;
654 END IF;
655 END PROCESS lpp_lfr_apbreg;
655 END PROCESS lpp_lfr_apbreg;
656
656
657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
659
659
660 apbo.pindex <= pindex;
660 apbo.pindex <= pindex;
661 apbo.pconfig <= pconfig;
661 apbo.pconfig <= pconfig;
662 apbo.prdata <= prdata;
662 apbo.prdata <= prdata;
663
663
664 -----------------------------------------------------------------------------
664 -----------------------------------------------------------------------------
665 -- IRQ
665 -- IRQ
666 -----------------------------------------------------------------------------
666 -----------------------------------------------------------------------------
667 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
667 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
668
668
669 PROCESS (HCLK, HRESETn)
669 PROCESS (HCLK, HRESETn)
670 BEGIN -- PROCESS
670 BEGIN -- PROCESS
671 IF HRESETn = '0' THEN -- asynchronous reset (active low)
671 IF HRESETn = '0' THEN -- asynchronous reset (active low)
672 irq_wfp_reg <= (OTHERS => '0');
672 irq_wfp_reg <= (OTHERS => '0');
673 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
673 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
674 irq_wfp_reg <= irq_wfp_reg_s;
674 irq_wfp_reg <= irq_wfp_reg_s;
675 END IF;
675 END IF;
676 END PROCESS;
676 END PROCESS;
677
677
678 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
678 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
679 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
679 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
680 END GENERATE all_irq_wfp;
680 END GENERATE all_irq_wfp;
681
681
682 irq_wfp_ZERO <= (OTHERS => '0');
682 irq_wfp_ZERO <= (OTHERS => '0');
683 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
683 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
684
684
685 run_ms <= reg_sp.config_ms_run;
685 run_ms <= reg_sp.config_ms_run;
686
686
687 -----------------------------------------------------------------------------
687 -----------------------------------------------------------------------------
688 --
688 --
689 -----------------------------------------------------------------------------
689 -----------------------------------------------------------------------------
690 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
690 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
691 PORT MAP (
691 PORT MAP (
692 clk => HCLK,
692 clk => HCLK,
693 rstn => HRESETn,
693 rstn => HRESETn,
694
694
695 run => reg_sp.config_ms_run,
695 run => '1',--reg_sp.config_ms_run,
696
696
697 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
697 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
698 reg0_ready_matrix => reg0_ready_matrix_f0,
698 reg0_ready_matrix => reg0_ready_matrix_f0,
699 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
699 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
700 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
700 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
701
701
702 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
702 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
703 reg1_ready_matrix => reg1_ready_matrix_f0,
703 reg1_ready_matrix => reg1_ready_matrix_f0,
704 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
704 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
705 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
705 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
706
706
707 ready_matrix => ready_matrix_f0,
707 ready_matrix => ready_matrix_f0,
708 status_ready_matrix => status_ready_matrix_f0,
708 status_ready_matrix => status_ready_matrix_f0,
709 addr_matrix => addr_matrix_f0,
709 addr_matrix => addr_matrix_f0,
710 matrix_time => matrix_time_f0);
710 matrix_time => matrix_time_f0);
711
711
712 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
712 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
713 PORT MAP (
713 PORT MAP (
714 clk => HCLK,
714 clk => HCLK,
715 rstn => HRESETn,
715 rstn => HRESETn,
716
716
717 run => reg_sp.config_ms_run,
717 run => '1',--reg_sp.config_ms_run,
718
718
719 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
719 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
720 reg0_ready_matrix => reg0_ready_matrix_f1,
720 reg0_ready_matrix => reg0_ready_matrix_f1,
721 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
721 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
722 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
722 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
723
723
724 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
724 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
725 reg1_ready_matrix => reg1_ready_matrix_f1,
725 reg1_ready_matrix => reg1_ready_matrix_f1,
726 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
726 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
727 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
727 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
728
728
729 ready_matrix => ready_matrix_f1,
729 ready_matrix => ready_matrix_f1,
730 status_ready_matrix => status_ready_matrix_f1,
730 status_ready_matrix => status_ready_matrix_f1,
731 addr_matrix => addr_matrix_f1,
731 addr_matrix => addr_matrix_f1,
732 matrix_time => matrix_time_f1);
732 matrix_time => matrix_time_f1);
733
733
734 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
734 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
735 PORT MAP (
735 PORT MAP (
736 clk => HCLK,
736 clk => HCLK,
737 rstn => HRESETn,
737 rstn => HRESETn,
738
738
739 run => reg_sp.config_ms_run,
739 run => '1',--reg_sp.config_ms_run,
740
740
741 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
741 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
742 reg0_ready_matrix => reg0_ready_matrix_f2,
742 reg0_ready_matrix => reg0_ready_matrix_f2,
743 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
743 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
744 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
744 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
745
745
746 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
746 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
747 reg1_ready_matrix => reg1_ready_matrix_f2,
747 reg1_ready_matrix => reg1_ready_matrix_f2,
748 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
748 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
749 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
749 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
750
750
751 ready_matrix => ready_matrix_f2,
751 ready_matrix => ready_matrix_f2,
752 status_ready_matrix => status_ready_matrix_f2,
752 status_ready_matrix => status_ready_matrix_f2,
753 addr_matrix => addr_matrix_f2,
753 addr_matrix => addr_matrix_f2,
754 matrix_time => matrix_time_f2);
754 matrix_time => matrix_time_f2);
755
755
756 -----------------------------------------------------------------------------
756 -----------------------------------------------------------------------------
757 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
757 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
758 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
758 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
759 PORT MAP (
759 PORT MAP (
760 clk => HCLK,
760 clk => HCLK,
761 rstn => HRESETn,
761 rstn => HRESETn,
762
762
763 run => reg_wp.run,
763 run => '1',--reg_wp.run,
764
764
765 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
765 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
766 reg0_ready_matrix => reg_ready_buffer_f(2*I),
766 reg0_ready_matrix => reg_ready_buffer_f(2*I),
767 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
767 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
768 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
768 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
769
769
770 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
770 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
771 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
771 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
772 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
772 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
773 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
773 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
774
774
775 ready_matrix => wfp_ready_buffer(I),
775 ready_matrix => wfp_ready_buffer(I),
776 status_ready_matrix => wfp_status_buffer_ready(I),
776 status_ready_matrix => wfp_status_buffer_ready(I),
777 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
777 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
778 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
778 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
779 );
779 );
780
780
781 END GENERATE all_wfp_pointer;
781 END GENERATE all_wfp_pointer;
782 -----------------------------------------------------------------------------
782 -----------------------------------------------------------------------------
783
783
784 END beh;
784 END beh;
Show file before | Show file after | Hide comments
@@ -1,1144 +1,1174
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3
4
4
5
5 LIBRARY lpp;
6 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16 USE lpp.fft_components.ALL;
16
17
17 ENTITY lpp_lfr_ms IS
18 ENTITY lpp_lfr_ms IS
18 GENERIC (
19 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 Mem_use : INTEGER := use_RAM
20 );
21 );
21 PORT (
22 PORT (
22 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 run : IN STD_LOGIC;
25 run : IN STD_LOGIC;
25
26
26 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
27 -- DATA INPUT
28 -- DATA INPUT
28 ---------------------------------------------------------------------------
29 ---------------------------------------------------------------------------
30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
29 -- TIME
31 -- TIME
30 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
32 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
31 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
32 --
34 --
33 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
37 --
36 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 --
40 --
39 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
41
43
42 ---------------------------------------------------------------------------
44 ---------------------------------------------------------------------------
43 -- DMA
45 -- DMA
44 ---------------------------------------------------------------------------
46 ---------------------------------------------------------------------------
45 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
47 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
46 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
48 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
47 dma_fifo_ren : IN STD_LOGIC; --TODO
49 dma_fifo_ren : IN STD_LOGIC; --TODO
48 dma_buffer_new : OUT STD_LOGIC; --TODOx
50 dma_buffer_new : OUT STD_LOGIC; --TODOx
49 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
50 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
52 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
51 dma_buffer_full : IN STD_LOGIC; --TODO
53 dma_buffer_full : IN STD_LOGIC; --TODO
52 dma_buffer_full_err : IN STD_LOGIC; --TODO
54 dma_buffer_full_err : IN STD_LOGIC; --TODO
53
55
54 -- Reg out
56 -- Reg out
55 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
57 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
56 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
58 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
57 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
59 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
58 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
60 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
59 error_buffer_full : OUT STD_LOGIC; -- TODO
61 error_buffer_full : OUT STD_LOGIC; -- TODO
60 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
62 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
61
63
62 -- Reg In
64 -- Reg In
63 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
65 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
64 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
66 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
65 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
67 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
66
68
67 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
69 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
68 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
69 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
71 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
70
72
71 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
73 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
72 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
73 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
75 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
74
76
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
77 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
78 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
79 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
78
80
79 );
81 );
80 END;
82 END;
81
83
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
84 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83
85
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89
91
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
97
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
102
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
104
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
105 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
109
108 SIGNAL error_wen_f0 : STD_LOGIC;
110 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
111 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
112 SIGNAL error_wen_f2 : STD_LOGIC;
111
113
112 SIGNAL one_sample_f1_full : STD_LOGIC;
114 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
115 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
116 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
117 SIGNAL one_sample_f2_wen : STD_LOGIC;
116
118
117 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
118 -- FSM / SWITCH SELECT CHANNEL
120 -- FSM / SWITCH SELECT CHANNEL
119 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
122 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
123 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
124 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123
125
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
126 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
129 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128
130
129 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
130 -- FSM LOAD FFT
132 -- FSM LOAD FFT
131 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
134 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
135 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
136 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135
137
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
138 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_load : STD_LOGIC;
139 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
140 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
141 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
142 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141
143
142
144
143 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
144 -- FFT
146 -- FFT
145 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
146 SIGNAL fft_read : STD_LOGIC;
148 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
149 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_valid : STD_LOGIC;
152 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
153 SIGNAL fft_ready : STD_LOGIC;
152 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
157 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
158 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL current_fifo_empty : STD_LOGIC;
160 SIGNAL current_fifo_empty : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
161 SIGNAL current_fifo_locked : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
162 SIGNAL current_fifo_full : STD_LOGIC;
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162
164
163 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
171 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
175 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
177 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176
178
177 SIGNAL SM_correlation_start : STD_LOGIC;
179 SIGNAL SM_correlation_start : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
180 SIGNAL SM_correlation_auto : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
181 SIGNAL SM_correlation_done : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
183 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
184 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
185 SIGNAL SM_correlation_begin : STD_LOGIC;
184
186
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
189 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188
190
189 SIGNAL current_matrix_write : STD_LOGIC;
191 SIGNAL current_matrix_write : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
192 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
192 SIGNAL fifo_0_ready : STD_LOGIC;
194 SIGNAL fifo_0_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
195 SIGNAL fifo_1_ready : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
196 SIGNAL fifo_ongoing : STD_LOGIC;
195
197
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
199 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
200 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
199 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
202 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
201 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
202 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
207 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
208 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
209 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
208 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
210 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
209
211
210 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
211 -- TIME REG & INFOs
213 -- TIME REG & INFOs
212 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
213 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
215 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
214
216
215 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
219 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
220 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
219
221
220 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
223 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
224 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
223 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
225 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
224
226
225 --SIGNAL time_update_f0_A : STD_LOGIC;
227 --SIGNAL time_update_f0_A : STD_LOGIC;
226 --SIGNAL time_update_f0_B : STD_LOGIC;
228 --SIGNAL time_update_f0_B : STD_LOGIC;
227 --SIGNAL time_update_f1 : STD_LOGIC;
229 --SIGNAL time_update_f1 : STD_LOGIC;
228 --SIGNAL time_update_f2 : STD_LOGIC;
230 --SIGNAL time_update_f2 : STD_LOGIC;
229 --
231 --
230 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
232 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
231 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
233 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
232 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
233
235
234 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
236 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
235 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
237 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
236 SIGNAL status_component_fifo_0_end : STD_LOGIC;
238 SIGNAL status_component_fifo_0_end : STD_LOGIC;
237 SIGNAL status_component_fifo_1_end : STD_LOGIC;
239 SIGNAL status_component_fifo_1_end : STD_LOGIC;
238 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
239 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
241 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
240
242
241 SIGNAL fft_ready_reg : STD_LOGIC;
243 SIGNAL fft_ready_reg : STD_LOGIC;
242 SIGNAL fft_ready_rising_down : STD_LOGIC;
244 SIGNAL fft_ready_rising_down : STD_LOGIC;
243
245
244 SIGNAL sample_load_reg : STD_LOGIC;
246 SIGNAL sample_load_reg : STD_LOGIC;
245 SIGNAL sample_load_rising_down : STD_LOGIC;
247 SIGNAL sample_load_rising_down : STD_LOGIC;
246
248
247 -----------------------------------------------------------------------------
249 -----------------------------------------------------------------------------
248 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
250 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
249 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
251 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
250 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
252 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
251 SIGNAL sample_f1_full_head_in : STD_LOGIC;
253 SIGNAL sample_f1_full_head_in : STD_LOGIC;
252 SIGNAL sample_f1_full_head_out : STD_LOGIC;
254 SIGNAL sample_f1_full_head_out : STD_LOGIC;
253 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
255 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
254
256
255 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
257 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
258 -----------------------------------------------------------------------------
259 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
260 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
261 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
262 SIGNAL ongoing : STD_LOGIC;
256
263
257 BEGIN
264 BEGIN
258
265
266 PROCESS (clk, rstn)
267 BEGIN -- PROCESS
268 IF rstn = '0' THEN -- asynchronous reset (active low)
269 sample_f0_wen_s <= (OTHERS => '1');
270 sample_f1_wen_s <= (OTHERS => '1');
271 sample_f2_wen_s <= (OTHERS => '1');
272 ongoing <= '0';
273 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
274 IF ongoing = '1' THEN
275 sample_f0_wen_s <= sample_f0_wen;
276 sample_f1_wen_s <= sample_f1_wen;
277 sample_f2_wen_s <= sample_f2_wen;
278 ELSE
279 IF start_date = coarse_time(30 DOWNTO 0) THEN
280 ongoing <= '1';
281 END IF;
282 sample_f0_wen_s <= (OTHERS => '1');
283 sample_f1_wen_s <= (OTHERS => '1');
284 sample_f2_wen_s <= (OTHERS => '1');
285 END IF;
286 END IF;
287 END PROCESS;
288
259
289
260 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
290 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
261
291
262
292
263 switch_f0_inst : spectral_matrix_switch_f0
293 switch_f0_inst : spectral_matrix_switch_f0
264 PORT MAP (
294 PORT MAP (
265 clk => clk,
295 clk => clk,
266 rstn => rstn,
296 rstn => rstn,
267
297
268 sample_wen => sample_f0_wen,
298 sample_wen => sample_f0_wen_s,
269
299
270 fifo_A_empty => sample_f0_A_empty,
300 fifo_A_empty => sample_f0_A_empty,
271 fifo_A_full => sample_f0_A_full,
301 fifo_A_full => sample_f0_A_full,
272 fifo_A_wen => sample_f0_A_wen,
302 fifo_A_wen => sample_f0_A_wen,
273
303
274 fifo_B_empty => sample_f0_B_empty,
304 fifo_B_empty => sample_f0_B_empty,
275 fifo_B_full => sample_f0_B_full,
305 fifo_B_full => sample_f0_B_full,
276 fifo_B_wen => sample_f0_B_wen,
306 fifo_B_wen => sample_f0_B_wen,
277
307
278 error_wen => error_wen_f0); -- TODO
308 error_wen => error_wen_f0); -- TODO
279
309
280 -----------------------------------------------------------------------------
310 -----------------------------------------------------------------------------
281 -- FIFO IN
311 -- FIFO IN
282 -----------------------------------------------------------------------------
312 -----------------------------------------------------------------------------
283 lppFIFOxN_f0_a : lppFIFOxN
313 lppFIFOxN_f0_a : lppFIFOxN
284 GENERIC MAP (
314 GENERIC MAP (
285 tech => 0,
315 tech => 0,
286 Mem_use => Mem_use,
316 Mem_use => Mem_use,
287 Data_sz => 16,
317 Data_sz => 16,
288 Addr_sz => 8,
318 Addr_sz => 8,
289 FifoCnt => 5)
319 FifoCnt => 5)
290 PORT MAP (
320 PORT MAP (
291 clk => clk,
321 clk => clk,
292 rstn => rstn,
322 rstn => rstn,
293
323
294 ReUse => (OTHERS => '0'),
324 ReUse => (OTHERS => '0'),
295
325
296 run => (OTHERS => '1'),
326 run => (OTHERS => '1'),
297
327
298 wen => sample_f0_A_wen,
328 wen => sample_f0_A_wen,
299 wdata => sample_f0_wdata,
329 wdata => sample_f0_wdata,
300
330
301 ren => sample_f0_A_ren,
331 ren => sample_f0_A_ren,
302 rdata => sample_f0_A_rdata,
332 rdata => sample_f0_A_rdata,
303
333
304 empty => sample_f0_A_empty,
334 empty => sample_f0_A_empty,
305 full => sample_f0_A_full,
335 full => sample_f0_A_full,
306 almost_full => OPEN);
336 almost_full => OPEN);
307
337
308 lppFIFOxN_f0_b : lppFIFOxN
338 lppFIFOxN_f0_b : lppFIFOxN
309 GENERIC MAP (
339 GENERIC MAP (
310 tech => 0,
340 tech => 0,
311 Mem_use => Mem_use,
341 Mem_use => Mem_use,
312 Data_sz => 16,
342 Data_sz => 16,
313 Addr_sz => 8,
343 Addr_sz => 8,
314 FifoCnt => 5)
344 FifoCnt => 5)
315 PORT MAP (
345 PORT MAP (
316 clk => clk,
346 clk => clk,
317 rstn => rstn,
347 rstn => rstn,
318
348
319 ReUse => (OTHERS => '0'),
349 ReUse => (OTHERS => '0'),
320 run => (OTHERS => '1'),
350 run => (OTHERS => '1'),
321
351
322 wen => sample_f0_B_wen,
352 wen => sample_f0_B_wen,
323 wdata => sample_f0_wdata,
353 wdata => sample_f0_wdata,
324 ren => sample_f0_B_ren,
354 ren => sample_f0_B_ren,
325 rdata => sample_f0_B_rdata,
355 rdata => sample_f0_B_rdata,
326 empty => sample_f0_B_empty,
356 empty => sample_f0_B_empty,
327 full => sample_f0_B_full,
357 full => sample_f0_B_full,
328 almost_full => OPEN);
358 almost_full => OPEN);
329
359
330 -----------------------------------------------------------------------------
360 -----------------------------------------------------------------------------
331 -- sample_f1_wen in
361 -- sample_f1_wen in
332 -- sample_f1_wdata in
362 -- sample_f1_wdata in
333 -- sample_f1_full OUT
363 -- sample_f1_full OUT
334
364
335 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
365 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
336 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
366 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
337 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
367 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
338
368
339 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
369 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
340 PORT MAP (
370 PORT MAP (
341 clk => clk,
371 clk => clk,
342 rstn => rstn,
372 rstn => rstn,
343 in_wen => sample_f1_wen_head_in,
373 in_wen => sample_f1_wen_head_in,
344 in_data => sample_f1_wdata,
374 in_data => sample_f1_wdata,
345 in_full => sample_f1_full_head_in,
375 in_full => sample_f1_full_head_in,
346 in_empty => sample_f1_empty_head_in,
376 in_empty => sample_f1_empty_head_in,
347 out_wen => sample_f1_wen_head_out,
377 out_wen => sample_f1_wen_head_out,
348 out_data => sample_f1_wdata_head,
378 out_data => sample_f1_wdata_head,
349 out_full => sample_f1_full_head_out);
379 out_full => sample_f1_full_head_out);
350
380
351 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
381 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
352
382
353
383
354 lppFIFOxN_f1 : lppFIFOxN
384 lppFIFOxN_f1 : lppFIFOxN
355 GENERIC MAP (
385 GENERIC MAP (
356 tech => 0,
386 tech => 0,
357 Mem_use => Mem_use,
387 Mem_use => Mem_use,
358 Data_sz => 16,
388 Data_sz => 16,
359 Addr_sz => 8,
389 Addr_sz => 8,
360 FifoCnt => 5)
390 FifoCnt => 5)
361 PORT MAP (
391 PORT MAP (
362 clk => clk,
392 clk => clk,
363 rstn => rstn,
393 rstn => rstn,
364
394
365 ReUse => (OTHERS => '0'),
395 ReUse => (OTHERS => '0'),
366 run => (OTHERS => '1'),
396 run => (OTHERS => '1'),
367
397
368 wen => sample_f1_wen_head,
398 wen => sample_f1_wen_head,
369 wdata => sample_f1_wdata_head,
399 wdata => sample_f1_wdata_head,
370 ren => sample_f1_ren,
400 ren => sample_f1_ren,
371 rdata => sample_f1_rdata,
401 rdata => sample_f1_rdata,
372 empty => sample_f1_empty,
402 empty => sample_f1_empty,
373 full => sample_f1_full,
403 full => sample_f1_full,
374 almost_full => sample_f1_almost_full);
404 almost_full => sample_f1_almost_full);
375
405
376
406
377 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
407 one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
378
408
379 PROCESS (clk, rstn)
409 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
410 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
411 IF rstn = '0' THEN -- asynchronous reset (active low)
382 one_sample_f1_full <= '0';
412 one_sample_f1_full <= '0';
383 error_wen_f1 <= '0';
413 error_wen_f1 <= '0';
384 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
414 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
385 IF sample_f1_full_head_out = '0' THEN
415 IF sample_f1_full_head_out = '0' THEN
386 one_sample_f1_full <= '0';
416 one_sample_f1_full <= '0';
387 ELSE
417 ELSE
388 one_sample_f1_full <= '1';
418 one_sample_f1_full <= '1';
389 END IF;
419 END IF;
390 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
420 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
391 END IF;
421 END IF;
392 END PROCESS;
422 END PROCESS;
393
423
394 -----------------------------------------------------------------------------
424 -----------------------------------------------------------------------------
395
425
396
426
397 lppFIFOxN_f2 : lppFIFOxN
427 lppFIFOxN_f2 : lppFIFOxN
398 GENERIC MAP (
428 GENERIC MAP (
399 tech => 0,
429 tech => 0,
400 Mem_use => Mem_use,
430 Mem_use => Mem_use,
401 Data_sz => 16,
431 Data_sz => 16,
402 Addr_sz => 8,
432 Addr_sz => 8,
403 FifoCnt => 5)
433 FifoCnt => 5)
404 PORT MAP (
434 PORT MAP (
405 clk => clk,
435 clk => clk,
406 rstn => rstn,
436 rstn => rstn,
407
437
408 ReUse => (OTHERS => '0'),
438 ReUse => (OTHERS => '0'),
409 run => (OTHERS => '1'),
439 run => (OTHERS => '1'),
410
440
411 wen => sample_f2_wen,
441 wen => sample_f2_wen,
412 wdata => sample_f2_wdata,
442 wdata => sample_f2_wdata,
413 ren => sample_f2_ren,
443 ren => sample_f2_ren,
414 rdata => sample_f2_rdata,
444 rdata => sample_f2_rdata,
415 empty => sample_f2_empty,
445 empty => sample_f2_empty,
416 full => sample_f2_full,
446 full => sample_f2_full,
417 almost_full => OPEN);
447 almost_full => OPEN);
418
448
419
449
420 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
450 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
421
451
422 PROCESS (clk, rstn)
452 PROCESS (clk, rstn)
423 BEGIN -- PROCESS
453 BEGIN -- PROCESS
424 IF rstn = '0' THEN -- asynchronous reset (active low)
454 IF rstn = '0' THEN -- asynchronous reset (active low)
425 one_sample_f2_full <= '0';
455 one_sample_f2_full <= '0';
426 error_wen_f2 <= '0';
456 error_wen_f2 <= '0';
427 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
457 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
428 IF sample_f2_full = "00000" THEN
458 IF sample_f2_full = "00000" THEN
429 one_sample_f2_full <= '0';
459 one_sample_f2_full <= '0';
430 ELSE
460 ELSE
431 one_sample_f2_full <= '1';
461 one_sample_f2_full <= '1';
432 END IF;
462 END IF;
433 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
463 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
434 END IF;
464 END IF;
435 END PROCESS;
465 END PROCESS;
436
466
437 -----------------------------------------------------------------------------
467 -----------------------------------------------------------------------------
438 -- FSM SELECT CHANNEL
468 -- FSM SELECT CHANNEL
439 -----------------------------------------------------------------------------
469 -----------------------------------------------------------------------------
440 PROCESS (clk, rstn)
470 PROCESS (clk, rstn)
441 BEGIN
471 BEGIN
442 IF rstn = '0' THEN
472 IF rstn = '0' THEN
443 state_fsm_select_channel <= IDLE;
473 state_fsm_select_channel <= IDLE;
444 ELSIF clk'EVENT AND clk = '1' THEN
474 ELSIF clk'EVENT AND clk = '1' THEN
445 CASE state_fsm_select_channel IS
475 CASE state_fsm_select_channel IS
446 WHEN IDLE =>
476 WHEN IDLE =>
447 IF sample_f1_full = "11111" THEN
477 IF sample_f1_full = "11111" THEN
448 state_fsm_select_channel <= SWITCH_F1;
478 state_fsm_select_channel <= SWITCH_F1;
449 ELSIF sample_f1_almost_full = "00000" THEN
479 ELSIF sample_f1_almost_full = "00000" THEN
450 IF sample_f0_A_full = "11111" THEN
480 IF sample_f0_A_full = "11111" THEN
451 state_fsm_select_channel <= SWITCH_F0_A;
481 state_fsm_select_channel <= SWITCH_F0_A;
452 ELSIF sample_f0_B_full = "11111" THEN
482 ELSIF sample_f0_B_full = "11111" THEN
453 state_fsm_select_channel <= SWITCH_F0_B;
483 state_fsm_select_channel <= SWITCH_F0_B;
454 ELSIF sample_f2_full = "11111" THEN
484 ELSIF sample_f2_full = "11111" THEN
455 state_fsm_select_channel <= SWITCH_F2;
485 state_fsm_select_channel <= SWITCH_F2;
456 END IF;
486 END IF;
457 END IF;
487 END IF;
458
488
459 WHEN SWITCH_F0_A =>
489 WHEN SWITCH_F0_A =>
460 IF sample_f0_A_empty = "11111" THEN
490 IF sample_f0_A_empty = "11111" THEN
461 state_fsm_select_channel <= IDLE;
491 state_fsm_select_channel <= IDLE;
462 END IF;
492 END IF;
463 WHEN SWITCH_F0_B =>
493 WHEN SWITCH_F0_B =>
464 IF sample_f0_B_empty = "11111" THEN
494 IF sample_f0_B_empty = "11111" THEN
465 state_fsm_select_channel <= IDLE;
495 state_fsm_select_channel <= IDLE;
466 END IF;
496 END IF;
467 WHEN SWITCH_F1 =>
497 WHEN SWITCH_F1 =>
468 IF sample_f1_empty = "11111" THEN
498 IF sample_f1_empty = "11111" THEN
469 state_fsm_select_channel <= IDLE;
499 state_fsm_select_channel <= IDLE;
470 END IF;
500 END IF;
471 WHEN SWITCH_F2 =>
501 WHEN SWITCH_F2 =>
472 IF sample_f2_empty = "11111" THEN
502 IF sample_f2_empty = "11111" THEN
473 state_fsm_select_channel <= IDLE;
503 state_fsm_select_channel <= IDLE;
474 END IF;
504 END IF;
475 WHEN OTHERS => NULL;
505 WHEN OTHERS => NULL;
476 END CASE;
506 END CASE;
477
507
478 END IF;
508 END IF;
479 END PROCESS;
509 END PROCESS;
480
510
481 PROCESS (clk, rstn)
511 PROCESS (clk, rstn)
482 BEGIN
512 BEGIN
483 IF rstn = '0' THEN
513 IF rstn = '0' THEN
484 pre_state_fsm_select_channel <= IDLE;
514 pre_state_fsm_select_channel <= IDLE;
485 ELSIF clk'EVENT AND clk = '1' THEN
515 ELSIF clk'EVENT AND clk = '1' THEN
486 pre_state_fsm_select_channel <= state_fsm_select_channel;
516 pre_state_fsm_select_channel <= state_fsm_select_channel;
487 END IF;
517 END IF;
488 END PROCESS;
518 END PROCESS;
489
519
490
520
491 -----------------------------------------------------------------------------
521 -----------------------------------------------------------------------------
492 -- SWITCH SELECT CHANNEL
522 -- SWITCH SELECT CHANNEL
493 -----------------------------------------------------------------------------
523 -----------------------------------------------------------------------------
494 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
524 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
495 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
525 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
496 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
526 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
497 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
527 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
498 (OTHERS => '1');
528 (OTHERS => '1');
499
529
500 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
530 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
501 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
531 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
502 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
532 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
503 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
533 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
504 (OTHERS => '0');
534 (OTHERS => '0');
505
535
506 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
536 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
507 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
537 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
508 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
538 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
509 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
539 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
510
540
511
541
512 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
542 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
513 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
543 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
514 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
544 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
515 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
545 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
516
546
517
547
518 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
548 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
519 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
549 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
520 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
550 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
521 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
551 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
522
552
523 -----------------------------------------------------------------------------
553 -----------------------------------------------------------------------------
524 -- FSM LOAD FFT
554 -- FSM LOAD FFT
525 -----------------------------------------------------------------------------
555 -----------------------------------------------------------------------------
526
556
527 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
557 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
528 sample_ren_s WHEN sample_load = '1' ELSE
558 sample_ren_s WHEN sample_load = '1' ELSE
529 (OTHERS => '1');
559 (OTHERS => '1');
530
560
531 PROCESS (clk, rstn)
561 PROCESS (clk, rstn)
532 BEGIN
562 BEGIN
533 IF rstn = '0' THEN
563 IF rstn = '0' THEN
534 sample_ren_s <= (OTHERS => '1');
564 sample_ren_s <= (OTHERS => '1');
535 state_fsm_load_FFT <= IDLE;
565 state_fsm_load_FFT <= IDLE;
536 status_MS_input <= (OTHERS => '0');
566 status_MS_input <= (OTHERS => '0');
537 --next_state_fsm_load_FFT <= IDLE;
567 --next_state_fsm_load_FFT <= IDLE;
538 --sample_valid <= '0';
568 --sample_valid <= '0';
539 ELSIF clk'EVENT AND clk = '1' THEN
569 ELSIF clk'EVENT AND clk = '1' THEN
540 CASE state_fsm_load_FFT IS
570 CASE state_fsm_load_FFT IS
541 WHEN IDLE =>
571 WHEN IDLE =>
542 --sample_valid <= '0';
572 --sample_valid <= '0';
543 sample_ren_s <= (OTHERS => '1');
573 sample_ren_s <= (OTHERS => '1');
544 IF sample_full = "11111" AND sample_load = '1' THEN
574 IF sample_full = "11111" AND sample_load = '1' THEN
545 state_fsm_load_FFT <= FIFO_1;
575 state_fsm_load_FFT <= FIFO_1;
546 status_MS_input <= status_channel;
576 status_MS_input <= status_channel;
547 END IF;
577 END IF;
548
578
549 WHEN FIFO_1 =>
579 WHEN FIFO_1 =>
550 sample_ren_s <= "1111" & NOT(sample_load);
580 sample_ren_s <= "1111" & NOT(sample_load);
551 IF sample_empty(0) = '1' THEN
581 IF sample_empty(0) = '1' THEN
552 sample_ren_s <= (OTHERS => '1');
582 sample_ren_s <= (OTHERS => '1');
553 state_fsm_load_FFT <= FIFO_2;
583 state_fsm_load_FFT <= FIFO_2;
554 END IF;
584 END IF;
555
585
556 WHEN FIFO_2 =>
586 WHEN FIFO_2 =>
557 sample_ren_s <= "111" & NOT(sample_load) & '1';
587 sample_ren_s <= "111" & NOT(sample_load) & '1';
558 IF sample_empty(1) = '1' THEN
588 IF sample_empty(1) = '1' THEN
559 sample_ren_s <= (OTHERS => '1');
589 sample_ren_s <= (OTHERS => '1');
560 state_fsm_load_FFT <= FIFO_3;
590 state_fsm_load_FFT <= FIFO_3;
561 END IF;
591 END IF;
562
592
563 WHEN FIFO_3 =>
593 WHEN FIFO_3 =>
564 sample_ren_s <= "11" & NOT(sample_load) & "11";
594 sample_ren_s <= "11" & NOT(sample_load) & "11";
565 IF sample_empty(2) = '1' THEN
595 IF sample_empty(2) = '1' THEN
566 sample_ren_s <= (OTHERS => '1');
596 sample_ren_s <= (OTHERS => '1');
567 state_fsm_load_FFT <= FIFO_4;
597 state_fsm_load_FFT <= FIFO_4;
568 END IF;
598 END IF;
569
599
570 WHEN FIFO_4 =>
600 WHEN FIFO_4 =>
571 sample_ren_s <= '1' & NOT(sample_load) & "111";
601 sample_ren_s <= '1' & NOT(sample_load) & "111";
572 IF sample_empty(3) = '1' THEN
602 IF sample_empty(3) = '1' THEN
573 sample_ren_s <= (OTHERS => '1');
603 sample_ren_s <= (OTHERS => '1');
574 state_fsm_load_FFT <= FIFO_5;
604 state_fsm_load_FFT <= FIFO_5;
575 END IF;
605 END IF;
576
606
577 WHEN FIFO_5 =>
607 WHEN FIFO_5 =>
578 sample_ren_s <= NOT(sample_load) & "1111";
608 sample_ren_s <= NOT(sample_load) & "1111";
579 IF sample_empty(4) = '1' THEN
609 IF sample_empty(4) = '1' THEN
580 sample_ren_s <= (OTHERS => '1');
610 sample_ren_s <= (OTHERS => '1');
581 state_fsm_load_FFT <= IDLE;
611 state_fsm_load_FFT <= IDLE;
582 END IF;
612 END IF;
583 WHEN OTHERS => NULL;
613 WHEN OTHERS => NULL;
584 END CASE;
614 END CASE;
585 END IF;
615 END IF;
586 END PROCESS;
616 END PROCESS;
587
617
588 PROCESS (clk, rstn)
618 PROCESS (clk, rstn)
589 BEGIN
619 BEGIN
590 IF rstn = '0' THEN
620 IF rstn = '0' THEN
591 sample_valid_r <= '0';
621 sample_valid_r <= '0';
592 next_state_fsm_load_FFT <= IDLE;
622 next_state_fsm_load_FFT <= IDLE;
593 ELSIF clk'EVENT AND clk = '1' THEN
623 ELSIF clk'EVENT AND clk = '1' THEN
594 next_state_fsm_load_FFT <= state_fsm_load_FFT;
624 next_state_fsm_load_FFT <= state_fsm_load_FFT;
595 IF sample_ren_s = "11111" THEN
625 IF sample_ren_s = "11111" THEN
596 sample_valid_r <= '0';
626 sample_valid_r <= '0';
597 ELSE
627 ELSE
598 sample_valid_r <= '1';
628 sample_valid_r <= '1';
599 END IF;
629 END IF;
600 END IF;
630 END IF;
601 END PROCESS;
631 END PROCESS;
602
632
603 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
633 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
604
634
605 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
635 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
606 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
636 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
607 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
637 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
608 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
638 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
609 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
639 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
610
640
611 -----------------------------------------------------------------------------
641 -----------------------------------------------------------------------------
612 -- FFT
642 -- FFT
613 -----------------------------------------------------------------------------
643 -----------------------------------------------------------------------------
614 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
644 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
615 PORT MAP (
645 PORT MAP (
616 clk => clk,
646 clk => clk,
617 rstn => rstn,
647 rstn => rstn,
618 sample_valid => sample_valid,
648 sample_valid => sample_valid,
619 fft_read => fft_read,
649 fft_read => fft_read,
620 sample_data => sample_data,
650 sample_data => sample_data,
621 sample_load => sample_load,
651 sample_load => sample_load,
622 fft_pong => fft_pong,
652 fft_pong => fft_pong,
623 fft_data_im => fft_data_im,
653 fft_data_im => fft_data_im,
624 fft_data_re => fft_data_re,
654 fft_data_re => fft_data_re,
625 fft_data_valid => fft_data_valid,
655 fft_data_valid => fft_data_valid,
626 fft_ready => fft_ready);
656 fft_ready => fft_ready);
627
657
628 -----------------------------------------------------------------------------
658 -----------------------------------------------------------------------------
629 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
659 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
630 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
660 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
631
661
632 PROCESS (clk, rstn)
662 PROCESS (clk, rstn)
633 BEGIN
663 BEGIN
634 IF rstn = '0' THEN
664 IF rstn = '0' THEN
635 fft_ready_reg <= '0';
665 fft_ready_reg <= '0';
636 sample_load_reg <= '0';
666 sample_load_reg <= '0';
637
667
638 fft_ongoing_counter <= '0';
668 fft_ongoing_counter <= '0';
639 ELSIF clk'event AND clk = '1' THEN
669 ELSIF clk'event AND clk = '1' THEN
640 fft_ready_reg <= fft_ready;
670 fft_ready_reg <= fft_ready;
641 sample_load_reg <= sample_load;
671 sample_load_reg <= sample_load;
642
672
643 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
673 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
644 fft_ongoing_counter <= '0';
674 fft_ongoing_counter <= '0';
645
675
646 -- CASE fft_ongoing_counter IS
676 -- CASE fft_ongoing_counter IS
647 -- WHEN "01" => fft_ongoing_counter <= "00";
677 -- WHEN "01" => fft_ongoing_counter <= "00";
648 ---- WHEN "10" => fft_ongoing_counter <= "01";
678 ---- WHEN "10" => fft_ongoing_counter <= "01";
649 -- WHEN OTHERS => NULL;
679 -- WHEN OTHERS => NULL;
650 -- END CASE;
680 -- END CASE;
651 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
681 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
652 fft_ongoing_counter <= '1';
682 fft_ongoing_counter <= '1';
653 -- CASE fft_ongoing_counter IS
683 -- CASE fft_ongoing_counter IS
654 -- WHEN "00" => fft_ongoing_counter <= "01";
684 -- WHEN "00" => fft_ongoing_counter <= "01";
655 ---- WHEN "01" => fft_ongoing_counter <= "10";
685 ---- WHEN "01" => fft_ongoing_counter <= "10";
656 -- WHEN OTHERS => NULL;
686 -- WHEN OTHERS => NULL;
657 -- END CASE;
687 -- END CASE;
658 END IF;
688 END IF;
659
689
660 END IF;
690 END IF;
661 END PROCESS;
691 END PROCESS;
662
692
663 -----------------------------------------------------------------------------
693 -----------------------------------------------------------------------------
664 PROCESS (clk, rstn)
694 PROCESS (clk, rstn)
665 BEGIN
695 BEGIN
666 IF rstn = '0' THEN
696 IF rstn = '0' THEN
667 state_fsm_load_MS_memory <= IDLE;
697 state_fsm_load_MS_memory <= IDLE;
668 current_fifo_load <= "00001";
698 current_fifo_load <= "00001";
669 ELSIF clk'EVENT AND clk = '1' THEN
699 ELSIF clk'EVENT AND clk = '1' THEN
670 CASE state_fsm_load_MS_memory IS
700 CASE state_fsm_load_MS_memory IS
671 WHEN IDLE =>
701 WHEN IDLE =>
672 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
702 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
673 state_fsm_load_MS_memory <= LOAD_FIFO;
703 state_fsm_load_MS_memory <= LOAD_FIFO;
674 END IF;
704 END IF;
675 WHEN LOAD_FIFO =>
705 WHEN LOAD_FIFO =>
676 IF current_fifo_full = '1' THEN
706 IF current_fifo_full = '1' THEN
677 state_fsm_load_MS_memory <= TRASH_FFT;
707 state_fsm_load_MS_memory <= TRASH_FFT;
678 END IF;
708 END IF;
679 WHEN TRASH_FFT =>
709 WHEN TRASH_FFT =>
680 IF fft_ready = '0' THEN
710 IF fft_ready = '0' THEN
681 state_fsm_load_MS_memory <= IDLE;
711 state_fsm_load_MS_memory <= IDLE;
682 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
712 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
683 END IF;
713 END IF;
684 WHEN OTHERS => NULL;
714 WHEN OTHERS => NULL;
685 END CASE;
715 END CASE;
686
716
687 END IF;
717 END IF;
688 END PROCESS;
718 END PROCESS;
689
719
690 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
720 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
691 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
721 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
692 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
722 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
693 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
723 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
694 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
724 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
695
725
696 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
726 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
697 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
727 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
698 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
728 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
699 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
729 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
700 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
730 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
701
731
702 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
732 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
703 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
733 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
704 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
734 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
705 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
735 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
706 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
736 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
707
737
708 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
738 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
709
739
710 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
740 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
711 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
741 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
712 AND state_fsm_load_MS_memory = LOAD_FIFO
742 AND state_fsm_load_MS_memory = LOAD_FIFO
713 AND current_fifo_load(I) = '1'
743 AND current_fifo_load(I) = '1'
714 ELSE '1';
744 ELSE '1';
715 END GENERATE all_fifo;
745 END GENERATE all_fifo;
716
746
717 PROCESS (clk, rstn)
747 PROCESS (clk, rstn)
718 BEGIN
748 BEGIN
719 IF rstn = '0' THEN
749 IF rstn = '0' THEN
720 MEM_IN_SM_wen <= (OTHERS => '1');
750 MEM_IN_SM_wen <= (OTHERS => '1');
721 ELSIF clk'EVENT AND clk = '1' THEN
751 ELSIF clk'EVENT AND clk = '1' THEN
722 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
752 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
723 END IF;
753 END IF;
724 END PROCESS;
754 END PROCESS;
725
755
726 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
756 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
727 (fft_data_im & fft_data_re) &
757 (fft_data_im & fft_data_re) &
728 (fft_data_im & fft_data_re) &
758 (fft_data_im & fft_data_re) &
729 (fft_data_im & fft_data_re) &
759 (fft_data_im & fft_data_re) &
730 (fft_data_im & fft_data_re);
760 (fft_data_im & fft_data_re);
731 -----------------------------------------------------------------------------
761 -----------------------------------------------------------------------------
732
762
733
763
734 -----------------------------------------------------------------------------
764 -----------------------------------------------------------------------------
735 Mem_In_SpectralMatrix : lppFIFOxN
765 Mem_In_SpectralMatrix : lppFIFOxN
736 GENERIC MAP (
766 GENERIC MAP (
737 tech => 0,
767 tech => 0,
738 Mem_use => Mem_use,
768 Mem_use => Mem_use,
739 Data_sz => 32, --16,
769 Data_sz => 32, --16,
740 Addr_sz => 7, --8
770 Addr_sz => 7, --8
741 FifoCnt => 5)
771 FifoCnt => 5)
742 PORT MAP (
772 PORT MAP (
743 clk => clk,
773 clk => clk,
744 rstn => rstn,
774 rstn => rstn,
745
775
746 ReUse => MEM_IN_SM_ReUse,
776 ReUse => MEM_IN_SM_ReUse,
747 run => (OTHERS => '1'),
777 run => (OTHERS => '1'),
748
778
749 wen => MEM_IN_SM_wen,
779 wen => MEM_IN_SM_wen,
750 wdata => MEM_IN_SM_wData,
780 wdata => MEM_IN_SM_wData,
751
781
752 ren => MEM_IN_SM_ren,
782 ren => MEM_IN_SM_ren,
753 rdata => MEM_IN_SM_rData,
783 rdata => MEM_IN_SM_rData,
754 full => MEM_IN_SM_Full,
784 full => MEM_IN_SM_Full,
755 empty => MEM_IN_SM_Empty,
785 empty => MEM_IN_SM_Empty,
756 almost_full => OPEN);
786 almost_full => OPEN);
757
787
758
788
759 -----------------------------------------------------------------------------
789 -----------------------------------------------------------------------------
760 MS_control_1 : MS_control
790 MS_control_1 : MS_control
761 PORT MAP (
791 PORT MAP (
762 clk => clk,
792 clk => clk,
763 rstn => rstn,
793 rstn => rstn,
764
794
765 current_status_ms => status_MS_input,
795 current_status_ms => status_MS_input,
766
796
767 fifo_in_lock => MEM_IN_SM_locked,
797 fifo_in_lock => MEM_IN_SM_locked,
768 fifo_in_data => MEM_IN_SM_rdata,
798 fifo_in_data => MEM_IN_SM_rdata,
769 fifo_in_full => MEM_IN_SM_Full,
799 fifo_in_full => MEM_IN_SM_Full,
770 fifo_in_empty => MEM_IN_SM_Empty,
800 fifo_in_empty => MEM_IN_SM_Empty,
771 fifo_in_ren => MEM_IN_SM_ren,
801 fifo_in_ren => MEM_IN_SM_ren,
772 fifo_in_reuse => MEM_IN_SM_ReUse,
802 fifo_in_reuse => MEM_IN_SM_ReUse,
773
803
774 fifo_out_data => SM_in_data,
804 fifo_out_data => SM_in_data,
775 fifo_out_ren => SM_in_ren,
805 fifo_out_ren => SM_in_ren,
776 fifo_out_empty => SM_in_empty,
806 fifo_out_empty => SM_in_empty,
777
807
778 current_status_component => status_component,
808 current_status_component => status_component,
779
809
780 correlation_start => SM_correlation_start,
810 correlation_start => SM_correlation_start,
781 correlation_auto => SM_correlation_auto,
811 correlation_auto => SM_correlation_auto,
782 correlation_done => SM_correlation_done);
812 correlation_done => SM_correlation_done);
783
813
784
814
785 MS_calculation_1 : MS_calculation
815 MS_calculation_1 : MS_calculation
786 PORT MAP (
816 PORT MAP (
787 clk => clk,
817 clk => clk,
788 rstn => rstn,
818 rstn => rstn,
789
819
790 fifo_in_data => SM_in_data,
820 fifo_in_data => SM_in_data,
791 fifo_in_ren => SM_in_ren,
821 fifo_in_ren => SM_in_ren,
792 fifo_in_empty => SM_in_empty,
822 fifo_in_empty => SM_in_empty,
793
823
794 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
824 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
795 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
825 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
796 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
826 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
797
827
798 correlation_start => SM_correlation_start,
828 correlation_start => SM_correlation_start,
799 correlation_auto => SM_correlation_auto,
829 correlation_auto => SM_correlation_auto,
800 correlation_begin => SM_correlation_begin,
830 correlation_begin => SM_correlation_begin,
801 correlation_done => SM_correlation_done);
831 correlation_done => SM_correlation_done);
802
832
803 -----------------------------------------------------------------------------
833 -----------------------------------------------------------------------------
804 PROCESS (clk, rstn)
834 PROCESS (clk, rstn)
805 BEGIN -- PROCESS
835 BEGIN -- PROCESS
806 IF rstn = '0' THEN -- asynchronous reset (active low)
836 IF rstn = '0' THEN -- asynchronous reset (active low)
807 current_matrix_write <= '0';
837 current_matrix_write <= '0';
808 current_matrix_wait_empty <= '1';
838 current_matrix_wait_empty <= '1';
809 status_component_fifo_0 <= (OTHERS => '0');
839 status_component_fifo_0 <= (OTHERS => '0');
810 status_component_fifo_1 <= (OTHERS => '0');
840 status_component_fifo_1 <= (OTHERS => '0');
811 status_component_fifo_0_end <= '0';
841 status_component_fifo_0_end <= '0';
812 status_component_fifo_1_end <= '0';
842 status_component_fifo_1_end <= '0';
813 SM_correlation_done_reg1 <= '0';
843 SM_correlation_done_reg1 <= '0';
814 SM_correlation_done_reg2 <= '0';
844 SM_correlation_done_reg2 <= '0';
815 SM_correlation_done_reg3 <= '0';
845 SM_correlation_done_reg3 <= '0';
816
846
817 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
847 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
818 SM_correlation_done_reg1 <= SM_correlation_done;
848 SM_correlation_done_reg1 <= SM_correlation_done;
819 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
849 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
820 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
850 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
821 status_component_fifo_0_end <= '0';
851 status_component_fifo_0_end <= '0';
822 status_component_fifo_1_end <= '0';
852 status_component_fifo_1_end <= '0';
823 IF SM_correlation_begin = '1' THEN
853 IF SM_correlation_begin = '1' THEN
824 IF current_matrix_write = '0' THEN
854 IF current_matrix_write = '0' THEN
825 status_component_fifo_0 <= status_component;
855 status_component_fifo_0 <= status_component;
826 ELSE
856 ELSE
827 status_component_fifo_1 <= status_component;
857 status_component_fifo_1 <= status_component;
828 END IF;
858 END IF;
829 END IF;
859 END IF;
830
860
831 IF SM_correlation_done_reg3 = '1' THEN
861 IF SM_correlation_done_reg3 = '1' THEN
832 IF current_matrix_write = '0' THEN
862 IF current_matrix_write = '0' THEN
833 status_component_fifo_0_end <= '1';
863 status_component_fifo_0_end <= '1';
834 ELSE
864 ELSE
835 status_component_fifo_1_end <= '1';
865 status_component_fifo_1_end <= '1';
836 END IF;
866 END IF;
837 current_matrix_wait_empty <= '1';
867 current_matrix_wait_empty <= '1';
838 current_matrix_write <= NOT current_matrix_write;
868 current_matrix_write <= NOT current_matrix_write;
839 END IF;
869 END IF;
840
870
841 IF current_matrix_wait_empty <= '1' THEN
871 IF current_matrix_wait_empty <= '1' THEN
842 IF current_matrix_write = '0' THEN
872 IF current_matrix_write = '0' THEN
843 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
873 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
844 ELSE
874 ELSE
845 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
875 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
846 END IF;
876 END IF;
847 END IF;
877 END IF;
848
878
849 END IF;
879 END IF;
850 END PROCESS;
880 END PROCESS;
851
881
852 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
882 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
853 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
883 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
854 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
884 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
855 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
885 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
856 '1' WHEN current_matrix_wait_empty = '1' ELSE
886 '1' WHEN current_matrix_wait_empty = '1' ELSE
857 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
887 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
858 MEM_OUT_SM_Full(1);
888 MEM_OUT_SM_Full(1);
859
889
860 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
890 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
861 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
891 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
862
892
863 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
893 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
864 -----------------------------------------------------------------------------
894 -----------------------------------------------------------------------------
865
895
866 --Mem_Out_SpectralMatrix : lppFIFOxN
896 --Mem_Out_SpectralMatrix : lppFIFOxN
867 -- GENERIC MAP (
897 -- GENERIC MAP (
868 -- tech => 0,
898 -- tech => 0,
869 -- Mem_use => Mem_use,
899 -- Mem_use => Mem_use,
870 -- Data_sz => 32,
900 -- Data_sz => 32,
871 -- Addr_sz => 8,
901 -- Addr_sz => 8,
872 -- FifoCnt => 2)
902 -- FifoCnt => 2)
873 -- PORT MAP (
903 -- PORT MAP (
874 -- clk => clk,
904 -- clk => clk,
875 -- rstn => rstn,
905 -- rstn => rstn,
876
906
877 -- ReUse => (OTHERS => '0'),
907 -- ReUse => (OTHERS => '0'),
878 -- run => (OTHERS => '1'),
908 -- run => (OTHERS => '1'),
879
909
880 -- wen => MEM_OUT_SM_Write,
910 -- wen => MEM_OUT_SM_Write,
881 -- wdata => MEM_OUT_SM_Data_in,
911 -- wdata => MEM_OUT_SM_Data_in,
882
912
883 -- ren => MEM_OUT_SM_Read,
913 -- ren => MEM_OUT_SM_Read,
884 -- rdata => MEM_OUT_SM_Data_out,
914 -- rdata => MEM_OUT_SM_Data_out,
885
915
886 -- full => MEM_OUT_SM_Full,
916 -- full => MEM_OUT_SM_Full,
887 -- empty => MEM_OUT_SM_Empty,
917 -- empty => MEM_OUT_SM_Empty,
888 -- almost_full => OPEN);
918 -- almost_full => OPEN);
889
919
890
920
891 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
921 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
892 Mem_Out_SpectralMatrix_I: lpp_fifo
922 Mem_Out_SpectralMatrix_I: lpp_fifo
893 GENERIC MAP (
923 GENERIC MAP (
894 tech => 0,
924 tech => 0,
895 Mem_use => Mem_use,
925 Mem_use => Mem_use,
896 EMPTY_THRESHOLD_LIMIT => 15,
926 EMPTY_THRESHOLD_LIMIT => 15,
897 FULL_THRESHOLD_LIMIT => 1,
927 FULL_THRESHOLD_LIMIT => 1,
898 DataSz => 32,
928 DataSz => 32,
899 AddrSz => 8)
929 AddrSz => 8)
900 PORT MAP (
930 PORT MAP (
901 clk => clk,
931 clk => clk,
902 rstn => rstn,
932 rstn => rstn,
903 reUse => '0',
933 reUse => '0',
904 run => run,
934 run => run,
905
935
906 ren => MEM_OUT_SM_Read(I),
936 ren => MEM_OUT_SM_Read(I),
907 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
937 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
908
938
909 wen => MEM_OUT_SM_Write(I),
939 wen => MEM_OUT_SM_Write(I),
910 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
940 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
911
941
912 empty => MEM_OUT_SM_Empty(I),
942 empty => MEM_OUT_SM_Empty(I),
913 full => MEM_OUT_SM_Full(I),
943 full => MEM_OUT_SM_Full(I),
914 full_almost => OPEN,
944 full_almost => OPEN,
915 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
945 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
916
946
917 full_threshold => OPEN);
947 full_threshold => OPEN);
918
948
919 END GENERATE all_Mem_Out_SpectralMatrix;
949 END GENERATE all_Mem_Out_SpectralMatrix;
920
950
921 -----------------------------------------------------------------------------
951 -----------------------------------------------------------------------------
922 -- MEM_OUT_SM_Read <= "00";
952 -- MEM_OUT_SM_Read <= "00";
923 PROCESS (clk, rstn)
953 PROCESS (clk, rstn)
924 BEGIN
954 BEGIN
925 IF rstn = '0' THEN
955 IF rstn = '0' THEN
926 fifo_0_ready <= '0';
956 fifo_0_ready <= '0';
927 fifo_1_ready <= '0';
957 fifo_1_ready <= '0';
928 fifo_ongoing <= '0';
958 fifo_ongoing <= '0';
929 ELSIF clk'EVENT AND clk = '1' THEN
959 ELSIF clk'EVENT AND clk = '1' THEN
930 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
960 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
931 fifo_ongoing <= '1';
961 fifo_ongoing <= '1';
932 fifo_0_ready <= '0';
962 fifo_0_ready <= '0';
933 ELSIF status_component_fifo_0_end = '1' THEN
963 ELSIF status_component_fifo_0_end = '1' THEN
934 fifo_0_ready <= '1';
964 fifo_0_ready <= '1';
935 END IF;
965 END IF;
936
966
937 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
967 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
938 fifo_ongoing <= '0';
968 fifo_ongoing <= '0';
939 fifo_1_ready <= '0';
969 fifo_1_ready <= '0';
940 ELSIF status_component_fifo_1_end = '1' THEN
970 ELSIF status_component_fifo_1_end = '1' THEN
941 fifo_1_ready <= '1';
971 fifo_1_ready <= '1';
942 END IF;
972 END IF;
943
973
944 END IF;
974 END IF;
945 END PROCESS;
975 END PROCESS;
946
976
947 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
977 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
948 '1' WHEN fifo_0_ready = '0' ELSE
978 '1' WHEN fifo_0_ready = '0' ELSE
949 FSM_DMA_fifo_ren;
979 FSM_DMA_fifo_ren;
950
980
951 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
981 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
952 '1' WHEN fifo_1_ready = '0' ELSE
982 '1' WHEN fifo_1_ready = '0' ELSE
953 FSM_DMA_fifo_ren;
983 FSM_DMA_fifo_ren;
954
984
955 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
985 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
956 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
986 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
957 '1';
987 '1';
958
988
959 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
989 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
960 status_component_fifo_1;
990 status_component_fifo_1;
961
991
962 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
992 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
963 MEM_OUT_SM_Data_out(63 DOWNTO 32);
993 MEM_OUT_SM_Data_out(63 DOWNTO 32);
964
994
965
995
966 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
996 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
967 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
997 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
968 '1';
998 '1';
969
999
970 -----------------------------------------------------------------------------
1000 -----------------------------------------------------------------------------
971 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1001 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
972 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1002 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
973 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1003 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
974 -- fifo_data => FSM_DMA_fifo_data, --IN
1004 -- fifo_data => FSM_DMA_fifo_data, --IN
975 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1005 -- fifo_empty => FSM_DMA_fifo_empty, --IN
976 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1006 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
977 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1007 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
978
1008
979
1009
980 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1010 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
981 PORT MAP (
1011 PORT MAP (
982 clk => clk,
1012 clk => clk,
983 rstn => rstn,
1013 rstn => rstn,
984 run => run,
1014 run => run,
985
1015
986 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1016 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
987 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1017 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
988 fifo_data => FSM_DMA_fifo_data,
1018 fifo_data => FSM_DMA_fifo_data,
989 fifo_empty => FSM_DMA_fifo_empty,
1019 fifo_empty => FSM_DMA_fifo_empty,
990 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1020 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
991 fifo_ren => FSM_DMA_fifo_ren,
1021 fifo_ren => FSM_DMA_fifo_ren,
992
1022
993 dma_fifo_valid_burst => dma_fifo_burst_valid,
1023 dma_fifo_valid_burst => dma_fifo_burst_valid,
994 dma_fifo_data => dma_fifo_data,
1024 dma_fifo_data => dma_fifo_data,
995 dma_fifo_ren => dma_fifo_ren,
1025 dma_fifo_ren => dma_fifo_ren,
996 dma_buffer_new => dma_buffer_new,
1026 dma_buffer_new => dma_buffer_new,
997 dma_buffer_addr => dma_buffer_addr,
1027 dma_buffer_addr => dma_buffer_addr,
998 dma_buffer_length => dma_buffer_length,
1028 dma_buffer_length => dma_buffer_length,
999 dma_buffer_full => dma_buffer_full,
1029 dma_buffer_full => dma_buffer_full,
1000 dma_buffer_full_err => dma_buffer_full_err,
1030 dma_buffer_full_err => dma_buffer_full_err,
1001
1031
1002 status_ready_matrix_f0 => status_ready_matrix_f0,
1032 status_ready_matrix_f0 => status_ready_matrix_f0,
1003 status_ready_matrix_f1 => status_ready_matrix_f1,
1033 status_ready_matrix_f1 => status_ready_matrix_f1,
1004 status_ready_matrix_f2 => status_ready_matrix_f2,
1034 status_ready_matrix_f2 => status_ready_matrix_f2,
1005 addr_matrix_f0 => addr_matrix_f0,
1035 addr_matrix_f0 => addr_matrix_f0,
1006 addr_matrix_f1 => addr_matrix_f1,
1036 addr_matrix_f1 => addr_matrix_f1,
1007 addr_matrix_f2 => addr_matrix_f2,
1037 addr_matrix_f2 => addr_matrix_f2,
1008 length_matrix_f0 => length_matrix_f0,
1038 length_matrix_f0 => length_matrix_f0,
1009 length_matrix_f1 => length_matrix_f1,
1039 length_matrix_f1 => length_matrix_f1,
1010 length_matrix_f2 => length_matrix_f2,
1040 length_matrix_f2 => length_matrix_f2,
1011 ready_matrix_f0 => ready_matrix_f0,
1041 ready_matrix_f0 => ready_matrix_f0,
1012 ready_matrix_f1 => ready_matrix_f1,
1042 ready_matrix_f1 => ready_matrix_f1,
1013 ready_matrix_f2 => ready_matrix_f2,
1043 ready_matrix_f2 => ready_matrix_f2,
1014 matrix_time_f0 => matrix_time_f0,
1044 matrix_time_f0 => matrix_time_f0,
1015 matrix_time_f1 => matrix_time_f1,
1045 matrix_time_f1 => matrix_time_f1,
1016 matrix_time_f2 => matrix_time_f2,
1046 matrix_time_f2 => matrix_time_f2,
1017 error_buffer_full => error_buffer_full);
1047 error_buffer_full => error_buffer_full);
1018
1048
1019
1049
1020
1050
1021
1051
1022
1052
1023 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1053 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1024 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1054 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1025 --dma_fifo_ren : IN STD_LOGIC; --TODO
1055 --dma_fifo_ren : IN STD_LOGIC; --TODO
1026 --dma_buffer_new : OUT STD_LOGIC; --TODO
1056 --dma_buffer_new : OUT STD_LOGIC; --TODO
1027 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1057 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1028 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1058 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1029 --dma_buffer_full : IN STD_LOGIC; --TODO
1059 --dma_buffer_full : IN STD_LOGIC; --TODO
1030 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1060 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1031
1061
1032 ---- Reg out
1062 ---- Reg out
1033 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1063 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1034 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1064 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1035 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1065 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1036 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1066 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1037 --error_buffer_full : OUT STD_LOGIC; -- TODO
1067 --error_buffer_full : OUT STD_LOGIC; -- TODO
1038
1068
1039 ---- Reg In
1069 ---- Reg In
1040 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1070 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1041 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1071 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1042 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1072 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1043
1073
1044 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1074 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1045 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1075 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1046 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1076 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1047
1077
1048 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1078 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1049 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1079 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1050 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1080 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1051 -----------------------------------------------------------------------------
1081 -----------------------------------------------------------------------------
1052
1082
1053 -----------------------------------------------------------------------------
1083 -----------------------------------------------------------------------------
1054 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1084 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1055 -- PORT MAP (
1085 -- PORT MAP (
1056 -- HCLK => clk,
1086 -- HCLK => clk,
1057 -- HRESETn => rstn,
1087 -- HRESETn => rstn,
1058
1088
1059 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1089 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1060 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1090 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1061 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1091 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1062 -- fifo_data => FSM_DMA_fifo_data,
1092 -- fifo_data => FSM_DMA_fifo_data,
1063 -- fifo_empty => FSM_DMA_fifo_empty,
1093 -- fifo_empty => FSM_DMA_fifo_empty,
1064 -- fifo_ren => FSM_DMA_fifo_ren,
1094 -- fifo_ren => FSM_DMA_fifo_ren,
1065
1095
1066 -- dma_addr => dma_addr,
1096 -- dma_addr => dma_addr,
1067 -- dma_data => dma_data,
1097 -- dma_data => dma_data,
1068 -- dma_valid => dma_valid,
1098 -- dma_valid => dma_valid,
1069 -- dma_valid_burst => dma_valid_burst,
1099 -- dma_valid_burst => dma_valid_burst,
1070 -- dma_ren => dma_ren,
1100 -- dma_ren => dma_ren,
1071 -- dma_done => dma_done,
1101 -- dma_done => dma_done,
1072
1102
1073 -- ready_matrix_f0 => ready_matrix_f0,
1103 -- ready_matrix_f0 => ready_matrix_f0,
1074 -- ready_matrix_f1 => ready_matrix_f1,
1104 -- ready_matrix_f1 => ready_matrix_f1,
1075 -- ready_matrix_f2 => ready_matrix_f2,
1105 -- ready_matrix_f2 => ready_matrix_f2,
1076
1106
1077 -- error_bad_component_error => error_bad_component_error,
1107 -- error_bad_component_error => error_bad_component_error,
1078 -- error_buffer_full => error_buffer_full,
1108 -- error_buffer_full => error_buffer_full,
1079
1109
1080 -- debug_reg => debug_reg,
1110 -- debug_reg => debug_reg,
1081 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1111 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1082 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1112 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1083 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1113 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1084
1114
1085 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1115 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1086 -- config_active_interruption_onError => config_active_interruption_onError,
1116 -- config_active_interruption_onError => config_active_interruption_onError,
1087
1117
1088 -- addr_matrix_f0 => addr_matrix_f0,
1118 -- addr_matrix_f0 => addr_matrix_f0,
1089 -- addr_matrix_f1 => addr_matrix_f1,
1119 -- addr_matrix_f1 => addr_matrix_f1,
1090 -- addr_matrix_f2 => addr_matrix_f2,
1120 -- addr_matrix_f2 => addr_matrix_f2,
1091
1121
1092 -- matrix_time_f0 => matrix_time_f0,
1122 -- matrix_time_f0 => matrix_time_f0,
1093 -- matrix_time_f1 => matrix_time_f1,
1123 -- matrix_time_f1 => matrix_time_f1,
1094 -- matrix_time_f2 => matrix_time_f2
1124 -- matrix_time_f2 => matrix_time_f2
1095 -- );
1125 -- );
1096 -----------------------------------------------------------------------------
1126 -----------------------------------------------------------------------------
1097
1127
1098
1128
1099
1129
1100
1130
1101
1131
1102
1132
1103 -----------------------------------------------------------------------------
1133 -----------------------------------------------------------------------------
1104 -- TIME MANAGMENT
1134 -- TIME MANAGMENT
1105 -----------------------------------------------------------------------------
1135 -----------------------------------------------------------------------------
1106 all_time <= coarse_time & fine_time;
1136 all_time <= coarse_time & fine_time;
1107 --
1137 --
1108 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1138 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1109 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1139 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1110 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1140 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1111 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1141 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1112
1142
1113 all_time_reg: FOR I IN 0 TO 3 GENERATE
1143 all_time_reg: FOR I IN 0 TO 3 GENERATE
1114
1144
1115 PROCESS (clk, rstn)
1145 PROCESS (clk, rstn)
1116 BEGIN
1146 BEGIN
1117 IF rstn = '0' THEN
1147 IF rstn = '0' THEN
1118 f_empty_reg(I) <= '1';
1148 f_empty_reg(I) <= '1';
1119 ELSIF clk'event AND clk = '1' THEN
1149 ELSIF clk'event AND clk = '1' THEN
1120 f_empty_reg(I) <= f_empty(I);
1150 f_empty_reg(I) <= f_empty(I);
1121 END IF;
1151 END IF;
1122 END PROCESS;
1152 END PROCESS;
1123
1153
1124 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1154 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1125
1155
1126 s_m_t_m_f0_A : spectral_matrix_time_managment
1156 s_m_t_m_f0_A : spectral_matrix_time_managment
1127 PORT MAP (
1157 PORT MAP (
1128 clk => clk,
1158 clk => clk,
1129 rstn => rstn,
1159 rstn => rstn,
1130 time_in => all_time,
1160 time_in => all_time,
1131 update_1 => time_update_f(I),
1161 update_1 => time_update_f(I),
1132 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1162 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1133 );
1163 );
1134
1164
1135 END GENERATE all_time_reg;
1165 END GENERATE all_time_reg;
1136
1166
1137 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1167 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1138 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1168 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1139 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1169 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1140 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1170 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1141
1171
1142 -----------------------------------------------------------------------------
1172 -----------------------------------------------------------------------------
1143
1173
1144 END Behavioral;
1174 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,385 +1,386
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER);
72 Mem_use : INTEGER);
73 PORT (
73 PORT (
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 dma_fifo_burst_valid : OUT STD_LOGIC;
86 dma_fifo_burst_valid : OUT STD_LOGIC;
86 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 dma_fifo_ren : IN STD_LOGIC;
88 dma_fifo_ren : IN STD_LOGIC;
88 dma_buffer_new : OUT STD_LOGIC;
89 dma_buffer_new : OUT STD_LOGIC;
89 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 dma_buffer_full : IN STD_LOGIC;
92 dma_buffer_full : IN STD_LOGIC;
92 dma_buffer_full_err : IN STD_LOGIC;
93 dma_buffer_full_err : IN STD_LOGIC;
93 ready_matrix_f0 : OUT STD_LOGIC;
94 ready_matrix_f0 : OUT STD_LOGIC;
94 ready_matrix_f1 : OUT STD_LOGIC;
95 ready_matrix_f1 : OUT STD_LOGIC;
95 ready_matrix_f2 : OUT STD_LOGIC;
96 ready_matrix_f2 : OUT STD_LOGIC;
96 error_buffer_full : OUT STD_LOGIC;
97 error_buffer_full : OUT STD_LOGIC;
97 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
98 status_ready_matrix_f0 : IN STD_LOGIC;
99 status_ready_matrix_f0 : IN STD_LOGIC;
99 status_ready_matrix_f1 : IN STD_LOGIC;
100 status_ready_matrix_f1 : IN STD_LOGIC;
100 status_ready_matrix_f2 : IN STD_LOGIC;
101 status_ready_matrix_f2 : IN STD_LOGIC;
101 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
105 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
106 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
109 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
110 END COMPONENT;
111 END COMPONENT;
111
112
112 COMPONENT lpp_lfr_ms_fsmdma
113 COMPONENT lpp_lfr_ms_fsmdma
113 PORT (
114 PORT (
114 clk : IN STD_ULOGIC;
115 clk : IN STD_ULOGIC;
115 rstn : IN STD_ULOGIC;
116 rstn : IN STD_ULOGIC;
116 run : IN STD_LOGIC;
117 run : IN STD_LOGIC;
117 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
118 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
118 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
119 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
119 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 fifo_empty : IN STD_LOGIC;
121 fifo_empty : IN STD_LOGIC;
121 fifo_empty_threshold : IN STD_LOGIC;
122 fifo_empty_threshold : IN STD_LOGIC;
122 fifo_ren : OUT STD_LOGIC;
123 fifo_ren : OUT STD_LOGIC;
123 dma_fifo_valid_burst : OUT STD_LOGIC;
124 dma_fifo_valid_burst : OUT STD_LOGIC;
124 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 dma_fifo_ren : IN STD_LOGIC;
126 dma_fifo_ren : IN STD_LOGIC;
126 dma_buffer_new : OUT STD_LOGIC;
127 dma_buffer_new : OUT STD_LOGIC;
127 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
129 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
129 dma_buffer_full : IN STD_LOGIC;
130 dma_buffer_full : IN STD_LOGIC;
130 dma_buffer_full_err : IN STD_LOGIC;
131 dma_buffer_full_err : IN STD_LOGIC;
131 status_ready_matrix_f0 : IN STD_LOGIC;
132 status_ready_matrix_f0 : IN STD_LOGIC;
132 status_ready_matrix_f1 : IN STD_LOGIC;
133 status_ready_matrix_f1 : IN STD_LOGIC;
133 status_ready_matrix_f2 : IN STD_LOGIC;
134 status_ready_matrix_f2 : IN STD_LOGIC;
134 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
138 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
139 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
140 ready_matrix_f0 : OUT STD_LOGIC;
141 ready_matrix_f0 : OUT STD_LOGIC;
141 ready_matrix_f1 : OUT STD_LOGIC;
142 ready_matrix_f1 : OUT STD_LOGIC;
142 ready_matrix_f2 : OUT STD_LOGIC;
143 ready_matrix_f2 : OUT STD_LOGIC;
143 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
144 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
145 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
146 error_buffer_full : OUT STD_LOGIC);
147 error_buffer_full : OUT STD_LOGIC);
147 END COMPONENT;
148 END COMPONENT;
148
149
149 COMPONENT lpp_lfr_ms_FFT
150 COMPONENT lpp_lfr_ms_FFT
150 PORT (
151 PORT (
151 clk : IN STD_LOGIC;
152 clk : IN STD_LOGIC;
152 rstn : IN STD_LOGIC;
153 rstn : IN STD_LOGIC;
153 sample_valid : IN STD_LOGIC;
154 sample_valid : IN STD_LOGIC;
154 fft_read : IN STD_LOGIC;
155 fft_read : IN STD_LOGIC;
155 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
156 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
156 sample_load : OUT STD_LOGIC;
157 sample_load : OUT STD_LOGIC;
157 fft_pong : OUT STD_LOGIC;
158 fft_pong : OUT STD_LOGIC;
158 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
159 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
160 fft_data_valid : OUT STD_LOGIC;
161 fft_data_valid : OUT STD_LOGIC;
161 fft_ready : OUT STD_LOGIC);
162 fft_ready : OUT STD_LOGIC);
162 END COMPONENT;
163 END COMPONENT;
163
164
164 COMPONENT lpp_lfr_filter
165 COMPONENT lpp_lfr_filter
165 GENERIC (
166 GENERIC (
166 Mem_use : INTEGER);
167 Mem_use : INTEGER);
167 PORT (
168 PORT (
168 sample : IN Samples(7 DOWNTO 0);
169 sample : IN Samples(7 DOWNTO 0);
169 sample_val : IN STD_LOGIC;
170 sample_val : IN STD_LOGIC;
170 clk : IN STD_LOGIC;
171 clk : IN STD_LOGIC;
171 rstn : IN STD_LOGIC;
172 rstn : IN STD_LOGIC;
172 data_shaping_SP0 : IN STD_LOGIC;
173 data_shaping_SP0 : IN STD_LOGIC;
173 data_shaping_SP1 : IN STD_LOGIC;
174 data_shaping_SP1 : IN STD_LOGIC;
174 data_shaping_R0 : IN STD_LOGIC;
175 data_shaping_R0 : IN STD_LOGIC;
175 data_shaping_R1 : IN STD_LOGIC;
176 data_shaping_R1 : IN STD_LOGIC;
176 data_shaping_R2 : IN STD_LOGIC;
177 data_shaping_R2 : IN STD_LOGIC;
177 sample_f0_val : OUT STD_LOGIC;
178 sample_f0_val : OUT STD_LOGIC;
178 sample_f1_val : OUT STD_LOGIC;
179 sample_f1_val : OUT STD_LOGIC;
179 sample_f2_val : OUT STD_LOGIC;
180 sample_f2_val : OUT STD_LOGIC;
180 sample_f3_val : OUT STD_LOGIC;
181 sample_f3_val : OUT STD_LOGIC;
181 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
182 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
183 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
184 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
185 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
185 END COMPONENT;
186 END COMPONENT;
186
187
187 COMPONENT lpp_lfr
188 COMPONENT lpp_lfr
188 GENERIC (
189 GENERIC (
189 Mem_use : INTEGER;
190 Mem_use : INTEGER;
190 nb_data_by_buffer_size : INTEGER;
191 nb_data_by_buffer_size : INTEGER;
191 -- nb_word_by_buffer_size : INTEGER;
192 -- nb_word_by_buffer_size : INTEGER;
192 nb_snapshot_param_size : INTEGER;
193 nb_snapshot_param_size : INTEGER;
193 delta_vector_size : INTEGER;
194 delta_vector_size : INTEGER;
194 delta_vector_size_f0_2 : INTEGER;
195 delta_vector_size_f0_2 : INTEGER;
195 pindex : INTEGER;
196 pindex : INTEGER;
196 paddr : INTEGER;
197 paddr : INTEGER;
197 pmask : INTEGER;
198 pmask : INTEGER;
198 pirq_ms : INTEGER;
199 pirq_ms : INTEGER;
199 pirq_wfp : INTEGER;
200 pirq_wfp : INTEGER;
200 hindex : INTEGER;
201 hindex : INTEGER;
201 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
202 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
202 );
203 );
203 PORT (
204 PORT (
204 clk : IN STD_LOGIC;
205 clk : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
206 rstn : IN STD_LOGIC;
206 sample_B : IN Samples(2 DOWNTO 0);
207 sample_B : IN Samples(2 DOWNTO 0);
207 sample_E : IN Samples(4 DOWNTO 0);
208 sample_E : IN Samples(4 DOWNTO 0);
208 sample_val : IN STD_LOGIC;
209 sample_val : IN STD_LOGIC;
209 apbi : IN apb_slv_in_type;
210 apbi : IN apb_slv_in_type;
210 apbo : OUT apb_slv_out_type;
211 apbo : OUT apb_slv_out_type;
211 ahbi : IN AHB_Mst_In_Type;
212 ahbi : IN AHB_Mst_In_Type;
212 ahbo : OUT AHB_Mst_Out_Type;
213 ahbo : OUT AHB_Mst_Out_Type;
213 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
215 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
215 data_shaping_BW : OUT STD_LOGIC
216 data_shaping_BW : OUT STD_LOGIC
216 );
217 );
217 END COMPONENT;
218 END COMPONENT;
218
219
219 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
220 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
221 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
221 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
222 COMPONENT lpp_lfr_WFP_nMS
223 COMPONENT lpp_lfr_WFP_nMS
223 GENERIC (
224 GENERIC (
224 Mem_use : INTEGER;
225 Mem_use : INTEGER;
225 nb_data_by_buffer_size : INTEGER;
226 nb_data_by_buffer_size : INTEGER;
226 nb_word_by_buffer_size : INTEGER;
227 nb_word_by_buffer_size : INTEGER;
227 nb_snapshot_param_size : INTEGER;
228 nb_snapshot_param_size : INTEGER;
228 delta_vector_size : INTEGER;
229 delta_vector_size : INTEGER;
229 delta_vector_size_f0_2 : INTEGER;
230 delta_vector_size_f0_2 : INTEGER;
230 pindex : INTEGER;
231 pindex : INTEGER;
231 paddr : INTEGER;
232 paddr : INTEGER;
232 pmask : INTEGER;
233 pmask : INTEGER;
233 pirq_ms : INTEGER;
234 pirq_ms : INTEGER;
234 pirq_wfp : INTEGER;
235 pirq_wfp : INTEGER;
235 hindex : INTEGER;
236 hindex : INTEGER;
236 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
237 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
237 PORT (
238 PORT (
238 clk : IN STD_LOGIC;
239 clk : IN STD_LOGIC;
239 rstn : IN STD_LOGIC;
240 rstn : IN STD_LOGIC;
240 sample_B : IN Samples(2 DOWNTO 0);
241 sample_B : IN Samples(2 DOWNTO 0);
241 sample_E : IN Samples(4 DOWNTO 0);
242 sample_E : IN Samples(4 DOWNTO 0);
242 sample_val : IN STD_LOGIC;
243 sample_val : IN STD_LOGIC;
243 apbi : IN apb_slv_in_type;
244 apbi : IN apb_slv_in_type;
244 apbo : OUT apb_slv_out_type;
245 apbo : OUT apb_slv_out_type;
245 ahbi : IN AHB_Mst_In_Type;
246 ahbi : IN AHB_Mst_In_Type;
246 ahbo : OUT AHB_Mst_Out_Type;
247 ahbo : OUT AHB_Mst_Out_Type;
247 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
248 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
248 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
249 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
249 data_shaping_BW : OUT STD_LOGIC;
250 data_shaping_BW : OUT STD_LOGIC;
250 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
251 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
251 END COMPONENT;
252 END COMPONENT;
252 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
253
254
254 COMPONENT lpp_lfr_apbreg
255 COMPONENT lpp_lfr_apbreg
255 GENERIC (
256 GENERIC (
256 nb_data_by_buffer_size : INTEGER;
257 nb_data_by_buffer_size : INTEGER;
257 nb_snapshot_param_size : INTEGER;
258 nb_snapshot_param_size : INTEGER;
258 delta_vector_size : INTEGER;
259 delta_vector_size : INTEGER;
259 delta_vector_size_f0_2 : INTEGER;
260 delta_vector_size_f0_2 : INTEGER;
260 pindex : INTEGER;
261 pindex : INTEGER;
261 paddr : INTEGER;
262 paddr : INTEGER;
262 pmask : INTEGER;
263 pmask : INTEGER;
263 pirq_ms : INTEGER;
264 pirq_ms : INTEGER;
264 pirq_wfp : INTEGER;
265 pirq_wfp : INTEGER;
265 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
266 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
266 PORT (
267 PORT (
267 HCLK : IN STD_ULOGIC;
268 HCLK : IN STD_ULOGIC;
268 HRESETn : IN STD_ULOGIC;
269 HRESETn : IN STD_ULOGIC;
269 apbi : IN apb_slv_in_type;
270 apbi : IN apb_slv_in_type;
270 apbo : OUT apb_slv_out_type;
271 apbo : OUT apb_slv_out_type;
271 run_ms : OUT STD_LOGIC;
272 run_ms : OUT STD_LOGIC;
272 ready_matrix_f0 : IN STD_LOGIC;
273 ready_matrix_f0 : IN STD_LOGIC;
273 ready_matrix_f1 : IN STD_LOGIC;
274 ready_matrix_f1 : IN STD_LOGIC;
274 ready_matrix_f2 : IN STD_LOGIC;
275 ready_matrix_f2 : IN STD_LOGIC;
275 error_buffer_full : IN STD_LOGIC;
276 error_buffer_full : IN STD_LOGIC;
276 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
277 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
277 status_ready_matrix_f0 : OUT STD_LOGIC;
278 status_ready_matrix_f0 : OUT STD_LOGIC;
278 status_ready_matrix_f1 : OUT STD_LOGIC;
279 status_ready_matrix_f1 : OUT STD_LOGIC;
279 status_ready_matrix_f2 : OUT STD_LOGIC;
280 status_ready_matrix_f2 : OUT STD_LOGIC;
280 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
281 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
281 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
284 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
284 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
285 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
285 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
286 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
286 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
287 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
287 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
288 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
288 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
289 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
289 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
290 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
290 data_shaping_BW : OUT STD_LOGIC;
291 data_shaping_BW : OUT STD_LOGIC;
291 data_shaping_SP0 : OUT STD_LOGIC;
292 data_shaping_SP0 : OUT STD_LOGIC;
292 data_shaping_SP1 : OUT STD_LOGIC;
293 data_shaping_SP1 : OUT STD_LOGIC;
293 data_shaping_R0 : OUT STD_LOGIC;
294 data_shaping_R0 : OUT STD_LOGIC;
294 data_shaping_R1 : OUT STD_LOGIC;
295 data_shaping_R1 : OUT STD_LOGIC;
295 data_shaping_R2 : OUT STD_LOGIC;
296 data_shaping_R2 : OUT STD_LOGIC;
296 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
297 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
297 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
298 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
298 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
299 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
299 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
300 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
300 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
301 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
302 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
302 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
303 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
303 enable_f0 : OUT STD_LOGIC;
304 enable_f0 : OUT STD_LOGIC;
304 enable_f1 : OUT STD_LOGIC;
305 enable_f1 : OUT STD_LOGIC;
305 enable_f2 : OUT STD_LOGIC;
306 enable_f2 : OUT STD_LOGIC;
306 enable_f3 : OUT STD_LOGIC;
307 enable_f3 : OUT STD_LOGIC;
307 burst_f0 : OUT STD_LOGIC;
308 burst_f0 : OUT STD_LOGIC;
308 burst_f1 : OUT STD_LOGIC;
309 burst_f1 : OUT STD_LOGIC;
309 burst_f2 : OUT STD_LOGIC;
310 burst_f2 : OUT STD_LOGIC;
310 run : OUT STD_LOGIC;
311 run : OUT STD_LOGIC;
311 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
312 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
312 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
313 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
313 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
314 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
314 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
315 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
315 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
316 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
316 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
317 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
317 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
318 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
318 END COMPONENT;
319 END COMPONENT;
319
320
320 COMPONENT lpp_top_ms
321 COMPONENT lpp_top_ms
321 GENERIC (
322 GENERIC (
322 Mem_use : INTEGER;
323 Mem_use : INTEGER;
323 nb_burst_available_size : INTEGER;
324 nb_burst_available_size : INTEGER;
324 nb_snapshot_param_size : INTEGER;
325 nb_snapshot_param_size : INTEGER;
325 delta_snapshot_size : INTEGER;
326 delta_snapshot_size : INTEGER;
326 delta_f2_f0_size : INTEGER;
327 delta_f2_f0_size : INTEGER;
327 delta_f2_f1_size : INTEGER;
328 delta_f2_f1_size : INTEGER;
328 pindex : INTEGER;
329 pindex : INTEGER;
329 paddr : INTEGER;
330 paddr : INTEGER;
330 pmask : INTEGER;
331 pmask : INTEGER;
331 pirq_ms : INTEGER;
332 pirq_ms : INTEGER;
332 pirq_wfp : INTEGER;
333 pirq_wfp : INTEGER;
333 hindex_wfp : INTEGER;
334 hindex_wfp : INTEGER;
334 hindex_ms : INTEGER);
335 hindex_ms : INTEGER);
335 PORT (
336 PORT (
336 clk : IN STD_LOGIC;
337 clk : IN STD_LOGIC;
337 rstn : IN STD_LOGIC;
338 rstn : IN STD_LOGIC;
338 sample_B : IN Samples14v(2 DOWNTO 0);
339 sample_B : IN Samples14v(2 DOWNTO 0);
339 sample_E : IN Samples14v(4 DOWNTO 0);
340 sample_E : IN Samples14v(4 DOWNTO 0);
340 sample_val : IN STD_LOGIC;
341 sample_val : IN STD_LOGIC;
341 apbi : IN apb_slv_in_type;
342 apbi : IN apb_slv_in_type;
342 apbo : OUT apb_slv_out_type;
343 apbo : OUT apb_slv_out_type;
343 ahbi_ms : IN AHB_Mst_In_Type;
344 ahbi_ms : IN AHB_Mst_In_Type;
344 ahbo_ms : OUT AHB_Mst_Out_Type;
345 ahbo_ms : OUT AHB_Mst_Out_Type;
345 data_shaping_BW : OUT STD_LOGIC;
346 data_shaping_BW : OUT STD_LOGIC;
346 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
347 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
347 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
348 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
349 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
350 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
350 );
351 );
351 END COMPONENT;
352 END COMPONENT;
352
353
353 COMPONENT lpp_apbreg_ms_pointer
354 COMPONENT lpp_apbreg_ms_pointer
354 PORT (
355 PORT (
355 clk : IN STD_LOGIC;
356 clk : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
357 rstn : IN STD_LOGIC;
357 run : IN STD_LOGIC;
358 run : IN STD_LOGIC;
358 reg0_status_ready_matrix : IN STD_LOGIC;
359 reg0_status_ready_matrix : IN STD_LOGIC;
359 reg0_ready_matrix : OUT STD_LOGIC;
360 reg0_ready_matrix : OUT STD_LOGIC;
360 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
361 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
361 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
362 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
362 reg1_status_ready_matrix : IN STD_LOGIC;
363 reg1_status_ready_matrix : IN STD_LOGIC;
363 reg1_ready_matrix : OUT STD_LOGIC;
364 reg1_ready_matrix : OUT STD_LOGIC;
364 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
366 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
366 ready_matrix : IN STD_LOGIC;
367 ready_matrix : IN STD_LOGIC;
367 status_ready_matrix : OUT STD_LOGIC;
368 status_ready_matrix : OUT STD_LOGIC;
368 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
369 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
369 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
370 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
370 END COMPONENT;
371 END COMPONENT;
371
372
372 COMPONENT lpp_lfr_ms_reg_head
373 COMPONENT lpp_lfr_ms_reg_head
373 PORT (
374 PORT (
374 clk : IN STD_LOGIC;
375 clk : IN STD_LOGIC;
375 rstn : IN STD_LOGIC;
376 rstn : IN STD_LOGIC;
376 in_wen : IN STD_LOGIC;
377 in_wen : IN STD_LOGIC;
377 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
378 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
378 in_full : IN STD_LOGIC;
379 in_full : IN STD_LOGIC;
379 in_empty : IN STD_LOGIC;
380 in_empty : IN STD_LOGIC;
380 out_wen : OUT STD_LOGIC;
381 out_wen : OUT STD_LOGIC;
381 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
382 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
382 out_full : OUT STD_LOGIC);
383 out_full : OUT STD_LOGIC);
383 END COMPONENT;
384 END COMPONENT;
384
385
385 END lpp_lfr_pkg;
386 END lpp_lfr_pkg;
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