diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -175,6 +175,9 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); ----------------------------------------------------------------------------- + + SIGNAL LFR_soft_rstn : STD_LOGIC; + SIGNAL LFR_rstn : STD_LOGIC; BEGIN -- beh @@ -323,7 +326,9 @@ BEGIN -- beh apbi => apbi_ext, apbo => apbo_ext(6), coarse_time => coarse_time, - fine_time => fine_time); + fine_time => fine_time, + LFR_soft_rstn => LFR_soft_rstn + ); ----------------------------------------------------------------------- --- SpaceWire -------------------------------------------------------- @@ -414,11 +419,14 @@ BEGIN -- beh ------------------------------------------------------------------------------- -- LFR ------------------------------------------------------------------------ ------------------------------------------------------------------------------- + + + LFR_rstn <= LFR_soft_rstn AND reset; + lpp_lfr_1 : lpp_lfr GENERIC MAP ( Mem_use => use_RAM, nb_data_by_buffer_size => 32, --- nb_word_by_buffer_size => 30, nb_snapshot_param_size => 32, delta_vector_size => 32, delta_vector_size_f0_2 => 7, -- log2(96) @@ -428,10 +436,10 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00011F") -- aa.bb.cc version + top_lfr_version => X"000120") -- aa.bb.cc version PORT MAP ( clk => clk_25, - rstn => reset, + rstn => LFR_rstn, sample_B => sample_s(2 DOWNTO 0), sample_E => sample_s(7 DOWNTO 3), sample_val => sample_val, diff --git a/lib/lpp/dsp/cic/cic_lfr_control.vhd b/lib/lpp/dsp/cic/cic_lfr_control.vhd --- a/lib/lpp/dsp/cic/cic_lfr_control.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_control.vhd @@ -78,9 +78,9 @@ ARCHITECTURE beh OF cic_lfr_control IS READ_INT_2_d1, Wait_step, - INT_0, INT_1, INT_2 ); + SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -50,7 +50,9 @@ ENTITY apb_lfr_time_management IS apbo : OUT apb_slv_out_type; --! APB slave output signals coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME + --------------------------------------------------------------------------- + LFR_soft_rstn : OUT STD_LOGIC ); END apb_lfr_time_management; @@ -69,6 +71,7 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + LFR_soft_reset : STD_LOGIC; END RECORD; SIGNAL r : apb_lfr_time_management_Reg; @@ -108,6 +111,8 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ BEGIN + LFR_soft_rstn <= NOT r.LFR_soft_reset; + PROCESS(resetn, clk25MHz) BEGIN @@ -116,6 +121,8 @@ BEGIN r.coarse_time_load <= (OTHERS => '0'); r.soft_reset <= '0'; r.ctrl <= '0'; + r.LFR_soft_reset <= '1'; + force_tick <= '0'; previous_force_tick <= '0'; soft_tick <= '0'; @@ -145,8 +152,9 @@ BEGIN IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN CASE apbi.paddr(7 DOWNTO 2) IS WHEN "000000" => - r.ctrl <= apbi.pwdata(0); - r.soft_reset <= apbi.pwdata(1); + r.ctrl <= apbi.pwdata(0); + r.soft_reset <= apbi.pwdata(1); + r.LFR_soft_reset <= apbi.pwdata(2); WHEN "000001" => r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); coarsetime_reg_updated <= '1'; @@ -168,7 +176,8 @@ BEGIN WHEN "000000" => Rdata(0) <= r.ctrl; Rdata(1) <= r.soft_reset; - Rdata(31 DOWNTO 1) <= (others => '0'); + Rdata(2) <= r.LFR_soft_reset; + Rdata(31 DOWNTO 3) <= (others => '0'); WHEN "000001" => Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); WHEN "000010" => diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd @@ -44,7 +44,8 @@ PACKAGE lpp_lfr_time_management IS apbi : IN apb_slv_in_type; --! APB slave input signals apbo : OUT apb_slv_out_type; --! APB slave output signals coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME + LFR_soft_rstn : OUT STD_LOGIC ); END COMPONENT; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -181,7 +181,7 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL burst_f1 : STD_LOGIC; SIGNAL burst_f2 : STD_LOGIC; - SIGNAL run : STD_LOGIC; + --SIGNAL run : STD_LOGIC; SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); ----------------------------------------------------------------------------- @@ -255,7 +255,7 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL data_ms_done : STD_LOGIC; SIGNAL dma_ms_ongoing : STD_LOGIC; - SIGNAL run_ms : STD_LOGIC; +-- SIGNAL run_ms : STD_LOGIC; SIGNAL ms_softandhard_rstn : STD_LOGIC; SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); @@ -282,7 +282,7 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL dma_grant_error : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL run_dma : STD_LOGIC; +-- SIGNAL run_dma : STD_LOGIC; BEGIN sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); @@ -335,7 +335,7 @@ BEGIN apbi => apbi, apbo => apbo, - run_ms => run_ms, + run_ms => OPEN,--run_ms, ready_matrix_f0 => ready_matrix_f0, ready_matrix_f1 => ready_matrix_f1, @@ -383,7 +383,7 @@ BEGIN burst_f0 => burst_f0, burst_f1 => burst_f1, burst_f2 => burst_f2, - run => run, + run => OPEN, --run, start_date => start_date, -- debug_signal => debug_signal, wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO @@ -410,7 +410,7 @@ BEGIN clk => clk, rstn => rstn, - reg_run => run, + reg_run => '1',--run, reg_start_date => start_date, reg_delta_snapshot => delta_snapshot, reg_delta_f0 => delta_f0, @@ -481,7 +481,7 @@ BEGIN ------------------------------------------------------------------------------- - ms_softandhard_rstn <= rstn AND run_ms AND run; + --ms_softandhard_rstn <= rstn AND run_ms AND run; ----------------------------------------------------------------------------- lpp_lfr_ms_1 : lpp_lfr_ms @@ -492,8 +492,10 @@ BEGIN --rstn => ms_softandhard_rstn, --rstn, rstn => rstn, - run => run_ms, + run => '1',--run_ms, + start_date => start_date, + coarse_time => coarse_time, fine_time => fine_time, @@ -539,7 +541,7 @@ BEGIN matrix_time_f2 => matrix_time_f2); ----------------------------------------------------------------------------- - run_dma <= run_ms OR run; + --run_dma <= run_ms OR run; DMA_SubSystem_1 : DMA_SubSystem GENERIC MAP ( @@ -547,7 +549,7 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, - run => run_dma, + run => '1',--run_dma, ahbi => ahbi, ahbo => ahbo, diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -381,7 +381,7 @@ BEGIN -- beh reg_wp.delta_f2 <= (OTHERS => '0'); reg_wp.nb_data_by_buffer <= (OTHERS => '0'); reg_wp.nb_snapshot_param <= (OTHERS => '0'); - reg_wp.start_date <= (OTHERS => '0'); + reg_wp.start_date <= (OTHERS => '1'); reg_wp.status_ready_buffer_f <= (OTHERS => '0'); reg_wp.length_buffer <= (OTHERS => '0'); @@ -692,7 +692,7 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => reg_sp.config_ms_run, + run => '1',--reg_sp.config_ms_run, reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, reg0_ready_matrix => reg0_ready_matrix_f0, @@ -714,7 +714,7 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => reg_sp.config_ms_run, + run => '1',--reg_sp.config_ms_run, reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, reg0_ready_matrix => reg0_ready_matrix_f1, @@ -736,7 +736,7 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => reg_sp.config_ms_run, + run => '1',--reg_sp.config_ms_run, reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, reg0_ready_matrix => reg0_ready_matrix_f2, @@ -760,7 +760,7 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => reg_wp.run, + run => '1',--reg_wp.run, reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), reg0_ready_matrix => reg_ready_buffer_f(2*I), diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -1,5 +1,6 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; LIBRARY lpp; @@ -26,6 +27,7 @@ ENTITY lpp_lfr_ms IS --------------------------------------------------------------------------- -- DATA INPUT --------------------------------------------------------------------------- + start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); -- TIME coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo @@ -253,9 +255,37 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL sample_f1_empty_head_in : STD_LOGIC; SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ongoing : STD_LOGIC; BEGIN + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_f0_wen_s <= (OTHERS => '1'); + sample_f1_wen_s <= (OTHERS => '1'); + sample_f2_wen_s <= (OTHERS => '1'); + ongoing <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF ongoing = '1' THEN + sample_f0_wen_s <= sample_f0_wen; + sample_f1_wen_s <= sample_f1_wen; + sample_f2_wen_s <= sample_f2_wen; + ELSE + IF start_date = coarse_time(30 DOWNTO 0) THEN + ongoing <= '1'; + END IF; + sample_f0_wen_s <= (OTHERS => '1'); + sample_f1_wen_s <= (OTHERS => '1'); + sample_f2_wen_s <= (OTHERS => '1'); + END IF; + END IF; + END PROCESS; + error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; @@ -265,7 +295,7 @@ BEGIN clk => clk, rstn => rstn, - sample_wen => sample_f0_wen, + sample_wen => sample_f0_wen_s, fifo_A_empty => sample_f0_A_empty, fifo_A_full => sample_f0_A_full, @@ -332,7 +362,7 @@ BEGIN -- sample_f1_wdata in -- sample_f1_full OUT - sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; + sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1'; sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; @@ -374,7 +404,7 @@ BEGIN almost_full => sample_f1_almost_full); - one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; + one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1'; PROCESS (clk, rstn) BEGIN -- PROCESS @@ -417,7 +447,7 @@ BEGIN almost_full => OPEN); - one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; + one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1'; PROCESS (clk, rstn) BEGIN -- PROCESS diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -74,6 +74,7 @@ PACKAGE lpp_lfr_pkg IS clk : IN STD_LOGIC; rstn : IN STD_LOGIC; run : IN STD_LOGIC; + start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);