@@ -175,6 +175,9 ARCHITECTURE beh OF MINI_LFR_top IS | |||||
175 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); |
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175 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
176 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); |
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176 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
177 | ----------------------------------------------------------------------------- |
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177 | ----------------------------------------------------------------------------- | |
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178 | ||||
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179 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |||
|
180 | SIGNAL LFR_rstn : STD_LOGIC; | |||
178 |
|
181 | |||
179 | BEGIN -- beh |
|
182 | BEGIN -- beh | |
180 |
|
183 | |||
@@ -323,7 +326,9 BEGIN -- beh | |||||
323 | apbi => apbi_ext, |
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326 | apbi => apbi_ext, | |
324 | apbo => apbo_ext(6), |
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327 | apbo => apbo_ext(6), | |
325 | coarse_time => coarse_time, |
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328 | coarse_time => coarse_time, | |
326 |
fine_time => fine_time |
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329 | fine_time => fine_time, | |
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330 | LFR_soft_rstn => LFR_soft_rstn | |||
|
331 | ); | |||
327 |
|
332 | |||
328 | ----------------------------------------------------------------------- |
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333 | ----------------------------------------------------------------------- | |
329 | --- SpaceWire -------------------------------------------------------- |
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334 | --- SpaceWire -------------------------------------------------------- | |
@@ -414,11 +419,14 BEGIN -- beh | |||||
414 | ------------------------------------------------------------------------------- |
|
419 | ------------------------------------------------------------------------------- | |
415 | -- LFR ------------------------------------------------------------------------ |
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420 | -- LFR ------------------------------------------------------------------------ | |
416 | ------------------------------------------------------------------------------- |
|
421 | ------------------------------------------------------------------------------- | |
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422 | ||||
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423 | ||||
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424 | LFR_rstn <= LFR_soft_rstn AND reset; | |||
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425 | ||||
417 |
|
|
426 | lpp_lfr_1 : lpp_lfr | |
418 | GENERIC MAP ( |
|
427 | GENERIC MAP ( | |
419 | Mem_use => use_RAM, |
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428 | Mem_use => use_RAM, | |
420 | nb_data_by_buffer_size => 32, |
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429 | nb_data_by_buffer_size => 32, | |
421 | -- nb_word_by_buffer_size => 30, |
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|||
422 | nb_snapshot_param_size => 32, |
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430 | nb_snapshot_param_size => 32, | |
423 | delta_vector_size => 32, |
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431 | delta_vector_size => 32, | |
424 | delta_vector_size_f0_2 => 7, -- log2(96) |
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432 | delta_vector_size_f0_2 => 7, -- log2(96) | |
@@ -428,10 +436,10 BEGIN -- beh | |||||
428 | pirq_ms => 6, |
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436 | pirq_ms => 6, | |
429 | pirq_wfp => 14, |
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437 | pirq_wfp => 14, | |
430 | hindex => 2, |
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438 | hindex => 2, | |
431 |
top_lfr_version => X"0001 |
|
439 | top_lfr_version => X"000120") -- aa.bb.cc version | |
432 | PORT MAP ( |
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440 | PORT MAP ( | |
433 | clk => clk_25, |
|
441 | clk => clk_25, | |
434 |
rstn => r |
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442 | rstn => LFR_rstn, | |
435 | sample_B => sample_s(2 DOWNTO 0), |
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443 | sample_B => sample_s(2 DOWNTO 0), | |
436 | sample_E => sample_s(7 DOWNTO 3), |
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444 | sample_E => sample_s(7 DOWNTO 3), | |
437 | sample_val => sample_val, |
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445 | sample_val => sample_val, |
@@ -78,9 +78,9 ARCHITECTURE beh OF cic_lfr_control IS | |||||
78 | READ_INT_2_d1, |
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78 | READ_INT_2_d1, | |
79 |
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79 | |||
80 | Wait_step, |
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80 | Wait_step, | |
81 |
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||||
82 | INT_0, INT_1, INT_2 |
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81 | INT_0, INT_1, INT_2 | |
83 | ); |
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82 | ); | |
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83 | ||||
84 |
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84 | SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE; | |
85 | SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; |
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85 | SIGNAL STATE_CIC_LFR_pre : STATE_CIC_LFR_TYPE; | |
86 |
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86 |
@@ -50,7 +50,9 ENTITY apb_lfr_time_management IS | |||||
50 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
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50 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
51 |
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51 | |||
52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
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52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
53 |
fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine |
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53 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME | |
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54 | --------------------------------------------------------------------------- | |||
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55 | LFR_soft_rstn : OUT STD_LOGIC | |||
54 | ); |
|
56 | ); | |
55 |
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57 | |||
56 | END apb_lfr_time_management; |
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58 | END apb_lfr_time_management; | |
@@ -69,6 +71,7 ARCHITECTURE Behavioral OF apb_lfr_time_ | |||||
69 | coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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71 | coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
70 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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72 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
71 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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73 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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74 | LFR_soft_reset : STD_LOGIC; | |||
72 | END RECORD; |
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75 | END RECORD; | |
73 | SIGNAL r : apb_lfr_time_management_Reg; |
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76 | SIGNAL r : apb_lfr_time_management_Reg; | |
74 |
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77 | |||
@@ -108,6 +111,8 ARCHITECTURE Behavioral OF apb_lfr_time_ | |||||
108 |
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111 | |||
109 | BEGIN |
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112 | BEGIN | |
110 |
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113 | |||
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114 | LFR_soft_rstn <= NOT r.LFR_soft_reset; | |||
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115 | ||||
111 |
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116 | PROCESS(resetn, clk25MHz) | |
112 | BEGIN |
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117 | BEGIN | |
113 |
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118 | |||
@@ -116,6 +121,8 BEGIN | |||||
116 | r.coarse_time_load <= (OTHERS => '0'); |
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121 | r.coarse_time_load <= (OTHERS => '0'); | |
117 | r.soft_reset <= '0'; |
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122 | r.soft_reset <= '0'; | |
118 | r.ctrl <= '0'; |
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123 | r.ctrl <= '0'; | |
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124 | r.LFR_soft_reset <= '1'; | |||
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125 | ||||
119 |
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126 | force_tick <= '0'; | |
120 | previous_force_tick <= '0'; |
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127 | previous_force_tick <= '0'; | |
121 | soft_tick <= '0'; |
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128 | soft_tick <= '0'; | |
@@ -145,8 +152,9 BEGIN | |||||
145 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN |
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152 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
146 | CASE apbi.paddr(7 DOWNTO 2) IS |
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153 | CASE apbi.paddr(7 DOWNTO 2) IS | |
147 | WHEN "000000" => |
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154 | WHEN "000000" => | |
148 | r.ctrl <= apbi.pwdata(0); |
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155 | r.ctrl <= apbi.pwdata(0); | |
149 | r.soft_reset <= apbi.pwdata(1); |
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156 | r.soft_reset <= apbi.pwdata(1); | |
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157 | r.LFR_soft_reset <= apbi.pwdata(2); | |||
150 | WHEN "000001" => |
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158 | WHEN "000001" => | |
151 | r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); |
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159 | r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); | |
152 | coarsetime_reg_updated <= '1'; |
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160 | coarsetime_reg_updated <= '1'; | |
@@ -168,7 +176,8 BEGIN | |||||
168 | WHEN "000000" => |
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176 | WHEN "000000" => | |
169 | Rdata(0) <= r.ctrl; |
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177 | Rdata(0) <= r.ctrl; | |
170 | Rdata(1) <= r.soft_reset; |
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178 | Rdata(1) <= r.soft_reset; | |
171 | Rdata(31 DOWNTO 1) <= (others => '0'); |
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179 | Rdata(2) <= r.LFR_soft_reset; | |
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180 | Rdata(31 DOWNTO 3) <= (others => '0'); | |||
172 | WHEN "000001" => |
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181 | WHEN "000001" => | |
173 | Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); |
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182 | Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); | |
174 | WHEN "000010" => |
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183 | WHEN "000010" => |
@@ -44,7 +44,8 PACKAGE lpp_lfr_time_management IS | |||||
44 | apbi : IN apb_slv_in_type; --! APB slave input signals |
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44 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
45 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
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45 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
46 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
|
46 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
47 |
fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine |
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47 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME | |
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48 | LFR_soft_rstn : OUT STD_LOGIC | |||
48 |
|
|
49 | ); | |
49 | END COMPONENT; |
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50 | END COMPONENT; | |
50 |
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51 |
@@ -181,7 +181,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
181 | SIGNAL burst_f1 : STD_LOGIC; |
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181 | SIGNAL burst_f1 : STD_LOGIC; | |
182 | SIGNAL burst_f2 : STD_LOGIC; |
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182 | SIGNAL burst_f2 : STD_LOGIC; | |
183 |
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183 | |||
184 | SIGNAL run : STD_LOGIC; |
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184 | --SIGNAL run : STD_LOGIC; | |
185 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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185 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
186 |
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186 | |||
187 | ----------------------------------------------------------------------------- |
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187 | ----------------------------------------------------------------------------- | |
@@ -255,7 +255,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
255 | SIGNAL data_ms_done : STD_LOGIC; |
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255 | SIGNAL data_ms_done : STD_LOGIC; | |
256 | SIGNAL dma_ms_ongoing : STD_LOGIC; |
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256 | SIGNAL dma_ms_ongoing : STD_LOGIC; | |
257 |
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257 | |||
258 | SIGNAL run_ms : STD_LOGIC; |
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258 | -- SIGNAL run_ms : STD_LOGIC; | |
259 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
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259 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
260 |
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260 | |||
261 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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261 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
@@ -282,7 +282,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
282 | SIGNAL dma_grant_error : STD_LOGIC; |
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282 | SIGNAL dma_grant_error : STD_LOGIC; | |
283 |
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283 | |||
284 | ----------------------------------------------------------------------------- |
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284 | ----------------------------------------------------------------------------- | |
285 | SIGNAL run_dma : STD_LOGIC; |
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285 | -- SIGNAL run_dma : STD_LOGIC; | |
286 | BEGIN |
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286 | BEGIN | |
287 |
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287 | |||
288 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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288 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
@@ -335,7 +335,7 BEGIN | |||||
335 | apbi => apbi, |
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335 | apbi => apbi, | |
336 | apbo => apbo, |
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336 | apbo => apbo, | |
337 |
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337 | |||
338 |
run_ms => |
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338 | run_ms => OPEN,--run_ms, | |
339 |
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339 | |||
340 | ready_matrix_f0 => ready_matrix_f0, |
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340 | ready_matrix_f0 => ready_matrix_f0, | |
341 | ready_matrix_f1 => ready_matrix_f1, |
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341 | ready_matrix_f1 => ready_matrix_f1, | |
@@ -383,7 +383,7 BEGIN | |||||
383 | burst_f0 => burst_f0, |
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383 | burst_f0 => burst_f0, | |
384 | burst_f1 => burst_f1, |
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384 | burst_f1 => burst_f1, | |
385 | burst_f2 => burst_f2, |
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385 | burst_f2 => burst_f2, | |
386 |
run => |
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386 | run => OPEN, --run, | |
387 | start_date => start_date, |
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387 | start_date => start_date, | |
388 | -- debug_signal => debug_signal, |
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388 | -- debug_signal => debug_signal, | |
389 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO |
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389 | wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO | |
@@ -410,7 +410,7 BEGIN | |||||
410 | clk => clk, |
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410 | clk => clk, | |
411 | rstn => rstn, |
|
411 | rstn => rstn, | |
412 |
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412 | |||
413 |
reg_run => |
|
413 | reg_run => '1',--run, | |
414 | reg_start_date => start_date, |
|
414 | reg_start_date => start_date, | |
415 | reg_delta_snapshot => delta_snapshot, |
|
415 | reg_delta_snapshot => delta_snapshot, | |
416 | reg_delta_f0 => delta_f0, |
|
416 | reg_delta_f0 => delta_f0, | |
@@ -481,7 +481,7 BEGIN | |||||
481 |
|
481 | |||
482 | ------------------------------------------------------------------------------- |
|
482 | ------------------------------------------------------------------------------- | |
483 |
|
483 | |||
484 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
484 | --ms_softandhard_rstn <= rstn AND run_ms AND run; | |
485 |
|
485 | |||
486 | ----------------------------------------------------------------------------- |
|
486 | ----------------------------------------------------------------------------- | |
487 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
487 | lpp_lfr_ms_1 : lpp_lfr_ms | |
@@ -492,8 +492,10 BEGIN | |||||
492 | --rstn => ms_softandhard_rstn, --rstn, |
|
492 | --rstn => ms_softandhard_rstn, --rstn, | |
493 | rstn => rstn, |
|
493 | rstn => rstn, | |
494 |
|
494 | |||
495 |
run => |
|
495 | run => '1',--run_ms, | |
496 |
|
496 | |||
|
497 | start_date => start_date, | |||
|
498 | ||||
497 |
|
|
499 | coarse_time => coarse_time, | |
498 | fine_time => fine_time, |
|
500 | fine_time => fine_time, | |
499 |
|
501 | |||
@@ -539,7 +541,7 BEGIN | |||||
539 | matrix_time_f2 => matrix_time_f2); |
|
541 | matrix_time_f2 => matrix_time_f2); | |
540 |
|
542 | |||
541 | ----------------------------------------------------------------------------- |
|
543 | ----------------------------------------------------------------------------- | |
542 | run_dma <= run_ms OR run; |
|
544 | --run_dma <= run_ms OR run; | |
543 |
|
545 | |||
544 | DMA_SubSystem_1 : DMA_SubSystem |
|
546 | DMA_SubSystem_1 : DMA_SubSystem | |
545 | GENERIC MAP ( |
|
547 | GENERIC MAP ( | |
@@ -547,7 +549,7 BEGIN | |||||
547 | PORT MAP ( |
|
549 | PORT MAP ( | |
548 | clk => clk, |
|
550 | clk => clk, | |
549 | rstn => rstn, |
|
551 | rstn => rstn, | |
550 |
run => |
|
552 | run => '1',--run_dma, | |
551 | ahbi => ahbi, |
|
553 | ahbi => ahbi, | |
552 | ahbo => ahbo, |
|
554 | ahbo => ahbo, | |
553 |
|
555 |
@@ -381,7 +381,7 BEGIN -- beh | |||||
381 | reg_wp.delta_f2 <= (OTHERS => '0'); |
|
381 | reg_wp.delta_f2 <= (OTHERS => '0'); | |
382 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
382 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
383 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
|
383 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
384 |
reg_wp.start_date <= (OTHERS => ' |
|
384 | reg_wp.start_date <= (OTHERS => '1'); | |
385 |
|
385 | |||
386 | reg_wp.status_ready_buffer_f <= (OTHERS => '0'); |
|
386 | reg_wp.status_ready_buffer_f <= (OTHERS => '0'); | |
387 | reg_wp.length_buffer <= (OTHERS => '0'); |
|
387 | reg_wp.length_buffer <= (OTHERS => '0'); | |
@@ -692,7 +692,7 BEGIN -- beh | |||||
692 | clk => HCLK, |
|
692 | clk => HCLK, | |
693 | rstn => HRESETn, |
|
693 | rstn => HRESETn, | |
694 |
|
694 | |||
695 |
run => |
|
695 | run => '1',--reg_sp.config_ms_run, | |
696 |
|
696 | |||
697 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, |
|
697 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |
698 | reg0_ready_matrix => reg0_ready_matrix_f0, |
|
698 | reg0_ready_matrix => reg0_ready_matrix_f0, | |
@@ -714,7 +714,7 BEGIN -- beh | |||||
714 | clk => HCLK, |
|
714 | clk => HCLK, | |
715 | rstn => HRESETn, |
|
715 | rstn => HRESETn, | |
716 |
|
716 | |||
717 |
run => |
|
717 | run => '1',--reg_sp.config_ms_run, | |
718 |
|
718 | |||
719 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, |
|
719 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |
720 | reg0_ready_matrix => reg0_ready_matrix_f1, |
|
720 | reg0_ready_matrix => reg0_ready_matrix_f1, | |
@@ -736,7 +736,7 BEGIN -- beh | |||||
736 | clk => HCLK, |
|
736 | clk => HCLK, | |
737 | rstn => HRESETn, |
|
737 | rstn => HRESETn, | |
738 |
|
738 | |||
739 |
run => |
|
739 | run => '1',--reg_sp.config_ms_run, | |
740 |
|
740 | |||
741 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, |
|
741 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |
742 | reg0_ready_matrix => reg0_ready_matrix_f2, |
|
742 | reg0_ready_matrix => reg0_ready_matrix_f2, | |
@@ -760,7 +760,7 BEGIN -- beh | |||||
760 | clk => HCLK, |
|
760 | clk => HCLK, | |
761 | rstn => HRESETn, |
|
761 | rstn => HRESETn, | |
762 |
|
762 | |||
763 |
run => |
|
763 | run => '1',--reg_wp.run, | |
764 |
|
764 | |||
765 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), |
|
765 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), | |
766 | reg0_ready_matrix => reg_ready_buffer_f(2*I), |
|
766 | reg0_ready_matrix => reg_ready_buffer_f(2*I), |
@@ -1,5 +1,6 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |||
3 |
|
4 | |||
4 |
|
5 | |||
5 | LIBRARY lpp; |
|
6 | LIBRARY lpp; | |
@@ -26,6 +27,7 ENTITY lpp_lfr_ms IS | |||||
26 | --------------------------------------------------------------------------- |
|
27 | --------------------------------------------------------------------------- | |
27 | -- DATA INPUT |
|
28 | -- DATA INPUT | |
28 | --------------------------------------------------------------------------- |
|
29 | --------------------------------------------------------------------------- | |
|
30 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |||
29 | -- TIME |
|
31 | -- TIME | |
30 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
32 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
31 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
33 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
@@ -253,9 +255,37 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||||
253 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; |
|
255 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; | |
254 |
|
256 | |||
255 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
257 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
258 | ----------------------------------------------------------------------------- | |||
|
259 | SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
260 | SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
261 | SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
262 | SIGNAL ongoing : STD_LOGIC; | |||
256 |
|
263 | |||
257 | BEGIN |
|
264 | BEGIN | |
258 |
|
265 | |||
|
266 | PROCESS (clk, rstn) | |||
|
267 | BEGIN -- PROCESS | |||
|
268 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
269 | sample_f0_wen_s <= (OTHERS => '1'); | |||
|
270 | sample_f1_wen_s <= (OTHERS => '1'); | |||
|
271 | sample_f2_wen_s <= (OTHERS => '1'); | |||
|
272 | ongoing <= '0'; | |||
|
273 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
274 | IF ongoing = '1' THEN | |||
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275 | sample_f0_wen_s <= sample_f0_wen; | |||
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276 | sample_f1_wen_s <= sample_f1_wen; | |||
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277 | sample_f2_wen_s <= sample_f2_wen; | |||
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278 | ELSE | |||
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279 | IF start_date = coarse_time(30 DOWNTO 0) THEN | |||
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280 | ongoing <= '1'; | |||
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281 | END IF; | |||
|
282 | sample_f0_wen_s <= (OTHERS => '1'); | |||
|
283 | sample_f1_wen_s <= (OTHERS => '1'); | |||
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284 | sample_f2_wen_s <= (OTHERS => '1'); | |||
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285 | END IF; | |||
|
286 | END IF; | |||
|
287 | END PROCESS; | |||
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288 | ||||
259 |
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289 | ||
260 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
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290 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
261 |
|
291 | |||
@@ -265,7 +295,7 BEGIN | |||||
265 | clk => clk, |
|
295 | clk => clk, | |
266 | rstn => rstn, |
|
296 | rstn => rstn, | |
267 |
|
297 | |||
268 | sample_wen => sample_f0_wen, |
|
298 | sample_wen => sample_f0_wen_s, | |
269 |
|
299 | |||
270 | fifo_A_empty => sample_f0_A_empty, |
|
300 | fifo_A_empty => sample_f0_A_empty, | |
271 | fifo_A_full => sample_f0_A_full, |
|
301 | fifo_A_full => sample_f0_A_full, | |
@@ -332,7 +362,7 BEGIN | |||||
332 | -- sample_f1_wdata in |
|
362 | -- sample_f1_wdata in | |
333 | -- sample_f1_full OUT |
|
363 | -- sample_f1_full OUT | |
334 |
|
364 | |||
335 | sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1'; |
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365 | sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1'; | |
336 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; |
|
366 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; | |
337 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
367 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |
338 |
|
368 | |||
@@ -374,7 +404,7 BEGIN | |||||
374 | almost_full => sample_f1_almost_full); |
|
404 | almost_full => sample_f1_almost_full); | |
375 |
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405 | |||
376 |
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406 | |||
377 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
407 | one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1'; | |
378 |
|
408 | |||
379 | PROCESS (clk, rstn) |
|
409 | PROCESS (clk, rstn) | |
380 | BEGIN -- PROCESS |
|
410 | BEGIN -- PROCESS | |
@@ -417,7 +447,7 BEGIN | |||||
417 | almost_full => OPEN); |
|
447 | almost_full => OPEN); | |
418 |
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448 | |||
419 |
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449 | |||
420 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
450 | one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1'; | |
421 |
|
451 | |||
422 | PROCESS (clk, rstn) |
|
452 | PROCESS (clk, rstn) | |
423 | BEGIN -- PROCESS |
|
453 | BEGIN -- PROCESS |
@@ -74,6 +74,7 PACKAGE lpp_lfr_pkg IS | |||||
74 | clk : IN STD_LOGIC; |
|
74 | clk : IN STD_LOGIC; | |
75 | rstn : IN STD_LOGIC; |
|
75 | rstn : IN STD_LOGIC; | |
76 | run : IN STD_LOGIC; |
|
76 | run : IN STD_LOGIC; | |
|
77 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |||
77 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
79 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
80 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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