##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

5 FIFO Matrix added (VHDL,C)
martin -
r94:87d4a9c4bb62 martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,193
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity TopMatrix_PDR is
27 generic(
28 Input_SZ : integer := 16);
29 port(
30 clk : in std_logic;
31 reset : in std_logic;
32 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
33 FULLin : in std_logic_vector(4 downto 0);
34 READin : in std_logic_vector(1 downto 0);
35 WRITEin : in std_logic;
36 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
37 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
38 Start : out std_logic;
39 Read : out std_logic_vector(4 downto 0);
40 Statu : out std_logic_vector(3 downto 0)
41 );
42 end entity;
43
44 architecture ar_TopMatrix_PDR of TopMatrix_PDR is
45
46 type state is (st0,st1,st2,st3);
47 signal ect : state;
48
49 signal i,j : integer;
50 signal full_int : std_logic_vector(1 downto 0);
51 signal WRITEin_reg : std_logic;
52
53 begin
54 process(clk,reset)
55 begin
56
57 if(reset='0')then
58 i <= 1;
59 j <= 0;
60 Start <= '0';
61 WRITEin_reg <= '0';
62 ect <= st0;
63
64 elsif(clk'event and clk='1')then
65 WRITEin_reg <= WRITEin;
66
67 case ect is
68
69 when st0 =>
70 if(full_int = "11")then
71 Start <= '1';
72 ect <= st1;
73 end if;
74
75 when st1 =>
76 if(WRITEin_reg='1' and WRITEin='0')then
77 if(i=1 or i=3 or i=6 or i=10 or i=15)then
78 ect <= st2;
79 else
80 ect <= st3;
81 end if;
82 end if;
83
84 when st2 =>
85 if(j=127)then
86 if(i=15)then
87 i <= 1;
88 else
89 i <= i+1;
90 end if;
91 j <= 0;
92 Start <= '0';
93 ect <= st0;
94 elsif(WRITEin_reg='1' and WRITEin='0')then
95 j <= j+1;
96 end if;
97
98 when st3 =>
99 if(j=255)then
100 j <= 0;
101 i <= i+1;
102 Start <= '0';
103 ect <= st0;
104 elsif(WRITEin_reg='1' and WRITEin='0')then
105 j <= j+1;
106 end if;
107
108 end case;
109 end if;
110 end process;
111
112 Statu <= std_logic_vector(to_unsigned(i,4));
113
114 with i select
115 FIFO1 <= Data(15 downto 0) when 1,
116 Data(15 downto 0) when 2,
117 Data(31 downto 16) when 3,
118 Data(15 downto 0) when 4,
119 Data(31 downto 16) when 5,
120 Data(47 downto 32) when 6,
121 Data(15 downto 0) when 7,
122 Data(31 downto 16) when 8,
123 Data(47 downto 32) when 9,
124 Data(63 downto 48) when 10,
125 Data(15 downto 0) when 11,
126 Data(31 downto 16) when 12,
127 Data(47 downto 32) when 13,
128 Data(63 downto 48) when 14,
129 Data(79 downto 64) when 15,
130 X"0000" when others;
131
132
133 with i select
134 FIFO2 <= (others => '0') when 1,
135 Data(31 downto 16) when 2,
136 (others => '0') when 3,
137 Data(47 downto 32) when 4,
138 Data(47 downto 32) when 5,
139 (others => '0') when 6,
140 Data(63 downto 48) when 7,
141 Data(63 downto 48) when 8,
142 Data(63 downto 48) when 9,
143 (others => '0') when 10,
144 Data(79 downto 64) when 11,
145 Data(79 downto 64) when 12,
146 Data(79 downto 64) when 13,
147 Data(79 downto 64) when 14,
148 (others => '0') when 15,
149 X"0000" when others;
150
151 with i select
152 Read <= "1111" & not READin(0) when 1,
153 "111" & not READin(1) & not READin(0) when 2,
154 "111" & not READin(0) & '1' when 3,
155 "11" & not READin(1) & '1' & not READin(0) when 4,
156 "11" & not READin(1) & not READin(0) & '1' when 5,
157 "11" & not READin(0) & "11" when 6,
158 "1" & not READin(1) & "11" & not READin(0) when 7,
159 '1' & not READin(1) & '1' & not READin(0) & '1' when 8,
160 '1' & not READin(1) & not READin(0) & "11" when 9,
161 '1' & not READin(0) & "111" when 10,
162 not READin(1) & "111" & not READin(0) when 11,
163 not READin(1) & "11" & not READin(0) & '1' when 12,
164 not READin(1) & '1' & not READin(0) & "11" when 13,
165 not READin(1) & not READin(0) & "111" when 14,
166 not READin(0) & "1111" when 15,
167 "11111" when others;
168
169 with i select
170 full_int <= FULLin(0) & FULLin(0) when 1,
171 FULLin(1) & FULLin(0) when 2,
172 FULLin(1) & FULLin(1) when 3,
173 FULLin(2) & FULLin(0) when 4,
174 FULLin(2) & FULLin(1) when 5,
175 FULLin(2) & FULLin(2) when 6,
176 FULLin(3) & FULLin(0) when 7,
177 FULLin(3) & FULLin(1) when 8,
178 FULLin(3) & FULLin(2) when 9,
179 FULLin(3) & FULLin(3) when 10,
180 FULLin(4) & FULLin(0) when 11,
181 FULLin(4) & FULLin(1) when 12,
182 FULLin(4) & FULLin(2) when 13,
183 FULLin(4) & FULLin(3) when 14,
184 FULLin(4) & FULLin(4) when 15,
185 "00" when others;
186
187 end architecture;
188
189
190
191
192
193
Show file before | Show file after | Hide comments
@@ -26,17 +26,16 int main()
26 26 {
27 27 int d=0;
28 28 int i=0;
29 FIFO_Device* FIFO0;
30 FIFO0 = openFIFO(0);
29 FIFO_Device* FIFO0 = openFIFO(0);
31 30
32 31 for(i=0;i<1024;i++)
33 32 {
34 FIFO0->rwdata = i;
33 FIFO0->FIFOreg[(2*0)+FIFO_RWdata] = i;
35 34 }
36 35
37 36 for(i=0;i<1024;i++)
38 37 {
39 printf("%x",FIFO0->rwdata);
38 printf("%x",FIFO0->FIFOreg[(2*0)+FIFO_RWdata]);
40 39 }
41 40
42 41
Show file before | Show file after | Hide comments
@@ -6,11 +6,11
6 6 #include "apb_delay_Driver.h"
7 7 #include "apb_gpio_Driver.h"
8 8
9 // Matrix With 2 FIFO Input
9 10 int main()
10 11 {
11 12 int i=0,save;
12 13 char temp[256];
13 //int TblX[10] = {0x11,0x22,0x33,0x04,0x05,0x06,0x07,0x08,0x09,0x0a};
14 14 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
15 15 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
16 16 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
@@ -109,7 +109,53 int main()
109 109 }
110 110
111 111
112 // Matrix With 5 FIFO Input
113 int main2()
114 {
115 int save1,save2;
116 char temp[256];
117 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
118 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
119 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
120 int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
121 int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
112 122
123 FIFO_Device* fifoX = openFIFO(0);
124 UART_Device* uart0 = openUART(0);
125 FIFO_Device* fifoIn = openFIFO(1);
126 FIFO_Device* fifoOut = openFIFO(2);
127
128 printf("\nDebut Main\n\n");
129
130 FillFifo(fifoIn,0,TblB1);
131 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
132
133 FillFifo(fifoIn,1,TblB2);
134 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
135
136 FillFifo(fifoIn,2,TblB3);
137 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
138
139 FillFifo(fifoIn,3,TblE1);
140 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
141
142 FillFifo(fifoIn,4,TblE2);
143
144 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
145
146 while(1){
147
148 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
149
150 save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
151 save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
152
153 sprintf(temp,"%d\t%d\n\r",save1,save2);
154 uartputs(uart0,temp);
155 }
156 printf("\nFin Main\n\n");
157 return 0;
158 }
113 159
114 160
115 161
@@ -130,129 +176,3 int main()
130 176 printf("data: %x\n",Table[3]);
131 177 printf("data: %x\n",Table[4]);*/
132 178
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160 /*int main()
161 {
162 int i=0;
163 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
164 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
165 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
166 int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
167 int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
168
169
170 printf("\nDebut Main\n\n");
171
172 FIFO_Device* fifoB1 = openFIFO(0);
173 FIFO_Device* fifoB2 = openFIFO(1);
174 FIFO_Device* fifoB3 = openFIFO(2);
175 FIFO_Device* fifoE1 = openFIFO(3);
176 FIFO_Device* fifoE2 = openFIFO(4);
177
178 for (i = 0 ; i < 256 ; i++)
179 {
180 fifoB1->rwdata = TblB1[i];
181 fifoB2->rwdata = TblB2[i];
182 fifoB3->rwdata = TblB3[i];
183 fifoE1->rwdata = TblE1[i];
184 fifoE2->rwdata = TblE2[i];
185 }
186
187 fifoB1->cfgreg = fifoB1->cfgreg | Boucle;
188 fifoB2->cfgreg = fifoB2->cfgreg | Boucle;
189 fifoB3->cfgreg = fifoB3->cfgreg | Boucle;
190 fifoE1->cfgreg = fifoE1->cfgreg | Boucle;
191 fifoE2->cfgreg = fifoE2->cfgreg | Boucle;
192
193 printf("\t*** Boucl� ***\n\n");
194
195 return 0;
196 }*/
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225 /*
226 while((fifoB1->cfgreg & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
227 {
228 while((Mspec0->Cfg & Read) != Read); // TANT QUE read a 0 RIEN
229
230 Mspec0->IN1 = fifoB1->rwdata;
231 Mspec0->IN2 = fifoB1->rwdata;
232 Mspec0->Cfg = 0x1;
233 printf("Input: %x / %x\n",Mspec0->IN1,Mspec0->IN2);
234
235 while((Mspec0->Cfg & Read) != Read); // TANT QUE read a 0 RIEN
236
237 Mspec0->IN1 = fifoB1->rwdata;
238 Mspec0->IN2 = fifoB1->rwdata;
239 Mspec0->Cfg = 0x0;
240 printf("Input: %x / %x\n",Mspec0->IN1,Mspec0->IN2);
241
242 while((Mspec0->Cfg & Valid) != Valid); // TANT QUE valid a 0 RIEN
243
244 //printf("Result: %d\n",Mspec0->RES);
245 Mspec0->Cfg = 0x100;
246 TabResB1B1[i] = Mspec0->RES;
247 i++;
248 printf("Result: %d\n",Mspec0->RES);
249
250 while((Mspec0->Cfg & Valid) != Valid); // TANT QUE valid a 0 RIEN
251
252 //printf("Result: %d\n",Mspec0->RES);
253 Mspec0->Cfg = 0x000;
254 TabResB1B1[i] = Mspec0->RES;
255 i++;
256 printf("Result: %d\n",Mspec0->RES);
257 }
258 */
Show file before | Show file after | Hide comments
@@ -28,12 +28,18
28 28 This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working,
29 29 used in many type of application.
30 30
31 \todo Check "DEVICE1 => count = 2" function Open
31 32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
32 33 */
33 #define FIFO_Empty 0x00000100 /**< Show that the FIFO is Empty */
34 #define FIFO_Full 0x00001000 /**< Show that the FIFO is Full */
35 #define Boucle 0x00110000 /**< Configuration for reused the same value of the FIFO */
36 #define NoBoucle 0xFFEEFFFF /**< Unlock the previous configuration */
34 #define FIFO_Ctrl 0
35 #define FIFO_RWdata 1
36
37 #define FIFO_Full 0x00010000
38 #define FIFO_Empty 0x00000001
39 #define FIFO_ReUse 0x00000002
40
41 #define Mask_2hex 0x000000FF
42 #define Mask_4hex 0x0000FFFF
37 43
38 44
39 45 /*===================================================
@@ -45,18 +51,8
45 51 */
46 52 struct APB_FIFO_REG
47 53 {
48 int rwdata; /**< \brief Data register Write/Read */
49 int raddr; /**< \brief Address register for the reading operation */
50 int cfgreg; /**< \brief Configuration register composed of Read enable Flag [HEX 0]
51 Write enable Flag [HEX 1]
52 Empty Flag [HEX 2]
53 Full Flag [HEX 3]
54 ReUse Flag [HEX 4]
55 Lock Flag [HEX 5]
56 Dummy "C" [HEX 6/7] */
57 int dummy0; /**< \brief Unused register, aesthetic interest */
58 int dummy1; /**< \brief Unused register, aesthetic interest */
59 int waddr; /**< \brief Address register for the writing operation */
54 int IDreg;
55 int FIFOreg[2*8];
60 56 };
61 57
62 58 typedef volatile struct APB_FIFO_REG FIFO_Device;
@@ -75,16 +71,6 typedef volatile struct APB_FIFO_REG FIF
75 71 \return The pointer to the device.
76 72 */
77 73 FIFO_Device* openFIFO(int count);
78
79 /*! \fn int FillFifo(FIFO_Device* dev,int Tbl[],int A);
80 \brief a Fill in FIFO function.
81
82 This Function fill in the FIFO with a table data.
83
84 \param dev The FFT pointer.
85 \param Tbl[] The data table.
86 \param A The data table size.
87 */
88 int FillFifo(FIFO_Device* dev,int Tbl[],int A);
74 int FillFifo(FIFO_Device* dev,int ID,int Tbl[]);
89 75
90 76 #endif
Show file before | Show file after | Hide comments
@@ -33,8 +33,11
33 33 */
34 34 #define FIFO_Ctrl 0
35 35 #define FIFO_RWdata 1
36
36 37 #define FIFO_Full 0x00010000
37 38 #define FIFO_Empty 0x00000001
39 #define FIFO_ReUse 0x00000002
40
38 41 #define Mask_2hex 0x000000FF
39 42 #define Mask_4hex 0x0000FFFF
40 43
@@ -50,7 +53,6 struct APB_FIFO_REG
50 53 {
51 54 int IDreg;
52 55 int FIFOreg[2*8];
53
54 56 };
55 57
56 58 typedef volatile struct APB_FIFO_REG FIFO_Device;
Show file before | Show file after | Hide comments
@@ -42,26 +42,15 entity APB_Matrix is
42 42 Input_SZ : integer := 16;
43 43 Result_SZ : integer := 32);
44 44 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
51 ReadFIFO : out std_logic_vector(1 downto 0);
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 ReadFIFO : out std_logic_vector(1 downto 0);
52 50 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 Start : out std_logic;
55 Read : out std_logic;
56 Take : out std_logic;
57 Valid : out std_logic;
58 Received : out std_logic;
59 Res : out std_logic_vector(Result_SZ-1 downto 0);
60 -- Conjugate : out std_logic;
61 OP1 : out std_logic_vector(3 downto 0);
62 OP2 : out std_logic_vector(3 downto 0);
63 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
64 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 Result : out std_logic_vector(Result_SZ-1 downto 0);
52 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
65 54 );
66 55 end APB_Matrix;
67 56
@@ -75,22 +64,27 constant pconfig : apb_config_type := (
75 64 1 => apb_iobar(paddr, pmask));
76 65
77 66 type MATRIX_ctrlr_Reg is record
78 MATRIX_Statu : std_logic_vector(3 downto 0);
67 MATRIX_Ctrl : std_logic_vector(4 downto 0);
79 68 end record;
80 69
81 70 signal Rec : MATRIX_ctrlr_Reg;
82 71 signal Rdata : std_logic_vector(31 downto 0);
72 signal Start : std_logic;
73 signal statu : std_logic_vector(3 downto 0);
83 74
84 75 begin
85 76
86 77 Mspec0 : SpectralMatrix
87 78 generic map (Input_SZ,Result_SZ)
88 port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Read,Take,Valid,Received,Res,OP1,OP2,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2
79 port map(clk,rst,Start,FIFO1,FIFO2,Statu,ReadFIFO,WriteFIFO,Result);
80
81 Statu <= Rec.MATRIX_Ctrl(3 downto 0);
82 Start <= Rec.MATRIX_Ctrl(4);
89 83
90 84 process(rst,clk)
91 85 begin
92 86 if(rst='0')then
93 Rec.MATRIX_Statu <= (others => '0');
87 Rec.MATRIX_Ctrl <= (others => '0');
94 88
95 89 elsif(clk'event and clk='1')then
96 90
@@ -98,26 +92,18 Mspec0 : SpectralMatrix
98 92 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
99 93 case apbi.paddr(abits-1 downto 2) is
100 94 when "000000" =>
101 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
95 Rec.MATRIX_Ctrl <= apbi.pwdata(4 downto 0);
102 96 when others =>
103 97 null;
104 98 end case;
105 99 end if;
106 100
107 --APB READ OP
101 --APB Read OP
108 102 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
109 103 case apbi.paddr(abits-1 downto 2) is
110 104 when "000000" =>
111 Rdata(31 downto 4) <= (others => '0');
112 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
113 --when "000001" =>
114 -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
115 -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
116 -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
117 -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
118 -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4);
119 -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5);
120 -- Rdata(31 downto 24) <= X"CC";
105 Rdata(31 downto 5) <= (others => '0');
106 Rdata(4 downto 0) <= Rec.MATRIX_Ctrl;
121 107 when others =>
122 108 Rdata <= (others => '0');
123 109 end case;
Show file before | Show file after | Hide comments
@@ -25,17 +25,12 use IEEE.std_logic_1164.all;
25 25
26 26 entity DriveInputs is
27 27 port(
28 clk : in std_logic;
29 raz : in std_logic;
30 Read : in std_logic;
31 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
32 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
33 -- Statu : in std_logic_vector(3 downto 0);
34 Conjugate : in std_logic;
35 Take : out std_logic;
36 ReadFIFO : out std_logic_vector(1 downto 0)
37 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
38 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
28 clk : in std_logic;
29 raz : in std_logic;
30 Read : in std_logic;
31 Conjugate : in std_logic;
32 Take : out std_logic;
33 ReadFIFO : out std_logic_vector(1 downto 0)
39 34 );
40 35 end DriveInputs;
41 36
@@ -43,9 +38,7 end DriveInputs;
43 38 architecture ar_DriveInputs of DriveInputs is
44 39
45 40 signal Read_reg : std_logic;
46 signal i : integer range 0 to 128;
47 --signal j : integer range 0 to 15;
48 --signal Read_int : std_logic_vector(4 downto 0);
41 signal i : integer range 0 to 128;
49 42
50 43 type state is (stX,sta,stb,st1,st2,idl1,idl2);
51 44 signal ect : state;
@@ -58,7 +51,6 begin
58 51 Take <= '0';
59 52 i <= 0;
60 53 ReadFIFO <= "00";
61 -- j <= 0;
62 54 Read_reg <= '0';
63 55 ect <= stX;
64 56
@@ -70,11 +62,6 begin
70 62 when stX =>
71 63 i <= 1;
72 64 if(Read_reg='0' and Read='1')then
73 -- if(j=15)then
74 -- j <= 1;
75 -- else
76 -- j<= j+1;
77 -- end if;
78 65 ect <= idl1;
79 66 end if;
80 67
@@ -109,7 +96,7 begin
109 96 ect <= stb;
110 97
111 98 when stb =>
112 Take <= '0';
99 Take <= '0';
113 100 if(i=128)then
114 101 ect <= stX;
115 102 elsif(Read_reg='0' and Read='1')then
Show file before | Show file after | Hide comments
@@ -32,8 +32,8 port(
32 32 Valid : in std_logic;
33 33 Conjugate : in std_logic;
34 34 Res : in std_logic_vector(Result_SZ-1 downto 0);
35 -- Full : in std_logic;
36 WriteFIFO : out std_logic;
35 Full : in std_logic;
36 WriteFIFO : out std_logic;
37 37 Received : out std_logic;
38 38 Result : out std_logic_vector(Result_SZ-1 downto 0)
39 39 );
@@ -44,7 +44,7 architecture ar_GetResult of GetResult i
44 44
45 45 signal Valid_reg : std_logic;
46 46
47 type state is (st0,st1);
47 type state is (st0,st1,stX,stY);
48 48 signal ect : state;
49 49
50 50 begin
@@ -63,25 +63,37 begin
63 63
64 64 case ect is
65 65 when st0 =>
66 Received <= '0';
67 WriteFIFO <= '0';
68 if(Valid_reg='0' and Valid='1')then
66 if(Full='0' and Valid='1')then
69 67 Result <= Res;
70 68 WriteFIFO <= '1';
69 Received <= '1';
70 ect <= stX;
71 end if;
72
73 when stX =>
74 WriteFIFO <= '0';
75 if(Conjugate='1')then
76 Received <= '0';
77 end if;
78 if(Valid_reg='1' and Valid='0')then
71 79 if(Conjugate='1')then
72 Received <= '1';
73 80 ect <= st0;
74 81 else
75 82 ect <= st1;
76 end if;
77 end if;
78
79 when st1 =>
80 Received <= '1';
81 WriteFIFO <= '0';
82 if(Valid_reg='0' and Valid='1')then
83 end if;
84 end if;
85
86 when st1 =>
87 if(Full='0' and Valid='1')then
83 88 Result <= Res;
84 89 WriteFIFO <= '1';
90 Received <= '0';
91 ect <= stY;
92 end if;
93
94 when stY =>
95 WriteFIFO <= '0';
96 if(Valid_reg='1' and Valid='0')then
85 97 ect <= st0;
86 98 end if;
87 99
Show file before | Show file after | Hide comments
@@ -39,8 +39,6 entity Matrix is
39 39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 40 Valid : out std_logic; --! Flag, R�sultat disponible
41 41 Read : out std_logic; --! Flag, op�rande disponible
42 OPin1 : out std_logic_vector(3 downto 0);
43 OPin2 : out std_logic_vector(3 downto 0);
44 42 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
45 43 );
46 44 end Matrix;
@@ -53,9 +51,6 signal OP1 : std_logic_vector(Input_SZ
53 51 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
54 52
55 53 begin
56 OPin1 <= OP1(3 downto 0);
57 OPin2 <= OP1(3 downto 0);
58
59 54
60 55 DRIVE : ALU_Driver
61 56 generic map(Input_SZ,Input_SZ)
Show file before | Show file after | Hide comments
@@ -29,65 +29,48 generic(
29 29 Input_SZ : integer := 16;
30 30 Result_SZ : integer := 32);
31 31 port(
32 clk : in std_logic;
33 reset : in std_logic;
34 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
35 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
36 Full : in std_logic_vector(1 downto 0);
37 Empty : in std_logic_vector(1 downto 0);
38 Statu : in std_logic_vector(3 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
41 Start : out std_logic;
42 Read : out std_logic;
43 Take : out std_logic;
44 Valid : out std_logic;
45 Received : out std_logic;
46 Res : out std_logic_vector(Result_SZ-1 downto 0);
47 -- Conjugate : out std_logic;
48 OP1 : out std_logic_vector(3 downto 0);
49 OP2 : out std_logic_vector(3 downto 0);
50 Result : out std_logic_vector(Result_SZ-1 downto 0)
32 clk : in std_logic;
33 reset : in std_logic;
34 Start : in std_logic;
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 Statu : in std_logic_vector(3 downto 0);
38 FullFIFO : in std_logic;
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 WriteFIFO : out std_logic;
41 Result : out std_logic_vector(Result_SZ-1 downto 0)
51 42 );
52 43 end SpectralMatrix;
53 44
54 45
55 46 architecture ar_SpectralMatrix of SpectralMatrix is
56 47
57 signal Start_int : std_logic;
48 signal RaZ : std_logic;
58 49 signal Read_int : std_logic;
59 50 signal Take_int : std_logic;
60 51 signal Received_int : std_logic;
61 52 signal Valid_int : std_logic;
62 53 signal Conjugate_int : std_logic;
63 54
64 --signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
65 --signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
66 55 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
67 --signal Res : std_logic_vector(Result_SZ-1 downto 0);
68 56
69 57
70 58 begin
71 59
72 ST0 : Starter
73 port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int);
74
75 --IN0 : SelectInputs
76 -- generic map(Input_SZ)
77 -- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2);
60 RaZ <= reset and Start;
78 61
79 62 IN1 : DriveInputs
80 port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO);
63 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
81 64
82 65
83 66 CALC0 : Matrix
84 67 generic map(Input_SZ)
85 port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,OP1,OP2,Resultat);
68 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
86 69
87 70
88 71 RES0 : GetResult
89 72 generic map(Result_SZ)
90 port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,FullFIFO,WriteFIFO,Received_int,Result);
91 74
92 75
93 76 With Statu select
@@ -98,12 +81,4 With Statu select
98 81 '1' when "1111",
99 82 '0' when others;
100 83
101 Start <= Start_int;
102 Read <= Read_int;
103 Take <= Take_int;
104 Received <= Received_int;
105 Valid <= Valid_int;
106 --Conjugate <= Conjugate_int;
107 Res <= Resultat;
108
109 84 end ar_SpectralMatrix; No newline at end of file
Show file before | Show file after | Hide comments
@@ -41,26 +41,15 component APB_Matrix is
41 41 Input_SZ : integer := 16;
42 42 Result_SZ : integer := 32);
43 43 port (
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 ReadFIFO : out std_logic_vector(1 downto 0);
51 49 WriteFIFO : out std_logic;
52 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Start : out std_logic;
54 Read : out std_logic;
55 Take : out std_logic;
56 Valid : out std_logic;
57 Received : out std_logic;
58 Res : out std_logic_vector(Result_SZ-1 downto 0);
59 -- Conjugate : out std_logic;
60 OP1 : out std_logic_vector(3 downto 0);
61 OP2 : out std_logic_vector(3 downto 0);
62 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
63 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
50 Result : out std_logic_vector(Result_SZ-1 downto 0);
51 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
52 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
64 53 );
65 54 end component;
66 55
@@ -70,25 +59,16 generic(
70 59 Input_SZ : integer := 16;
71 60 Result_SZ : integer := 32);
72 61 port(
73 clk : in std_logic;
74 reset : in std_logic;
75 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
76 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
77 Full : in std_logic_vector(1 downto 0);
78 Empty : in std_logic_vector(1 downto 0);
79 Statu : in std_logic_vector(3 downto 0);
80 ReadFIFO : out std_logic_vector(1 downto 0);
81 WriteFIFO : out std_logic;
82 Start : out std_logic;
83 Read : out std_logic;
84 Take : out std_logic;
85 Valid : out std_logic;
86 Received : out std_logic;
87 Res : out std_logic_vector(Result_SZ-1 downto 0);
88 -- Conjugate : out std_logic;
89 OP1 : out std_logic_vector(3 downto 0);
90 OP2 : out std_logic_vector(3 downto 0);
91 Result : out std_logic_vector(Result_SZ-1 downto 0)
62 clk : in std_logic;
63 reset : in std_logic;
64 Start : in std_logic;
65 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
66 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
67 Statu : in std_logic_vector(3 downto 0);
68 FullFIFO : in std_logic;
69 ReadFIFO : out std_logic_vector(1 downto 0);
70 WriteFIFO : out std_logic;
71 Result : out std_logic_vector(Result_SZ-1 downto 0)
92 72 );
93 73 end component;
94 74
@@ -106,12 +86,58 component Matrix is
106 86 Conjugate : in std_logic;
107 87 Valid : out std_logic;
108 88 Read : out std_logic;
109 OPin1 : out std_logic_vector(3 downto 0);
110 OPin2 : out std_logic_vector(3 downto 0);
111 89 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
112 90 );
113 91 end component;
114 92
93 component GetResult is
94 generic(
95 Result_SZ : integer := 32);
96 port(
97 clk : in std_logic;
98 raz : in std_logic;
99 Valid : in std_logic;
100 Conjugate : in std_logic;
101 Res : in std_logic_vector(Result_SZ-1 downto 0);
102 Full : in std_logic;
103 WriteFIFO : out std_logic;
104 Received : out std_logic;
105 Result : out std_logic_vector(Result_SZ-1 downto 0)
106 );
107 end component;
108
109
110 component TopMatrix_PDR is
111 generic(
112 Input_SZ : integer := 16;
113 Result_SZ : integer := 32);
114 port(
115 clk : in std_logic;
116 reset : in std_logic;
117 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
118 FULLin : in std_logic_vector(4 downto 0);
119 READin : in std_logic_vector(1 downto 0);
120 WRITEin : in std_logic;
121 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
122 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
123 Start : out std_logic;
124 Read : out std_logic_vector(4 downto 0);
125 Statu : out std_logic_vector(3 downto 0)
126 );
127 end component;
128
129
130 component DriveInputs is
131 port(
132 clk : in std_logic;
133 raz : in std_logic;
134 Read : in std_logic;
135 Conjugate : in std_logic;
136 Take : out std_logic;
137 ReadFIFO : out std_logic_vector(1 downto 0)
138 );
139 end component;
140
115 141
116 142 component ALU_Driver is
117 143 generic(
@@ -178,72 +204,6 port(
178 204 OP : in std_logic_vector(Input_SZ-1 downto 0);
179 205 RES : out std_logic_vector(Input_SZ-1 downto 0)
180 206 );
181 end component;
182
183
184 component GetResult is
185 generic(
186 Result_SZ : integer := 32);
187 port(
188 clk : in std_logic;
189 raz : in std_logic;
190 Valid : in std_logic;
191 Conjugate : in std_logic;
192 Res : in std_logic_vector(Result_SZ-1 downto 0);
193 WriteFIFO : out std_logic;
194 Received : out std_logic;
195 Result : out std_logic_vector(Result_SZ-1 downto 0)
196 );
197 end component;
198
199
200 component SelectInputs is
201 generic(
202 Input_SZ : integer := 16);
203 port(
204 clk : in std_logic;
205 raz : in std_logic;
206 Read : in std_logic;
207 B1 : in std_logic_vector(Input_SZ-1 downto 0);
208 B2 : in std_logic_vector(Input_SZ-1 downto 0);
209 B3 : in std_logic_vector(Input_SZ-1 downto 0);
210 E1 : in std_logic_vector(Input_SZ-1 downto 0);
211 E2 : in std_logic_vector(Input_SZ-1 downto 0);
212 Conjugate : out std_logic;
213 Take : out std_logic;
214 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
215 Statu : out std_logic_vector(3 downto 0);
216 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
217 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
218 );
219 end component;
220 ---------------------------------------------------------------------------
221 component DriveInputs is
222 port(
223 clk : in std_logic;
224 raz : in std_logic;
225 Read : in std_logic;
226 -- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
227 -- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
228 -- Statu : in std_logic_vector(3 downto 0);
229 Conjugate : in std_logic;
230 Take : out std_logic;
231 ReadFIFO : out std_logic_vector(1 downto 0)
232 -- OP1 : out std_logic_vector(Input_SZ-1 downto 0);
233 -- OP2 : out std_logic_vector(Input_SZ-1 downto 0)
234 );
235 end component;
236
237 component Starter is
238 port(
239 clk : in std_logic;
240 raz : in std_logic;
241 Full : in std_logic_vector(1 downto 0);
242 Empty : in std_logic_vector(1 downto 0);
243 Conjugate : in std_logic;
244 received : in std_logic;
245 Start : out std_logic
246 );
247 207 end component;
248 208
249 209 end; No newline at end of file
Show file before | Show file after | Hide comments
@@ -101,7 +101,8 signal sRen_APB : std_logic_vector(Fifo
101 101 signal sRDATA : fifodatabus;
102 102 signal sWDATA : fifodatabus;
103 103 signal sWADDR : fifoaddressbus;
104 signal sRADDR : fifoaddressbus;
104 signal sRADDR : fifoaddressbus;
105 signal ReUse : std_logic_vector(FifoCnt-1 downto 0); --27/01/12
105 106
106 107 type state_t is (idle,Read);
107 108 signal fiforeadfsmst : state_t;
@@ -153,9 +154,13 ctrlregs: for i in 0 to FifoCnt-1 genera
153 154 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
154 155 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
155 156 Rec(i).FIFO_Ctrl(16) <= sFull(i);
156 Rec(i).FIFO_Ctrl(Addr_sz downto 1) <= sRADDR(i);
157 Rec(i).FIFO_Ctrl((Addr_sz+16) downto 17) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty|
158 end generate; -- 31 17 16 15 1 0
157 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
158 ReUse(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
159 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
160 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
161 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
162 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty|
163 end generate; -- 31 17 16 15 1 0
159 164
160 165 Empty <= sEmpty;
161 166 Full <= sFull;
@@ -164,7 +169,7 Full <= sFull;
164 169 fifos: for i in 0 to FifoCnt-1 generate
165 170 FIFO0 : lpp_fifo
166 171 generic map (tech,Data_sz,Addr_sz)
167 port map(rst,srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
172 port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
168 173 end generate;
169 174
170 175 process(rst,clk)
@@ -172,14 +177,19 end generate;
172 177 if(rst='0')then
173 178 rstloop1: for i in 0 to FifoCnt-1 loop
174 179 Rec(i).FIFO_Wdata <= (others => '0');
180 Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
181 --Rec(i).FIFO_Ctrl(17) <= '0';
175 182 sWen_APB(i) <= '1';
176 183 end loop;
177 184 elsif(clk'event and clk='1')then
178 185 --APB Write OP
179 186 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
180 writelp: for i in 0 to FifoCnt-1 loop
181 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
182 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
187 writelp: for i in 0 to FifoCnt-1 loop
188 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
189 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
190 --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
191 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
192 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
183 193 sWen_APB(i) <= '0';
184 194 end if;
185 195 end loop;
@@ -195,7 +205,7 end generate;
195 205 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
196 206 PRdata <= Rec(i).FIFO_Ctrl;
197 207 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
198 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
208 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
199 209 end if;
200 210 end loop;
201 211 end if;
Show file before | Show file after | Hide comments
@@ -35,6 +35,7 generic(
35 35 );
36 36 port(
37 37 rstn : in std_logic;
38 ReUse : in std_logic; --27/01/12
38 39 rclk : in std_logic;
39 40 ren : in std_logic;
40 41 rdata : out std_logic_vector(DataSz-1 downto 0);
@@ -84,7 +85,9 begin
84 85 Raddr_vect_d <= (others =>'1');
85 86 sempty <= '1';
86 87 elsif(rclk'event and rclk='1')then
87 if(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
88 if(ReUse = '1')then --27/01/12
89 sempty <= '0'; --27/01/12
90 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
88 91 sempty <= '1';
89 92 elsif(Raddr_vect/=Waddr_vect) then
90 93 sempty <= '0';
@@ -109,7 +112,9 begin
109 112 Waddr_vect_d <= (others =>'1');
110 113 sfull <= '0';
111 114 elsif(wclk'event and wclk='1')then
112 if(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
115 if(ReUse = '1')then --27/01/12
116 sfull <= '1'; --27/01/12
117 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
113 118 sfull <= '1';
114 119 elsif(Raddr_vect/=Waddr_vect) then
115 120 sfull <= '0';
Show file before | Show file after | Hide comments
@@ -77,6 +77,7 generic(
77 77 );
78 78 port(
79 79 rstn : in std_logic;
80 ReUse : in std_logic; --27/01/12
80 81 rclk : in std_logic;
81 82 ren : in std_logic;
82 83 rdata : out std_logic_vector(DataSz-1 downto 0);
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now