diff --git a/LPP_drivers/exemples/BenchFIFO/main.c b/LPP_drivers/exemples/BenchFIFO/main.c --- a/LPP_drivers/exemples/BenchFIFO/main.c +++ b/LPP_drivers/exemples/BenchFIFO/main.c @@ -26,17 +26,16 @@ int main() { int d=0; int i=0; - FIFO_Device* FIFO0; - FIFO0 = openFIFO(0); + FIFO_Device* FIFO0 = openFIFO(0); for(i=0;i<1024;i++) { - FIFO0->rwdata = i; + FIFO0->FIFOreg[(2*0)+FIFO_RWdata] = i; } for(i=0;i<1024;i++) { - printf("%x",FIFO0->rwdata); + printf("%x",FIFO0->FIFOreg[(2*0)+FIFO_RWdata]); } diff --git a/LPP_drivers/exemples/BenchMatrix/main.c b/LPP_drivers/exemples/BenchMatrix/main.c --- a/LPP_drivers/exemples/BenchMatrix/main.c +++ b/LPP_drivers/exemples/BenchMatrix/main.c @@ -6,11 +6,11 @@ #include "apb_delay_Driver.h" #include "apb_gpio_Driver.h" +// Matrix With 2 FIFO Input int main() { int i=0,save; char temp[256]; - //int TblX[10] = {0x11,0x22,0x33,0x04,0x05,0x06,0x07,0x08,0x09,0x0a}; int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; @@ -109,7 +109,53 @@ int main() } +// Matrix With 5 FIFO Input +int main2() +{ + int save1,save2; + char temp[256]; + int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; + int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; + int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; + int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; + int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; + FIFO_Device* fifoX = openFIFO(0); + UART_Device* uart0 = openUART(0); + FIFO_Device* fifoIn = openFIFO(1); + FIFO_Device* fifoOut = openFIFO(2); + + printf("\nDebut Main\n\n"); + + FillFifo(fifoIn,0,TblB1); + fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,1,TblB2); + fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,2,TblB3); + fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,3,TblE1); + fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,4,TblE2); + + fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); + +while(1){ + + while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN + + save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; + save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; + + sprintf(temp,"%d\t%d\n\r",save1,save2); + uartputs(uart0,temp); +} + printf("\nFin Main\n\n"); + return 0; +} @@ -130,129 +176,3 @@ int main() printf("data: %x\n",Table[3]); printf("data: %x\n",Table[4]);*/ - - - - - - - - - - - - - - - - - - - - - - - - - - - -/*int main() -{ - int i=0; - int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100}; - int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105}; - int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A}; - int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F}; - int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114}; - - - printf("\nDebut Main\n\n"); - - FIFO_Device* fifoB1 = openFIFO(0); - FIFO_Device* fifoB2 = openFIFO(1); - FIFO_Device* fifoB3 = openFIFO(2); - FIFO_Device* fifoE1 = openFIFO(3); - FIFO_Device* fifoE2 = openFIFO(4); - - for (i = 0 ; i < 256 ; i++) - { - fifoB1->rwdata = TblB1[i]; - fifoB2->rwdata = TblB2[i]; - fifoB3->rwdata = TblB3[i]; - fifoE1->rwdata = TblE1[i]; - fifoE2->rwdata = TblE2[i]; - } - - fifoB1->cfgreg = fifoB1->cfgreg | Boucle; - fifoB2->cfgreg = fifoB2->cfgreg | Boucle; - fifoB3->cfgreg = fifoB3->cfgreg | Boucle; - fifoE1->cfgreg = fifoE1->cfgreg | Boucle; - fifoE2->cfgreg = fifoE2->cfgreg | Boucle; - - printf("\t*** Bouclé ***\n\n"); - - return 0; -}*/ - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/* -while((fifoB1->cfgreg & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS - { - while((Mspec0->Cfg & Read) != Read); // TANT QUE read a 0 RIEN - - Mspec0->IN1 = fifoB1->rwdata; - Mspec0->IN2 = fifoB1->rwdata; - Mspec0->Cfg = 0x1; - printf("Input: %x / %x\n",Mspec0->IN1,Mspec0->IN2); - - while((Mspec0->Cfg & Read) != Read); // TANT QUE read a 0 RIEN - - Mspec0->IN1 = fifoB1->rwdata; - Mspec0->IN2 = fifoB1->rwdata; - Mspec0->Cfg = 0x0; - printf("Input: %x / %x\n",Mspec0->IN1,Mspec0->IN2); - - while((Mspec0->Cfg & Valid) != Valid); // TANT QUE valid a 0 RIEN - - //printf("Result: %d\n",Mspec0->RES); - Mspec0->Cfg = 0x100; - TabResB1B1[i] = Mspec0->RES; - i++; - printf("Result: %d\n",Mspec0->RES); - - while((Mspec0->Cfg & Valid) != Valid); // TANT QUE valid a 0 RIEN - - //printf("Result: %d\n",Mspec0->RES); - Mspec0->Cfg = 0x000; - TabResB1B1[i] = Mspec0->RES; - i++; - printf("Result: %d\n",Mspec0->RES); - } -*/ diff --git a/LPP_drivers/includes/apb_fifo_Driver.h b/LPP_drivers/includes/apb_fifo_Driver.h --- a/LPP_drivers/includes/apb_fifo_Driver.h +++ b/LPP_drivers/includes/apb_fifo_Driver.h @@ -28,12 +28,18 @@ This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working, used in many type of application. + \todo Check "DEVICE1 => count = 2" function Open \author Martin Morlot martin.morlot@lpp.polytechnique.fr */ -#define FIFO_Empty 0x00000100 /**< Show that the FIFO is Empty */ -#define FIFO_Full 0x00001000 /**< Show that the FIFO is Full */ -#define Boucle 0x00110000 /**< Configuration for reused the same value of the FIFO */ -#define NoBoucle 0xFFEEFFFF /**< Unlock the previous configuration */ +#define FIFO_Ctrl 0 +#define FIFO_RWdata 1 + +#define FIFO_Full 0x00010000 +#define FIFO_Empty 0x00000001 +#define FIFO_ReUse 0x00000002 + +#define Mask_2hex 0x000000FF +#define Mask_4hex 0x0000FFFF /*=================================================== @@ -45,18 +51,8 @@ */ struct APB_FIFO_REG { - int rwdata; /**< \brief Data register Write/Read */ - int raddr; /**< \brief Address register for the reading operation */ - int cfgreg; /**< \brief Configuration register composed of Read enable Flag [HEX 0] - Write enable Flag [HEX 1] - Empty Flag [HEX 2] - Full Flag [HEX 3] - ReUse Flag [HEX 4] - Lock Flag [HEX 5] - Dummy "C" [HEX 6/7] */ - int dummy0; /**< \brief Unused register, aesthetic interest */ - int dummy1; /**< \brief Unused register, aesthetic interest */ - int waddr; /**< \brief Address register for the writing operation */ + int IDreg; + int FIFOreg[2*8]; }; typedef volatile struct APB_FIFO_REG FIFO_Device; @@ -75,16 +71,6 @@ typedef volatile struct APB_FIFO_REG FIF \return The pointer to the device. */ FIFO_Device* openFIFO(int count); - -/*! \fn int FillFifo(FIFO_Device* dev,int Tbl[],int A); - \brief a Fill in FIFO function. - - This Function fill in the FIFO with a table data. - - \param dev The FFT pointer. - \param Tbl[] The data table. - \param A The data table size. -*/ -int FillFifo(FIFO_Device* dev,int Tbl[],int A); +int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); #endif diff --git a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h --- a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h +++ b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h @@ -33,8 +33,11 @@ */ #define FIFO_Ctrl 0 #define FIFO_RWdata 1 + #define FIFO_Full 0x00010000 #define FIFO_Empty 0x00000001 +#define FIFO_ReUse 0x00000002 + #define Mask_2hex 0x000000FF #define Mask_4hex 0x0000FFFF @@ -50,7 +53,6 @@ struct APB_FIFO_REG { int IDreg; int FIFOreg[2*8]; - }; typedef volatile struct APB_FIFO_REG FIFO_Device; diff --git a/lib/lpp/lpp_matrix/APB_Matrix.vhd b/lib/lpp/lpp_matrix/APB_Matrix.vhd --- a/lib/lpp/lpp_matrix/APB_Matrix.vhd +++ b/lib/lpp/lpp_matrix/APB_Matrix.vhd @@ -42,26 +42,15 @@ entity APB_Matrix is Input_SZ : integer := 16; Result_SZ : integer := 32); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); - FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); - Full : in std_logic_vector(1 downto 0); - Empty : in std_logic_vector(1 downto 0); - ReadFIFO : out std_logic_vector(1 downto 0); + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; - Result : out std_logic_vector(Result_SZ-1 downto 0); - Start : out std_logic; - Read : out std_logic; - Take : out std_logic; - Valid : out std_logic; - Received : out std_logic; -Res : out std_logic_vector(Result_SZ-1 downto 0); --- Conjugate : out std_logic; - OP1 : out std_logic_vector(3 downto 0); - OP2 : out std_logic_vector(3 downto 0); - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + Result : out std_logic_vector(Result_SZ-1 downto 0); + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end APB_Matrix; @@ -75,22 +64,27 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); type MATRIX_ctrlr_Reg is record - MATRIX_Statu : std_logic_vector(3 downto 0); + MATRIX_Ctrl : std_logic_vector(4 downto 0); end record; signal Rec : MATRIX_ctrlr_Reg; signal Rdata : std_logic_vector(31 downto 0); +signal Start : std_logic; +signal statu : std_logic_vector(3 downto 0); begin Mspec0 : SpectralMatrix generic map (Input_SZ,Result_SZ) - port map(clk,rst,FIFO1,FIFO2,Full,Empty,Rec.MATRIX_Statu,ReadFIFO,WriteFIFO,Start,Read,Take,Valid,Received,Res,OP1,OP2,Result); --Start,Read,Take,Valid,Received,Conjugate,OP1,OP2 + port map(clk,rst,Start,FIFO1,FIFO2,Statu,ReadFIFO,WriteFIFO,Result); + +Statu <= Rec.MATRIX_Ctrl(3 downto 0); +Start <= Rec.MATRIX_Ctrl(4); process(rst,clk) begin if(rst='0')then - Rec.MATRIX_Statu <= (others => '0'); + Rec.MATRIX_Ctrl <= (others => '0'); elsif(clk'event and clk='1')then @@ -98,26 +92,18 @@ Mspec0 : SpectralMatrix if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0); + Rec.MATRIX_Ctrl <= apbi.pwdata(4 downto 0); when others => null; end case; end if; - --APB READ OP + --APB Read OP if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rdata(31 downto 4) <= (others => '0'); - Rdata(3 downto 0) <= Rec.MATRIX_Statu; - --when "000001" => - -- Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0); - -- Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1); - -- Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2); - -- Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3); - -- Rdata(19 downto 16) <= "000" & Rec.MATRIX_Cfg(4); - -- Rdata(23 downto 20) <= "000" & Rec.MATRIX_Cfg(5); - -- Rdata(31 downto 24) <= X"CC"; + Rdata(31 downto 5) <= (others => '0'); + Rdata(4 downto 0) <= Rec.MATRIX_Ctrl; when others => Rdata <= (others => '0'); end case; diff --git a/lib/lpp/lpp_matrix/DriveInputs.vhd b/lib/lpp/lpp_matrix/DriveInputs.vhd --- a/lib/lpp/lpp_matrix/DriveInputs.vhd +++ b/lib/lpp/lpp_matrix/DriveInputs.vhd @@ -25,17 +25,12 @@ use IEEE.std_logic_1164.all; entity DriveInputs is port( - clk : in std_logic; - raz : in std_logic; - Read : in std_logic; --- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); --- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); --- Statu : in std_logic_vector(3 downto 0); - Conjugate : in std_logic; - Take : out std_logic; - ReadFIFO : out std_logic_vector(1 downto 0) --- OP1 : out std_logic_vector(Input_SZ-1 downto 0); --- OP2 : out std_logic_vector(Input_SZ-1 downto 0) + clk : in std_logic; + raz : in std_logic; + Read : in std_logic; + Conjugate : in std_logic; + Take : out std_logic; + ReadFIFO : out std_logic_vector(1 downto 0) ); end DriveInputs; @@ -43,9 +38,7 @@ end DriveInputs; architecture ar_DriveInputs of DriveInputs is signal Read_reg : std_logic; -signal i : integer range 0 to 128; ---signal j : integer range 0 to 15; ---signal Read_int : std_logic_vector(4 downto 0); +signal i : integer range 0 to 128; type state is (stX,sta,stb,st1,st2,idl1,idl2); signal ect : state; @@ -58,7 +51,6 @@ begin Take <= '0'; i <= 0; ReadFIFO <= "00"; --- j <= 0; Read_reg <= '0'; ect <= stX; @@ -70,11 +62,6 @@ begin when stX => i <= 1; if(Read_reg='0' and Read='1')then --- if(j=15)then --- j <= 1; --- else --- j<= j+1; --- end if; ect <= idl1; end if; @@ -109,7 +96,7 @@ begin ect <= stb; when stb => - Take <= '0'; + Take <= '0'; if(i=128)then ect <= stX; elsif(Read_reg='0' and Read='1')then diff --git a/lib/lpp/lpp_matrix/GetResult.vhd b/lib/lpp/lpp_matrix/GetResult.vhd --- a/lib/lpp/lpp_matrix/GetResult.vhd +++ b/lib/lpp/lpp_matrix/GetResult.vhd @@ -32,8 +32,8 @@ port( Valid : in std_logic; Conjugate : in std_logic; Res : in std_logic_vector(Result_SZ-1 downto 0); --- Full : in std_logic; - WriteFIFO : out std_logic; + Full : in std_logic; + WriteFIFO : out std_logic; Received : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0) ); @@ -44,7 +44,7 @@ architecture ar_GetResult of GetResult i signal Valid_reg : std_logic; -type state is (st0,st1); +type state is (st0,st1,stX,stY); signal ect : state; begin @@ -63,25 +63,37 @@ begin case ect is when st0 => - Received <= '0'; - WriteFIFO <= '0'; - if(Valid_reg='0' and Valid='1')then + if(Full='0' and Valid='1')then Result <= Res; WriteFIFO <= '1'; + Received <= '1'; + ect <= stX; + end if; + + when stX => + WriteFIFO <= '0'; + if(Conjugate='1')then + Received <= '0'; + end if; + if(Valid_reg='1' and Valid='0')then if(Conjugate='1')then - Received <= '1'; ect <= st0; else ect <= st1; - end if; - end if; - - when st1 => - Received <= '1'; - WriteFIFO <= '0'; - if(Valid_reg='0' and Valid='1')then + end if; + end if; + + when st1 => + if(Full='0' and Valid='1')then Result <= Res; WriteFIFO <= '1'; + Received <= '0'; + ect <= stY; + end if; + + when stY => + WriteFIFO <= '0'; + if(Valid_reg='1' and Valid='0')then ect <= st0; end if; diff --git a/lib/lpp/lpp_matrix/Matrix.vhd b/lib/lpp/lpp_matrix/Matrix.vhd --- a/lib/lpp/lpp_matrix/Matrix.vhd +++ b/lib/lpp/lpp_matrix/Matrix.vhd @@ -39,8 +39,6 @@ entity Matrix is Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugué Valid : out std_logic; --! Flag, Résultat disponible Read : out std_logic; --! Flag, opérande disponible - OPin1 : out std_logic_vector(3 downto 0); - OPin2 : out std_logic_vector(3 downto 0); Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! Résultat du calcul ); end Matrix; @@ -53,9 +51,6 @@ signal OP1 : std_logic_vector(Input_SZ signal OP2 : std_logic_vector(Input_SZ-1 downto 0); begin -OPin1 <= OP1(3 downto 0); -OPin2 <= OP1(3 downto 0); - DRIVE : ALU_Driver generic map(Input_SZ,Input_SZ) diff --git a/lib/lpp/lpp_matrix/SelectInputs.vhd b/lib/lpp/lpp_matrix/SelectInputs.vhd deleted file mode 100644 --- a/lib/lpp/lpp_matrix/SelectInputs.vhd +++ /dev/null @@ -1,189 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity SelectInputs is -generic( - Input_SZ : integer := 16); -port( - clk : in std_logic; - raz : in std_logic; - Read : in std_logic; - B1 : in std_logic_vector(Input_SZ-1 downto 0); - B2 : in std_logic_vector(Input_SZ-1 downto 0); - B3 : in std_logic_vector(Input_SZ-1 downto 0); - E1 : in std_logic_vector(Input_SZ-1 downto 0); - E2 : in std_logic_vector(Input_SZ-1 downto 0); - Conjugate : out std_logic; - Take : out std_logic; - ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 - Statu : out std_logic_vector(3 downto 0); - OP1 : out std_logic_vector(Input_SZ-1 downto 0); - OP2 : out std_logic_vector(Input_SZ-1 downto 0) -); -end SelectInputs; - - -architecture ar_SelectInputs of SelectInputs is - -signal Read_reg : std_logic; -signal i : integer range 0 to 128; -signal j : integer range 0 to 15; -signal Read_int : std_logic_vector(4 downto 0); - -type state is (stX,sta,stb,st1,st2,idl1,idl2); -signal ect : state; - -begin - process(clk,raz) - begin - - if(raz='0')then - Take <= '0'; - i <= 0; - j <= 0; - Read_reg <= '0'; - ect <= stX; - - elsif(clk'event and clk='1')then - Read_reg <= Read; - - case ect is - - when stX => - i <= 1; - if(Read_reg='0' and Read='1')then - if(j=15)then - j <= 1; - else - j<= j+1; - end if; - ect <= idl1; - end if; - - when idl1 => - ect <= st1; - - when st1 => - Take <= '1'; - ect <= sta; - - when sta => - if(Read_reg='0' and Read='1')then - ect <= idl2; - end if; - - when idl2 => - ect <= st2; - - when st2 => - Take <= '0'; - ect <= stb; - - when stb => - if(i=128)then - ect <= stX; - elsif(Read_reg='0' and Read='1')then - i <= i+1; - ect <= idl1; - end if; - - end case; - end if; - end process; - -Statu <= std_logic_vector(to_unsigned(j,4)); - -with j select - Read_int <= "10000" when 1, - "11000" when 2, - "01000" when 3, - "10100" when 4, - "01100" when 5, - "00100" when 6, - "10010" when 7, - "01010" when 8, - "00110" when 9, - "00010" when 10, - "10001" when 11, - "01001" when 12, - "00101" when 13, - "00011" when 14, - "00001" when 15, - "00000" when others; - -with ect select - ReadFIFO <= Read_int when idl1, - Read_int when idl2, - "00000" when others; - - -with j select - OP1 <= B1 when 1, - B1 when 2, - B1 when 4, - B1 when 7, - B1 when 11, - B2 when 3, - B2 when 5, - B2 when 8, - B2 when 12, - B3 when 6, - B3 when 9, - B3 when 13, - E1 when 10, - E1 when 14, - E2 when 15, - X"FFFF" when others; - - -with j select - OP2 <= B1 when 1, - B2 when 2, - B2 when 3, - B3 when 4, - B3 when 5, - B3 when 6, - E1 when 7, - E1 when 8, - E1 when 9, - E1 when 10, - E2 when 11, - E2 when 12, - E2 when 13, - E2 when 14, - E2 when 15, - X"FFFF" when others; - - -with j select - Conjugate <= '1' when 1, - '1' when 3, - '1' when 6, - '1' when 10, - '1' when 15, - '0' when others; - - -end ar_SelectInputs; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd --- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -29,65 +29,48 @@ generic( Input_SZ : integer := 16; Result_SZ : integer := 32); port( - clk : in std_logic; - reset : in std_logic; - FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); - FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); - Full : in std_logic_vector(1 downto 0); - Empty : in std_logic_vector(1 downto 0); - Statu : in std_logic_vector(3 downto 0); - ReadFIFO : out std_logic_vector(1 downto 0); - WriteFIFO : out std_logic; - Start : out std_logic; - Read : out std_logic; - Take : out std_logic; - Valid : out std_logic; - Received : out std_logic; - Res : out std_logic_vector(Result_SZ-1 downto 0); --- Conjugate : out std_logic; - OP1 : out std_logic_vector(3 downto 0); - OP2 : out std_logic_vector(3 downto 0); - Result : out std_logic_vector(Result_SZ-1 downto 0) + clk : in std_logic; + reset : in std_logic; + Start : in std_logic; + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Statu : in std_logic_vector(3 downto 0); + FullFIFO : in std_logic; + ReadFIFO : out std_logic_vector(1 downto 0); + WriteFIFO : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) ); end SpectralMatrix; architecture ar_SpectralMatrix of SpectralMatrix is -signal Start_int : std_logic; +signal RaZ : std_logic; signal Read_int : std_logic; signal Take_int : std_logic; signal Received_int : std_logic; signal Valid_int : std_logic; signal Conjugate_int : std_logic; ---signal OP1 : std_logic_vector(Input_SZ-1 downto 0); ---signal OP2 : std_logic_vector(Input_SZ-1 downto 0); signal Resultat : std_logic_vector(Result_SZ-1 downto 0); ---signal Res : std_logic_vector(Result_SZ-1 downto 0); begin -ST0 : Starter - port map(clk,reset,Full,Empty,Conjugate_int,Received_int,Start_int); - ---IN0 : SelectInputs --- generic map(Input_SZ) --- port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2); +RaZ <= reset and Start; IN1 : DriveInputs - port map(clk,Start_int,Read_int,Conjugate_int,Take_int,ReadFIFO); + port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO); CALC0 : Matrix generic map(Input_SZ) - port map(clk,Start_int,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,OP1,OP2,Resultat); + port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); RES0 : GetResult generic map(Result_SZ) - port map(clk,Start_int,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result); + port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,FullFIFO,WriteFIFO,Received_int,Result); With Statu select @@ -98,12 +81,4 @@ With Statu select '1' when "1111", '0' when others; -Start <= Start_int; -Read <= Read_int; -Take <= Take_int; -Received <= Received_int; -Valid <= Valid_int; ---Conjugate <= Conjugate_int; -Res <= Resultat; - end ar_SpectralMatrix; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/Starter.vhd b/lib/lpp/lpp_matrix/Starter.vhd deleted file mode 100644 --- a/lib/lpp/lpp_matrix/Starter.vhd +++ /dev/null @@ -1,114 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity Starter is -port( - clk : in std_logic; - raz : in std_logic; - Full : in std_logic_vector(1 downto 0); - Empty : in std_logic_vector(1 downto 0); - Conjugate : in std_logic; - received : in std_logic; - Start : out std_logic -); -end Starter; - - -architecture ar_Starter of Starter is - -type etat is (eX,e0,e1); -signal ect : etat; - -signal received_reg : std_logic; - -begin - process(clk,raz) - begin - - if(raz='0')then - Start <= '0'; - ect <= eX; - - elsif(clk'event and clk='1')then - received_reg <= received; - - case ect is - when eX => - if(Conjugate='0')then - if(full="11")then - Start <= '1'; - ect <= e0; - end if; - else - if(full(0)='1')then - Start <= '1'; - ect <= e0; - end if; - end if; - - when e0 => - if(Conjugate='0')then - if(empty="11")then - --Start <= '0'; - ect <= e1; - end if; - else - if(empty(0)='1')then - --Start <= '0'; - ect <= e1; - end if; - end if; - - when e1 => - if(received_reg='1' and received='0')then - Start <= '0'; - ect <= eX; - end if; - - end case; - - end if; - end process; - -end ar_Starter; - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/lpp_matrix/TopMatrix_PDR.vhd b/lib/lpp/lpp_matrix/TopMatrix_PDR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/TopMatrix_PDR.vhd @@ -0,0 +1,193 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity TopMatrix_PDR is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; + reset : in std_logic; + Data : in std_logic_vector((5*Input_SZ)-1 downto 0); + FULLin : in std_logic_vector(4 downto 0); + READin : in std_logic_vector(1 downto 0); + WRITEin : in std_logic; + FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); + Start : out std_logic; + Read : out std_logic_vector(4 downto 0); + Statu : out std_logic_vector(3 downto 0) +); +end entity; + +architecture ar_TopMatrix_PDR of TopMatrix_PDR is + +type state is (st0,st1,st2,st3); +signal ect : state; + +signal i,j : integer; +signal full_int : std_logic_vector(1 downto 0); +signal WRITEin_reg : std_logic; + +begin + process(clk,reset) + begin + + if(reset='0')then + i <= 1; + j <= 0; + Start <= '0'; + WRITEin_reg <= '0'; + ect <= st0; + + elsif(clk'event and clk='1')then + WRITEin_reg <= WRITEin; + + case ect is + + when st0 => + if(full_int = "11")then + Start <= '1'; + ect <= st1; + end if; + + when st1 => + if(WRITEin_reg='1' and WRITEin='0')then + if(i=1 or i=3 or i=6 or i=10 or i=15)then + ect <= st2; + else + ect <= st3; + end if; + end if; + + when st2 => + if(j=127)then + if(i=15)then + i <= 1; + else + i <= i+1; + end if; + j <= 0; + Start <= '0'; + ect <= st0; + elsif(WRITEin_reg='1' and WRITEin='0')then + j <= j+1; + end if; + + when st3 => + if(j=255)then + j <= 0; + i <= i+1; + Start <= '0'; + ect <= st0; + elsif(WRITEin_reg='1' and WRITEin='0')then + j <= j+1; + end if; + + end case; + end if; + end process; + +Statu <= std_logic_vector(to_unsigned(i,4)); + +with i select + FIFO1 <= Data(15 downto 0) when 1, + Data(15 downto 0) when 2, + Data(31 downto 16) when 3, + Data(15 downto 0) when 4, + Data(31 downto 16) when 5, + Data(47 downto 32) when 6, + Data(15 downto 0) when 7, + Data(31 downto 16) when 8, + Data(47 downto 32) when 9, + Data(63 downto 48) when 10, + Data(15 downto 0) when 11, + Data(31 downto 16) when 12, + Data(47 downto 32) when 13, + Data(63 downto 48) when 14, + Data(79 downto 64) when 15, + X"0000" when others; + + +with i select + FIFO2 <= (others => '0') when 1, + Data(31 downto 16) when 2, + (others => '0') when 3, + Data(47 downto 32) when 4, + Data(47 downto 32) when 5, + (others => '0') when 6, + Data(63 downto 48) when 7, + Data(63 downto 48) when 8, + Data(63 downto 48) when 9, + (others => '0') when 10, + Data(79 downto 64) when 11, + Data(79 downto 64) when 12, + Data(79 downto 64) when 13, + Data(79 downto 64) when 14, + (others => '0') when 15, + X"0000" when others; + +with i select + Read <= "1111" & not READin(0) when 1, + "111" & not READin(1) & not READin(0) when 2, + "111" & not READin(0) & '1' when 3, + "11" & not READin(1) & '1' & not READin(0) when 4, + "11" & not READin(1) & not READin(0) & '1' when 5, + "11" & not READin(0) & "11" when 6, + "1" & not READin(1) & "11" & not READin(0) when 7, + '1' & not READin(1) & '1' & not READin(0) & '1' when 8, + '1' & not READin(1) & not READin(0) & "11" when 9, + '1' & not READin(0) & "111" when 10, + not READin(1) & "111" & not READin(0) when 11, + not READin(1) & "11" & not READin(0) & '1' when 12, + not READin(1) & '1' & not READin(0) & "11" when 13, + not READin(1) & not READin(0) & "111" when 14, + not READin(0) & "1111" when 15, + "11111" when others; + +with i select + full_int <= FULLin(0) & FULLin(0) when 1, + FULLin(1) & FULLin(0) when 2, + FULLin(1) & FULLin(1) when 3, + FULLin(2) & FULLin(0) when 4, + FULLin(2) & FULLin(1) when 5, + FULLin(2) & FULLin(2) when 6, + FULLin(3) & FULLin(0) when 7, + FULLin(3) & FULLin(1) when 8, + FULLin(3) & FULLin(2) when 9, + FULLin(3) & FULLin(3) when 10, + FULLin(4) & FULLin(0) when 11, + FULLin(4) & FULLin(1) when 12, + FULLin(4) & FULLin(2) when 13, + FULLin(4) & FULLin(3) when 14, + FULLin(4) & FULLin(4) when 15, + "00" when others; + +end architecture; + + + + + + diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -41,26 +41,15 @@ component APB_Matrix is Input_SZ : integer := 16; Result_SZ : integer := 32); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); - FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); - Full : in std_logic_vector(1 downto 0); - Empty : in std_logic_vector(1 downto 0); - ReadFIFO : out std_logic_vector(1 downto 0); + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + ReadFIFO : out std_logic_vector(1 downto 0); WriteFIFO : out std_logic; - Result : out std_logic_vector(Result_SZ-1 downto 0); - Start : out std_logic; - Read : out std_logic; - Take : out std_logic; - Valid : out std_logic; - Received : out std_logic; -Res : out std_logic_vector(Result_SZ-1 downto 0); --- Conjugate : out std_logic; - OP1 : out std_logic_vector(3 downto 0); - OP2 : out std_logic_vector(3 downto 0); - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + Result : out std_logic_vector(Result_SZ-1 downto 0); + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end component; @@ -70,25 +59,16 @@ generic( Input_SZ : integer := 16; Result_SZ : integer := 32); port( - clk : in std_logic; - reset : in std_logic; - FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); - FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); - Full : in std_logic_vector(1 downto 0); - Empty : in std_logic_vector(1 downto 0); - Statu : in std_logic_vector(3 downto 0); - ReadFIFO : out std_logic_vector(1 downto 0); - WriteFIFO : out std_logic; - Start : out std_logic; - Read : out std_logic; - Take : out std_logic; - Valid : out std_logic; - Received : out std_logic; - Res : out std_logic_vector(Result_SZ-1 downto 0); --- Conjugate : out std_logic; - OP1 : out std_logic_vector(3 downto 0); - OP2 : out std_logic_vector(3 downto 0); - Result : out std_logic_vector(Result_SZ-1 downto 0) + clk : in std_logic; + reset : in std_logic; + Start : in std_logic; + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Statu : in std_logic_vector(3 downto 0); + FullFIFO : in std_logic; + ReadFIFO : out std_logic_vector(1 downto 0); + WriteFIFO : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) ); end component; @@ -106,12 +86,58 @@ component Matrix is Conjugate : in std_logic; Valid : out std_logic; Read : out std_logic; - OPin1 : out std_logic_vector(3 downto 0); - OPin2 : out std_logic_vector(3 downto 0); Result : out std_logic_vector(2*Input_SZ-1 downto 0) ); end component; +component GetResult is +generic( + Result_SZ : integer := 32); +port( + clk : in std_logic; + raz : in std_logic; + Valid : in std_logic; + Conjugate : in std_logic; + Res : in std_logic_vector(Result_SZ-1 downto 0); + Full : in std_logic; + WriteFIFO : out std_logic; + Received : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end component; + + +component TopMatrix_PDR is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + Data : in std_logic_vector((5*Input_SZ)-1 downto 0); + FULLin : in std_logic_vector(4 downto 0); + READin : in std_logic_vector(1 downto 0); + WRITEin : in std_logic; + FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); + Start : out std_logic; + Read : out std_logic_vector(4 downto 0); + Statu : out std_logic_vector(3 downto 0) +); +end component; + + +component DriveInputs is +port( + clk : in std_logic; + raz : in std_logic; + Read : in std_logic; + Conjugate : in std_logic; + Take : out std_logic; + ReadFIFO : out std_logic_vector(1 downto 0) +); +end component; + component ALU_Driver is generic( @@ -178,72 +204,6 @@ port( OP : in std_logic_vector(Input_SZ-1 downto 0); RES : out std_logic_vector(Input_SZ-1 downto 0) ); -end component; - - -component GetResult is -generic( - Result_SZ : integer := 32); -port( - clk : in std_logic; - raz : in std_logic; - Valid : in std_logic; - Conjugate : in std_logic; - Res : in std_logic_vector(Result_SZ-1 downto 0); - WriteFIFO : out std_logic; - Received : out std_logic; - Result : out std_logic_vector(Result_SZ-1 downto 0) -); -end component; - - -component SelectInputs is -generic( - Input_SZ : integer := 16); -port( - clk : in std_logic; - raz : in std_logic; - Read : in std_logic; - B1 : in std_logic_vector(Input_SZ-1 downto 0); - B2 : in std_logic_vector(Input_SZ-1 downto 0); - B3 : in std_logic_vector(Input_SZ-1 downto 0); - E1 : in std_logic_vector(Input_SZ-1 downto 0); - E2 : in std_logic_vector(Input_SZ-1 downto 0); - Conjugate : out std_logic; - Take : out std_logic; - ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 - Statu : out std_logic_vector(3 downto 0); - OP1 : out std_logic_vector(Input_SZ-1 downto 0); - OP2 : out std_logic_vector(Input_SZ-1 downto 0) -); -end component; ---------------------------------------------------------------------------- -component DriveInputs is -port( - clk : in std_logic; - raz : in std_logic; - Read : in std_logic; --- FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); --- FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); --- Statu : in std_logic_vector(3 downto 0); - Conjugate : in std_logic; - Take : out std_logic; - ReadFIFO : out std_logic_vector(1 downto 0) --- OP1 : out std_logic_vector(Input_SZ-1 downto 0); --- OP2 : out std_logic_vector(Input_SZ-1 downto 0) -); -end component; - -component Starter is -port( - clk : in std_logic; - raz : in std_logic; - Full : in std_logic_vector(1 downto 0); - Empty : in std_logic_vector(1 downto 0); - Conjugate : in std_logic; - received : in std_logic; - Start : out std_logic -); end component; end; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -101,7 +101,8 @@ signal sRen_APB : std_logic_vector(Fifo signal sRDATA : fifodatabus; signal sWDATA : fifodatabus; signal sWADDR : fifoaddressbus; -signal sRADDR : fifoaddressbus; +signal sRADDR : fifoaddressbus; +signal ReUse : std_logic_vector(FifoCnt-1 downto 0); --27/01/12 type state_t is (idle,Read); signal fiforeadfsmst : state_t; @@ -153,9 +154,13 @@ ctrlregs: for i in 0 to FifoCnt-1 genera RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); Rec(i).FIFO_Ctrl(16) <= sFull(i); - Rec(i).FIFO_Ctrl(Addr_sz downto 1) <= sRADDR(i); - Rec(i).FIFO_Ctrl((Addr_sz+16) downto 17) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty| -end generate; -- 31 17 16 15 1 0 + --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12 + ReUse(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12 + Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12 + Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12 + Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i); + Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty| +end generate; -- 31 17 16 15 1 0 Empty <= sEmpty; Full <= sFull; @@ -164,7 +169,7 @@ Full <= sFull; fifos: for i in 0 to FifoCnt-1 generate FIFO0 : lpp_fifo generic map (tech,Data_sz,Addr_sz) - port map(rst,srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); + port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); end generate; process(rst,clk) @@ -172,14 +177,19 @@ end generate; if(rst='0')then rstloop1: for i in 0 to FifoCnt-1 loop Rec(i).FIFO_Wdata <= (others => '0'); + Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12 + --Rec(i).FIFO_Ctrl(17) <= '0'; sWen_APB(i) <= '1'; end loop; elsif(clk'event and clk='1')then --APB Write OP if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - writelp: for i in 0 to FifoCnt-1 loop - if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then - Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); + writelp: for i in 0 to FifoCnt-1 loop + if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then + Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1); + --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17); + elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then + Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); sWen_APB(i) <= '0'; end if; end loop; @@ -195,7 +205,7 @@ end generate; if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then PRdata <= Rec(i).FIFO_Ctrl; elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then - PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; + PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; end if; end loop; end if; diff --git a/lib/lpp/lpp_memory/ApbFifoDriverV.vhd b/lib/lpp/lpp_memory/ApbFifoDriverV.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/ApbFifoDriverV.vhd +++ /dev/null @@ -1,186 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; - ---! Driver APB "Générique" qui va faire le lien entre le bus Amba et la FIFO - -entity ApbFifoDriverV is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - LPP_DEVICE : integer; - FifoCnt : integer := 1; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - ReadEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire - WriteEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire - FlagEmpty : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide - FlagFull : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine - ReUse : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de relire la mémoire du début - Lock : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de bloquer l'écriture dans la mémoire - DataIn : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée - DataOut : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie - AddrIn : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) - AddrOut : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end ApbFifoDriverV; - ---! @details Utilisable avec n'importe quelle IP VHDL de type FIFO - -architecture ar_ApbFifoDriverV of ApbFifoDriverV is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(5 downto 0); - DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); - DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); - DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); - DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); -end record; - -type DEVICE_ctrlr_RegV is array(FifoCnt-1 downto 0) of DEVICE_ctrlr_Reg; - -signal Rec : DEVICE_ctrlr_RegV; -signal Rdata : std_logic_vector(31 downto 0); - -signal FlagRE : std_logic; -signal FlagWR : std_logic; - -begin - -fifoflags: for i in 0 to FifoCnt-1 generate: - - Rec(i).DEVICE_Cfg(0) <= FlagRE(i); - Rec(i).DEVICE_Cfg(1) <= FlagWR(i); - Rec(i).DEVICE_Cfg(2) <= FlagEmpty(i); - Rec(i).DEVICE_Cfg(3) <= FlagFull(i); - - ReUse(i) <= Rec(i).DEVICE_Cfg(4); - Lock(i) <= Rec(i).DEVICE_Cfg(5); - - DataIn(i*(Data_sz-1 downto 0)) <= Rec(i).DEVICE_DataW; - - Rec(i).DEVICE_DataR <= DataOut(i*(Data_sz-1 downto 0)); - Rec(i).DEVICE_AddrW <= AddrIn(i*(Addr_sz-1 downto 0)); - Rec(i).DEVICE_AddrR <= AddrOut(i*(Addr_sz-1 downto 0)); - - WriteEnable(i) <= FlagWR(i); - ReadEnable(i) <= FlagRE(i); - -end generate; - - - process(rst,clk) - begin - if(rst='0')then - Rec.DEVICE_DataW <= (others => '0'); - FlagWR <= '0'; - FlagRE <= '0'; - Rec.DEVICE_Cfg(4) <= '0'; - Rec.DEVICE_Cfg(5) <= '0'; - - elsif(clk'event and clk='1')then - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - FlagWR <= '1'; - Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); - when "000010" => - Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); - Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); - when others => - null; - end case; - else - FlagWR <= (others => '0'); - end if; - - --APB Read OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - for i in 0 to FifoCnt-1 loop - if conv_integer(apbi.paddr(7 downto 3)) = i then - case apbi.paddr(2 downto 2) is - when "0" => - CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when "1" => - CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when others => - end case; - end if; - end loop; - when "000000" => - FlagRE <= '1'; - Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; - when "000001" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.DEVICE_AddrR; - when "000101" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.DEVICE_AddrW; - when "000010" => - Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); - Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); - Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); - Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); - Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); - Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); - Rdata(31 downto 24) <= X"CC"; - when others => - Rdata <= (others => '0'); - end case; - else - FlagRE <= (others => '0'); - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; - - -end ar_ApbFifoDriverV; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd --- a/lib/lpp/lpp_memory/lpp_FIFO.vhd +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -35,6 +35,7 @@ generic( ); port( rstn : in std_logic; + ReUse : in std_logic; --27/01/12 rclk : in std_logic; ren : in std_logic; rdata : out std_logic_vector(DataSz-1 downto 0); @@ -84,7 +85,9 @@ begin Raddr_vect_d <= (others =>'1'); sempty <= '1'; elsif(rclk'event and rclk='1')then - if(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then + if(ReUse = '1')then --27/01/12 + sempty <= '0'; --27/01/12 + elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then sempty <= '1'; elsif(Raddr_vect/=Waddr_vect) then sempty <= '0'; @@ -109,7 +112,9 @@ begin Waddr_vect_d <= (others =>'1'); sfull <= '0'; elsif(wclk'event and wclk='1')then - if(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then + if(ReUse = '1')then --27/01/12 + sfull <= '1'; --27/01/12 + elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then sfull <= '1'; elsif(Raddr_vect/=Waddr_vect) then sfull <= '0'; diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -77,6 +77,7 @@ generic( ); port( rstn : in std_logic; + ReUse : in std_logic; --27/01/12 rclk : in std_logic; ren : in std_logic; rdata : out std_logic_vector(DataSz-1 downto 0);