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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 --
23 -- This module implements the SyncSignal generator explained in:
24 -- Data Transfer between Asynchronous Clock Domains without Pain
25 -- from Markus Schutti, Markus Pfaff, Richard Hagelauer
26 -- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
27 -- see page 4
28 --
29 --
30
31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL;
33
34 entity CrossDomainSyncGen is
35 Port (
36 reset : in STD_LOGIC;
37 ClockS : in STD_LOGIC;
38 ClockF : in STD_LOGIC;
39 SyncSignal : out STD_LOGIC
40 );
41 end CrossDomainSyncGen;
42
43 architecture AR_CrossDomainSyncGen of CrossDomainSyncGen is
44
45 signal FFSYNC : std_logic_vector(2 downto 0);
46
47 begin
48
49 SyncSignal <= FFSYNC(2);
50
51 process(reset,ClockF)
52 begin
53 if reset = '0' then
54 FFSYNC <= (others => '0');
55 elsif ClockF'event and ClockF = '1' then
56 FFSYNC(0) <= ClockS;
57 FFSYNC(1) <= FFSYNC(0);
58 FFSYNC(2) <= FFSYNC(1);
59 end if;
60 end process;
61
62 end AR_CrossDomainSyncGen;
63
64
65
66
67
68
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1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 library lpp;
5 use lpp.lpp_ad_conv.all;
6 use lpp.lpp_amba.all;
7 use lpp.apb_devices_list.all;
8 use lpp.general_purpose.all;
9 use lpp.Rocket_PCM_Encoder.all;
10
11 use work.config.all;
12
13
14 entity DC_ACQ_TOP is
15 generic(
16 WordSize : integer := 8;
17 WordCnt : integer := 144;
18 MinFCount : integer := 64;
19 EnableSR : integer := 1;
20 CstDATA : integer := 0;
21 FakeADC : integer := 0;
22 CDS : integer := 0
23 );
24 port(
25
26 reset : in std_logic;
27 clk : in std_logic;
28 SyncSig : in STD_LOGIC;
29 minorF : in std_logic;
30 majorF : in std_logic;
31 sclk : in std_logic;
32 WordClk : in std_logic;
33
34 DC_ADC_Sclk : out std_logic;
35 DC_ADC_IN : in std_logic_vector(1 downto 0);
36 DC_ADC_ClkDiv : out std_logic;
37 DC_ADC_FSynch : out std_logic;
38 SET_RESET0 : out std_logic;
39 SET_RESET1 : out std_logic;
40
41 AMR1X : out std_logic_vector(23 downto 0);
42 AMR1Y : out std_logic_vector(23 downto 0);
43 AMR1Z : out std_logic_vector(23 downto 0);
44
45 AMR2X : out std_logic_vector(23 downto 0);
46 AMR2Y : out std_logic_vector(23 downto 0);
47 AMR2Z : out std_logic_vector(23 downto 0);
48
49 AMR3X : out std_logic_vector(23 downto 0);
50 AMR3Y : out std_logic_vector(23 downto 0);
51 AMR3Z : out std_logic_vector(23 downto 0);
52
53 AMR4X : out std_logic_vector(23 downto 0);
54 AMR4Y : out std_logic_vector(23 downto 0);
55 AMR4Z : out std_logic_vector(23 downto 0);
56
57 Temp1 : out std_logic_vector(23 downto 0);
58 Temp2 : out std_logic_vector(23 downto 0);
59 Temp3 : out std_logic_vector(23 downto 0);
60 Temp4 : out std_logic_vector(23 downto 0)
61 );
62 end DC_ACQ_TOP;
63
64 architecture Behavioral of DC_ACQ_TOP is
65
66 signal DC_ADC_SmplClk : std_logic;
67 signal LF_ADC_SmplClk : std_logic;
68 signal SET_RESET0_sig : std_logic;
69 signal SET_RESET1_sig : std_logic;
70 signal SET_RESET_counter : integer range 0 to 31:=0;
71
72 signal AMR1X_Sync : std_logic_vector(23 downto 0);
73 signal AMR1Y_Sync : std_logic_vector(23 downto 0);
74 signal AMR1Z_Sync : std_logic_vector(23 downto 0);
75
76 signal AMR2X_Sync : std_logic_vector(23 downto 0);
77 signal AMR2Y_Sync : std_logic_vector(23 downto 0);
78 signal AMR2Z_Sync : std_logic_vector(23 downto 0);
79
80 signal AMR3X_Sync : std_logic_vector(23 downto 0);
81 signal AMR3Y_Sync : std_logic_vector(23 downto 0);
82 signal AMR3Z_Sync : std_logic_vector(23 downto 0);
83
84 signal AMR4X_Sync : std_logic_vector(23 downto 0);
85 signal AMR4Y_Sync : std_logic_vector(23 downto 0);
86 signal AMR4Z_Sync : std_logic_vector(23 downto 0);
87
88 signal Temp1_Sync : std_logic_vector(23 downto 0);
89 signal Temp2_Sync : std_logic_vector(23 downto 0);
90 signal Temp3_Sync : std_logic_vector(23 downto 0);
91 signal Temp4_Sync : std_logic_vector(23 downto 0);
92
93 begin
94
95 ------------------------------------------------------------------
96 --
97 -- DC sampling clock generation
98 --
99 ------------------------------------------------------------------
100
101
102 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
103 --generic map(36)
104 generic map(288)
105 port map(
106 reset => reset,
107 wclk => WordClk,
108 SMPL_CLK => DC_ADC_SmplClk
109 );
110 ------------------------------------------------------------------
111
112
113
114
115 ------------------------------------------------------------------
116 --
117 -- DC ADC
118 --
119 ------------------------------------------------------------------
120 ADC1: IF CstDATA /= 1 GENERATE
121 ADC : IF FakeADC /=1 GENERATE
122
123 DC_ADC0 : DUAL_ADS1278_DRIVER
124 port map(
125 Clk => clk,
126 reset => reset,
127 SpiClk => DC_ADC_Sclk,
128 DIN => DC_ADC_IN,
129 SmplClk => DC_ADC_SmplClk,
130 OUT00 => AMR1X_Sync,
131 OUT01 => AMR1Y_Sync,
132 OUT02 => AMR1Z_Sync,
133 OUT03 => AMR2X_Sync,
134 OUT04 => AMR2Y_Sync,
135 OUT05 => AMR2Z_Sync,
136 OUT06 => Temp1_Sync,
137 OUT07 => Temp2_Sync,
138 OUT10 => AMR3X_Sync,
139 OUT11 => AMR3Y_Sync,
140 OUT12 => AMR3Z_Sync,
141 OUT13 => AMR4X_Sync,
142 OUT14 => AMR4Y_Sync,
143 OUT15 => AMR4Z_Sync,
144 OUT16 => Temp3_Sync,
145 OUT17 => Temp4_Sync,
146 FSynch => DC_ADC_FSynch
147 );
148 END GENERATE;
149
150 NOADC: IF FakeADC=1 GENERATE
151
152 DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
153 port map(
154 Clk => clk,
155 reset => reset,
156 SpiClk => DC_ADC_Sclk,
157 DIN => DC_ADC_IN,
158 SmplClk => DC_ADC_SmplClk,
159 OUT00 => AMR1X_Sync,
160 OUT01 => AMR1Y_Sync,
161 OUT02 => AMR1Z_Sync,
162 OUT03 => AMR2X_Sync,
163 OUT04 => AMR2Y_Sync,
164 OUT05 => AMR2Z_Sync,
165 OUT06 => Temp1_Sync,
166 OUT07 => Temp2_Sync,
167 OUT10 => AMR3X_Sync,
168 OUT11 => AMR3Y_Sync,
169 OUT12 => AMR3Z_Sync,
170 OUT13 => AMR4X_Sync,
171 OUT14 => AMR4Y_Sync,
172 OUT15 => AMR4Z_Sync,
173 OUT16 => Temp3_Sync,
174 OUT17 => Temp4_Sync,
175 FSynch => DC_ADC_FSynch
176 );
177 END GENERATE;
178
179 END GENERATE;
180 ------------------------------------------------------------------
181
182 NOADC: IF CstDATA = 1 GENERATE
183
184 AMR1X_Sync <= AMR1Xcst;
185 AMR1Y_Sync <= AMR1Ycst;
186 AMR1Z_Sync <= AMR1Zcst;
187 AMR2X_Sync <= AMR2Xcst;
188 AMR2Y_Sync <= AMR2Ycst;
189 AMR2Z_Sync <= AMR2Zcst;
190 Temp1_Sync <= Temp1cst;
191 Temp2_Sync <= Temp2cst;
192 AMR3X_Sync <= AMR3Xcst;
193 AMR3Y_Sync <= AMR3Ycst;
194 AMR3Z_Sync <= AMR3Zcst;
195 AMR4X_Sync <= AMR4Xcst;
196 AMR4Y_Sync <= AMR4Ycst;
197 AMR4Z_Sync <= AMR4Zcst;
198 Temp3_Sync <= Temp3cst;
199 Temp4_Sync <= Temp4cst;
200
201
202
203
204
205 END GENERATE;
206
207
208
209
210 ------------------------------------------------------------------
211 --
212 -- SET/RESET GEN
213 --
214 ------------------------------------------------------------------
215
216 SR: IF EnableSR /=0 GENERATE
217 process(reset,DC_ADC_SmplClk)
218 begin
219 if reset = '0' then
220 SET_RESET0_sig <= '0';
221 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
222 if(SET_RESET_counter = 31) then
223 SET_RESET0_sig <= not SET_RESET0_sig;
224 SET_RESET_counter <= 0;
225 else
226 SET_RESET_counter <= SET_RESET_counter +1;
227 end if;
228 end if;
229 end process;
230
231 END GENERATE;
232 NOSR: IF EnableSR=0 GENERATE
233 SET_RESET0_sig <= '0';
234 END GENERATE;
235
236 SET_RESET1_sig <= SET_RESET0_sig;
237 SET_RESET0 <= SET_RESET0_sig;
238 SET_RESET1 <= SET_RESET1_sig;
239 ------------------------------------------------------------------
240 ------------------------------------------------------------------
241
242
243 ------------------------------------------------------------------
244 --
245 -- Cross domain clock synchronisation
246 --
247 ------------------------------------------------------------------
248
249 IF CDS =1 GENERATE
250
251 AMR1Xsync: entity work.Fast2SlowSync
252 generic map(N => 24)
253 port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
254 AMR1Ysync: entity work.Fast2SlowSync
255 generic map(N => 24)
256 port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
257 AMR1Zsync: entity work.Fast2SlowSync
258 generic map(N => 24)
259 port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
260
261 AMR2Xsync: entity work.Fast2SlowSync
262 generic map(N => 24)
263 port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
264 AMR2Ysync: entity work.Fast2SlowSync
265 generic map(N => 24)
266 port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
267 AMR2Zsync: entity work.Fast2SlowSync
268 generic map(N => 24)
269 port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
270
271 AMR3Xsync: entity work.Fast2SlowSync
272 generic map(N => 24)
273 port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
274 AMR3Ysync: entity work.Fast2SlowSync
275 generic map(N => 24)
276 port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
277 AMR3Zsync: entity work.Fast2SlowSync
278 generic map(N => 24)
279 port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
280
281
282 AMR4Xsync: entity work.Fast2SlowSync
283 generic map(N => 24)
284 port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
285 AMR4Ysync: entity work.Fast2SlowSync
286 generic map(N => 24)
287 port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
288 AMR4Zsync: entity work.Fast2SlowSync
289 generic map(N => 24)
290 port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
291
292
293 TEMP1sync: entity work.Fast2SlowSync
294 generic map(N => 24)
295 port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
296 TEMP2sync: entity work.Fast2SlowSync
297 generic map(N => 24)
298 port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
299 TEMP3sync: entity work.Fast2SlowSync
300 generic map(N => 24)
301 port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
302 TEMP4sync: entity work.Fast2SlowSync
303 generic map(N => 24)
304 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
305
306 END GENERATE;
307
308 IF CDS /= 1 GENERATE
309
310
311 AMR1X_Sync <= AMR1X;
312 AMR1Y_Sync <= AMR1Y;
313 AMR1Z_Sync <= AMR1Z;
314 AMR2X_Sync <= AMR2X;
315 AMR2Y_Sync <= AMR2Y;
316 AMR2Z_Sync <= AMR2Z;
317 Temp1_Sync <= Temp1;
318 Temp2_Sync <= Temp2;
319 AMR3X_Sync <= AMR3X;
320 AMR3Y_Sync <= AMR3Y;
321 AMR3Z_Sync <= AMR3Z;
322 AMR4X_Sync <= AMR4X;
323 AMR4Y_Sync <= AMR4Y;
324 AMR4Z_Sync <= AMR4Z;
325 Temp3_Sync <= Temp3;
326 Temp4_Sync <= Temp4;
327
328 END GENERATE;
329 ------------------------------------------------------------------
330
331
332 end Behavioral;
333
334
335
336
337
338
339
340
341
342
343
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1 -- ADS1274_DRIVER.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5 library lpp;
6 use lpp.lpp_ad_conv.all;
7 use lpp.general_purpose.all;
8
9
10
11
12
13 entity FAKE_DUAL_ADS1278_DRIVER is
14 generic
15 (
16 SCLKDIV : integer range 2 to 256 :=16
17 );
18 port(
19 Clk : in std_logic;
20 reset : in std_logic;
21 SpiClk : out std_logic;
22 DIN : in std_logic_vector(1 downto 0);
23 SmplClk : in std_logic;
24 OUT00 : out std_logic_vector(23 downto 0);
25 OUT01 : out std_logic_vector(23 downto 0);
26 OUT02 : out std_logic_vector(23 downto 0);
27 OUT03 : out std_logic_vector(23 downto 0);
28 OUT04 : out std_logic_vector(23 downto 0);
29 OUT05 : out std_logic_vector(23 downto 0);
30 OUT06 : out std_logic_vector(23 downto 0);
31 OUT07 : out std_logic_vector(23 downto 0);
32 OUT10 : out std_logic_vector(23 downto 0);
33 OUT11 : out std_logic_vector(23 downto 0);
34 OUT12 : out std_logic_vector(23 downto 0);
35 OUT13 : out std_logic_vector(23 downto 0);
36 OUT14 : out std_logic_vector(23 downto 0);
37 OUT15 : out std_logic_vector(23 downto 0);
38 OUT16 : out std_logic_vector(23 downto 0);
39 OUT17 : out std_logic_vector(23 downto 0);
40 FSynch : out std_logic
41 );
42 end FAKE_DUAL_ADS1278_DRIVER;
43
44
45
46
47
48
49 architecture ar_FAKE_DUAL_ADS1278_DRIVER of FAKE_DUAL_ADS1278_DRIVER is
50 signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0);
51 signal ShiftGeg20,ShiftGeg21 : std_logic_vector((8*24)-1 downto 0);
52 signal SmplClk_Reg : std_logic:= '0';
53 signal N : integer range 0 to (24*8) := 0;
54 signal SPI_CLk : std_logic;
55 signal SmplClk_clkd : std_logic:= '0';
56 signal OUT00_r : std_logic_vector(23 downto 0) := (others => '0');
57 signal OUT01_r : std_logic_vector(23 downto 0) := (others => '0');
58 signal OUT02_r : std_logic_vector(23 downto 0) := (others => '0');
59 signal OUT03_r : std_logic_vector(23 downto 0) := (others => '0');
60 signal OUT04_r : std_logic_vector(23 downto 0) := (others => '0');
61 signal OUT05_r : std_logic_vector(23 downto 0) := (others => '0');
62 signal OUT06_r : std_logic_vector(23 downto 0) := (others => '0');
63 signal OUT07_r : std_logic_vector(23 downto 0) := (others => '0');
64 signal OUT10_r : std_logic_vector(23 downto 0) := (others => '0');
65 signal OUT11_r : std_logic_vector(23 downto 0) := (others => '0');
66 signal OUT12_r : std_logic_vector(23 downto 0) := (others => '0');
67 signal OUT13_r : std_logic_vector(23 downto 0) := (others => '0');
68 signal OUT14_r : std_logic_vector(23 downto 0) := (others => '0');
69 signal OUT15_r : std_logic_vector(23 downto 0) := (others => '0');
70 signal OUT16_r : std_logic_vector(23 downto 0) := (others => '0');
71 signal OUT17_r : std_logic_vector(23 downto 0) := (others => '0');
72
73 begin
74
75
76 CLKDIV0 : Clk_Divider2
77 generic map(SCLKDIV)
78 port map(Clk,SPI_CLk);
79
80
81 FSynch <= SmplClk;
82 SpiClk <= SPI_CLk;
83
84 process(reset,SPI_CLk)
85 begin
86
87 if reset = '0' then
88 ShiftGeg0 <= (others => '0');
89 ShiftGeg1 <= (others => '0');
90 N <= 0;
91 OUT00_r <= (others => '0');
92 OUT01_r <= (others => '0');
93 OUT02_r <= (others => '0');
94 OUT03_r <= (others => '0');
95 OUT04_r <= (others => '0');
96 OUT05_r <= (others => '0');
97 OUT06_r <= (others => '0');
98 OUT07_r <= (others => '0');
99 OUT10_r <= (others => '0');
100 OUT11_r <= (others => '0');
101 OUT12_r <= (others => '0');
102 OUT13_r <= (others => '0');
103 OUT14_r <= (others => '0');
104 OUT15_r <= (others => '0');
105 OUT16_r <= (others => '0');
106 OUT17_r <= (others => '0');
107 ShiftGeg20 <= (others => '0');
108 ShiftGeg21 <= (others => '0');
109
110 elsif SPI_CLk'event and SPI_CLk = '1' then
111 if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
112 ShiftGeg20((8*24)-1 downto 0) <= ShiftGeg20((8*24)-2 downto 0) & '0';
113 ShiftGeg21((8*24)-1 downto 0) <= ShiftGeg21((8*24)-2 downto 0) & '0';
114 ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & ShiftGeg20((8*24)-1);
115 ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & ShiftGeg21((8*24)-1);
116 if N = ((24*8)-1) then
117 N <= 0;
118 OUT00_r <= std_logic_vector(UNSIGNED(OUT00_r) + 1);
119 OUT01_r <= std_logic_vector(UNSIGNED(OUT01_r) + 2);
120 OUT02_r <= std_logic_vector(UNSIGNED(OUT02_r) + 3);
121 OUT03_r <= std_logic_vector(UNSIGNED(OUT03_r) + 4);
122 OUT04_r <= std_logic_vector(UNSIGNED(OUT04_r) + 5);
123 OUT05_r <= std_logic_vector(UNSIGNED(OUT05_r) + 6);
124 OUT06_r <= std_logic_vector(UNSIGNED(OUT06_r) + 7);
125 OUT07_r <= std_logic_vector(UNSIGNED(OUT07_r) + 8);
126 OUT10_r <= std_logic_vector(UNSIGNED(OUT10_r) + 9);
127 OUT11_r <= std_logic_vector(UNSIGNED(OUT11_r) + 10);
128 OUT12_r <= std_logic_vector(UNSIGNED(OUT12_r) + 11);
129 OUT13_r <= std_logic_vector(UNSIGNED(OUT13_r) + 12);
130 OUT14_r <= std_logic_vector(UNSIGNED(OUT14_r) + 13);
131 OUT15_r <= std_logic_vector(UNSIGNED(OUT15_r) + 14);
132 OUT16_r <= std_logic_vector(UNSIGNED(OUT16_r) + 15);
133 OUT17_r <= std_logic_vector(UNSIGNED(OUT17_r) + 16);
134
135 ShiftGeg20((24*1)-1 downto (24*(1-1))) <= OUT00_r;
136 ShiftGeg20((24*2)-1 downto (24*(2-1))) <= OUT01_r;
137 ShiftGeg20((24*3)-1 downto (24*(3-1))) <= OUT02_r;
138 ShiftGeg20((24*4)-1 downto (24*(4-1))) <= OUT03_r;
139 ShiftGeg20((24*5)-1 downto (24*(5-1))) <= OUT04_r;
140 ShiftGeg20((24*6)-1 downto (24*(6-1))) <= OUT05_r;
141 ShiftGeg20((24*7)-1 downto (24*(7-1))) <= OUT06_r;
142 ShiftGeg20((24*8)-1 downto (24*(8-1))) <= OUT07_r;
143
144 ShiftGeg21((24*1)-1 downto (24*(1-1))) <= OUT10_r;
145 ShiftGeg21((24*2)-1 downto (24*(2-1))) <= OUT11_r;
146 ShiftGeg21((24*3)-1 downto (24*(3-1))) <= OUT12_r;
147 ShiftGeg21((24*4)-1 downto (24*(4-1))) <= OUT13_r;
148 ShiftGeg21((24*5)-1 downto (24*(5-1))) <= OUT14_r;
149 ShiftGeg21((24*6)-1 downto (24*(6-1))) <= OUT15_r;
150 ShiftGeg21((24*7)-1 downto (24*(7-1))) <= OUT16_r;
151 ShiftGeg21((24*8)-1 downto (24*(8-1))) <= OUT17_r;
152 else
153 N <= N+1;
154 end if;
155 end if;
156 end if;
157 end process;
158
159
160 process(SPI_CLk)
161 begin
162 if SPI_CLk'event and SPI_CLk ='0' then
163 SmplClk_clkd <= SmplClk;
164 SmplClk_Reg <= SmplClk_clkd;
165 end if;
166 end process;
167
168
169 process(clk,reset)
170 begin
171 if reset = '0' then
172 OUT00 <= (others => '0');
173 OUT01 <= (others => '0');
174 OUT02 <= (others => '0');
175 OUT03 <= (others => '0');
176 OUT04 <= (others => '0');
177 OUT05 <= (others => '0');
178 OUT06 <= (others => '0');
179 OUT07 <= (others => '0');
180
181 OUT10 <= (others => '0');
182 OUT11 <= (others => '0');
183 OUT12 <= (others => '0');
184 OUT13 <= (others => '0');
185 OUT14 <= (others => '0');
186 OUT15 <= (others => '0');
187 OUT16 <= (others => '0');
188 OUT17 <= (others => '0');
189 elsif clk'event and clk ='1' then
190 if N = 0 then
191 OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1)));
192 OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1)));
193 OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1)));
194 OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1)));
195 OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1)));
196 OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1)));
197 OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1)));
198 OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1)));
199
200 OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1)));
201 OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1)));
202 OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1)));
203 OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1)));
204 OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1)));
205 OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1)));
206 OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1)));
207 OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1)));
208
209 end if;
210 end if;
211 end process;
212
213 end ar_FAKE_DUAL_ADS1278_DRIVER;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 --
23 -- This module implements the Fast to Slow clock transfer:
24 -- Data Transfer between Asynchronous Clock Domains without Pain
25 -- from Markus Schutti, Markus Pfaff, Richard Hagelauer
26 -- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
27 -- see page 6
28 --
29 --
30
31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL;
33
34 entity Fast2SlowSync is
35 generic
36 (
37 N : integer range 0 to 256:=8
38 );
39 Port
40 (
41 Data : in STD_LOGIC_VECTOR (N-1 downto 0);
42 ClockF : in STD_LOGIC;
43 ClockS : in STD_LOGIC;
44 SyncSignal : in STD_LOGIC;
45 DataSinkF : out STD_LOGIC_VECTOR (N-1 downto 0)
46 );
47 end Fast2SlowSync;
48
49 architecture AR_Fast2SlowSync of Fast2SlowSync is
50
51 signal DataF : STD_LOGIC_VECTOR (N-1 downto 0);
52 signal DataFlocked : STD_LOGIC_VECTOR (N-1 downto 0);
53
54 signal MuxOut : STD_LOGIC_VECTOR (N-1 downto 0);
55
56 begin
57
58 MuxOut <= DataF when SyncSignal = '1' else
59 DataFlocked;
60
61 process(ClockF)
62 begin
63 if ClockF'event and ClockF = '1' then
64 DataF <= Data;
65 DataFlocked <= MuxOut;
66 end if;
67 end process;
68
69 process(ClockS)
70 begin
71 if ClockS'event and ClockS = '1' then
72 DataSinkF <= DataFlocked;
73 end if;
74 end process;
75
76 end AR_Fast2SlowSync;
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1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 --use gaisler.sim.all;
16 library lpp;
17 use lpp.lpp_ad_conv.all;
18 use lpp.lpp_amba.all;
19 use lpp.apb_devices_list.all;
20 use lpp.general_purpose.all;
21 use lpp.Rocket_PCM_Encoder.all;
22
23
24 use work.Convertisseur_config.all;
25
26
27 use work.config.all;
28 --==================================================================
29 --
30 --
31 -- FPGA FREQ = 48MHz
32 -- ADC Oscillator frequency = 4MHz
33 --
34 --
35 --==================================================================
36
37 entity ici4_OLD is
38 generic (
39 fabtech : integer := CFG_FABTECH;
40 memtech : integer := CFG_MEMTECH;
41 padtech : integer := CFG_PADTECH;
42 clktech : integer := CFG_CLKTECH;
43 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
44 );
45 port (
46 reset : in std_ulogic;
47 clk : in std_ulogic;
48 sclk : in std_logic;
49 Gate : in std_logic;
50 MinF : in std_logic;
51 MajF : in std_logic;
52 Data : out std_logic;
53 DC_ADC_Sclk : out std_logic;
54 DC_ADC_IN : in std_logic_vector(1 downto 0);
55 DC_ADC_ClkDiv : out std_logic;
56 DC_ADC_FSynch : out std_logic;
57 SET_RESET0 : out std_logic;
58 SET_RESET1 : out std_logic;
59 LED : out std_logic
60 );
61 end;
62
63 architecture rtl of ici4_OLD is
64
65 signal clk_buf,reset_buf : std_logic;
66
67 Constant FramePlacerCount : integer := 2;
68
69 signal MinF_Inv : std_logic;
70 signal Gate_Inv : std_logic;
71 signal sclk_Inv : std_logic;
72 signal WordCount : integer range 0 to WordCnt-1;
73 signal WordClk : std_logic;
74
75 signal data_int : std_logic;
76
77 signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
78 signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
79 signal Sel : integer range 0 to 1;
80
81 signal AMR1X : std_logic_vector(23 downto 0);
82 signal AMR1Y : std_logic_vector(23 downto 0);
83 signal AMR1Z : std_logic_vector(23 downto 0);
84
85 signal AMR2X : std_logic_vector(23 downto 0);
86 signal AMR2Y : std_logic_vector(23 downto 0);
87 signal AMR2Z : std_logic_vector(23 downto 0);
88
89 signal AMR3X : std_logic_vector(23 downto 0);
90 signal AMR3Y : std_logic_vector(23 downto 0);
91 signal AMR3Z : std_logic_vector(23 downto 0);
92
93 signal AMR4X : std_logic_vector(23 downto 0);
94 signal AMR4Y : std_logic_vector(23 downto 0);
95 signal AMR4Z : std_logic_vector(23 downto 0);
96
97 signal AMR1X_ADC : std_logic_vector(23 downto 0);
98 signal AMR1Y_ADC : std_logic_vector(23 downto 0);
99 signal AMR1Z_ADC : std_logic_vector(23 downto 0);
100
101 signal AMR2X_ADC : std_logic_vector(23 downto 0);
102 signal AMR2Y_ADC : std_logic_vector(23 downto 0);
103 signal AMR2Z_ADC : std_logic_vector(23 downto 0);
104
105 signal AMR3X_ADC : std_logic_vector(23 downto 0);
106 signal AMR3Y_ADC : std_logic_vector(23 downto 0);
107 signal AMR3Z_ADC : std_logic_vector(23 downto 0);
108
109 signal AMR4X_ADC : std_logic_vector(23 downto 0);
110 signal AMR4Y_ADC : std_logic_vector(23 downto 0);
111 signal AMR4Z_ADC : std_logic_vector(23 downto 0);
112
113 signal AMR1X_R : std_logic_vector(23 downto 0);
114 signal AMR1Y_R : std_logic_vector(23 downto 0);
115 signal AMR1Z_R : std_logic_vector(23 downto 0);
116
117 signal AMR2X_R : std_logic_vector(23 downto 0);
118 signal AMR2Y_R : std_logic_vector(23 downto 0);
119 signal AMR2Z_R : std_logic_vector(23 downto 0);
120
121 signal AMR3X_R : std_logic_vector(23 downto 0);
122 signal AMR3Y_R : std_logic_vector(23 downto 0);
123 signal AMR3Z_R : std_logic_vector(23 downto 0);
124
125 signal AMR4X_R : std_logic_vector(23 downto 0);
126 signal AMR4Y_R : std_logic_vector(23 downto 0);
127 signal AMR4Z_R : std_logic_vector(23 downto 0);
128
129 signal AMR1X_S : std_logic_vector(23 downto 0);
130 signal AMR1Y_S : std_logic_vector(23 downto 0);
131 signal AMR1Z_S : std_logic_vector(23 downto 0);
132
133 signal AMR2X_S : std_logic_vector(23 downto 0);
134 signal AMR2Y_S : std_logic_vector(23 downto 0);
135 signal AMR2Z_S : std_logic_vector(23 downto 0);
136
137 signal AMR3X_S : std_logic_vector(23 downto 0);
138 signal AMR3Y_S : std_logic_vector(23 downto 0);
139 signal AMR3Z_S : std_logic_vector(23 downto 0);
140
141 signal AMR4X_S : std_logic_vector(23 downto 0);
142 signal AMR4Y_S : std_logic_vector(23 downto 0);
143 signal AMR4Z_s : std_logic_vector(23 downto 0);
144
145
146
147 signal Temp1 : std_logic_vector(23 downto 0);
148 signal Temp2 : std_logic_vector(23 downto 0);
149 signal Temp3 : std_logic_vector(23 downto 0);
150 signal Temp4 : std_logic_vector(23 downto 0);
151
152
153 signal LF1 : std_logic_vector(15 downto 0);
154 signal LF2 : std_logic_vector(15 downto 0);
155 signal LF3 : std_logic_vector(15 downto 0);
156
157
158 signal LF1_int : std_logic_vector(23 downto 0);
159 signal LF2_int : std_logic_vector(23 downto 0);
160 signal LF3_int : std_logic_vector(23 downto 0);
161
162 signal DC_ADC_SmplClk : std_logic;
163 signal LF_ADC_SmplClk : std_logic;
164 signal SET_RESET0_sig : std_logic;
165 signal SET_RESET1_sig : std_logic;
166 signal SET_RESET_counter : integer range 0 to 31:=0;
167
168 signal MinFCnt : integer range 0 to MinFCount-1;
169
170 signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
171
172 begin
173
174
175 clk_buf <= clk;
176 reset_buf <= reset;
177 --
178
179 Gate_Inv <= not Gate;
180 sclk_Inv <= not Sclk;
181 MinF_Inv <= not MinF;
182
183 LED <= not data_int;
184 data <= data_int;
185
186
187
188 SD0 : Serial_Driver
189 generic map(WordSize)
190 port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
191
192 WC0 : Word_Cntr
193 generic map(WordSize,WordCnt)
194 port map(sclk_Inv,MinF,WordClk,WordCount);
195
196 MFC0 : MinF_Cntr
197 generic map(MinFCount)
198 port map(
199 clk => MinF_Inv,
200 reset => MajF,
201 Cnt_out => MinFCnt
202 );
203
204
205 MUX0 : Serial_Driver_Multiplexor
206 generic map(FramePlacerCount,WordSize)
207 port map(sclk_Inv,Sel,MuxIN,MuxOUT);
208
209
210 DCFP0 : entity work.DC_FRAME_PLACER
211 generic map(WordSize,WordCnt,MinFCount)
212 port map(
213 clk => Sclk,
214 Wcount => WordCount,
215 MinFCnt => MinFCnt,
216 Flag => FramePlacerFlags(0),
217 AMR1X => AMR1X,
218 AMR1Y => AMR1Y,
219 AMR1Z => AMR1Z,
220 AMR2X => AMR2X,
221 AMR2Y => AMR2Y,
222 AMR2Z => AMR2Z,
223 AMR3X => AMR3X,
224 AMR3Y => AMR3Y,
225 AMR3Z => AMR3Z,
226 AMR4X => AMR4X,
227 AMR4Y => AMR4Y,
228 AMR4Z => AMR4Z,
229 Temp1 => Temp1,
230 Temp2 => Temp2,
231 Temp3 => Temp3,
232 Temp4 => Temp4,
233 WordOut => MuxIN(7 downto 0));
234
235
236
237 LFP0 : entity work.LF_FRAME_PLACER
238 generic map(WordSize,WordCnt,MinFCount)
239 port map(
240 clk => Sclk,
241 Wcount => WordCount,
242 Flag => FramePlacerFlags(1),
243 LF1 => LF1,
244 LF2 => LF2,
245 LF3 => LF3,
246 WordOut => MuxIN(15 downto 8));
247
248
249
250 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
251 generic map(36)
252 port map(
253 reset => reset,
254 wclk => WordClk,
255 SMPL_CLK => DC_ADC_SmplClk);
256
257 process(reset,DC_ADC_SmplClk)
258 begin
259 if reset = '0' then
260 SET_RESET0_sig <= '0';
261 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
262 if(SET_RESET_counter = 31) then
263 SET_RESET0_sig <= not SET_RESET0_sig;
264 SET_RESET_counter <= 0;
265 else
266 SET_RESET_counter <= SET_RESET_counter +1;
267 end if;
268 end if;
269 end process;
270
271 SET_RESET1_sig <= SET_RESET0_sig;
272 SET_RESET0 <= SET_RESET0_sig;
273 SET_RESET1 <= SET_RESET1_sig;
274 --
275
276
277
278 send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE
279 DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin
280 port map(
281 Clk => clk_buf,
282 reset => reset_buf,
283 SpiClk => DC_ADC_Sclk,
284 DIN => DC_ADC_IN,
285 SmplClk => DC_ADC_SmplClk,
286 OUT00 => AMR1X,
287 OUT01 => AMR1Y,
288 OUT02 => AMR1Z,
289 OUT03 => AMR2X,
290 OUT04 => AMR2Y,
291 OUT05 => AMR2Z,
292 OUT06 => Temp1,
293 OUT07 => Temp2,
294 OUT10 => AMR3X,
295 OUT11 => AMR3Y,
296 OUT12 => AMR3Z,
297 OUT13 => AMR4X,
298 OUT14 => AMR4Y,
299 OUT15 => AMR4Z,
300 OUT16 => Temp3,
301 OUT17 => Temp4,
302 FSynch => DC_ADC_FSynch
303 );
304 LF1 <= LF1cst;
305 LF2 <= LF2cst;
306 LF3 <= LF3cst;
307 END GENERATE;
308
309 send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE
310 AMR1X <= AMR1Xcst;
311 AMR1Y <= AMR1Ycst;
312 AMR1Z <= AMR1Zcst;
313 AMR2X <= AMR2Xcst;
314 AMR2Y <= AMR2Ycst;
315 AMR2Z <= AMR2Zcst;
316 Temp1 <= Temp1cst;
317 Temp2 <= Temp2cst;
318 AMR3X <= AMR3Xcst;
319 AMR3Y <= AMR3Ycst;
320 AMR3Z <= AMR3Zcst;
321 AMR4X <= AMR4Xcst;
322 AMR4Y <= AMR4Ycst;
323 AMR4Z <= AMR4Zcst;
324 Temp3 <= Temp3cst;
325 Temp4 <= Temp4cst;
326
327 LF1 <= LF1cst;
328 LF2 <= LF2cst;
329 LF3 <= LF3cst;
330 END GENERATE;
331
332
333
334
335 send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE
336 AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
337 AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
338 AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
339 AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
340 AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
341 AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
342 Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
343 Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
344 AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
345 AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
346 AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
347 AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
348 AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
349 AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
350 Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
351 Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
352
353 LF1 <= LF1cst;
354 LF2 <= LF2cst;
355 LF3 <= LF3cst;
356 END GENERATE;
357
358 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
359 port map(
360 reset => reset,
361 wclk => WordClk,
362 SMPL_CLK => LF_ADC_SmplClk
363 );
364
365
366 sr_hndl: IF SEND_CONSTANT_DATA = 0 GENERATE
367 process(clk)
368 begin
369 if clk'event and clk ='1' then
370 if SET_RESET0_sig = '1' then
371 AMR1X_S <= AMR1X_ADC;
372 AMR1Y_S <= AMR1Y_ADC;
373 AMR1Z_S <= AMR1Z_ADC;
374 AMR2X_S <= AMR2X_ADC;
375 AMR2Y_S <= AMR2Y_ADC;
376 AMR2Z_S <= AMR2Z_ADC;
377 AMR3X_S <= AMR3X_ADC;
378 AMR3Y_S <= AMR3Y_ADC;
379 AMR3Z_S <= AMR3Z_ADC;
380 AMR4X_S <= AMR4X_ADC;
381 AMR4Y_S <= AMR4Y_ADC;
382 AMR4Z_S <= AMR4Z_ADC;
383 else
384 AMR1X_R <= AMR1X_ADC;
385 AMR1Y_R <= AMR1Y_ADC;
386 AMR1Z_R <= AMR1Z_ADC;
387 AMR2X_R <= AMR2X_ADC;
388 AMR2Y_R <= AMR2Y_ADC;
389 AMR2Z_R <= AMR2Z_ADC;
390 AMR3X_R <= AMR3X_ADC;
391 AMR3Y_R <= AMR3Y_ADC;
392 AMR3Z_R <= AMR3Z_ADC;
393 AMR4X_R <= AMR4X_ADC;
394 AMR4Y_R <= AMR4Y_ADC;
395 AMR4Z_R <= AMR4Z_ADC;
396 end if;
397 -- AMR1X <= std_logic_vector((signed(AMR1X_S) - signed(AMR1X_R))/2);
398 -- AMR1Y <= std_logic_vector((signed(AMR1Y_S) - signed(AMR1Y_R))/2);
399 -- AMR1Z <= std_logic_vector((signed(AMR1Z_S) - signed(AMR1Z_R))/2);
400 -- AMR2X <= std_logic_vector((signed(AMR2X_S) - signed(AMR2X_R))/2);
401 -- AMR2Y <= std_logic_vector((signed(AMR2Y_S) - signed(AMR2Y_R))/2);
402 -- AMR2Z <= std_logic_vector((signed(AMR2Z_S) - signed(AMR2Z_R))/2);
403 -- AMR3X <= std_logic_vector((signed(AMR3X_S) - signed(AMR3X_R))/2);
404 -- AMR3Y <= std_logic_vector((signed(AMR3Y_S) - signed(AMR3Y_R))/2);
405 -- AMR3Z <= std_logic_vector((signed(AMR3Z_S) - signed(AMR3Z_R))/2);
406 -- AMR4X <= std_logic_vector((signed(AMR4X_S) - signed(AMR4X_R))/2);
407 -- AMR4Y <= std_logic_vector((signed(AMR4Y_S) - signed(AMR4Y_R))/2);
408 -- AMR4Z <= std_logic_vector((signed(AMR4Z_S) - signed(AMR4Z_R))/2);
409 -- AMR1X <= AMR1X_S;
410 -- AMR1Y <= AMR1Y_S;
411 -- AMR1Z <= AMR1Z_S;
412 -- AMR2X <= AMR2X_S;
413 -- AMR2Y <= AMR2Y_S;
414 -- AMR2Z <= AMR2Z_S;
415 -- AMR3X <= AMR3X_S;
416 -- AMR3Y <= AMR3Y_S;
417 -- AMR3Z <= AMR3Z_S;
418 -- AMR4X <= AMR4X_S;
419 -- AMR4Y <= AMR4Y_S;
420 -- AMR4Z <= AMR4Z_S;
421 end if;
422 end process;
423 end generate;
424
425
426 process(clk)
427 variable SelVar : integer range 0 to 1;
428 begin
429 if clk'event and clk ='1' then
430 Decoder: FOR i IN 0 to FramePlacerCount-1 loop
431 if FramePlacerFlags(i) = '1' then
432 SelVar := i;
433 end if;
434 END loop Decoder;
435 Sel <= SelVar;
436 end if;
437 end process;
438
439
440 end rtl;
441
442
443
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1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 library lpp;
4 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_amba.all;
6 use lpp.apb_devices_list.all;
7 use lpp.general_purpose.all;
8 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.iir_filter.all;
10 use work.config.all;
11
12
13 entity IIR_FILTER_TOP is
14 generic
15 (
16 V2 : integer :=0 -- IF 1 uses V2 else use V1
17 );
18 port
19 (
20 rstn : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22
23 SMPclk : IN STD_LOGIC;
24 LF1_IN : IN std_logic_vector(15 downto 0);
25 LF2_IN : IN std_logic_vector(15 downto 0);
26 LF3_IN : IN std_logic_vector(15 downto 0);
27
28 SMPCLKOut : OUT STD_LOGIC;
29 LF1_OUT : OUT std_logic_vector(15 downto 0);
30 LF2_OUT : OUT std_logic_vector(15 downto 0);
31 LF3_OUT : OUT std_logic_vector(15 downto 0)
32 );
33 end IIR_FILTER_TOP;
34
35 architecture AR_IIR_FILTER_TOP of IIR_FILTER_TOP is
36 signal sps : Samples(2 DOWNTO 0);
37
38 signal LFX : Samples(2 DOWNTO 0);
39 signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
40 signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
41 signal sample_out_val : std_logic;
42 signal LF_ADC_SpPulse : std_logic;
43
44 begin
45
46 sps(0) <= LF1_IN;
47 sps(1) <= LF2_IN;
48 sps(2) <= LF3_IN;
49
50 LF1_OUT <= LFX(0);
51 LF2_OUT <= LFX(1);
52 LF3_OUT <= LFX(2);
53
54 SMPCLKOut <= sample_out_val;
55
56 loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
57
58 loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
59 process(rstn,clk)
60 begin
61 if rstn ='0' then
62 Filter_sp_in(I,J) <= '0';
63 -- LFX(I) <= (others => '0');
64 elsif clk'event and clk ='1' then
65 if sample_out_val = '1' then
66 LFX(I)(J) <= Filter_sp_out(I,J);
67 Filter_sp_in(I,J) <= sps(I)(J);
68 end if;
69 end if;
70 end process;
71 END GENERATE;
72 END GENERATE;
73
74 V2FILTER: IF V2 = 1 GENERATE
75
76 smpPulse: entity work.OneShot
77 Port map(
78 reset => rstn,
79 clk => clk,
80 input => SMPclk,
81 output => LF_ADC_SpPulse
82 );
83
84 FilterV2: IIR_CEL_CTRLR_v2
85 GENERIC map(
86 tech => CFG_MEMTECH,
87 Mem_use => use_RAM,
88 Sample_SZ => Sample_SZ,
89 Coef_SZ => Coef_SZ,
90 Coef_Nb => 25,
91 Coef_sel_SZ => 5,
92 Cels_count => 5,
93 ChanelsCount => ChanelsCount
94 )
95 PORT map(
96 rstn => rstn,
97 clk => clk,
98
99 virg_pos => virgPos,
100 coefs => CoefsInitValCst_v2,
101
102 sample_in_val => LF_ADC_SpPulse,
103 sample_in => Filter_sp_in,
104
105 sample_out_val => sample_out_val,
106 sample_out => Filter_sp_out
107 );
108
109
110
111 END GENERATE;
112
113 V1FILTER: IF V2 /= 1 GENERATE
114
115 sample_out_val <= SMPclk;
116
117
118 FilterV1: IIR_CEL_CTRLR
119 generic map(
120 tech => CFG_MEMTECH,
121 Sample_SZ => Sample_SZ,
122 ChanelsCount => 3,
123 Coef_SZ => Coef_SZ,
124 CoefCntPerCel=> CoefCntPerCel,
125 Cels_count => Cels_count,
126 Mem_use => use_RAM
127 )
128 port map(
129 reset => rstn,
130 clk => clk,
131 sample_clk => SMPclk,
132 sample_in => Filter_sp_in,
133 sample_out => Filter_sp_out,
134 virg_pos => virgPos,
135 GOtest => open,
136 coefs => CoefsInitValCst
137 );
138
139 END GENERATE;
140
141
142 end AR_IIR_FILTER_TOP;
143
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1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 library lpp;
4 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_amba.all;
6 use lpp.apb_devices_list.all;
7 use lpp.general_purpose.all;
8 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.iir_filter.all;
10 use work.config.all;
11
12 entity LF_ACQ_TOP is
13 generic(
14 WordSize : integer := 8;
15 WordCnt : integer := 144;
16 MinFCount : integer := 64;
17 CstDATA : integer := 0;
18 IIRFilter : integer := 0
19 );
20 port(
21
22 reset : in std_logic;
23 clk : in std_logic;
24 SyncSig : in STD_LOGIC;
25 minorF : in std_logic;
26 majorF : in std_logic;
27 sclk : in std_logic;
28 WordClk : in std_logic;
29 LF_SCK : out std_logic;
30 LF_CNV : out std_logic;
31 LF_SDO1 : in std_logic;
32 LF_SDO2 : in std_logic;
33 LF_SDO3 : in std_logic;
34 LF1 : out std_logic_vector(15 downto 0);
35 LF2 : out std_logic_vector(15 downto 0);
36 LF3 : out std_logic_vector(15 downto 0)
37 );
38 end LF_ACQ_TOP;
39
40 architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is
41
42 signal LF_ADC_SmplClk : std_logic;
43
44 signal LF_ADC_SpPulse : std_logic;
45 signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0);
46 signal sps : Samples(2 DOWNTO 0);
47
48 signal LFX : Samples(2 DOWNTO 0);
49 signal sample_val : std_logic;
50 signal AD_in : AD7688_in(2 DOWNTO 0);
51 signal AD_out : AD7688_out;
52 signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
53 signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
54 signal sample_out_val : std_logic;
55
56 signal LF1_sync : std_logic_vector(15 downto 0);
57 signal LF2_sync : std_logic_vector(15 downto 0);
58 signal LF3_sync : std_logic_vector(15 downto 0);
59
60 begin
61
62
63 AD_in(0).sdi <= LF_SDO1;
64 AD_in(1).sdi <= LF_SDO2;
65 AD_in(2).sdi <= LF_SDO3;
66 LF_SCK <= AD_out.SCK;
67 LF_CNV <= AD_out.CNV;
68
69
70 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
71 generic map(6)
72 port map(
73 reset => reset,
74 wclk => WordClk,
75 SMPL_CLK => LF_ADC_SmplClk
76 );
77
78
79 ADC: IF CstDATA =0 GENERATE
80 ADCs: AD7688_drvr
81 GENERIC map
82 (
83 ChanelCount => 3,
84 clkkHz => 48000
85 )
86 PORT map
87 (
88 clk => clk,
89 rstn => reset,
90 enable => '1',
91 smplClk => LF_ADC_SmplClk,
92 DataReady => sample_val,
93 smpout => sps,
94 AD_in => AD_in,
95 AD_out => AD_out
96 );
97
98 smpPulse: entity work.OneShot
99 Port map(
100 reset => reset,
101 clk => clk,
102 input => LF_ADC_SmplClk,
103 output => LF_ADC_SpPulse
104 );
105
106
107
108
109 NOfilt: IF IIRFilter = 0 GENERATE
110 process(reset,clk)
111 begin
112 if reset ='0' then
113 LF1_sync <= (others => '0');
114 LF2_sync <= (others => '0');
115 LF3_sync <= (others => '0');
116 elsif clk'event and clk ='1' then
117 if sample_val = '1' then
118 LF1_sync <= sps(0);
119 LF2_sync <= sps(1);
120 LF3_sync <= sps(2);
121 end if;
122 end if;
123 end process;
124 END GENERATE;
125
126
127 filt: IF IIRFilter /= 0 GENERATE
128
129
130 filtertop: entity work.IIR_FILTER_TOP
131 generic map
132 (
133 V2 => 0
134 )
135 port map
136 (
137 rstn => reset,
138 clk => clk,
139
140 SMPclk => LF_ADC_SmplClk,
141 LF1_IN => sps(0),
142 LF2_IN => sps(1),
143 LF3_IN => sps(2),
144
145 SMPCLKOut => open,
146 LF1_OUT => LF1_sync,
147 LF2_OUT => LF2_sync,
148 LF3_OUT => LF3_sync
149 );
150
151 END GENERATE;
152
153
154
155
156 END GENERATE;
157
158 CST: IF CstDATA /=0 GENERATE
159
160 LF1_sync <= LF1cst;
161 LF2_sync <= LF2cst;
162 LF3_sync <= LF3cst;
163
164 END GENERATE;
165
166
167
168 LF1sync: entity work.Fast2SlowSync
169 generic map(N => 16)
170 port map( LF1_sync,clk,sclk,SyncSig,LF1);
171
172 LF2sync: entity work.Fast2SlowSync
173 generic map(N => 16)
174 port map( LF2_sync,clk,sclk,SyncSig,LF2);
175
176 LF3sync: entity work.Fast2SlowSync
177 generic map(N => 16)
178 port map( LF3_sync,clk,sclk,SyncSig,LF3);
179
180 --Filter: IIR_CEL_FILTER
181 -- GENERIC map(
182 -- tech => CFG_MEMTECH,
183 -- Sample_SZ => Sample_SZ,
184 -- ChanelsCount => ChanelsCount,
185 -- Coef_SZ => Coef_SZ,
186 -- CoefCntPerCel => CoefCntPerCel,
187 -- Cels_count => Cels_count,
188 -- Mem_use => use_RAM
189 -- )
190 -- PORT map(
191 -- reset => reset,
192 -- clk => clk,
193 -- sample_clk => LF_ADC_SmplClk,
194 -- regs_in : IN in_IIR_CEL_reg;
195 -- regs_out : IN out_IIR_CEL_reg;
196 -- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
197 -- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
198 -- GOtest : OUT STD_LOGIC;
199 -- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
200 --
201 -- );
202
203
204
205
206 end AR_LF_ACQ_TOP;
207
208
209
210
211
212
213
214
215
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 21:06:46 08/22/2013
6 -- Design Name:
7 -- Module Name: OneShot - AR_OneShot
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity OneShot is
33 Port ( reset : in STD_LOGIC;
34 clk : in STD_LOGIC;
35 input : in STD_LOGIC;
36 output : out STD_LOGIC);
37 end OneShot;
38
39 architecture AR_OneShot of OneShot is
40 signal inreg : std_logic;
41 begin
42
43 process(clk,reset)
44 begin
45 if reset = '0' then
46 output <= '0';
47 elsif clk'event and clk = '1' then
48 inreg <= input;
49 if inreg = '0' and input = '1' then
50 output <= '1';
51 else
52 output <= '0';
53 end if;
54 end if;
55 end process;
56
57 end AR_OneShot;
58
59
60
61
62
63
64
65
66
67
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
22 --
23 -- This module implements the Slow to Slow Fast transfer:
24 -- Data Transfer between Asynchronous Clock Domains without Pain
25 -- from Markus Schutti, Markus Pfaff, Richard Hagelauer
26 -- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf
27 -- see page 5
28 --
29 --
30
31 library IEEE;
32 use IEEE.STD_LOGIC_1164.ALL;
33
34 entity Slow2FastSync is
35 generic
36 (
37 N : integer range 0 to 256:=8
38 );
39 Port
40 (
41 Data : in STD_LOGIC_VECTOR (N-1 downto 0);
42 ClockF : in STD_LOGIC;
43 ClockS : in STD_LOGIC;
44 SyncSignal : in STD_LOGIC;
45 DataSinkS : out STD_LOGIC_VECTOR (N-1 downto 0)
46 );
47 end Slow2FastSync;
48
49 architecture AR_Slow2FastSync of Slow2FastSync is
50
51 signal DataS : STD_LOGIC_VECTOR (N-1 downto 0);
52
53
54 begin
55
56
57
58 process(ClockF)
59 begin
60 if ClockF'event and ClockF = '1' and SyncSignal = '1' then
61 DataSinkS <= DataS;
62 end if;
63 end process;
64
65 process(ClockS)
66 begin
67 if ClockS'event and ClockS = '1' then
68 DataS <= Data;
69 end if;
70 end process;
71
72 end AR_Slow2FastSync;
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:03:54 08/21/2013
6 -- Design Name:
7 -- Module Name: TM_MODULE - AR_TM_MODULE
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 library lpp;
23 use lpp.lpp_ad_conv.all;
24 use lpp.lpp_amba.all;
25 use lpp.apb_devices_list.all;
26 use lpp.general_purpose.all;
27 use lpp.Rocket_PCM_Encoder.all;
28
29 entity TM_MODULE is
30 generic(
31 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
32 );
33 port(
34
35 reset : in std_logic;
36 clk : in std_logic;
37 MinF : in std_logic;
38 MajF : in std_logic;
39 sclk : in std_logic;
40 gate : in std_logic;
41 data : out std_logic;
42 WordClk : out std_logic;
43
44
45 LF1 : in std_logic_vector(15 downto 0);
46 LF2 : in std_logic_vector(15 downto 0);
47 LF3 : in std_logic_vector(15 downto 0);
48
49 AMR1X : in std_logic_vector(23 downto 0);
50 AMR1Y : in std_logic_vector(23 downto 0);
51 AMR1Z : in std_logic_vector(23 downto 0);
52
53 AMR2X : in std_logic_vector(23 downto 0);
54 AMR2Y : in std_logic_vector(23 downto 0);
55 AMR2Z : in std_logic_vector(23 downto 0);
56
57 AMR3X : in std_logic_vector(23 downto 0);
58 AMR3Y : in std_logic_vector(23 downto 0);
59 AMR3Z : in std_logic_vector(23 downto 0);
60
61 AMR4X : in std_logic_vector(23 downto 0);
62 AMR4Y : in std_logic_vector(23 downto 0);
63 AMR4Z : in std_logic_vector(23 downto 0);
64
65 Temp1 : in std_logic_vector(23 downto 0);
66 Temp2 : in std_logic_vector(23 downto 0);
67 Temp3 : in std_logic_vector(23 downto 0);
68 Temp4 : in std_logic_vector(23 downto 0)
69 );
70 end TM_MODULE;
71
72 architecture AR_TM_MODULE of TM_MODULE is
73
74 Constant FramePlacerCount : integer := 2;
75 signal MinFCnt : integer range 0 to MinFCount-1;
76 signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
77
78 signal WordCount : integer range 0 to WordCnt-1;
79
80 signal data_int : std_logic;
81
82 signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
83 signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
84 signal Sel : integer range 0 to 1;
85
86
87 signal MinF_Inv : std_logic;
88 signal Gate_Inv : std_logic;
89 signal sclk_Inv : std_logic;
90
91 begin
92
93
94 Gate_Inv <= not Gate;
95 sclk_Inv <= not Sclk;
96 MinF_Inv <= not MinF;
97 data <= data_int;
98
99 SD0 : Serial_Driver
100 generic map(WordSize)
101 port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
102
103 WC0 : Word_Cntr
104 generic map(WordSize,WordCnt)
105 port map(sclk_Inv,MinF,WordClk,WordCount);
106
107 MFC0 : MinF_Cntr
108 generic map(MinFCount)
109 port map(
110 clk => MinF_Inv,
111 reset => MajF,
112 Cnt_out => MinFCnt
113 );
114
115
116 MUX0 : Serial_Driver_Multiplexor
117 generic map(FramePlacerCount,WordSize)
118 port map(sclk_Inv,Sel,MuxIN,MuxOUT);
119
120
121 DCFP0 : entity work.DC_FRAME_PLACER
122 generic map(WordSize,WordCnt,MinFCount)
123 port map(
124 clk => Sclk,
125 Wcount => WordCount,
126 MinFCnt => MinFCnt,
127 Flag => FramePlacerFlags(0),
128 AMR1X => AMR1X,
129 AMR1Y => AMR1Y,
130 AMR1Z => AMR1Z,
131 AMR2X => AMR2X,
132 AMR2Y => AMR2Y,
133 AMR2Z => AMR2Z,
134 AMR3X => AMR3X,
135 AMR3Y => AMR3Y,
136 AMR3Z => AMR3Z,
137 AMR4X => AMR4X,
138 AMR4Y => AMR4Y,
139 AMR4Z => AMR4Z,
140 Temp1 => Temp1,
141 Temp2 => Temp2,
142 Temp3 => Temp3,
143 Temp4 => Temp4,
144 WordOut => MuxIN(7 downto 0));
145
146
147
148 LFP0 : entity work.LF_FRAME_PLACER
149 generic map(WordSize,WordCnt,MinFCount)
150 port map(
151 clk => Sclk,
152 Wcount => WordCount,
153 Flag => FramePlacerFlags(1),
154 LF1 => LF1,
155 LF2 => LF2,
156 LF3 => LF3,
157 WordOut => MuxIN(15 downto 8));
158
159
160
161 process(clk)
162 variable SelVar : integer range 0 to 1;
163 begin
164 if clk'event and clk ='1' then
165 Decoder: FOR i IN 0 to FramePlacerCount-1 loop
166 if FramePlacerFlags(i) = '1' then
167 SelVar := i;
168 end if;
169 END loop Decoder;
170 Sel <= SelVar;
171 end if;
172 end process;
173
174
175
176 end AR_TM_MODULE;
177
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 --IDLE = 0000
28 --MAC = 0001
29 --MULT = 0010 and set MULT in ADD reg
30 --ADD = 0011
31 --CLRMAC = 0100
32
33
34 ENTITY ALU_V0 IS
35 GENERIC(
36 Arith_en : INTEGER := 1;
37 Logic_en : INTEGER := 1;
38 Input_SZ_1 : INTEGER := 16;
39 Input_SZ_2 : INTEGER := 9
40
41 );
42 PORT(
43 clk : IN STD_LOGIC;
44 reset : IN STD_LOGIC;
45 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
47 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
48 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
49 );
50 END ENTITY;
51
52 ARCHITECTURE ar_ALU OF ALU_V0 IS
53
54 SIGNAL clr_MAC : STD_LOGIC := '1';
55
56 BEGIN
57 clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
58
59 arith : IF Arith_en = 1 GENERATE
60 MACinst : MAC_V0
61 GENERIC MAP(Input_SZ_1, Input_SZ_2)
62 PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
63 END GENERATE;
64
65 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
29
30 entity Adder_V0 is
31 generic(
32 Input_SZ_A : integer := 16;
33 Input_SZ_B : integer := 16
34
35 );
36 port(
37 clk : in std_logic;
38 reset : in std_logic;
39 clr : in std_logic;
40 add : in std_logic;
41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
43 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
44 );
45 end entity;
46
47
48
49
50 architecture ar_Adder of Adder_V0 is
51
52 signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
53 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
54
55 begin
56
57 RES <= REG;
58 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
59
60 process(clk,reset)
61 begin
62 if reset = '0' then
63 REG <= (others => '0');
64 elsif clk'event and clk ='1' then
65 if clr = '1' then
66 REG <= (others => '0');
67 elsif add = '1' then
68 REG <= RESADD;
69 end if;
70 end if;
71 end process;
72 end ar_Adder;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 library IEEE;
7 use IEEE.numeric_std.all;
8 use IEEE.std_logic_1164.all;
9 library lpp;
10 use lpp.general_purpose.all;
11 --TODO
12 --terminer le testbensh puis changer le resize dans les instanciations
13 --par un resize sur un vecteur en combi
14
15
16
17
18
19 entity MAC_V0 is
20 generic(
21 Input_SZ_A : integer := 8;
22 Input_SZ_B : integer := 8
23
24 );
25 port(
26 clk : in std_logic;
27 reset : in std_logic;
28 clr_MAC : in std_logic;
29 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
30 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
31 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
32 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
33 );
34 end MAC_V0;
35
36
37
38
39 architecture ar_MAC of MAC_V0 is
40
41
42
43
44
45 signal add,mult : std_logic;
46 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
47
48 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51
52
53 signal MACMUXsel : std_logic;
54 signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
55 signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56
57
58
59 signal MACMUX2sel : std_logic;
60
61 signal add_D : std_logic;
62 signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
63 signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
64 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
65 signal MACMUXsel_D : std_logic;
66 signal MACMUX2sel_D : std_logic;
67 signal MACMUX2sel_D_D : std_logic;
68 signal clr_MAC_D : std_logic;
69 signal clr_MAC_D_D : std_logic;
70
71
72
73
74
75 begin
76
77
78
79
80 --==============================================================
81 --=============M A C C O N T R O L E R=========================
82 --==============================================================
83 MAC_CONTROLER1 : MAC_CONTROLER
84 port map(
85 ctrl => MAC_MUL_ADD,
86 MULT => mult,
87 ADD => add,
88 MACMUX_sel => MACMUXsel,
89 MACMUX2_sel => MACMUX2sel
90
91 );
92 --==============================================================
93
94
95
96
97 --==============================================================
98 --=============M U L T I P L I E R==============================
99 --==============================================================
100 Multiplieri_nst : Multiplier
101 generic map(
102 Input_SZ_A => Input_SZ_A,
103 Input_SZ_B => Input_SZ_B
104 )
105 port map(
106 clk => clk,
107 reset => reset,
108 mult => mult,
109 OP1 => OP1,
110 OP2 => OP2,
111 RES => MULTout
112 );
113
114 --==============================================================
115
116
117
118
119 --==============================================================
120 --======================A D D E R ==============================
121 --==============================================================
122 adder_inst : Adder_V0
123 generic map(
124 Input_SZ_A => Input_SZ_A+Input_SZ_B,
125 Input_SZ_B => Input_SZ_A+Input_SZ_B
126 )
127 port map(
128 clk => clk,
129 reset => reset,
130 clr => clr_MAC_D,
131 add => add_D,
132 OP1 => ADDERinA,
133 OP2 => ADDERinB,
134 RES => ADDERout
135 );
136
137 --==============================================================
138
139
140 clr_MACREG1 : MAC_REG
141 generic map(size => 1)
142 port map(
143 reset => reset,
144 clk => clk,
145 D(0) => clr_MAC,
146 Q(0) => clr_MAC_D
147 );
148
149 clr_MACREG2 : MAC_REG
150 generic map(size => 1)
151 port map(
152 reset => reset,
153 clk => clk,
154 D(0) => clr_MAC_D,
155 Q(0) => clr_MAC_D_D
156 );
157
158 addREG : MAC_REG
159 generic map(size => 1)
160 port map(
161 reset => reset,
162 clk => clk,
163 D(0) => add,
164 Q(0) => add_D
165 );
166
167 OP1REG : MAC_REG
168 generic map(size => Input_SZ_A)
169 port map(
170 reset => reset,
171 clk => clk,
172 D => OP1,
173 Q => OP1_D
174 );
175
176
177 OP2REG : MAC_REG
178 generic map(size => Input_SZ_B)
179 port map(
180 reset => reset,
181 clk => clk,
182 D => OP2,
183 Q => OP2_D
184 );
185
186
187 MULToutREG : MAC_REG
188 generic map(size => Input_SZ_A+Input_SZ_B)
189 port map(
190 reset => reset,
191 clk => clk,
192 D => MULTout,
193 Q => MULTout_D
194 );
195
196
197 MACMUXselREG : MAC_REG
198 generic map(size => 1)
199 port map(
200 reset => reset,
201 clk => clk,
202 D(0) => MACMUXsel,
203 Q(0) => MACMUXsel_D
204 );
205
206 MACMUX2selREG : MAC_REG
207 generic map(size => 1)
208 port map(
209 reset => reset,
210 clk => clk,
211 D(0) => MACMUX2sel,
212 Q(0) => MACMUX2sel_D
213 );
214
215 MACMUX2selREG2 : MAC_REG
216 generic map(size => 1)
217 port map(
218 reset => reset,
219 clk => clk,
220 D(0) => MACMUX2sel_D,
221 Q(0) => MACMUX2sel_D_D
222 );
223
224 --==============================================================
225 --======================M A C M U X ===========================
226 --==============================================================
227 MACMUX_inst : MAC_MUX
228 generic map(
229 Input_SZ_A => Input_SZ_A+Input_SZ_B,
230 Input_SZ_B => Input_SZ_A+Input_SZ_B
231
232 )
233 port map(
234 sel => MACMUXsel_D,
235 INA1 => ADDERout,
236 INA2 => OP2_D_Resz,
237 INB1 => MULTout,
238 INB2 => OP1_D_Resz,
239 OUTA => ADDERinA,
240 OUTB => ADDERinB
241 );
242 OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
243 OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
244 --==============================================================
245
246
247 --==============================================================
248 --======================M A C M U X2 ==========================
249 --==============================================================
250 MAC_MUX2_inst : MAC_MUX2
251 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
252 port map(
253 sel => MACMUX2sel_D_D,
254 RES2 => MULTout_D,
255 RES1 => ADDERout,
256 RES => RES
257 );
258
259
260 --==============================================================
261
262 end ar_MAC;
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@@ -1,80 +1,81
1 1 SCRIPTSDIR=scripts/
2 2 LIBDIR=lib/
3 3 BOARDSDIR=boards/
4 4 DESIGNSDIR=designs/
5 5
6 6
7 7 .PHONY:doc
8 8
9 9
10 10 all: help
11 11
12 12 help:
13 13 @echo
14 14 @echo " batch targets:"
15 15 @echo
16 16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
17 17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
18 18 @echo " make dist : create a tar file for using into an other computer"
19 19 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
20 20 @echo " into an other computer"
21 21 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
22 22 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
23 23 @echo " make doc : make documentation for VHDL IPs"
24 24 @echo " make pdf : make pdf documentation for VHDL IPs"
25 25 @echo " make C-libs : make C drivers for APB devices"
26 26 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
27 27 @echo
28 28
29 29
30 30
31 31 allGPL:
32 32 @echo "Scanning VHDL files ..."
33 33 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
34 34 @echo "Scanning C files ..."
35 35 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
36 36 @echo "Scanning H files ..."
37 37 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
38 38
39 39 init: C-libs
40 40 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
41 41 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
42 42
43 43 C-libs:APB_devs
44 44 make -C LPP_drivers
45 45
46 46
47 47 APB_devs:
48 48 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
49 49
50 50
51 51 Patch-GRLIB: init doc
52 52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
53 53
54 54 link:
55 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
55 56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 57 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57 58
58 59 dist: init
59 60 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
60 61
61 62
62 63 Patched-dist: Patch-GRLIB
63 64 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
64 65
65 66
66 67 doc:
67 68 mkdir -p doc/html
68 69 cp doc/ressources/*.jpg doc/html/
69 70 cp doc/ressources/doxygen.css doc/html/
70 71 make -C lib/lpp doc
71 72 make -C LPP_drivers doc
72 73
73 74
74 75 pdf: doc
75 76 sh $(SCRIPTSDIR)/doc.sh
76 77
77 78
78 79
79 80
80 81
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@@ -1,11 +1,31
1 NET "CLK" LOC = "B10";
1 NET "CLK" LOC = "B10" | IOSTANDARD = LVCMOS33;
2
3 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
2 4 NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL;
5
6 NET "SCLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 7 NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL;
8
4 9 NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL;
10
11 NET "MINF" CLOCK_DEDICATED_ROUTE = FALSE;
5 12 NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL;
13
6 14 NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL;
7 NET "DATA" LOC = "V21";
8 NET "DC_ADC_SCLK" LOC = "AB17";
15 NET "DATA" LOC = "V21" | IOSTANDARD = LVCMOS33;
16 NET "DC_ADC_SCLK" LOC = "AB17" | IOSTANDARD = LVCMOS33;
9 17 NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL;
10 18 NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL;
11 NET "DC_ADC_FSynch" LOC = "AB18";
19 NET "DC_ADC_FSynch" LOC = "AB18" | IOSTANDARD = LVCMOS33;
20 NET "LED" LOC = "A3" | IOSTANDARD = LVCMOS33;
21 NET "SET_RESET0" LOC = "AB21" | IOSTANDARD = LVCMOS33;
22 NET "SET_RESET1" LOC = "AB20" | IOSTANDARD = LVCMOS33;
23
24
25 NET "LF_SCK" LOC = "W20"| IOSTANDARD = LVCMOS33;
26 NET "LF_CNV" LOC = "Y18"| IOSTANDARD = LVCMOS33;
27 NET "LF_SDO1" LOC = "W17" | IOSTANDARD = LVTTL;
28 NET "LF_SDO2" LOC = "AA21" | IOSTANDARD = LVTTL;
29 NET "LF_SDO3" LOC = "AA16" | IOSTANDARD = LVTTL;
30
31
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@@ -1,46 +1,48
1 1 -- LF_SMPL_CLK.vhd
2 2 library IEEE;
3 3 use IEEE.numeric_std.all;
4 4 use IEEE.std_logic_1164.all;
5 5
6 6
7 entity LF_SMPL_CLK is
7 entity LF_SMPL_CLK is
8 generic(N : integer range 0 to 4096 :=24);
8 9 port(
9 Wclck : in std_logic;
10 MinF : in std_logic;
10 reset : in std_logic;
11 wclk : in std_logic;
11 12 SMPL_CLK : out std_logic
12 13 );
13 14 end entity;
14 15
15 16
16 17
17 18
18 19
19 20
20 21 architecture ar_LF_SMPL_CLK of LF_SMPL_CLK is
21 22
22 signal cpt : integer range 0 to 23 := 0;
23 signal cpt : integer range 0 to N-1 := 0;
23 24 begin
24 25
25 26
26 27
27 process(Wclck,MinF)
28 process(reset,wclk)
28 29 begin
29 if MinF = '0' then
30 SMPL_CLK <= '1';
31 elsif Wclck'event and Wclck = '1' then
32 if cpt = 23 then
30 if reset = '0' then
31 SMPL_CLK <= '1';
32 cpt <= 0;
33 elsif wclk'event and wclk = '1' then
34 if cpt = (N-1) then
33 35 cpt <= 0;
34 36 else
35 37 cpt <= cpt+1;
36 38 end if;
37 39 if cpt = 0 then
38 40 SMPL_CLK <= '1';
39 elsif cpt = 10 then
41 elsif cpt = (N/2) then
40 42 SMPL_CLK <= '0';
41 43 end if;
42 44 end if;
43 45
44 46 end process;
45 47
46 48 end ar_LF_SMPL_CLK; No newline at end of file
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@@ -1,50 +1,61
1 1 include .config
2 2
3 3 #GRLIB=$(GRLIB)
4 4 TOP=ici4
5 5 BOARD=ICI4-main-BD
6 6 #BOARD=SP601
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
7 include ../../boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
10 UCF=$(GRLIB)/boards/$(BOARD)/ICI4-Main-BD.ucf
11 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
12 12 EFFORT=high
13 13 ISEMAPOPT="-timing"
14 14 XSTOPT=""
15 15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
16 16 VHDLOPTSYNFILES= \
17 17 ICI4HDL/Convertisseur_config.vhd \
18 18 ICI4HDL/Convertisseur_Data.vhd \
19 19 ICI4HDL/DC_FRAME_PLACER.vhd \
20 20 ICI4HDL/DC_SMPL_CLK.vhd \
21 21 ICI4HDL/LF_FRAME_PLACER.vhd \
22 ICI4HDL/LF_SMPL_CLK.vhd
22 ICI4HDL/LF_SMPL_CLK.vhd \
23 ICI4HDL/Fast2SlowSync.vhd \
24 ICI4HDL/Slow2FastSync.vhd \
25 ICI4HDL/CrossDomainSyncGen.vhd \
26 ICI4HDL/TM_MODULE.vhd \
27 ICI4HDL/DC_ACQ_TOP.vhd \
28 ICI4HDL/LF_ACQ_TOP.vhd \
29 ICI4HDL/FAKE_ADC.vhd \
30 ICI4HDL/OneShot.vhd \
31 ICI4HDL/IIR_FILTER_TOP.vhd
32
23 33
24 34 VHDLSYNFILES= \
25 35 config.vhd ici4.vhd
26 36 VHDLSIMFILES=testbench.vhd
27 37 SIMTOP=testbench
28 38 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
29 39 SDCFILE=default.sdc
30 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
40 BITGEN=../../boards/$(BOARD)/default.ut
31 41 CLEAN=soft-clean
32 42 VCOMOPT=-explicit
33 43 TECHLIBS = secureip unisim
34 44
35 45 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
36 46 tmtc openchip cypress ihp gleichmann gsi fmf spansion
37 47 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
38 48 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
39 49 ac97 hcan usb
40 50 DIRADD =
41 51 FILEADD =
42 52 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
43 53
44 54 include $(GRLIB)/bin/Makefile
45 55 include $(GRLIB)/software/leon3/Makefile
46 56
47 57
48 58 ################## project specific targets ##########################
49 59
50
60 flash:
61 xc3sprog -c ftdi -p 1 ici4.bit
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@@ -1,52 +1,145
1 1
2 2
3 3
4 4 -----------------------------------------------------------------------------
5 5 -- LEON3 Demonstration design test bench configuration
6 6 -- Copyright (C) 2009 Aeroflex Gaisler
7 7 ------------------------------------------------------------------------------
8 8
9 9
10 10 library techmap;
11 11 use techmap.gencomp.all;
12 library ieee;
13 use ieee.std_logic_1164.all;
12 LIBRARY IEEE;
13 USE IEEE.numeric_std.ALL;
14 USE IEEE.std_logic_1164.ALL;
15
14 16
15 17 package config is
16 18 -- Technology and synthesis options
17 19 constant CFG_FABTECH : integer := spartan6;
18 20 constant CFG_MEMTECH : integer := spartan6;
19 21 constant CFG_PADTECH : integer := spartan6;
20 22 -- Clock generator
21 23 constant CFG_CLKTECH : integer := spartan6;
22 constant SEND_CONSTANT_DATA : integer := 1;
23 constant SEND_MINF_VALUE : integer := 1;
24 constant SEND_CONSTANT_DATA : integer := 0;
25 constant SEND_MINF_VALUE : integer := 0;
24 26
25 27
26 28
27 29 constant LF1cst : std_logic_vector(15 downto 0) := X"1111";
28 30 constant LF2cst : std_logic_vector(15 downto 0) := X"2222";
29 31 constant LF3cst : std_logic_vector(15 downto 0) := X"3333";
30 32
31 33
32 constant AMR1Xcst : std_logic_vector(23 downto 0):= X"444444";
33 constant AMR1Ycst : std_logic_vector(23 downto 0):= X"555555";
34 constant AMR1Zcst : std_logic_vector(23 downto 0):= X"666666";
34 constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001";
35 constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111";
36 constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF";
35 37
36 constant AMR2Xcst : std_logic_vector(23 downto 0):= X"777777";
37 constant AMR2Ycst : std_logic_vector(23 downto 0):= X"888888";
38 constant AMR2Zcst : std_logic_vector(23 downto 0):= X"999999";
38 constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000";
39 constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002";
40 constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001";
39 41
40 42 constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA";
41 43 constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB";
42 44 constant AMR3Zcst : std_logic_vector(23 downto 0):= X"CCCCCC";
43 45
44 46 constant AMR4Xcst : std_logic_vector(23 downto 0):= X"DDDDDD";
45 47 constant AMR4Ycst : std_logic_vector(23 downto 0):= X"EEEEEE";
46 48 constant AMR4Zcst : std_logic_vector(23 downto 0):= X"FFFFFF";
47 49
48 50 constant Temp1cst : std_logic_vector(23 downto 0):= X"121212";
49 51 constant Temp2cst : std_logic_vector(23 downto 0):= X"343434";
50 52 constant Temp3cst : std_logic_vector(23 downto 0):= X"565656";
51 53 constant Temp4cst : std_logic_vector(23 downto 0):= X"787878";
54
55
56
57 --===========================================================|
58 --========F I L T E R C O N F I G V A L U E S=============|
59 --===========================================================|
60 --____________________________
61 --Bus Width and chanels number|
62 --____________________________|
63 constant ChanelsCount : integer := 3;
64 constant Sample_SZ : integer := 16;
65 constant Coef_SZ : integer := 9;
66 constant CoefCntPerCel: integer := 6;
67 constant CoefPerCel: integer := 5;
68 constant Cels_count : integer := 5;
69 constant virgPos : integer := 7;
70 constant Mem_use : integer := 1;
71
72
73
74 --============================================================
75 -- create each initial values for each coefs ============
76 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
77 --============================================================
78 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
79 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
80 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
81
82 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
83 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
84 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
85
86 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
87 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
88 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
89
90 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
91 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
92 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
93
94 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
95 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
96 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
97
98 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
99 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
100 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
101
102 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
103 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
104 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
105
106
107 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
108 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
109 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
110
111 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
112 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
113 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
114
115 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
116 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
117 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
118
119 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
120 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
121 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
122
123 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
124 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
125 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
126
127 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
128 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
129 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
130 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
131 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
132 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
133
134 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
135
136 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
137 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
138 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
139 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
140 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
141 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
142
143
144
52 145 end;
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@@ -1,316 +1,248
1 1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 3 use IEEE.numeric_std.all;
4 4 library grlib, techmap;
5 5 use grlib.amba.all;
6 6 use grlib.amba.all;
7 7 use grlib.stdlib.all;
8 8 use techmap.gencomp.all;
9 9 use techmap.allclkgen.all;
10 10 library gaisler;
11 11 use gaisler.memctrl.all;
12 12 use gaisler.leon3.all;
13 13 use gaisler.uart.all;
14 14 use gaisler.misc.all;
15 15 --use gaisler.sim.all;
16 16 library lpp;
17 17 use lpp.lpp_ad_conv.all;
18 18 use lpp.lpp_amba.all;
19 19 use lpp.apb_devices_list.all;
20 20 use lpp.general_purpose.all;
21 21 use lpp.Rocket_PCM_Encoder.all;
22 22
23 23
24 24 use work.Convertisseur_config.all;
25 25
26 26
27 27 use work.config.all;
28 --==================================================================
29 --
30 --
31 -- FPGA FREQ = 48MHz
32 -- ADC Oscillator frequency = 12MHz
33 --
34 --
35 --==================================================================
28 36
29 37 entity ici4 is
30 38 generic (
31 39 fabtech : integer := CFG_FABTECH;
32 40 memtech : integer := CFG_MEMTECH;
33 41 padtech : integer := CFG_PADTECH;
34 42 clktech : integer := CFG_CLKTECH;
35 43 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
36 44 );
37 45 port (
38 reset : in std_ulogic;
39 clk : in std_ulogic;
40 sclk : in std_logic;
41 Gate : in std_logic;
42 MinF : in std_logic;
43 MajF : in std_logic;
44 Data : out std_logic;
45 DC_ADC_Sclk : out std_logic;
46 DC_ADC_IN : in std_logic_vector(1 downto 0);
47 DC_ADC_ClkDiv : out std_logic;
48 DC_ADC_FSynch : out std_logic;
49 SET_RESET0 : out std_logic;
50 SET_RESET1 : out std_logic;
51 LED : out std_logic
46 reset : in std_ulogic;
47 clk : in std_ulogic;
48 sclk : in std_logic;
49 Gate : in std_logic;
50 MinF : in std_logic;
51 MajF : in std_logic;
52 Data : out std_logic;
53 LF_SCK : out std_logic;
54 LF_CNV : out std_logic;
55 LF_SDO1 : in std_logic;
56 LF_SDO2 : in std_logic;
57 LF_SDO3 : in std_logic;
58 DC_ADC_Sclk : out std_logic;
59 DC_ADC_IN : in std_logic_vector(1 downto 0);
60 DC_ADC_ClkDiv : out std_logic;
61 DC_ADC_FSynch : out std_logic;
62 SET_RESET0 : out std_logic;
63 SET_RESET1 : out std_logic;
64 LED : out std_logic
52 65 );
53 66 end;
54 67
55 68 architecture rtl of ici4 is
56 69
57 70 signal clk_buf,reset_buf : std_logic;
58 71
59 72 Constant FramePlacerCount : integer := 2;
60 73
61 signal MinF_Inv : std_logic;
62 signal Gate_Inv : std_logic;
63 signal sclk_Inv : std_logic;
74
64 75 signal WordCount : integer range 0 to WordCnt-1;
65 76 signal WordClk : std_logic;
66 77
67 signal data_int : std_logic;
68
69 signal MuxOUT : std_logic_vector(WordSize-1 downto 0);
70 signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0);
71 signal Sel : integer range 0 to 1;
72 78
73 79 signal AMR1X : std_logic_vector(23 downto 0);
74 80 signal AMR1Y : std_logic_vector(23 downto 0);
75 81 signal AMR1Z : std_logic_vector(23 downto 0);
76 82
77 83 signal AMR2X : std_logic_vector(23 downto 0);
78 84 signal AMR2Y : std_logic_vector(23 downto 0);
79 85 signal AMR2Z : std_logic_vector(23 downto 0);
80 86
81 87 signal AMR3X : std_logic_vector(23 downto 0);
82 88 signal AMR3Y : std_logic_vector(23 downto 0);
83 89 signal AMR3Z : std_logic_vector(23 downto 0);
84 90
85 91 signal AMR4X : std_logic_vector(23 downto 0);
86 92 signal AMR4Y : std_logic_vector(23 downto 0);
87 93 signal AMR4Z : std_logic_vector(23 downto 0);
88 94
89 signal Temp1 : std_logic_vector(23 downto 0);
90 signal Temp2 : std_logic_vector(23 downto 0);
91 signal Temp3 : std_logic_vector(23 downto 0);
92 signal Temp4 : std_logic_vector(23 downto 0);
93 95
96 signal TEMP1 : std_logic_vector(23 downto 0);
97 signal TEMP2 : std_logic_vector(23 downto 0);
98 signal TEMP3 : std_logic_vector(23 downto 0);
99 signal TEMP4 : std_logic_vector(23 downto 0);
94 100
95 101 signal LF1 : std_logic_vector(15 downto 0);
96 102 signal LF2 : std_logic_vector(15 downto 0);
97 103 signal LF3 : std_logic_vector(15 downto 0);
98 104
99
100 signal LF1_int : std_logic_vector(23 downto 0);
101 signal LF2_int : std_logic_vector(23 downto 0);
102 signal LF3_int : std_logic_vector(23 downto 0);
105 signal data_int : std_logic;
103 106
104 signal DC_ADC_SmplClk : std_logic;
105 signal LF_ADC_SmplClk : std_logic;
106 signal SET_RESET0_sig : std_logic;
107 signal SET_RESET1_sig : std_logic;
108
109 signal MinFCnt : integer range 0 to MinFCount-1;
110
111 signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0);
107 signal CrossDomainSync : std_logic;
112 108
113 109 begin
114 110
115 111
116 clk_buf <= clk;
117 reset_buf <= reset;
118 --
119
120 Gate_Inv <= not Gate;
121 sclk_Inv <= not Sclk;
122 MinF_Inv <= not MinF;
123
124 112 LED <= not data_int;
125 data <= data_int;
126
127
128
129 SD0 : Serial_Driver
130 generic map(WordSize)
131 port map(sclk_Inv,MuxOUT,Gate_inv,data_int);
132
133 WC0 : Word_Cntr
134 generic map(WordSize,WordCnt)
135 port map(sclk_Inv,MinF,WordClk,WordCount);
136
137 MFC0 : MinF_Cntr
138 generic map(MinFCount)
139 port map(
140 clk => MinF_Inv,
141 reset => MajF,
142 Cnt_out => MinFCnt
143 );
144
145
146 MUX0 : Serial_Driver_Multiplexor
147 generic map(FramePlacerCount,WordSize)
148 port map(sclk_Inv,Sel,MuxIN,MuxOUT);
149
150
151 DCFP0 : entity work.DC_FRAME_PLACER
152 generic map(WordSize,WordCnt,MinFCount)
153 port map(
154 clk => Sclk,
155 Wcount => WordCount,
156 MinFCnt => MinFCnt,
157 Flag => FramePlacerFlags(0),
158 AMR1X => AMR1X,
159 AMR1Y => AMR1Y,
160 AMR1Z => AMR1Z,
161 AMR2X => AMR2X,
162 AMR2Y => AMR2Y,
163 AMR2Z => AMR2Z,
164 AMR3X => AMR3X,
165 AMR3Y => AMR3Y,
166 AMR3Z => AMR3Z,
167 AMR4X => AMR4X,
168 AMR4Y => AMR4Y,
169 AMR4Z => AMR4Z,
170 Temp1 => Temp1,
171 Temp2 => Temp2,
172 Temp3 => Temp3,
173 Temp4 => Temp4,
174 WordOut => MuxIN(7 downto 0));
175
176
177
178 LFP0 : entity work.LF_FRAME_PLACER
179 generic map(WordSize,WordCnt,MinFCount)
180 port map(
181 clk => Sclk,
182 Wcount => WordCount,
183 Flag => FramePlacerFlags(1),
184 LF1 => LF1,
185 LF2 => LF2,
186 LF3 => LF3,
187 WordOut => MuxIN(15 downto 8));
188
189
190
191 DC_SMPL_CLK0 : entity work.DC_SMPL_CLK
192 port map(MinF_Inv,DC_ADC_SmplClk);
193
194 process(reset,DC_ADC_SmplClk)
195 begin
196 if reset = '0' then
197 SET_RESET0_sig <= '0';
198 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '1' then
199 SET_RESET0_sig <= not SET_RESET0_sig;
200 end if;
201 end process;
202
203 SET_RESET1_sig <= SET_RESET0_sig;
204 SET_RESET0 <= SET_RESET0_sig;
205 SET_RESET1 <= SET_RESET1_sig;
206 --
113 data <= data_int;
207 114
208 115
209 116
210 send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE
211 DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin
212 port map(
213 Clk => clk_buf,
214 reset => reset_buf,
215 SpiClk => DC_ADC_Sclk,
216 DIN => DC_ADC_IN,
217 SmplClk => DC_ADC_SmplClk,
218 OUT00 => AMR1X,
219 OUT01 => AMR1Y,
220 OUT02 => AMR1Z,
221 OUT03 => AMR2X,
222 OUT04 => AMR2Y,
223 OUT05 => AMR2Z,
224 OUT06 => Temp1,
225 OUT07 => Temp2,
226 OUT10 => AMR3X,
227 OUT11 => AMR3Y,
228 OUT12 => AMR3Z,
229 OUT13 => AMR4X,
230 OUT14 => AMR4Y,
231 OUT15 => AMR4Z,
232 OUT16 => Temp3,
233 OUT17 => Temp4,
234 FSynch => DC_ADC_FSynch
235 );
236 LF1 <= LF1cst;
237 LF2 <= LF2cst;
238 LF3 <= LF3cst;
239 END GENERATE;
117 CDS0 : entity work.CrossDomainSyncGen
118 Port map(
119 reset => reset,
120 ClockS => sclk,
121 ClockF => clk,
122 SyncSignal => CrossDomainSync
123 );
240 124
241 send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE
242 AMR1X <= AMR1Xcst;
243 AMR1Y <= AMR1Ycst;
244 AMR1Z <= AMR1Zcst;
245 AMR2X <= AMR2Xcst;
246 AMR2Y <= AMR2Ycst;
247 AMR2Z <= AMR2Zcst;
248 Temp1 <= Temp1cst;
249 Temp2 <= Temp2cst;
250 AMR3X <= AMR3Xcst;
251 AMR3Y <= AMR3Ycst;
252 AMR3Z <= AMR3Zcst;
253 AMR4X <= AMR4Xcst;
254 AMR4Y <= AMR4Ycst;
255 AMR4Z <= AMR4Zcst;
256 Temp3 <= Temp3cst;
257 Temp4 <= Temp4cst;
258
259 LF1 <= LF1cst;
260 LF2 <= LF2cst;
261 LF3 <= LF3cst;
262 END GENERATE;
263
264
125 TM : entity work.TM_MODULE
126 generic map(
127 WordSize => WordSize,
128 WordCnt => WordCnt,
129 MinFCount => MinFCount
130 )
131 port map(
132
133 reset =>reset,
134 clk =>clk,
135 MinF =>MinF,
136 MajF =>MajF,
137 sclk =>sclk,
138 gate =>gate,
139 data =>data_int,
140 WordClk =>WordClk,
265 141
266 142
267 send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE
268 AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
269 AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
270 AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
271 AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
272 AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
273 AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
274 Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
275 Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
276 AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
277 AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
278 AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
279 AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
280 AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
281 AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
282 Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
283 Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9));
284
285 LF1 <= LF1cst;
286 LF2 <= LF2cst;
287 LF3 <= LF3cst;
288 END GENERATE;
143 LF1 => LF1,
144 LF2 => LF2,
145 LF3 => LF3,
146
147 AMR1X => AMR1X,
148 AMR1Y => AMR1Y,
149 AMR1Z => AMR1Z,
150
151 AMR2X => AMR2X,
152 AMR2Y => AMR2Y,
153 AMR2Z => AMR2Z,
154
155 AMR3X => AMR3X,
156 AMR3Y => AMR3Y,
157 AMR3Z => AMR3Z,
158
159 AMR4X => AMR4X,
160 AMR4Y => AMR4Y,
161 AMR4Z => AMR4Z,
162
163 Temp1 => Temp1,
164 Temp2 => Temp2,
165 Temp3 => Temp3,
166 Temp4 => Temp4
167 );
289 168
290 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
169 DC_ADC0:entity work.DC_ACQ_TOP
170 generic map (
171 WordSize => WordSize,
172 WordCnt => WordCnt,
173 MinFCount => MinFCount,
174 EnableSR => 0,
175 CstDATA => SEND_CONSTANT_DATA,
176 FakeADC => 0
177 )
291 178 port map(
292 Wclck => WordClk,
293 MinF => MinF,
294 SMPL_CLK => LF_ADC_SmplClk
179
180 reset => reset,
181 clk => clk,
182 SyncSig => CrossDomainSync,
183 minorF => minF,
184 majorF => majF,
185 sclk => sclk,
186 WordClk => WordClk,
187
188 DC_ADC_Sclk => DC_ADC_Sclk,
189 DC_ADC_IN => DC_ADC_IN,
190 DC_ADC_ClkDiv => DC_ADC_ClkDiv,
191 DC_ADC_FSynch => DC_ADC_FSynch,
192 SET_RESET0 => SET_RESET0,
193 SET_RESET1 => SET_RESET1,
194
195 AMR1X => AMR1X,
196 AMR1Y => AMR1Y,
197 AMR1Z => AMR1Z,
198
199 AMR2X => AMR2X,
200 AMR2Y => AMR2Y,
201 AMR2Z => AMR2Z,
202
203 AMR3X => AMR3X,
204 AMR3Y => AMR3Y,
205 AMR3Z => AMR3Z,
206
207 AMR4X => AMR4X,
208 AMR4Y => AMR4Y,
209 AMR4Z => AMR4Z,
210
211 Temp1 => Temp1,
212 Temp2 => Temp2,
213 Temp3 => Temp3,
214 Temp4 => Temp4
295 215 );
296 216
297 217
218 LF: entity work.LF_ACQ_TOP
219 generic map(
220 WordSize => WordSize,
221 WordCnt => WordCnt,
222 MinFCount => MinFCount,
223 CstDATA => SEND_CONSTANT_DATA,
224 IIRFilter => 0
225 )
226 port map(
298 227
299 process(clk)
300 variable SelVar : integer range 0 to 1;
301 begin
302 if clk'event and clk ='1' then
303 Decoder: FOR i IN 0 to FramePlacerCount-1 loop
304 if FramePlacerFlags(i) = '1' then
305 SelVar := i;
306 end if;
307 END loop Decoder;
308 Sel <= SelVar;
309 end if;
310 end process;
311
228 reset => reset,
229 clk => clk,
230 SyncSig => CrossDomainSync,
231 minorF => minF,
232 majorF => majF,
233 sclk => sclk,
234 WordClk => WordClk,
235 LF_SCK => LF_SCK,
236 LF_CNV => LF_CNV,
237 LF_SDO1 => LF_SDO1,
238 LF_SDO2 => LF_SDO2,
239 LF_SDO3 => LF_SDO3,
240 LF1 => LF1,
241 LF2 => LF2,
242 LF3 => LF3
243 );
312 244
313 245 end rtl;
314 246
315 247
316 248
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@@ -1,338 +1,338
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 library IEEE;
24 24 use IEEE.numeric_std.all;
25 25 use IEEE.std_logic_1164.all;
26 26 library lpp;
27 27 use lpp.iir_filter.all;
28 28 use lpp.general_purpose.all;
29 29
30 30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
31 31
32 32 entity IIR_CEL_CTRLR is
33 33 generic(
34 34 tech : integer := 0;
35 35 Sample_SZ : integer := 16;
36 36 ChanelsCount : integer := 1;
37 37 Coef_SZ : integer := 9;
38 38 CoefCntPerCel: integer := 6;
39 39 Cels_count : integer := 5;
40 40 Mem_use : integer := use_RAM
41 41 );
42 42 port(
43 43 reset : in std_logic;
44 44 clk : in std_logic;
45 45 sample_clk : in std_logic;
46 46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
48 48 virg_pos : in integer;
49 49 GOtest : out std_logic;
50 50 coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0)
51 51 );
52 52 end IIR_CEL_CTRLR;
53 53
54 54
55 55
56 56
57 57 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
58 58
59 59 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
60 60
61 61 signal smpl_clk_old : std_logic := '0';
62 62 signal WD_sel : std_logic := '0';
63 63 signal Read : std_logic := '0';
64 64 signal SVG_ADDR : std_logic := '0';
65 65 signal count : std_logic := '0';
66 66 signal Write : std_logic := '0';
67 67 signal WADDR_sel : std_logic := '0';
68 68 signal GO_0 : std_logic := '0';
69 69
70 70 signal RAM_sample_in : sampleVect;
71 71 signal RAM_sample_in_bk: sampleVect;
72 72 signal RAM_sample_out : sampleVect;
73 73 signal ALU_ctrl : std_logic_vector(3 downto 0);
74 74 signal ALU_sample_in : sampleVect;
75 75 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
76 76 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
77 77 signal curentCel : integer range 0 to Cels_count-1 := 0;
78 78 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
79 79
80 80
81 81 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
82 82
83 83 signal sample_in_BUFF : sampleBuffT;
84 84 signal sample_out_BUFF : sampleBuffT;
85 85
86 86 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
87 87 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
88 88
89 89 type CoefsRegT is record
90 90 numCoefs : CoefTblT;
91 91 denCoefs : CoefTblT;
92 92 end record;
93 93
94 94 signal CoefsReg : CoefsRegT;
95 95
96 96 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
97 97
98 98 signal IIR_CEL_STATE : fsmIIR_CEL_T;
99 99
100 100 begin
101 101 GOtest <= GO_0;
102 102
103 103 --coefsConnectL0: for z in 0 to Cels_count-1 generate
104 104 -- coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
105 105 -- coefsConnectL2: for x in 0 to Coef_SZ-1 generate
106 106 -- CoefsReg.numCoefs(z)(y)(x) <= coefs(x + (((2*y))*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
107 107 -- CoefsReg.denCoefs(z)(y)(x) <= coefs(x + (((2*y)+1)*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
108 108 -- end generate;
109 109 -- end generate;
110 110 --end generate;
111 111
112 112 coefsConnectL0: for z in 0 to Cels_count-1 generate
113 113 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
114 114 CoefsReg.numCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
115 115 CoefsReg.denCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
116 116 end generate;
117 117 end generate;
118 118
119 119
120 120
121 121
122 122 RAM_CTRLR2inst : RAM_CTRLR2
123 123 generic map(tech,Sample_SZ,Mem_use)
124 124 port map(
125 125 reset => reset,
126 126 clk => clk,
127 127 WD_sel => WD_sel,
128 128 Read => Read,
129 129 WADDR_sel => WADDR_sel,
130 130 count => count,
131 131 SVG_ADDR => SVG_ADDR,
132 132 Write => Write,
133 133 GO_0 => GO_0,
134 134 sample_in => RAM_sample_in,
135 135 sample_out => RAM_sample_out
136 136 );
137 137
138 138
139 139
140 ALU_inst :ALU
140 ALU_inst : ALU_V0
141 141 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
142 142 port map(
143 143 clk => clk,
144 144 reset => reset,
145 145 ctrl => ALU_ctrl,
146 146 OP1 => ALU_sample_in,
147 147 OP2 => ALU_coef_in,
148 148 RES => ALU_out
149 149 );
150 150
151 151
152 152
153 153
154 154
155 155
156 156 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
157 157 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
158 158 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
159 159 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
160 160 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
161 161 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
162 162 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
163 163
164 164 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
165 165
166 166
167 167
168 168
169 169
170 170
171 171
172 172 process(clk,reset)
173 173 variable result : std_logic_vector(Sample_SZ-1 downto 0);
174 174
175 175 begin
176 176
177 177 if reset = '0' then
178 178
179 179 smpl_clk_old <= '0';
180 180 RAM_sample_in <= (others=> '0');
181 ALU_ctrl <= IDLE;
181 ALU_ctrl <= IDLE_V0;
182 182 ALU_sample_in <= (others=> '0');
183 183 ALU_Coef_in <= (others=> '0');
184 184 RAM_sample_in_bk<= (others=> '0');
185 185 curentCel <= 0;
186 186 curentChan <= 0;
187 187 IIR_CEL_STATE <= waiting;
188 188 resetL0 : for i in 0 to ChanelsCount-1 loop
189 189 sample_in_BUFF(i) <= (others => '0');
190 190 sample_out_BUFF(i) <= (others => '0');
191 191 resetL1: for j in 0 to Sample_SZ-1 loop
192 192 sample_out(i,j) <= '0';
193 193 end loop;
194 194 end loop;
195 195
196 196 elsif clk'event and clk = '1' then
197 197
198 198 smpl_clk_old <= sample_clk;
199 199
200 200 case IIR_CEL_STATE is
201 201
202 202 when waiting =>
203 203 if sample_clk = '1' and smpl_clk_old = '0' then
204 204 IIR_CEL_STATE <= pipe1;
205 205 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
206 206 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
207 207
208 208 else
209 ALU_ctrl <= IDLE;
209 ALU_ctrl <= IDLE_V0;
210 210 smplConnectL0: for i in 0 to ChanelsCount-1 loop
211 211 smplConnectL1: for j in 0 to Sample_SZ-1 loop
212 212 sample_in_BUFF(i)(j) <= sample_in(i,j);
213 213 sample_out(i,j) <= sample_out_BUFF(i)(j);
214 214 end loop;
215 215 end loop;
216 216 end if;
217 217 curentCel <= 0;
218 218 curentChan <= 0;
219 219
220 220 when pipe1 =>
221 221 IIR_CEL_STATE <= computeb1;
222 ALU_ctrl <= MAC_op;
222 ALU_ctrl <= MAC_op_V0;
223 223 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
224 224
225 225 when computeb1 =>
226 226
227 ALU_ctrl <= MAC_op;
227 ALU_ctrl <= MAC_op_V0;
228 228 ALU_sample_in <= RAM_sample_out;
229 229 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
230 230 IIR_CEL_STATE <= computeb2;
231 231 RAM_sample_in <= RAM_sample_in_bk;
232 232 when computeb2 =>
233 233 ALU_sample_in <= RAM_sample_out;
234 234 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
235 235 IIR_CEL_STATE <= computea1;
236 236
237 237
238 238 when computea1 =>
239 239 ALU_sample_in <= RAM_sample_out;
240 240 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
241 241 IIR_CEL_STATE <= computea2;
242 242
243 243
244 244 when computea2 =>
245 245 ALU_sample_in <= RAM_sample_out;
246 246 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
247 247 IIR_CEL_STATE <= next_cel;
248 248
249 249
250 250 when next_cel =>
251 ALU_ctrl <= clr_mac;
251 ALU_ctrl <= clr_mac_V0;
252 252 IIR_CEL_STATE <= pipe2;
253 253
254 254 when pipe2 =>
255 255 IIR_CEL_STATE <= pipe3;
256 256
257 257
258 258 when pipe3 =>
259 259
260 260 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
261 261
262 262 sample_out_BUFF(0) <= result;
263 263 RAM_sample_in_bk <= result;
264 264 RAM_sample_in <= result;
265 265 if curentCel = Cels_count-1 then
266 266 IIR_CEL_STATE <= next_chan;
267 267 curentCel <= 0;
268 268 else
269 269 curentCel <= curentCel + 1;
270 270 IIR_CEL_STATE <= pipe1;
271 271 ALU_sample_in <= result;
272 272 end if;
273 273 when next_chan =>
274 274
275 275 rotate : for i in 1 to ChanelsCount-1 loop
276 276 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
277 277 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
278 278 end loop;
279 279 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
280 280 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
281 281
282 282 if curentChan = (ChanelsCount-1) then
283 283 IIR_CEL_STATE <= waiting;
284 ALU_ctrl <= clr_mac;
284 ALU_ctrl <= clr_mac_V0;
285 285 elsif ChanelsCount>1 then
286 286 curentChan <= curentChan + 1;
287 287 IIR_CEL_STATE <= pipe1;
288 288 ALU_sample_in <= sample_in_BUFF(1);
289 289 RAM_sample_in <= sample_in_BUFF(1);
290 290 end if;
291 291 end case;
292 292
293 293 end if;
294 294 end process;
295 295
296 296
297 297
298 298
299 299
300 300
301 301 end ar_IIR_CEL_CTRLR;
302 302
303 303
304 304
305 305
306 306
307 307
308 308
309 309
310 310
311 311
312 312
313 313
314 314
315 315
316 316
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323 323
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330 330
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332 332
333 333
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336 336
337 337
338 338
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@@ -1,19 +1,19
1 1 APB_IIR_CEL.vhd
2 2 APB_IIR_Filter.vhd
3 FILTER.vhd
4 FILTER_RAM_CTRLR.vhd
5 3 FILTERcfg.vhd
6 4 FilterCTRLR.vhd
7 IIR_CEL_CTRLR.vhd
8 IIR_CEL_CTRLR_v2.vhd
5 FILTER_RAM_CTRLR.vhd
6 FILTER.vhd
9 7 IIR_CEL_CTRLR_v2_CONTROL.vhd
10 8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
9 IIR_CEL_CTRLR_v2.vhd
10 IIR_CEL_CTRLR.vhd
11 11 IIR_CEL_FILTER.vhd
12 RAM.vhd
12 iir_filter.vhd
13 RAM_CEL_N.vhd
13 14 RAM_CEL.vhd
14 RAM_CEL_N.vhd
15 15 RAM_CTRLR2.vhd
16 16 RAM_CTRLR_v2.vhd
17 RAM.vhd
17 18 Top_Filtre_IIR.vhd
18 19 Top_IIR.vhd
19 iir_filter.vhd
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@@ -1,11 +1,11
1 APB_FFT_half.vhd
1 2 APB_FFT.vhd
2 APB_FFT_half.vhd
3 3 Driver_FFT.vhd
4 FFTamont.vhd
5 FFTaval.vhd
4 6 FFT.vhd
5 7 FFT.vhd.bak
6 FFTamont.vhd
7 FFTaval.vhd
8 8 Flag_Extremum.vhd
9 9 Flag_Extremum.vhd.bak
10 10 Linker_FFT.vhd
11 11 lpp_fft.vhd
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@@ -1,272 +1,331
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 --UPDATE
23 23 -------------------------------------------------------------------------------
24 24 -- 14-03-2013 - Jean-christophe Pellion
25 25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 26 -------------------------------------------------------------------------------
27 27
28 28 LIBRARY ieee;
29 29 USE ieee.std_logic_1164.ALL;
30 30
31 31
32 32
33 33 PACKAGE general_purpose IS
34 34
35 35
36 36
37 37 COMPONENT Clk_divider IS
38 38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 39 TargetFreq_Hz : INTEGER := 50000);
40 40 PORT (clk : IN STD_LOGIC;
41 41 reset : IN STD_LOGIC;
42 42 clk_divided : OUT STD_LOGIC);
43 43 END COMPONENT;
44 44
45 45
46 46 COMPONENT Clk_divider2 IS
47 47 generic(N : integer := 16);
48 48 port(
49 49 clk_in : in std_logic;
50 50 clk_out : out std_logic);
51 51 END COMPONENT;
52 52
53 53 COMPONENT Adder IS
54 54 GENERIC(
55 55 Input_SZ_A : INTEGER := 16;
56 56 Input_SZ_B : INTEGER := 16
57 57
58 58 );
59 59 PORT(
60 60 clk : IN STD_LOGIC;
61 61 reset : IN STD_LOGIC;
62 62 clr : IN STD_LOGIC;
63 63 load : IN STD_LOGIC;
64 64 add : IN STD_LOGIC;
65 65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 68 );
69 69 END COMPONENT;
70 70
71 COMPONENT Adder_V0 is
72 generic(
73 Input_SZ_A : integer := 16;
74 Input_SZ_B : integer := 16
75
76 );
77 port(
78 clk : in std_logic;
79 reset : in std_logic;
80 clr : in std_logic;
81 add : in std_logic;
82 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
83 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
84 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
85 );
86 end COMPONENT;
87
71 88 COMPONENT ADDRcntr IS
72 89 PORT(
73 90 clk : IN STD_LOGIC;
74 91 reset : IN STD_LOGIC;
75 92 count : IN STD_LOGIC;
76 93 clr : IN STD_LOGIC;
77 94 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 95 );
79 96 END COMPONENT;
80 97
81 98 COMPONENT ALU IS
82 99 GENERIC(
83 100 Arith_en : INTEGER := 1;
84 101 Logic_en : INTEGER := 1;
85 102 Input_SZ_1 : INTEGER := 16;
86 103 Input_SZ_2 : INTEGER := 9;
87 104 COMP_EN : INTEGER := 0 -- 1 => No Comp
88 105
89 106 );
90 107 PORT(
91 108 clk : IN STD_LOGIC;
92 109 reset : IN STD_LOGIC;
93 110 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
94 111 comp : IN STD_LOGIC_VECTOR(1 downto 0);
95 112 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
96 113 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
97 114 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
98 115 );
99 116 END COMPONENT;
100 117
118 COMPONENT ALU_V0 IS
119 GENERIC(
120 Arith_en : INTEGER := 1;
121 Logic_en : INTEGER := 1;
122 Input_SZ_1 : INTEGER := 16;
123 Input_SZ_2 : INTEGER := 9
124
125 );
126 PORT(
127 clk : IN STD_LOGIC;
128 reset : IN STD_LOGIC;
129 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
130 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
131 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
132 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
133 );
134 END COMPONENT;
135
136 COMPONENT MAC_V0 is
137 generic(
138 Input_SZ_A : integer := 8;
139 Input_SZ_B : integer := 8
140
141 );
142 port(
143 clk : in std_logic;
144 reset : in std_logic;
145 clr_MAC : in std_logic;
146 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
147 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
148 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
149 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
150 );
151 end COMPONENT;
152
101 153 ---------------------------------------------------------
102 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
154 -------- // Sélection grace a l'entrée "ctrl" \\ --------
103 155 ---------------------------------------------------------
104 156 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
105 157 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
106 158 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
107 159 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
108 160 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
161
162
163 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
164 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
165 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
166 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
167 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
109 168 ---------------------------------------------------------
110 169
111 170 COMPONENT MAC IS
112 171 GENERIC(
113 172 Input_SZ_A : INTEGER := 8;
114 173 Input_SZ_B : INTEGER := 8;
115 174 COMP_EN : INTEGER := 0 -- 1 => No Comp
116 175 );
117 176 PORT(
118 177 clk : IN STD_LOGIC;
119 178 reset : IN STD_LOGIC;
120 179 clr_MAC : IN STD_LOGIC;
121 180 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 181 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
123 182 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
124 183 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
125 184 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
126 185 );
127 186 END COMPONENT;
128 187
129 188 COMPONENT TwoComplementer is
130 189 generic(
131 190 Input_SZ : integer := 16);
132 191 port(
133 192 clk : in std_logic; --! Horloge du composant
134 193 reset : in std_logic; --! Reset general du composant
135 clr : in std_logic; --! Un reset sp�cifique au programme
136 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
137 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
138 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
194 clr : in std_logic; --! Un reset spécifique au programme
195 TwoComp : in std_logic; --! Autorise l'utilisation du complément
196 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée
197 RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non
139 198 );
140 199 end COMPONENT;
141 200
142 201 COMPONENT MAC_CONTROLER IS
143 202 PORT(
144 203 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
145 204 MULT : OUT STD_LOGIC;
146 205 ADD : OUT STD_LOGIC;
147 206 LOAD_ADDER : out std_logic;
148 207 MACMUX_sel : OUT STD_LOGIC;
149 208 MACMUX2_sel : OUT STD_LOGIC
150 209 );
151 210 END COMPONENT;
152 211
153 212 COMPONENT MAC_MUX IS
154 213 GENERIC(
155 214 Input_SZ_A : INTEGER := 16;
156 215 Input_SZ_B : INTEGER := 16
157 216
158 217 );
159 218 PORT(
160 219 sel : IN STD_LOGIC;
161 220 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 221 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
163 222 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
164 223 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
165 224 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
166 225 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
167 226 );
168 227 END COMPONENT;
169 228
170 229
171 230 COMPONENT MAC_MUX2 IS
172 231 GENERIC(Input_SZ : INTEGER := 16);
173 232 PORT(
174 233 sel : IN STD_LOGIC;
175 234 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
176 235 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
177 236 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
178 237 );
179 238 END COMPONENT;
180 239
181 240
182 241 COMPONENT MAC_REG IS
183 242 GENERIC(size : INTEGER := 16);
184 243 PORT(
185 244 reset : IN STD_LOGIC;
186 245 clk : IN STD_LOGIC;
187 246 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
188 247 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
189 248 );
190 249 END COMPONENT;
191 250
192 251
193 252 COMPONENT MUX2 IS
194 253 GENERIC(Input_SZ : INTEGER := 16);
195 254 PORT(
196 255 sel : IN STD_LOGIC;
197 256 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
198 257 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
199 258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
200 259 );
201 260 END COMPONENT;
202 261
203 262 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
204 263 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
205 264
206 265 COMPONENT MUXN
207 266 GENERIC (
208 267 Input_SZ : INTEGER;
209 268 NbStage : INTEGER);
210 269 PORT (
211 270 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
212 271 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
213 272 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
214 273 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
215 274 END COMPONENT;
216 275
217 276
218 277
219 278 COMPONENT Multiplier IS
220 279 GENERIC(
221 280 Input_SZ_A : INTEGER := 16;
222 281 Input_SZ_B : INTEGER := 16
223 282
224 283 );
225 284 PORT(
226 285 clk : IN STD_LOGIC;
227 286 reset : IN STD_LOGIC;
228 287 mult : IN STD_LOGIC;
229 288 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
230 289 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
231 290 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
232 291 );
233 292 END COMPONENT;
234 293
235 294 COMPONENT REG IS
236 295 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
237 296 PORT(
238 297 reset : IN STD_LOGIC;
239 298 clk : IN STD_LOGIC;
240 299 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
241 300 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
242 301 );
243 302 END COMPONENT;
244 303
245 304
246 305
247 306 COMPONENT RShifter IS
248 307 GENERIC(
249 308 Input_SZ : INTEGER := 16;
250 309 shift_SZ : INTEGER := 4
251 310 );
252 311 PORT(
253 312 clk : IN STD_LOGIC;
254 313 reset : IN STD_LOGIC;
255 314 shift : IN STD_LOGIC;
256 315 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
257 316 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
258 317 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
259 318 );
260 319 END COMPONENT;
261 320
262 321 COMPONENT SYNC_FF
263 322 GENERIC (
264 323 NB_FF_OF_SYNC : INTEGER);
265 324 PORT (
266 325 clk : IN STD_LOGIC;
267 326 rstn : IN STD_LOGIC;
268 327 A : IN STD_LOGIC;
269 328 A_sync : OUT STD_LOGIC);
270 329 END COMPONENT;
271 330
272 331 END;
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@@ -1,18 +1,24
1 Adder_V0.vhd
2 Adder.vhd
1 3 ADDRcntr.vhd
4 ALU_V0.vhd
5 ALU_V0.vhd~
2 6 ALU.vhd
3 Adder.vhd
4 7 Clk_Divider2.vhd
8 Clk_Divider2.vhd~
5 9 Clk_divider.vhd
6 MAC.vhd
10 general_purpose.vhd
11 general_purpose.vhd~
7 12 MAC_CONTROLER.vhd
13 MAC_MUX2.vhd
8 14 MAC_MUX.vhd
9 MAC_MUX2.vhd
10 15 MAC_REG.vhd
16 MAC_V0.vhd
17 MAC.vhd
18 Multiplier.vhd
11 19 MUX2.vhd
12 20 MUXN.vhd
13 Multiplier.vhd
14 21 REG.vhd
22 Shifter.vhd
15 23 SYNC_FF.vhd
16 Shifter.vhd
17 24 TwoComplementer.vhd
18 general_purpose.vhd
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@@ -1,198 +1,114
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
25 LIBRARY IEEE;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
30
31 ENTITY AD7688_drvr IS
32 GENERIC(
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
36 PORT (
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
42
43 -- DATA --
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
51 );
52 END AD7688_drvr;
53
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
55
56 COMPONENT SYNC_FF
57 GENERIC (
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
65
66
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
74
75 SIGNAL cnv_run_sync : STD_LOGIC;
76
77 BEGIN
78 -----------------------------------------------------------------------------
79 -- CONV
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
92 ELSE
93 cnv_s <= '0';
94 END IF;
95 ELSE
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
98 END IF;
99 ELSE
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
102 END IF;
103 END IF;
104 END PROCESS;
105
106 cnv <= cnv_s;
107
108 -----------------------------------------------------------------------------
109
110
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
114
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
119 clk => clk,
120 rstn => rstn,
121 A => cnv_s,
122 A_sync => cnv_sync);
123
124 PROCESS (clk, rstn)
125 BEGIN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
133 END PROCESS;
134
135 -----------------------------------------------------------------------------
136
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
141 clk => clk,
142 rstn => rstn,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
145
146
147
148 -----------------------------------------------------------------------------
149 -- DATA
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
156 sample(l)(15 DOWNTO 0) <= (OTHERS => '0');
157 END LOOP;
158 sample_bit_counter <= 0;
159 sample_val <= '0';
160 SCK <= '1';
161
162 ELSIF clk'EVENT AND clk = '1' THEN
163
164 IF cnv_run_sync = '0' THEN
165 sample_bit_counter <= 0;
166 ELSIF cnv_done = '1' THEN
167 sample_bit_counter <= 1;
168 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
169 sample_bit_counter <= sample_bit_counter + 1;
170 END IF;
171
172 IF (sample_bit_counter MOD 2) = 1 THEN
173 FOR l IN 0 TO ChanelCount-1 LOOP
174 --shift_reg(l)(15) <= sdo(l);
175 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
176 shift_reg(l)(0) <= sdo(l);
177 shift_reg(l)(14 DOWNTO 1) <= shift_reg(l)(13 DOWNTO 0);
178 END LOOP;
179 SCK <= '0';
180 ELSE
181 SCK <= '1';
182 END IF;
183
184 IF sample_bit_counter = 31 THEN
185 sample_val <= '1';
186 FOR l IN 0 TO ChanelCount-1 LOOP
187 --sample(l)(15) <= sdo(l);
188 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
189 sample(l)(0) <= sdo(l);
190 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
191 END LOOP;
192 ELSE
193 sample_val <= '0';
194 END IF;
195 END IF;
196 END PROCESS;
197
198 END ar_AD7688_drvr;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 library lpp;
25 use lpp.lpp_ad_conv.all;
26 use lpp.general_purpose.Clk_divider;
27
28 --! \brief AD7688 driver, generates all needed signal to drive this ADC.
29 --!
30 --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
31
32 entity AD7688_drvr is
33 generic(
34 ChanelCount :integer; --! Number of ADC you whant to drive
35 clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width.
36 );
37 Port(
38 clk : in STD_LOGIC; --! System clock
39 rstn : in STD_LOGIC; --! System reset
40 enable : in std_logic; --! Negative enable
41 smplClk : in STD_LOGIC; --! Sampling clock
42 DataReady : out std_logic; --! New sample available
43 smpout : out Samples(ChanelCount-1 downto 0); --! Samples
44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
45 AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv
46 );
47 end AD7688_drvr;
48
49 architecture ar_AD7688_drvr of AD7688_drvr is
50
51 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
52
53 signal i : integer range 0 to convTrigger :=0;
54 signal clk_int : std_logic;
55 signal clk_int_inv : std_logic;
56 signal smplClk_reg : std_logic;
57 signal cnv_int : std_logic;
58 signal reset : std_logic;
59
60 begin
61
62 clkdiv: if clkkHz>=66000 generate
63 clkdivider: entity work.Clk_divider
64 generic map(clkkHz*1000,60000000)
65 Port map( clk ,reset,clk_int);
66 end generate;
67
68 clknodiv: if clkkHz<66000 generate
69 nodiv: clk_int <= clk;
70 end generate;
71
72 clk_int_inv <= not clk_int;
73
74 AD_out.CNV <= cnv_int;
75 AD_out.SCK <= clk_int;
76 reset <= rstn and enable;
77
78 sckgen: process(clk,reset)
79 begin
80 if reset = '0' then
81 i <= 0;
82 cnv_int <= '0';
83 smplClk_reg <= '0';
84 elsif clk'event and clk = '1' then
85 if smplClk = '1' and smplClk_reg = '0' then
86 if i = convTrigger then
87 smplClk_reg <= '1';
88 i <= 0;
89 cnv_int <= '0';
90 else
91 i <= i+1;
92 cnv_int <= '1';
93 end if;
94 elsif smplClk = '0' and smplClk_reg = '1' then
95 smplClk_reg <= '0';
96 end if;
97 end if;
98 end process;
99
100
101
102 spidrvr: entity work.AD7688_spi_if
103 generic map(ChanelCount)
104 Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout);
105
106
107
108 end ar_AD7688_drvr;
109
110
111
112
113
114
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@@ -1,78 +1,78
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.STD_LOGIC_1164.ALL;
24 24 library lpp;
25 25 use lpp.lpp_ad_conv.all;
26 26 use lpp.general_purpose.Clk_divider;
27 27
28 28 entity AD7688_spi_if is
29 29 generic(ChanelCount : integer);
30 30 Port( clk : in STD_LOGIC;
31 31 reset : in STD_LOGIC;
32 32 cnv : in STD_LOGIC;
33 33 DataReady : out std_logic;
34 34 sdi : in AD7688_in(ChanelCount-1 downto 0);
35 smpout : out Samples_out(ChanelCount-1 downto 0)
35 smpout : out Samples(ChanelCount-1 downto 0)
36 36 );
37 37 end AD7688_spi_if;
38 38
39 39 architecture ar_AD7688_spi_if of AD7688_spi_if is
40 40
41 signal shift_reg : Samples_out(ChanelCount-1 downto 0);
41 signal shift_reg : Samples(ChanelCount-1 downto 0);
42 42 signal i : integer range 0 to 16 :=0;
43 43 signal cnv_reg : std_logic := '0';
44 44
45 45 begin
46 46
47 47
48 48
49 49 process(clk,reset)
50 50 begin
51 51 if reset = '0' then
52 52 for l in 0 to ChanelCount-1 loop
53 53 shift_reg(l) <= (others => '0');
54 54 end loop;
55 55 i <= 0;
56 56 cnv_reg <= '0';
57 57 elsif clk'event and clk = '1' then
58 58 if cnv = '0' and cnv_reg = '0' then
59 59 if i = 16 then
60 60 i <= 0;
61 61 cnv_reg <= '1';
62 62 else
63 63 DataReady <= '0';
64 64 i <= i+1;
65 65 for l in 0 to ChanelCount-1 loop
66 66 shift_reg(l)(0) <= sdi(l).SDI;
67 67 shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0);
68 68 end loop;
69 69 end if;
70 70 else
71 71 cnv_reg <= not cnv;
72 72 smpout <= shift_reg;
73 73 DataReady <= '1';
74 74 end if;
75 75 end if;
76 76 end process;
77 77
78 78 end ar_AD7688_spi_if;
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@@ -1,221 +1,169
1 1 -- ADS1274_DRIVER.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5 library lpp;
6 6 use lpp.lpp_ad_conv.all;
7 7 use lpp.general_purpose.all;
8 8
9 9
10 10
11 11
12 12
13 entity DUAL_ADS1278_DRIVER is
13 entity DUAL_ADS1278_DRIVER is
14 generic
15 (
16 SCLKDIV : integer range 2 to 256 :=16
17 );
14 18 port(
15 Clk : in std_logic;
16 reset : in std_logic;
17 SpiClk : out std_logic;
18 DIN : in std_logic_vector(1 downto 0);
19 SmplClk : in std_logic;
19 Clk : in std_logic;
20 reset : in std_logic;
21 SpiClk : out std_logic;
22 DIN : in std_logic_vector(1 downto 0);
23 SmplClk : in std_logic;
20 24 OUT00 : out std_logic_vector(23 downto 0);
21 25 OUT01 : out std_logic_vector(23 downto 0);
22 26 OUT02 : out std_logic_vector(23 downto 0);
23 27 OUT03 : out std_logic_vector(23 downto 0);
24 28 OUT04 : out std_logic_vector(23 downto 0);
25 29 OUT05 : out std_logic_vector(23 downto 0);
26 30 OUT06 : out std_logic_vector(23 downto 0);
27 31 OUT07 : out std_logic_vector(23 downto 0);
28 32 OUT10 : out std_logic_vector(23 downto 0);
29 33 OUT11 : out std_logic_vector(23 downto 0);
30 34 OUT12 : out std_logic_vector(23 downto 0);
31 35 OUT13 : out std_logic_vector(23 downto 0);
32 36 OUT14 : out std_logic_vector(23 downto 0);
33 37 OUT15 : out std_logic_vector(23 downto 0);
34 38 OUT16 : out std_logic_vector(23 downto 0);
35 39 OUT17 : out std_logic_vector(23 downto 0);
36 FSynch : out std_logic
40 FSynch : out std_logic
37 41 );
38 42 end DUAL_ADS1278_DRIVER;
39 43
40 44
41 45
42 46
43 47
44 48
45 49 architecture ar_DUAL_ADS1278_DRIVER of DUAL_ADS1278_DRIVER is
46
47 signal Vec00,Vec01,Vec02,Vec03,Vec04,Vec05,Vec06,Vec07,Vec10,Vec11,Vec12,Vec13,Vec14,Vec15,Vec16,Vec17 : std_logic_vector(23 downto 0);
50 signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0);
48 51 signal SmplClk_Reg : std_logic:= '0';
49 signal N : integer range 0 to 23*8 := 0;
52 signal N : integer range 0 to (24*8) := 0;
50 53 signal SPI_CLk : std_logic;
51 54 signal SmplClk_clkd : std_logic:= '0';
52 55
53 56 begin
54 57
55 58
56 59 CLKDIV0 : Clk_Divider2
57 generic map(16)
60 generic map(SCLKDIV)
58 61 port map(Clk,SPI_CLk);
59 62
60
61 FSynch <= SmplClk_clkd;
62 SpiClk <= SPI_CLk;
63 SpiClk <= not SPI_CLk;
63 64
64 65 process(reset,SPI_CLk)
65 66 begin
66 67
67 68 if reset = '0' then
68 Vec00 <= (others => '0');
69 Vec01 <= (others => '0');
70 Vec02 <= (others => '0');
71 Vec03 <= (others => '0');
72 Vec04 <= (others => '0');
73 Vec05 <= (others => '0');
74 Vec06 <= (others => '0');
75 Vec07 <= (others => '0');
76
77 Vec10 <= (others => '0');
78 Vec11 <= (others => '0');
79 Vec12 <= (others => '0');
80 Vec13 <= (others => '0');
81 Vec14 <= (others => '0');
82 Vec15 <= (others => '0');
83 Vec16 <= (others => '0');
84 Vec17 <= (others => '0');
85 N <= 0;
69 ShiftGeg0 <= (others => '0');
70 ShiftGeg1 <= (others => '0');
71 N <= 0;
86 72 elsif SPI_CLk'event and SPI_CLk = '1' then
87 -- SmplClk_clkd <= SmplClk;
88 -- SmplClk_Reg <= SmplClk_clkd;
89 --if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
90 if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
91 --Vec0(0) <= DIN(0);
92 --Vec1(0) <= DIN(1);
93 --Vec2(0) <= DIN(2);
94 --Vec3(0) <= DIN(3);
95 --Vec0(23 downto 1) <= Vec0(22 downto 0);
96 --Vec1(23 downto 1) <= Vec1(22 downto 0);
97 --Vec2(23 downto 1) <= Vec2(22 downto 0);
98 --Vec3(23 downto 1) <= Vec3(22 downto 0);
99 Vec00(0) <= DIN(0);
100 Vec00(23 downto 1) <= Vec00(22 downto 0);
101 Vec01(0) <= Vec00(23);
102
103 Vec01(23 downto 1) <= Vec01(22 downto 0);
104 Vec02(0) <= Vec01(23);
105
106 Vec02(23 downto 1) <= Vec02(22 downto 0);
107 Vec03(0) <= Vec02(23);
108
109 Vec03(23 downto 1) <= Vec03(22 downto 0);
110 Vec04(0) <= Vec03(23);
111
112 Vec04(23 downto 1) <= Vec04(22 downto 0);
113 Vec05(0) <= Vec04(23);
114
115 Vec05(23 downto 1) <= Vec05(22 downto 0);
116 Vec06(0) <= Vec05(23);
117
118 Vec06(23 downto 1) <= Vec06(22 downto 0);
119 Vec07(0) <= Vec06(23);
120
121 Vec07(23 downto 1) <= Vec07(22 downto 0);
122
123
124 Vec10(0) <= DIN(1);
125 Vec10(23 downto 1) <= Vec10(22 downto 0);
126 Vec11(0) <= Vec10(23);
127
128 Vec11(23 downto 1) <= Vec11(22 downto 0);
129 Vec12(0) <= Vec11(23);
130
131 Vec12(23 downto 1) <= Vec12(22 downto 0);
132 Vec13(0) <= Vec12(23);
133
134 Vec13(23 downto 1) <= Vec13(22 downto 0);
135 Vec14(0) <= Vec13(23);
136
137 Vec14(23 downto 1) <= Vec14(22 downto 0);
138 Vec15(0) <= Vec14(23);
139
140 Vec15(23 downto 1) <= Vec15(22 downto 0);
141 Vec16(0) <= Vec15(23);
142
143 Vec16(23 downto 1) <= Vec16(22 downto 0);
144 Vec17(0) <= Vec16(23);
145
146 Vec17(23 downto 1) <= Vec17(22 downto 0);
147 if N = (23*8) then
73 FSynch <= SmplClk;
74 if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then
75 ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & DIN(0);
76 ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & DIN(1);
77 if N = ((24*8)-1) then
148 78 N <= 0;
149 79 else
150 80 N <= N+1;
151 81 end if;
152 82 end if;
153 83 end if;
154 84 end process;
155 85
156 86
157 87 process(SPI_CLk)
158 88 begin
159 89 if SPI_CLk'event and SPI_CLk ='0' then
160 90 SmplClk_clkd <= SmplClk;
161 91 SmplClk_Reg <= SmplClk_clkd;
162 92 end if;
163 93 end process;
164 94
165 95
166 process(SPI_CLk)
167 begin
168 if SPI_CLk'event and SPI_CLk ='1' then
96 process(clk,reset)
97 begin
98 if reset = '0' then
99 OUT00 <= (others => '0');
100 OUT01 <= (others => '0');
101 OUT02 <= (others => '0');
102 OUT03 <= (others => '0');
103 OUT04 <= (others => '0');
104 OUT05 <= (others => '0');
105 OUT06 <= (others => '0');
106 OUT07 <= (others => '0');
107
108 OUT10 <= (others => '0');
109 OUT11 <= (others => '0');
110 OUT12 <= (others => '0');
111 OUT13 <= (others => '0');
112 OUT14 <= (others => '0');
113 OUT15 <= (others => '0');
114 OUT16 <= (others => '0');
115 OUT17 <= (others => '0');
116 elsif clk'event and clk ='1' then
169 117 if N = 0 then
170 OUT00 <= Vec00;
171 OUT01 <= Vec01;
172 OUT02 <= Vec02;
173 OUT03 <= Vec03;
174 OUT04 <= Vec04;
175 OUT05 <= Vec05;
176 OUT06 <= Vec06;
177 OUT07 <= Vec07;
118 OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1)));
119 OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1)));
120 OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1)));
121 OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1)));
122 OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1)));
123 OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1)));
124 OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1)));
125 OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1)));
178 126
179 OUT10 <= Vec10;
180 OUT11 <= Vec11;
181 OUT12 <= Vec12;
182 OUT13 <= Vec13;
183 OUT14 <= Vec14;
184 OUT15 <= Vec15;
185 OUT16 <= Vec16;
186 OUT17 <= Vec17;
127 OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1)));
128 OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1)));
129 OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1)));
130 OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1)));
131 OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1)));
132 OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1)));
133 OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1)));
134 OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1)));
187 135 end if;
188 136 end if;
189 137 end process;
190 138
191 139 end ar_DUAL_ADS1278_DRIVER;
192 140
193 141
194 142
195 143
196 144
197 145
198 146
199 147
200 148
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@@ -1,308 +1,224
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 USE grlib.devices.ALL;
29 29
30 30
31 31 PACKAGE lpp_ad_conv IS
32 32
33 33
34 34 --CONSTANT AD7688 : INTEGER := 0;
35 35 --CONSTANT ADS7886 : INTEGER := 1;
36 36
37 37
38 --TYPE AD7688_out IS
39 --RECORD
40 -- CNV : STD_LOGIC;
41 -- SCK : STD_LOGIC;
42 --END RECORD;
38 TYPE AD7688_out IS
39 RECORD
40 CNV : STD_LOGIC;
41 SCK : STD_LOGIC;
42 END RECORD;
43 43
44 --TYPE AD7688_in_element IS
45 --RECORD
46 -- SDI : STD_LOGIC;
47 --END RECORD;
44 TYPE AD7688_in_element IS
45 RECORD
46 SDI : STD_LOGIC;
47 END RECORD;
48 48
49 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
49 TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
50 50
51 51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52 52
53 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
54
55 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
56
57 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
58
59 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
60
61 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
62
63 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
64
65 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
66
67 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
68
69 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
70
71 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
72
73 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
74
75 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
76
77 COMPONENT AD7688_drvr
53 COMPONENT ADS7886_drvr
78 54 GENERIC (
79 55 ChanelCount : INTEGER;
80 56 ncycle_cnv_high : INTEGER := 79;
81 57 ncycle_cnv : INTEGER := 500);
82 58 PORT (
83 59 cnv_clk : IN STD_LOGIC;
84 60 cnv_rstn : IN STD_LOGIC;
85 cnv_run : IN STD_LOGIC;
61 cnv_run : IN STD_LOGIC;
86 62 cnv : OUT STD_LOGIC;
87 63 clk : IN STD_LOGIC;
88 64 rstn : IN STD_LOGIC;
89 65 sck : OUT STD_LOGIC;
90 66 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
91 67 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
92 68 sample_val : OUT STD_LOGIC);
93 69 END COMPONENT;
94
95 COMPONENT RHF1401_drvr IS
96 GENERIC(
97 ChanelCount : INTEGER := 8);
98 PORT (
99 cnv_clk : IN STD_LOGIC;
100 clk : IN STD_LOGIC;
101 rstn : IN STD_LOGIC;
102 ADC_data : IN Samples14;
103 --ADC_smpclk : OUT STD_LOGIC;
104 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
105 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
106 sample_val : OUT STD_LOGIC
107 );
108 END COMPONENT;
109
110 COMPONENT top_ad_conv_RHF1401
111 GENERIC (
112 ChanelCount : INTEGER;
113 ncycle_cnv_high : INTEGER := 79;
114 ncycle_cnv : INTEGER := 500);
115 PORT (
116 cnv_clk : IN STD_LOGIC;
117 cnv_rstn : IN STD_LOGIC;
118 cnv : OUT STD_LOGIC;
119 clk : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
121 ADC_data : IN Samples14;
122 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
123 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
124 sample_val : OUT STD_LOGIC);
70
71 COMPONENT AD7688_drvr IS
72 GENERIC(ChanelCount : INTEGER;
73 clkkHz : INTEGER);
74 PORT (clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 enable : IN STD_LOGIC;
77 smplClk : IN STD_LOGIC;
78 DataReady : OUT STD_LOGIC;
79 smpout : OUT Samples(ChanelCount-1 DOWNTO 0);
80 AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
81 AD_out : OUT AD7688_out);
125 82 END COMPONENT;
126 83
127 84
128 COMPONENT AD7688_drvr_sync
129 GENERIC (
130 ChanelCount : INTEGER;
131 ncycle_cnv_high : INTEGER;
132 ncycle_cnv : INTEGER);
133 PORT (
134 cnv_clk : IN STD_LOGIC;
135 cnv_rstn : IN STD_LOGIC;
136 cnv_run : IN STD_LOGIC;
137 cnv : OUT STD_LOGIC;
138 sck : OUT STD_LOGIC;
139 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
140 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
141 sample_val : OUT STD_LOGIC);
142 END COMPONENT;
143
144 COMPONENT TestModule_RHF1401
145 GENERIC (
146 freq : INTEGER;
147 amplitude : INTEGER;
148 impulsion : INTEGER);
149 PORT (
150 ADC_smpclk : IN STD_LOGIC;
151 ADC_OEB_bar : IN STD_LOGIC;
152 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
85 COMPONENT AD7688_spi_if IS
86 GENERIC(ChanelCount : INTEGER);
87 PORT(clk : IN STD_LOGIC;
88 reset : IN STD_LOGIC;
89 cnv : IN STD_LOGIC;
90 DataReady : OUT STD_LOGIC;
91 sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
92 smpout : OUT Samples(ChanelCount-1 DOWNTO 0)
93 );
153 94 END COMPONENT;
154 95
155 --COMPONENT AD7688_drvr IS
156 -- GENERIC(ChanelCount : INTEGER;
157 -- clkkHz : INTEGER);
158 -- PORT (clk : IN STD_LOGIC;
159 -- rstn : IN STD_LOGIC;
160 -- enable : IN STD_LOGIC;
161 -- smplClk : IN STD_LOGIC;
162 -- DataReady : OUT STD_LOGIC;
163 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
164 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
165 -- AD_out : OUT AD7688_out);
166 --END COMPONENT;
167
168
169 --COMPONENT AD7688_spi_if IS
170 -- GENERIC(ChanelCount : INTEGER);
171 -- PORT(clk : IN STD_LOGIC;
172 -- reset : IN STD_LOGIC;
173 -- cnv : IN STD_LOGIC;
174 -- DataReady : OUT STD_LOGIC;
175 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
176 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
177 -- );
178 --END COMPONENT;
179
180 96
181 97 --COMPONENT lpp_apb_ad_conv
182 98 -- GENERIC(
183 99 -- pindex : INTEGER := 0;
184 100 -- paddr : INTEGER := 0;
185 101 -- pmask : INTEGER := 16#fff#;
186 102 -- pirq : INTEGER := 0;
187 103 -- abits : INTEGER := 8;
188 104 -- ChanelCount : INTEGER := 1;
189 105 -- clkkHz : INTEGER := 50000;
190 106 -- smpClkHz : INTEGER := 100;
191 107 -- ADCref : INTEGER := AD7688);
192 108 -- PORT (
193 109 -- clk : IN STD_LOGIC;
194 110 -- reset : IN STD_LOGIC;
195 111 -- apbi : IN apb_slv_in_type;
196 112 -- apbo : OUT apb_slv_out_type;
197 113 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
198 114 -- AD_out : OUT AD7688_out);
199 115 --END COMPONENT;
200 116
201 117 --COMPONENT ADS7886_drvr IS
202 118 -- GENERIC(ChanelCount : INTEGER;
203 119 -- clkkHz : INTEGER);
204 120 -- PORT (
205 121 -- clk : IN STD_LOGIC;
206 122 -- reset : IN STD_LOGIC;
207 123 -- smplClk : IN STD_LOGIC;
208 124 -- DataReady : OUT STD_LOGIC;
209 125 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
210 126 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
211 127 -- AD_out : OUT AD7688_out
212 128 -- );
213 129 --END COMPONENT;
214 130
215 131 --COMPONENT WriteGen_ADC IS
216 132 -- PORT(
217 133 -- clk : IN STD_LOGIC;
218 134 -- rstn : IN STD_LOGIC;
219 135 -- SmplCLK : IN STD_LOGIC;
220 136 -- DataReady : IN STD_LOGIC;
221 137 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
222 138 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
223 139 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
224 140 -- );
225 141 --END COMPONENT;
226 142
227 143
228 144 --===========================================================|
229 145 --======================= ADS 127X =========================|
230 146 --===========================================================|
231 147
232 TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
233 CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
234 CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
148 Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic;
149 constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
150 constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
235 151
236 TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
237 CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
238 CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
239 CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
152 Type ADS127X_MODE_Type is array(1 downto 0) of std_logic;
153 constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
154 constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
155 constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
240 156
241 TYPE ADS127X_config IS
242 RECORD
243 SYNC : STD_LOGIC;
244 CLKDIV : STD_LOGIC;
245 FORMAT : ADS127X_FORMAT_Type;
246 MODE : ADS127X_MODE_Type;
247 END RECORD;
157 Type ADS127X_config is
158 record
159 SYNC : std_logic;
160 CLKDIV : std_logic;
161 FORMAT : ADS127X_FORMAT_Type;
162 MODE : ADS127X_MODE_Type;
163 end record;
248 164
249 COMPONENT ADS1274_DRIVER IS
250 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
251 PORT(
252 Clk : IN STD_LOGIC;
253 reset : IN STD_LOGIC;
254 SpiClk : OUT STD_LOGIC;
255 DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
256 Ready : IN STD_LOGIC;
257 Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
258 Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
259 ClkDiv : OUT STD_LOGIC;
260 PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
261 SmplClk : IN STD_LOGIC;
262 OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
263 OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
264 OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
265 OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
266 FSynch : OUT STD_LOGIC;
267 test : OUT STD_LOGIC
268 );
269 END COMPONENT;
165 COMPONENT ADS1274_DRIVER is
166 generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
167 port(
168 Clk : in std_logic;
169 reset : in std_logic;
170 SpiClk : out std_logic;
171 DIN : in std_logic_vector(3 downto 0);
172 Ready : in std_logic;
173 Format : out std_logic_vector(2 downto 0);
174 Mode : out std_logic_vector(1 downto 0);
175 ClkDiv : out std_logic;
176 PWDOWN : out std_logic_vector(3 downto 0);
177 SmplClk : in std_logic;
178 OUT0 : out std_logic_vector(23 downto 0);
179 OUT1 : out std_logic_vector(23 downto 0);
180 OUT2 : out std_logic_vector(23 downto 0);
181 OUT3 : out std_logic_vector(23 downto 0);
182 FSynch : out std_logic;
183 test : out std_logic
184 );
185 end COMPONENT;
270 186
271 187 -- todo clean file
272 COMPONENT DUAL_ADS1278_DRIVER IS
273 PORT(
274 Clk : IN STD_LOGIC;
275 reset : IN STD_LOGIC;
276 SpiClk : OUT STD_LOGIC;
277 DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
278 SmplClk : IN STD_LOGIC;
279 OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
280 OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
281 OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
282 OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
283 OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
284 OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
285 OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
286 OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
287 OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
288 OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
289 OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
290 OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
291 OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
292 OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
293 OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
294 OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
295 FSynch : OUT STD_LOGIC
296 );
297 END COMPONENT;
188 COMPONENT DUAL_ADS1278_DRIVER is
189 port(
190 Clk : in std_logic;
191 reset : in std_logic;
192 SpiClk : out std_logic;
193 DIN : in std_logic_vector(1 downto 0);
194 SmplClk : in std_logic;
195 OUT00 : out std_logic_vector(23 downto 0);
196 OUT01 : out std_logic_vector(23 downto 0);
197 OUT02 : out std_logic_vector(23 downto 0);
198 OUT03 : out std_logic_vector(23 downto 0);
199 OUT04 : out std_logic_vector(23 downto 0);
200 OUT05 : out std_logic_vector(23 downto 0);
201 OUT06 : out std_logic_vector(23 downto 0);
202 OUT07 : out std_logic_vector(23 downto 0);
203 OUT10 : out std_logic_vector(23 downto 0);
204 OUT11 : out std_logic_vector(23 downto 0);
205 OUT12 : out std_logic_vector(23 downto 0);
206 OUT13 : out std_logic_vector(23 downto 0);
207 OUT14 : out std_logic_vector(23 downto 0);
208 OUT15 : out std_logic_vector(23 downto 0);
209 OUT16 : out std_logic_vector(23 downto 0);
210 OUT17 : out std_logic_vector(23 downto 0);
211 FSynch : out std_logic
212 );
213 end COMPONENT;
298 214
299 215
300 216 END lpp_ad_conv;
301 217
302 218
303 219
304 220
305 221
306 222
307 223
308 224
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@@ -1,13 +1,19
1 AD7688_drvr_sync.vhd
1 2 AD7688_drvr.vhd
2 AD7688_drvr_sync.vhd
3 AD7688_drvr.vhd.orig
3 4 AD7688_spi_if.vhd
4 5 ADS1274_drvr.vhd
6 ADS1274_drvr.vhd~
5 7 ADS1278_drvr.vhd
8 ADS1278_drvr.vhd~
6 9 ADS7886_drvr.vhd
7 RHF1401.vhd
8 WriteGen_ADC.vhd
9 10 dual_ADS1278_drvr.vhd
11 dual_ADS1278_drvr.vhd~
10 12 lpp_ad_Conv.vhd
13 lpp_ad_Conv.vhd~
14 lpp_ad_Conv.vhd.orig
11 15 lpp_apb_ad_conv.vhd
16 RHF1401.vhd
17 top_ad_conv_RHF1401.vhd
12 18 top_ad_conv.vhd
13 top_ad_conv_RHF1401.vhd
19 WriteGen_ADC.vhd
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@@ -1,4 +1,4
1 apb_devices_list.vhd
1 2 APB_MULTI_DIODE.vhd
2 3 APB_SIMPLE_DIODE.vhd
3 apb_devices_list.vhd
4 4 lpp_amba.vhd
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@@ -1,3 +1,3
1 1 bootrom.vhd
2 lpp_bootloader_pkg.vhd
2 3 lpp_bootloader.vhd
3 lpp_bootloader_pkg.vhd
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@@ -1,8 +1,8
1 1 fifo_latency_correction.vhd
2 lpp_dma.vhd
3 2 lpp_dma_apbreg.vhd
4 3 lpp_dma_fsm.vhd
5 4 lpp_dma_ip.vhd
6 5 lpp_dma_pkg.vhd
7 6 lpp_dma_send_16word.vhd
8 7 lpp_dma_send_1word.vhd
8 lpp_dma.vhd
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@@ -1,17 +1,17
1 1 ALU_Driver.vhd
2 2 ALU_Driver.vhd.bak
3 3 APB_Matrix.vhd
4 4 Dispatch.vhd
5 5 DriveInputs.vhd
6 6 GetResult.vhd
7 lpp_matrix.vhd
7 8 MatriceSpectrale.vhd
8 9 MatriceSpectrale.vhd.bak
9 10 Matrix.vhd
10 11 ReUse_CTRLR.vhd
11 12 SpectralMatrix.vhd
12 13 SpectralMatrix.vhd.bak
13 14 Starter.vhd
14 15 TopMatrix_PDR.vhd
16 Top_MatrixSpec.vhd
15 17 TopSpecMatrix.vhd
16 Top_MatrixSpec.vhd
17 lpp_matrix.vhd
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@@ -1,11 +1,11
1 1 APB_FIFO.vhd
2 2 APB_FIFO.vhd.bak
3 3 FIFO_pipeline.vhd
4 4 FillFifo.vhd
5 SSRAM_plugin.vhd
6 SSRAM_plugin_vsim.vhd
5 lpp_FIFO.vhd
7 6 lppFIFOxN.vhd
8 7 lppFIFOxN.vhd.bak
9 lpp_FIFO.vhd
10 8 lpp_memory.vhd
11 9 lpp_memory.vhd.bak
10 SSRAM_plugin.vhd
11 SSRAM_plugin_vsim.vhd
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@@ -1,15 +1,15
1 lpp_lfr.vhd
2 1 lpp_lfr_apbreg.vhd
3 2 lpp_lfr_filter.vhd
4 3 lpp_lfr_ms.vhd
5 4 lpp_lfr_pkg.vhd
5 lpp_lfr.vhd
6 6 lpp_top_acq.vhd
7 7 lpp_top_acq.vhd.bak
8 8 lpp_top_apbreg.vhd
9 lpp_top_lfr.vhd
10 9 lpp_top_lfr_pkg.vhd
11 10 lpp_top_lfr_pkg.vhd.bak
12 lpp_top_lfr_wf_picker.vhd
11 lpp_top_lfr.vhd
13 12 lpp_top_lfr_wf_picker_ip.vhd
14 13 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
14 lpp_top_lfr_wf_picker.vhd
15 15 top_wf_picker.vhd
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@@ -1,13 +1,13
1 lpp_waveform.vhd
2 1 lpp_waveform_burst.vhd
3 lpp_waveform_dma.vhd
4 2 lpp_waveform_dma_genvalid.vhd
5 3 lpp_waveform_dma_selectaddress.vhd
6 4 lpp_waveform_dma_send_Nword.vhd
7 lpp_waveform_fifo.vhd
5 lpp_waveform_dma.vhd
8 6 lpp_waveform_fifo_arbiter.vhd
9 7 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo.vhd
10 9 lpp_waveform_pkg.vhd
10 lpp_waveform_snapshot_controler.vhd
11 11 lpp_waveform_snapshot.vhd
12 lpp_waveform_snapshot_controler.vhd
13 12 lpp_waveform_valid_ack.vhd
13 lpp_waveform.vhd
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