diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -52,6 +52,7 @@ Patch-GRLIB: init doc sh $(SCRIPTSDIR)/patch.sh $(GRLIB) link: + sh $(SCRIPTSDIR)/vhdlsynPatcher.sh sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB) diff --git a/boards/ICI4-main-BD/ICI4-Main-BD.ucf b/boards/ICI4-main-BD/ICI4-Main-BD.ucf --- a/boards/ICI4-main-BD/ICI4-Main-BD.ucf +++ b/boards/ICI4-main-BD/ICI4-Main-BD.ucf @@ -1,11 +1,31 @@ -NET "CLK" LOC = "B10"; +NET "CLK" LOC = "B10" | IOSTANDARD = LVCMOS33; + +NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; NET "RESET" LOC = "A5" | IOSTANDARD = LVTTL; + +NET "SCLK" CLOCK_DEDICATED_ROUTE = FALSE; NET "SCLK" LOC = "V22" | IOSTANDARD = LVTTL; + NET "GATE" LOC = "T22" | IOSTANDARD = LVTTL; + +NET "MINF" CLOCK_DEDICATED_ROUTE = FALSE; NET "MINF" LOC = "T21" | IOSTANDARD = LVTTL; + NET "MAJF" LOC = "U22" | IOSTANDARD = LVTTL; -NET "DATA" LOC = "V21"; -NET "DC_ADC_SCLK" LOC = "AB17"; +NET "DATA" LOC = "V21" | IOSTANDARD = LVCMOS33; +NET "DC_ADC_SCLK" LOC = "AB17" | IOSTANDARD = LVCMOS33; NET "DC_ADC_IN(0)" LOC = "AB19" | IOSTANDARD = LVTTL; NET "DC_ADC_IN(1)" LOC = "AA18" | IOSTANDARD = LVTTL; -NET "DC_ADC_FSynch" LOC = "AB18"; +NET "DC_ADC_FSynch" LOC = "AB18" | IOSTANDARD = LVCMOS33; +NET "LED" LOC = "A3" | IOSTANDARD = LVCMOS33; +NET "SET_RESET0" LOC = "AB21" | IOSTANDARD = LVCMOS33; +NET "SET_RESET1" LOC = "AB20" | IOSTANDARD = LVCMOS33; + + +NET "LF_SCK" LOC = "W20"| IOSTANDARD = LVCMOS33; +NET "LF_CNV" LOC = "Y18"| IOSTANDARD = LVCMOS33; +NET "LF_SDO1" LOC = "W17" | IOSTANDARD = LVTTL; +NET "LF_SDO2" LOC = "AA21" | IOSTANDARD = LVTTL; +NET "LF_SDO3" LOC = "AA16" | IOSTANDARD = LVTTL; + + diff --git a/designs/ICI4-Integ1/ICI4HDL/ClkDivider.vhd b/designs/ICI4-Integ1/ICI4HDL/ClkDivider.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/ClkDivider.vhd +++ /dev/null @@ -1,36 +0,0 @@ --- ClkDivider.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - - -entity ClkDivider is -generic(N : integer := 16); -port( - clk_in : in std_logic; - clk_out : out std_logic -); -end entity; - - - -architecture ar_ClkDivider of ClkDivider is -signal cpt : integer range 0 to N/2-1; -signal clk_int : std_logic:='0'; -begin - -clk_out <= clk_int; - -process(clk_in) -begin - if clk_in'event and clk_in = '1' then - if cpt = N/2-1 then - clk_int <= not clk_int; - cpt <= 0; - else - cpt <= cpt + 1; - end if; - end if; -end process; -end ar_ClkDivider; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/CrossDomainSyncGen.vhd b/designs/ICI4-Integ1/ICI4HDL/CrossDomainSyncGen.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/CrossDomainSyncGen.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------ +-- +-- This module implements the SyncSignal generator explained in: +-- Data Transfer between Asynchronous Clock Domains without Pain +-- from Markus Schutti, Markus Pfaff, Richard Hagelauer +-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf +-- see page 4 +-- +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity CrossDomainSyncGen is +Port ( + reset : in STD_LOGIC; + ClockS : in STD_LOGIC; + ClockF : in STD_LOGIC; + SyncSignal : out STD_LOGIC +); +end CrossDomainSyncGen; + +architecture AR_CrossDomainSyncGen of CrossDomainSyncGen is + +signal FFSYNC : std_logic_vector(2 downto 0); + +begin + +SyncSignal <= FFSYNC(2); + +process(reset,ClockF) +begin +if reset = '0' then + FFSYNC <= (others => '0'); +elsif ClockF'event and ClockF = '1' then + FFSYNC(0) <= ClockS; + FFSYNC(1) <= FFSYNC(0); + FFSYNC(2) <= FFSYNC(1); +end if; +end process; + +end AR_CrossDomainSyncGen; + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/DC_ACQ_TOP.vhd @@ -0,0 +1,343 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; + +use work.config.all; + + +entity DC_ACQ_TOP is +generic( + WordSize : integer := 8; + WordCnt : integer := 144; + MinFCount : integer := 64; + EnableSR : integer := 1; + CstDATA : integer := 0; + FakeADC : integer := 0; + CDS : integer := 0 +); +port( + + reset : in std_logic; + clk : in std_logic; + SyncSig : in STD_LOGIC; + minorF : in std_logic; + majorF : in std_logic; + sclk : in std_logic; + WordClk : in std_logic; + + DC_ADC_Sclk : out std_logic; + DC_ADC_IN : in std_logic_vector(1 downto 0); + DC_ADC_ClkDiv : out std_logic; + DC_ADC_FSynch : out std_logic; + SET_RESET0 : out std_logic; + SET_RESET1 : out std_logic; + + AMR1X : out std_logic_vector(23 downto 0); + AMR1Y : out std_logic_vector(23 downto 0); + AMR1Z : out std_logic_vector(23 downto 0); + + AMR2X : out std_logic_vector(23 downto 0); + AMR2Y : out std_logic_vector(23 downto 0); + AMR2Z : out std_logic_vector(23 downto 0); + + AMR3X : out std_logic_vector(23 downto 0); + AMR3Y : out std_logic_vector(23 downto 0); + AMR3Z : out std_logic_vector(23 downto 0); + + AMR4X : out std_logic_vector(23 downto 0); + AMR4Y : out std_logic_vector(23 downto 0); + AMR4Z : out std_logic_vector(23 downto 0); + + Temp1 : out std_logic_vector(23 downto 0); + Temp2 : out std_logic_vector(23 downto 0); + Temp3 : out std_logic_vector(23 downto 0); + Temp4 : out std_logic_vector(23 downto 0) +); +end DC_ACQ_TOP; + +architecture Behavioral of DC_ACQ_TOP is + +signal DC_ADC_SmplClk : std_logic; +signal LF_ADC_SmplClk : std_logic; +signal SET_RESET0_sig : std_logic; +signal SET_RESET1_sig : std_logic; +signal SET_RESET_counter : integer range 0 to 31:=0; + +signal AMR1X_Sync : std_logic_vector(23 downto 0); +signal AMR1Y_Sync : std_logic_vector(23 downto 0); +signal AMR1Z_Sync : std_logic_vector(23 downto 0); + +signal AMR2X_Sync : std_logic_vector(23 downto 0); +signal AMR2Y_Sync : std_logic_vector(23 downto 0); +signal AMR2Z_Sync : std_logic_vector(23 downto 0); + +signal AMR3X_Sync : std_logic_vector(23 downto 0); +signal AMR3Y_Sync : std_logic_vector(23 downto 0); +signal AMR3Z_Sync : std_logic_vector(23 downto 0); + +signal AMR4X_Sync : std_logic_vector(23 downto 0); +signal AMR4Y_Sync : std_logic_vector(23 downto 0); +signal AMR4Z_Sync : std_logic_vector(23 downto 0); + +signal Temp1_Sync : std_logic_vector(23 downto 0); +signal Temp2_Sync : std_logic_vector(23 downto 0); +signal Temp3_Sync : std_logic_vector(23 downto 0); +signal Temp4_Sync : std_logic_vector(23 downto 0); + +begin + +------------------------------------------------------------------ +-- +-- DC sampling clock generation +-- +------------------------------------------------------------------ + + +DC_SMPL_CLK0 : entity work.LF_SMPL_CLK +--generic map(36) +generic map(288) +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => DC_ADC_SmplClk +); +------------------------------------------------------------------ + + + + +------------------------------------------------------------------ +-- +-- DC ADC +-- +------------------------------------------------------------------ +ADC1: IF CstDATA /= 1 GENERATE + ADC : IF FakeADC /=1 GENERATE + + DC_ADC0 : DUAL_ADS1278_DRIVER + port map( + Clk => clk, + reset => reset, + SpiClk => DC_ADC_Sclk, + DIN => DC_ADC_IN, + SmplClk => DC_ADC_SmplClk, + OUT00 => AMR1X_Sync, + OUT01 => AMR1Y_Sync, + OUT02 => AMR1Z_Sync, + OUT03 => AMR2X_Sync, + OUT04 => AMR2Y_Sync, + OUT05 => AMR2Z_Sync, + OUT06 => Temp1_Sync, + OUT07 => Temp2_Sync, + OUT10 => AMR3X_Sync, + OUT11 => AMR3Y_Sync, + OUT12 => AMR3Z_Sync, + OUT13 => AMR4X_Sync, + OUT14 => AMR4Y_Sync, + OUT15 => AMR4Z_Sync, + OUT16 => Temp3_Sync, + OUT17 => Temp4_Sync, + FSynch => DC_ADC_FSynch + ); + END GENERATE; + + NOADC: IF FakeADC=1 GENERATE + + DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER + port map( + Clk => clk, + reset => reset, + SpiClk => DC_ADC_Sclk, + DIN => DC_ADC_IN, + SmplClk => DC_ADC_SmplClk, + OUT00 => AMR1X_Sync, + OUT01 => AMR1Y_Sync, + OUT02 => AMR1Z_Sync, + OUT03 => AMR2X_Sync, + OUT04 => AMR2Y_Sync, + OUT05 => AMR2Z_Sync, + OUT06 => Temp1_Sync, + OUT07 => Temp2_Sync, + OUT10 => AMR3X_Sync, + OUT11 => AMR3Y_Sync, + OUT12 => AMR3Z_Sync, + OUT13 => AMR4X_Sync, + OUT14 => AMR4Y_Sync, + OUT15 => AMR4Z_Sync, + OUT16 => Temp3_Sync, + OUT17 => Temp4_Sync, + FSynch => DC_ADC_FSynch + ); + END GENERATE; + +END GENERATE; +------------------------------------------------------------------ + +NOADC: IF CstDATA = 1 GENERATE + +AMR1X_Sync <= AMR1Xcst; +AMR1Y_Sync <= AMR1Ycst; +AMR1Z_Sync <= AMR1Zcst; +AMR2X_Sync <= AMR2Xcst; +AMR2Y_Sync <= AMR2Ycst; +AMR2Z_Sync <= AMR2Zcst; +Temp1_Sync <= Temp1cst; +Temp2_Sync <= Temp2cst; +AMR3X_Sync <= AMR3Xcst; +AMR3Y_Sync <= AMR3Ycst; +AMR3Z_Sync <= AMR3Zcst; +AMR4X_Sync <= AMR4Xcst; +AMR4Y_Sync <= AMR4Ycst; +AMR4Z_Sync <= AMR4Zcst; +Temp3_Sync <= Temp3cst; +Temp4_Sync <= Temp4cst; + + + + + +END GENERATE; + + + + +------------------------------------------------------------------ +-- +-- SET/RESET GEN +-- +------------------------------------------------------------------ + +SR: IF EnableSR /=0 GENERATE +process(reset,DC_ADC_SmplClk) +begin + if reset = '0' then + SET_RESET0_sig <= '0'; + elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then + if(SET_RESET_counter = 31) then + SET_RESET0_sig <= not SET_RESET0_sig; + SET_RESET_counter <= 0; + else + SET_RESET_counter <= SET_RESET_counter +1; + end if; + end if; +end process; + +END GENERATE; +NOSR: IF EnableSR=0 GENERATE + SET_RESET0_sig <= '0'; +END GENERATE; + +SET_RESET1_sig <= SET_RESET0_sig; +SET_RESET0 <= SET_RESET0_sig; +SET_RESET1 <= SET_RESET1_sig; +------------------------------------------------------------------ +------------------------------------------------------------------ + + +------------------------------------------------------------------ +-- +-- Cross domain clock synchronisation +-- +------------------------------------------------------------------ + +IF CDS =1 GENERATE + +AMR1Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X); +AMR1Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y); +AMR1Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z); + +AMR2Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X); +AMR2Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y); +AMR2Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z); + +AMR3Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X); +AMR3Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y); +AMR3Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z); + + +AMR4Xsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X); +AMR4Ysync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y); +AMR4Zsync: entity work.Fast2SlowSync +generic map(N => 24) +port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z); + + +TEMP1sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1); +TEMP2sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2); +TEMP3sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3); +TEMP4sync: entity work.Fast2SlowSync +generic map(N => 24) +port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4); + +END GENERATE; + +IF CDS /= 1 GENERATE + + +AMR1X_Sync <= AMR1X; +AMR1Y_Sync <= AMR1Y; +AMR1Z_Sync <= AMR1Z; +AMR2X_Sync <= AMR2X; +AMR2Y_Sync <= AMR2Y; +AMR2Z_Sync <= AMR2Z; +Temp1_Sync <= Temp1; +Temp2_Sync <= Temp2; +AMR3X_Sync <= AMR3X; +AMR3Y_Sync <= AMR3Y; +AMR3Z_Sync <= AMR3Z; +AMR4X_Sync <= AMR4X; +AMR4Y_Sync <= AMR4Y; +AMR4Z_Sync <= AMR4Z; +Temp3_Sync <= Temp3; +Temp4_Sync <= Temp4; + +END GENERATE; +------------------------------------------------------------------ + + +end Behavioral; + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/Data.vhd b/designs/ICI4-Integ1/ICI4HDL/Data.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Data.vhd +++ /dev/null @@ -1,60 +0,0 @@ --- Data.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -use work.Convertisseur_config.all; - -entity Data is - -port( - clk,raz : in std_logic; - ADS_HF_In : in IN_ADS; - ADS_LF_In : in IN_ADS; - sclk : out std_logic; - ADS_HF_config : out ADS_config; - ADS_LF_config : out ADS_config; - ADS_HF_out : out OUT_ADS; - ADS_LF_out : out OUT_ADS; - Bit_fin_HF,Bit_fin_LF : out std_logic; - Vector_HF1,Vector_HF2,Vector_HF3 : out std_logic_vector(15 downto 0)); - -end Data; - -architecture ar_Data of Data is - -constant ADS_HF_c : ADS_config :=('1','1',FSYNC_FORMAT,MODE_low_power); -constant ADS_LF_c : ADS_config :=('1','1',FSYNC_FORMAT,MODE_low_speed); - -signal Vect_1 : std_logic_vector(23 downto 0); -signal Vect_2 : std_logic_vector(23 downto 0); -signal Vect_3 : std_logic_vector(23 downto 0); -signal sclk_int : std_logic; - -begin - -Clock_systeme : entity work.Sys_Clock - generic map (nb_compteur_sclk) - port map (clk,raz,sclk_int); - - -Data_LF : entity work.Vectorize - port map (clk,raz,sclk_int,ADS_LF_In.RDY,ADS_LF_In.Data_in(1),ADS_LF_In.Data_in(2),ADS_LF_In.Data_in(3),Bit_fin_LF,ADS_LF_out.Vector_out(1),ADS_LF_out.Vector_out(2),ADS_LF_out.Vector_out(3)); - -Data_HF : entity work.Vectorize - port map (clk,raz,sclk_int,ADS_HF_In.RDY,ADS_HF_In.Data_in(1),ADS_HF_In.Data_in(2),ADS_HF_In.Data_in(3),Bit_fin_HF,Vect_1,Vect_2,Vect_3); - - -ADS_HF_config <= ADS_HF_c; -ADS_LF_config <= ADS_LF_c; - -ADS_HF_out.Vector_out(1) <= Vect_1; -ADS_HF_out.Vector_out(2) <= Vect_2; -ADS_HF_out.Vector_out(3) <= Vect_3; - -Vector_HF1 <= Vect_1(23 downto 8); -Vector_HF2 <= Vect_2(23 downto 8); -Vector_HF3 <= Vect_3(23 downto 8); - -sclk <= sclk_int; - -end ar_Data; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/FAKE_ADC.vhd b/designs/ICI4-Integ1/ICI4HDL/FAKE_ADC.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/FAKE_ADC.vhd @@ -0,0 +1,243 @@ +-- ADS1274_DRIVER.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.general_purpose.all; + + + + + +entity FAKE_DUAL_ADS1278_DRIVER is +generic +( + SCLKDIV : integer range 2 to 256 :=16 +); +port( + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(1 downto 0); + SmplClk : in std_logic; + OUT00 : out std_logic_vector(23 downto 0); + OUT01 : out std_logic_vector(23 downto 0); + OUT02 : out std_logic_vector(23 downto 0); + OUT03 : out std_logic_vector(23 downto 0); + OUT04 : out std_logic_vector(23 downto 0); + OUT05 : out std_logic_vector(23 downto 0); + OUT06 : out std_logic_vector(23 downto 0); + OUT07 : out std_logic_vector(23 downto 0); + OUT10 : out std_logic_vector(23 downto 0); + OUT11 : out std_logic_vector(23 downto 0); + OUT12 : out std_logic_vector(23 downto 0); + OUT13 : out std_logic_vector(23 downto 0); + OUT14 : out std_logic_vector(23 downto 0); + OUT15 : out std_logic_vector(23 downto 0); + OUT16 : out std_logic_vector(23 downto 0); + OUT17 : out std_logic_vector(23 downto 0); + FSynch : out std_logic +); +end FAKE_DUAL_ADS1278_DRIVER; + + + + + + +architecture ar_FAKE_DUAL_ADS1278_DRIVER of FAKE_DUAL_ADS1278_DRIVER is +signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0); +signal ShiftGeg20,ShiftGeg21 : std_logic_vector((8*24)-1 downto 0); +signal SmplClk_Reg : std_logic:= '0'; +signal N : integer range 0 to (24*8) := 0; +signal SPI_CLk : std_logic; +signal SmplClk_clkd : std_logic:= '0'; +signal OUT00_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT01_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT02_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT03_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT04_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT05_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT06_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT07_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT10_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT11_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT12_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT13_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT14_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT15_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT16_r : std_logic_vector(23 downto 0) := (others => '0'); +signal OUT17_r : std_logic_vector(23 downto 0) := (others => '0'); + +begin + + +CLKDIV0 : Clk_Divider2 +generic map(SCLKDIV) +port map(Clk,SPI_CLk); + + +FSynch <= SmplClk; +SpiClk <= SPI_CLk; + +process(reset,SPI_CLk) +begin + + if reset = '0' then + ShiftGeg0 <= (others => '0'); + ShiftGeg1 <= (others => '0'); + N <= 0; + OUT00_r <= (others => '0'); + OUT01_r <= (others => '0'); + OUT02_r <= (others => '0'); + OUT03_r <= (others => '0'); + OUT04_r <= (others => '0'); + OUT05_r <= (others => '0'); + OUT06_r <= (others => '0'); + OUT07_r <= (others => '0'); + OUT10_r <= (others => '0'); + OUT11_r <= (others => '0'); + OUT12_r <= (others => '0'); + OUT13_r <= (others => '0'); + OUT14_r <= (others => '0'); + OUT15_r <= (others => '0'); + OUT16_r <= (others => '0'); + OUT17_r <= (others => '0'); + ShiftGeg20 <= (others => '0'); + ShiftGeg21 <= (others => '0'); + + elsif SPI_CLk'event and SPI_CLk = '1' then + if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then + ShiftGeg20((8*24)-1 downto 0) <= ShiftGeg20((8*24)-2 downto 0) & '0'; + ShiftGeg21((8*24)-1 downto 0) <= ShiftGeg21((8*24)-2 downto 0) & '0'; + ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & ShiftGeg20((8*24)-1); + ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & ShiftGeg21((8*24)-1); + if N = ((24*8)-1) then + N <= 0; + OUT00_r <= std_logic_vector(UNSIGNED(OUT00_r) + 1); + OUT01_r <= std_logic_vector(UNSIGNED(OUT01_r) + 2); + OUT02_r <= std_logic_vector(UNSIGNED(OUT02_r) + 3); + OUT03_r <= std_logic_vector(UNSIGNED(OUT03_r) + 4); + OUT04_r <= std_logic_vector(UNSIGNED(OUT04_r) + 5); + OUT05_r <= std_logic_vector(UNSIGNED(OUT05_r) + 6); + OUT06_r <= std_logic_vector(UNSIGNED(OUT06_r) + 7); + OUT07_r <= std_logic_vector(UNSIGNED(OUT07_r) + 8); + OUT10_r <= std_logic_vector(UNSIGNED(OUT10_r) + 9); + OUT11_r <= std_logic_vector(UNSIGNED(OUT11_r) + 10); + OUT12_r <= std_logic_vector(UNSIGNED(OUT12_r) + 11); + OUT13_r <= std_logic_vector(UNSIGNED(OUT13_r) + 12); + OUT14_r <= std_logic_vector(UNSIGNED(OUT14_r) + 13); + OUT15_r <= std_logic_vector(UNSIGNED(OUT15_r) + 14); + OUT16_r <= std_logic_vector(UNSIGNED(OUT16_r) + 15); + OUT17_r <= std_logic_vector(UNSIGNED(OUT17_r) + 16); + + ShiftGeg20((24*1)-1 downto (24*(1-1))) <= OUT00_r; + ShiftGeg20((24*2)-1 downto (24*(2-1))) <= OUT01_r; + ShiftGeg20((24*3)-1 downto (24*(3-1))) <= OUT02_r; + ShiftGeg20((24*4)-1 downto (24*(4-1))) <= OUT03_r; + ShiftGeg20((24*5)-1 downto (24*(5-1))) <= OUT04_r; + ShiftGeg20((24*6)-1 downto (24*(6-1))) <= OUT05_r; + ShiftGeg20((24*7)-1 downto (24*(7-1))) <= OUT06_r; + ShiftGeg20((24*8)-1 downto (24*(8-1))) <= OUT07_r; + + ShiftGeg21((24*1)-1 downto (24*(1-1))) <= OUT10_r; + ShiftGeg21((24*2)-1 downto (24*(2-1))) <= OUT11_r; + ShiftGeg21((24*3)-1 downto (24*(3-1))) <= OUT12_r; + ShiftGeg21((24*4)-1 downto (24*(4-1))) <= OUT13_r; + ShiftGeg21((24*5)-1 downto (24*(5-1))) <= OUT14_r; + ShiftGeg21((24*6)-1 downto (24*(6-1))) <= OUT15_r; + ShiftGeg21((24*7)-1 downto (24*(7-1))) <= OUT16_r; + ShiftGeg21((24*8)-1 downto (24*(8-1))) <= OUT17_r; + else + N <= N+1; + end if; + end if; + end if; +end process; + + +process(SPI_CLk) +begin + if SPI_CLk'event and SPI_CLk ='0' then + SmplClk_clkd <= SmplClk; + SmplClk_Reg <= SmplClk_clkd; + end if; +end process; + + +process(clk,reset) +begin + if reset = '0' then + OUT00 <= (others => '0'); + OUT01 <= (others => '0'); + OUT02 <= (others => '0'); + OUT03 <= (others => '0'); + OUT04 <= (others => '0'); + OUT05 <= (others => '0'); + OUT06 <= (others => '0'); + OUT07 <= (others => '0'); + + OUT10 <= (others => '0'); + OUT11 <= (others => '0'); + OUT12 <= (others => '0'); + OUT13 <= (others => '0'); + OUT14 <= (others => '0'); + OUT15 <= (others => '0'); + OUT16 <= (others => '0'); + OUT17 <= (others => '0'); + elsif clk'event and clk ='1' then + if N = 0 then + OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1))); + OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1))); + OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1))); + OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1))); + OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1))); + OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1))); + OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1))); + OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1))); + + OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1))); + OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1))); + OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1))); + OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1))); + OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1))); + OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1))); + OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1))); + OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1))); + + end if; + end if; +end process; + +end ar_FAKE_DUAL_ADS1278_DRIVER; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/Fast2SlowSync.vhd b/designs/ICI4-Integ1/ICI4HDL/Fast2SlowSync.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/Fast2SlowSync.vhd @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------ +-- +-- This module implements the Fast to Slow clock transfer: +-- Data Transfer between Asynchronous Clock Domains without Pain +-- from Markus Schutti, Markus Pfaff, Richard Hagelauer +-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf +-- see page 6 +-- +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Fast2SlowSync is +generic +( + N : integer range 0 to 256:=8 +); +Port +( + Data : in STD_LOGIC_VECTOR (N-1 downto 0); + ClockF : in STD_LOGIC; + ClockS : in STD_LOGIC; + SyncSignal : in STD_LOGIC; + DataSinkF : out STD_LOGIC_VECTOR (N-1 downto 0) +); +end Fast2SlowSync; + +architecture AR_Fast2SlowSync of Fast2SlowSync is + +signal DataF : STD_LOGIC_VECTOR (N-1 downto 0); +signal DataFlocked : STD_LOGIC_VECTOR (N-1 downto 0); + +signal MuxOut : STD_LOGIC_VECTOR (N-1 downto 0); + +begin + +MuxOut <= DataF when SyncSignal = '1' else + DataFlocked; + +process(ClockF) +begin + if ClockF'event and ClockF = '1' then + DataF <= Data; + DataFlocked <= MuxOut; + end if; +end process; + +process(ClockS) +begin + if ClockS'event and ClockS = '1' then + DataSinkF <= DataFlocked; + end if; +end process; + +end AR_Fast2SlowSync; + + + + + + + + + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/Gene_17K36.vhd b/designs/ICI4-Integ1/ICI4HDL/Gene_17K36.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Gene_17K36.vhd +++ /dev/null @@ -1,45 +0,0 @@ --- Gene_17K36.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity Gene_17K36 is - -port( - clk,raz : in std_logic; - Pulse : in std_logic; - Clock_17K36 : out std_logic); - -end Gene_17K36; - - -architecture ar_Gene_17K36 of Gene_17K36 is - -signal pulse_reg : std_logic; -signal clk_int : std_logic; -signal count : integer range 0 to 6; - -begin - process(clk, raz) - begin - if (raz='0')then - clk_int <= '0'; - pulse_reg <= '0'; - count <= 0; - - elsif (clk'event and clk='1') then - pulse_reg <= Pulse; - if(pulse_reg='0' and Pulse='1')then - if(count=5)then - count <= 0; - clk_int <= not clk_int; - else - count <= count + 1; - end if; - end if; - end if; - end process; - -Clock_17K36 <= clk_int; - -end ar_Gene_17K36; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/Gene_1K4.vhd b/designs/ICI4-Integ1/ICI4HDL/Gene_1K4.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Gene_1K4.vhd +++ /dev/null @@ -1,45 +0,0 @@ --- Gene_1K4.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity Gene_1K4 is - -port( - clk,raz : in std_logic; - Minor_Frame : in std_logic; - Clock_1K4 : out std_logic); - -end Gene_1K4; - - -architecture ar_Gene_1K4 of Gene_1K4 is - -signal minor_reg : std_logic; -signal clk_int : std_logic; - -begin - process(clk, raz) - begin - if (raz='0')then - clk_int <= '0'; - minor_reg <= '0'; - - elsif (clk'event and clk='1') then - minor_reg <= Minor_Frame; - if(minor_reg='0' and Minor_Frame='1')then - clk_int <= not clk_int; - end if; - end if; - end process; - -Clock_1K4 <= clk_int; - -end ar_Gene_1K4; - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/Gene_Freq.vhd b/designs/ICI4-Integ1/ICI4HDL/Gene_Freq.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Gene_Freq.vhd +++ /dev/null @@ -1,37 +0,0 @@ --- Gene_Freq.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity Gene_Freq is - -generic(nb_mots : integer :=144); - -port( - clk,raz : in std_logic; - Minor_Frame : in std_logic; - Compt_mots : in integer range 0 to nb_mots; - Clock_1k4 : out std_logic; - Clock_17K36 : out std_logic); - -end Gene_Freq; - -architecture ar_Gene_Freq of Gene_Freq is - -signal Pulse_mot : std_logic; - -begin - -Gene_LF : entity work.Gene_1K4 - port map (clk,raz,Minor_Frame,Clock_1K4); - - -Gene_HF : entity work.Gene_17K36 - port map(clk,raz,Pulse_mot,Clock_17K36); - - -Pulsing : entity work.integer_to_clk - generic map(nb_mots) - port map(clk,raz,Compt_mots,Pulse_mot); - -end ar_Gene_Freq; diff --git a/designs/ICI4-Integ1/ICI4HDL/IC4_OLD_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/IC4_OLD_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/IC4_OLD_TOP.vhd @@ -0,0 +1,443 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; +library grlib, techmap; +use grlib.amba.all; +use grlib.amba.all; +use grlib.stdlib.all; +use techmap.gencomp.all; +use techmap.allclkgen.all; +library gaisler; +use gaisler.memctrl.all; +use gaisler.leon3.all; +use gaisler.uart.all; +use gaisler.misc.all; +--use gaisler.sim.all; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; + + +use work.Convertisseur_config.all; + + +use work.config.all; +--================================================================== +-- +-- +-- FPGA FREQ = 48MHz +-- ADC Oscillator frequency = 4MHz +-- +-- +--================================================================== + +entity ici4_OLD is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; +WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64 + ); + port ( + reset : in std_ulogic; + clk : in std_ulogic; + sclk : in std_logic; + Gate : in std_logic; + MinF : in std_logic; + MajF : in std_logic; + Data : out std_logic; + DC_ADC_Sclk : out std_logic; + DC_ADC_IN : in std_logic_vector(1 downto 0); + DC_ADC_ClkDiv : out std_logic; + DC_ADC_FSynch : out std_logic; + SET_RESET0 : out std_logic; + SET_RESET1 : out std_logic; + LED : out std_logic + ); +end; + +architecture rtl of ici4_OLD is + +signal clk_buf,reset_buf : std_logic; + +Constant FramePlacerCount : integer := 2; + +signal MinF_Inv : std_logic; +signal Gate_Inv : std_logic; +signal sclk_Inv : std_logic; +signal WordCount : integer range 0 to WordCnt-1; +signal WordClk : std_logic; + +signal data_int : std_logic; + +signal MuxOUT : std_logic_vector(WordSize-1 downto 0); +signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); +signal Sel : integer range 0 to 1; + +signal AMR1X : std_logic_vector(23 downto 0); +signal AMR1Y : std_logic_vector(23 downto 0); +signal AMR1Z : std_logic_vector(23 downto 0); + +signal AMR2X : std_logic_vector(23 downto 0); +signal AMR2Y : std_logic_vector(23 downto 0); +signal AMR2Z : std_logic_vector(23 downto 0); + +signal AMR3X : std_logic_vector(23 downto 0); +signal AMR3Y : std_logic_vector(23 downto 0); +signal AMR3Z : std_logic_vector(23 downto 0); + +signal AMR4X : std_logic_vector(23 downto 0); +signal AMR4Y : std_logic_vector(23 downto 0); +signal AMR4Z : std_logic_vector(23 downto 0); + +signal AMR1X_ADC : std_logic_vector(23 downto 0); +signal AMR1Y_ADC : std_logic_vector(23 downto 0); +signal AMR1Z_ADC : std_logic_vector(23 downto 0); + +signal AMR2X_ADC : std_logic_vector(23 downto 0); +signal AMR2Y_ADC : std_logic_vector(23 downto 0); +signal AMR2Z_ADC : std_logic_vector(23 downto 0); + +signal AMR3X_ADC : std_logic_vector(23 downto 0); +signal AMR3Y_ADC : std_logic_vector(23 downto 0); +signal AMR3Z_ADC : std_logic_vector(23 downto 0); + +signal AMR4X_ADC : std_logic_vector(23 downto 0); +signal AMR4Y_ADC : std_logic_vector(23 downto 0); +signal AMR4Z_ADC : std_logic_vector(23 downto 0); + +signal AMR1X_R : std_logic_vector(23 downto 0); +signal AMR1Y_R : std_logic_vector(23 downto 0); +signal AMR1Z_R : std_logic_vector(23 downto 0); + +signal AMR2X_R : std_logic_vector(23 downto 0); +signal AMR2Y_R : std_logic_vector(23 downto 0); +signal AMR2Z_R : std_logic_vector(23 downto 0); + +signal AMR3X_R : std_logic_vector(23 downto 0); +signal AMR3Y_R : std_logic_vector(23 downto 0); +signal AMR3Z_R : std_logic_vector(23 downto 0); + +signal AMR4X_R : std_logic_vector(23 downto 0); +signal AMR4Y_R : std_logic_vector(23 downto 0); +signal AMR4Z_R : std_logic_vector(23 downto 0); + +signal AMR1X_S : std_logic_vector(23 downto 0); +signal AMR1Y_S : std_logic_vector(23 downto 0); +signal AMR1Z_S : std_logic_vector(23 downto 0); + +signal AMR2X_S : std_logic_vector(23 downto 0); +signal AMR2Y_S : std_logic_vector(23 downto 0); +signal AMR2Z_S : std_logic_vector(23 downto 0); + +signal AMR3X_S : std_logic_vector(23 downto 0); +signal AMR3Y_S : std_logic_vector(23 downto 0); +signal AMR3Z_S : std_logic_vector(23 downto 0); + +signal AMR4X_S : std_logic_vector(23 downto 0); +signal AMR4Y_S : std_logic_vector(23 downto 0); +signal AMR4Z_s : std_logic_vector(23 downto 0); + + + +signal Temp1 : std_logic_vector(23 downto 0); +signal Temp2 : std_logic_vector(23 downto 0); +signal Temp3 : std_logic_vector(23 downto 0); +signal Temp4 : std_logic_vector(23 downto 0); + + +signal LF1 : std_logic_vector(15 downto 0); +signal LF2 : std_logic_vector(15 downto 0); +signal LF3 : std_logic_vector(15 downto 0); + + +signal LF1_int : std_logic_vector(23 downto 0); +signal LF2_int : std_logic_vector(23 downto 0); +signal LF3_int : std_logic_vector(23 downto 0); + +signal DC_ADC_SmplClk : std_logic; +signal LF_ADC_SmplClk : std_logic; +signal SET_RESET0_sig : std_logic; +signal SET_RESET1_sig : std_logic; +signal SET_RESET_counter : integer range 0 to 31:=0; + +signal MinFCnt : integer range 0 to MinFCount-1; + +signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); + +begin + + +clk_buf <= clk; +reset_buf <= reset; +-- + +Gate_Inv <= not Gate; +sclk_Inv <= not Sclk; +MinF_Inv <= not MinF; + +LED <= not data_int; +data <= data_int; + + + +SD0 : Serial_Driver +generic map(WordSize) +port map(sclk_Inv,MuxOUT,Gate_inv,data_int); + +WC0 : Word_Cntr +generic map(WordSize,WordCnt) +port map(sclk_Inv,MinF,WordClk,WordCount); + +MFC0 : MinF_Cntr +generic map(MinFCount) +port map( + clk => MinF_Inv, + reset => MajF, + Cnt_out => MinFCnt +); + + +MUX0 : Serial_Driver_Multiplexor +generic map(FramePlacerCount,WordSize) +port map(sclk_Inv,Sel,MuxIN,MuxOUT); + + +DCFP0 : entity work.DC_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + MinFCnt => MinFCnt, + Flag => FramePlacerFlags(0), + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4, + WordOut => MuxIN(7 downto 0)); + + + +LFP0 : entity work.LF_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + Flag => FramePlacerFlags(1), + LF1 => LF1, + LF2 => LF2, + LF3 => LF3, + WordOut => MuxIN(15 downto 8)); + + + +DC_SMPL_CLK0 : entity work.LF_SMPL_CLK +generic map(36) +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => DC_ADC_SmplClk); + +process(reset,DC_ADC_SmplClk) +begin +if reset = '0' then + SET_RESET0_sig <= '0'; +elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then + if(SET_RESET_counter = 31) then + SET_RESET0_sig <= not SET_RESET0_sig; + SET_RESET_counter <= 0; + else + SET_RESET_counter <= SET_RESET_counter +1; + end if; +end if; +end process; + +SET_RESET1_sig <= SET_RESET0_sig; +SET_RESET0 <= SET_RESET0_sig; +SET_RESET1 <= SET_RESET1_sig; +-- + + + +send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE + DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin + port map( + Clk => clk_buf, + reset => reset_buf, + SpiClk => DC_ADC_Sclk, + DIN => DC_ADC_IN, + SmplClk => DC_ADC_SmplClk, + OUT00 => AMR1X, + OUT01 => AMR1Y, + OUT02 => AMR1Z, + OUT03 => AMR2X, + OUT04 => AMR2Y, + OUT05 => AMR2Z, + OUT06 => Temp1, + OUT07 => Temp2, + OUT10 => AMR3X, + OUT11 => AMR3Y, + OUT12 => AMR3Z, + OUT13 => AMR4X, + OUT14 => AMR4Y, + OUT15 => AMR4Z, + OUT16 => Temp3, + OUT17 => Temp4, + FSynch => DC_ADC_FSynch + ); + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + END GENERATE; + +send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE + AMR1X <= AMR1Xcst; + AMR1Y <= AMR1Ycst; + AMR1Z <= AMR1Zcst; + AMR2X <= AMR2Xcst; + AMR2Y <= AMR2Ycst; + AMR2Z <= AMR2Zcst; + Temp1 <= Temp1cst; + Temp2 <= Temp2cst; + AMR3X <= AMR3Xcst; + AMR3Y <= AMR3Ycst; + AMR3Z <= AMR3Zcst; + AMR4X <= AMR4Xcst; + AMR4Y <= AMR4Ycst; + AMR4Z <= AMR4Zcst; + Temp3 <= Temp3cst; + Temp4 <= Temp4cst; + + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + END GENERATE; + + + + +send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE + AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); + + LF1 <= LF1cst; + LF2 <= LF2cst; + LF3 <= LF3cst; + END GENERATE; + +LF_SMPL_CLK0 : entity work.LF_SMPL_CLK +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => LF_ADC_SmplClk +); + + +sr_hndl: IF SEND_CONSTANT_DATA = 0 GENERATE +process(clk) +begin + if clk'event and clk ='1' then + if SET_RESET0_sig = '1' then + AMR1X_S <= AMR1X_ADC; + AMR1Y_S <= AMR1Y_ADC; + AMR1Z_S <= AMR1Z_ADC; + AMR2X_S <= AMR2X_ADC; + AMR2Y_S <= AMR2Y_ADC; + AMR2Z_S <= AMR2Z_ADC; + AMR3X_S <= AMR3X_ADC; + AMR3Y_S <= AMR3Y_ADC; + AMR3Z_S <= AMR3Z_ADC; + AMR4X_S <= AMR4X_ADC; + AMR4Y_S <= AMR4Y_ADC; + AMR4Z_S <= AMR4Z_ADC; + else + AMR1X_R <= AMR1X_ADC; + AMR1Y_R <= AMR1Y_ADC; + AMR1Z_R <= AMR1Z_ADC; + AMR2X_R <= AMR2X_ADC; + AMR2Y_R <= AMR2Y_ADC; + AMR2Z_R <= AMR2Z_ADC; + AMR3X_R <= AMR3X_ADC; + AMR3Y_R <= AMR3Y_ADC; + AMR3Z_R <= AMR3Z_ADC; + AMR4X_R <= AMR4X_ADC; + AMR4Y_R <= AMR4Y_ADC; + AMR4Z_R <= AMR4Z_ADC; + end if; +-- AMR1X <= std_logic_vector((signed(AMR1X_S) - signed(AMR1X_R))/2); +-- AMR1Y <= std_logic_vector((signed(AMR1Y_S) - signed(AMR1Y_R))/2); +-- AMR1Z <= std_logic_vector((signed(AMR1Z_S) - signed(AMR1Z_R))/2); +-- AMR2X <= std_logic_vector((signed(AMR2X_S) - signed(AMR2X_R))/2); +-- AMR2Y <= std_logic_vector((signed(AMR2Y_S) - signed(AMR2Y_R))/2); +-- AMR2Z <= std_logic_vector((signed(AMR2Z_S) - signed(AMR2Z_R))/2); +-- AMR3X <= std_logic_vector((signed(AMR3X_S) - signed(AMR3X_R))/2); +-- AMR3Y <= std_logic_vector((signed(AMR3Y_S) - signed(AMR3Y_R))/2); +-- AMR3Z <= std_logic_vector((signed(AMR3Z_S) - signed(AMR3Z_R))/2); +-- AMR4X <= std_logic_vector((signed(AMR4X_S) - signed(AMR4X_R))/2); +-- AMR4Y <= std_logic_vector((signed(AMR4Y_S) - signed(AMR4Y_R))/2); +-- AMR4Z <= std_logic_vector((signed(AMR4Z_S) - signed(AMR4Z_R))/2); +-- AMR1X <= AMR1X_S; +-- AMR1Y <= AMR1Y_S; +-- AMR1Z <= AMR1Z_S; +-- AMR2X <= AMR2X_S; +-- AMR2Y <= AMR2Y_S; +-- AMR2Z <= AMR2Z_S; +-- AMR3X <= AMR3X_S; +-- AMR3Y <= AMR3Y_S; +-- AMR3Z <= AMR3Z_S; +-- AMR4X <= AMR4X_S; +-- AMR4Y <= AMR4Y_S; +-- AMR4Z <= AMR4Z_S; + end if; +end process; +end generate; + + +process(clk) +variable SelVar : integer range 0 to 1; +begin + if clk'event and clk ='1' then + Decoder: FOR i IN 0 to FramePlacerCount-1 loop + if FramePlacerFlags(i) = '1' then + SelVar := i; + end if; + END loop Decoder; + Sel <= SelVar; + end if; +end process; + + +end rtl; + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/IIR_FILTER_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/IIR_FILTER_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/IIR_FILTER_TOP.vhd @@ -0,0 +1,143 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; +use lpp.iir_filter.all; +use work.config.all; + + +entity IIR_FILTER_TOP is +generic +( + V2 : integer :=0 -- IF 1 uses V2 else use V1 +); +port +( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + SMPclk : IN STD_LOGIC; + LF1_IN : IN std_logic_vector(15 downto 0); + LF2_IN : IN std_logic_vector(15 downto 0); + LF3_IN : IN std_logic_vector(15 downto 0); + + SMPCLKOut : OUT STD_LOGIC; + LF1_OUT : OUT std_logic_vector(15 downto 0); + LF2_OUT : OUT std_logic_vector(15 downto 0); + LF3_OUT : OUT std_logic_vector(15 downto 0) +); +end IIR_FILTER_TOP; + +architecture AR_IIR_FILTER_TOP of IIR_FILTER_TOP is +signal sps : Samples(2 DOWNTO 0); + +signal LFX : Samples(2 DOWNTO 0); +signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0); +signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0); +signal sample_out_val : std_logic; +signal LF_ADC_SpPulse : std_logic; + +begin + +sps(0) <= LF1_IN; +sps(1) <= LF2_IN; +sps(2) <= LF3_IN; + +LF1_OUT <= LFX(0); +LF2_OUT <= LFX(1); +LF3_OUT <= LFX(2); + +SMPCLKOut <= sample_out_val; + +loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE + + loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE + process(rstn,clk) + begin + if rstn ='0' then + Filter_sp_in(I,J) <= '0'; +-- LFX(I) <= (others => '0'); + elsif clk'event and clk ='1' then + if sample_out_val = '1' then + LFX(I)(J) <= Filter_sp_out(I,J); + Filter_sp_in(I,J) <= sps(I)(J); + end if; + end if; + end process; + END GENERATE; +END GENERATE; + +V2FILTER: IF V2 = 1 GENERATE + +smpPulse: entity work.OneShot + Port map( + reset => rstn, + clk => clk, + input => SMPclk, + output => LF_ADC_SpPulse +); + +FilterV2: IIR_CEL_CTRLR_v2 + GENERIC map( + tech => CFG_MEMTECH, + Mem_use => use_RAM, + Sample_SZ => Sample_SZ, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => 5, + ChanelsCount => ChanelsCount + ) + PORT map( + rstn => rstn, + clk => clk, + + virg_pos => virgPos, + coefs => CoefsInitValCst_v2, + + sample_in_val => LF_ADC_SpPulse, + sample_in => Filter_sp_in, + + sample_out_val => sample_out_val, + sample_out => Filter_sp_out +); + + + +END GENERATE; + +V1FILTER: IF V2 /= 1 GENERATE + +sample_out_val <= SMPclk; + + +FilterV1: IIR_CEL_CTRLR +generic map( + tech => CFG_MEMTECH, + Sample_SZ => Sample_SZ, + ChanelsCount => 3, + Coef_SZ => Coef_SZ, + CoefCntPerCel=> CoefCntPerCel, + Cels_count => Cels_count, + Mem_use => use_RAM +) +port map( + reset => rstn, + clk => clk, + sample_clk => SMPclk, + sample_in => Filter_sp_in, + sample_out => Filter_sp_out, + virg_pos => virgPos, + GOtest => open, + coefs => CoefsInitValCst +); + +END GENERATE; + + +end AR_IIR_FILTER_TOP; + diff --git a/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd b/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/LF_ACQ_TOP.vhd @@ -0,0 +1,215 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; +use lpp.iir_filter.all; +use work.config.all; + +entity LF_ACQ_TOP is +generic( + WordSize : integer := 8; + WordCnt : integer := 144; + MinFCount : integer := 64; + CstDATA : integer := 0; + IIRFilter : integer := 0 +); +port( + + reset : in std_logic; + clk : in std_logic; + SyncSig : in STD_LOGIC; + minorF : in std_logic; + majorF : in std_logic; + sclk : in std_logic; + WordClk : in std_logic; + LF_SCK : out std_logic; + LF_CNV : out std_logic; + LF_SDO1 : in std_logic; + LF_SDO2 : in std_logic; + LF_SDO3 : in std_logic; + LF1 : out std_logic_vector(15 downto 0); + LF2 : out std_logic_vector(15 downto 0); + LF3 : out std_logic_vector(15 downto 0) +); +end LF_ACQ_TOP; + +architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is + +signal LF_ADC_SmplClk : std_logic; + +signal LF_ADC_SpPulse : std_logic; +signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0); +signal sps : Samples(2 DOWNTO 0); + +signal LFX : Samples(2 DOWNTO 0); +signal sample_val : std_logic; +signal AD_in : AD7688_in(2 DOWNTO 0); +signal AD_out : AD7688_out; +signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0); +signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0); +signal sample_out_val : std_logic; + +signal LF1_sync : std_logic_vector(15 downto 0); +signal LF2_sync : std_logic_vector(15 downto 0); +signal LF3_sync : std_logic_vector(15 downto 0); + +begin + + +AD_in(0).sdi <= LF_SDO1; +AD_in(1).sdi <= LF_SDO2; +AD_in(2).sdi <= LF_SDO3; +LF_SCK <= AD_out.SCK; +LF_CNV <= AD_out.CNV; + + +LF_SMPL_CLK0 : entity work.LF_SMPL_CLK +generic map(6) +port map( + reset => reset, + wclk => WordClk, + SMPL_CLK => LF_ADC_SmplClk +); + + +ADC: IF CstDATA =0 GENERATE +ADCs: AD7688_drvr +GENERIC map +( + ChanelCount => 3, + clkkHz => 48000 +) +PORT map +( + clk => clk, + rstn => reset, + enable => '1', + smplClk => LF_ADC_SmplClk, + DataReady => sample_val, + smpout => sps, + AD_in => AD_in, + AD_out => AD_out +); + +smpPulse: entity work.OneShot + Port map( + reset => reset, + clk => clk, + input => LF_ADC_SmplClk, + output => LF_ADC_SpPulse +); + + + + +NOfilt: IF IIRFilter = 0 GENERATE + process(reset,clk) + begin + if reset ='0' then + LF1_sync <= (others => '0'); + LF2_sync <= (others => '0'); + LF3_sync <= (others => '0'); + elsif clk'event and clk ='1' then + if sample_val = '1' then + LF1_sync <= sps(0); + LF2_sync <= sps(1); + LF3_sync <= sps(2); + end if; + end if; + end process; + END GENERATE; + + +filt: IF IIRFilter /= 0 GENERATE + + +filtertop: entity work.IIR_FILTER_TOP +generic map +( + V2 => 0 +) +port map +( + rstn => reset, + clk => clk, + + SMPclk => LF_ADC_SmplClk, + LF1_IN => sps(0), + LF2_IN => sps(1), + LF3_IN => sps(2), + + SMPCLKOut => open, + LF1_OUT => LF1_sync, + LF2_OUT => LF2_sync, + LF3_OUT => LF3_sync +); + +END GENERATE; + + + + +END GENERATE; + +CST: IF CstDATA /=0 GENERATE + + LF1_sync <= LF1cst; + LF2_sync <= LF2cst; + LF3_sync <= LF3cst; + +END GENERATE; + + + +LF1sync: entity work.Fast2SlowSync +generic map(N => 16) +port map( LF1_sync,clk,sclk,SyncSig,LF1); + +LF2sync: entity work.Fast2SlowSync +generic map(N => 16) +port map( LF2_sync,clk,sclk,SyncSig,LF2); + +LF3sync: entity work.Fast2SlowSync +generic map(N => 16) +port map( LF3_sync,clk,sclk,SyncSig,LF3); + +--Filter: IIR_CEL_FILTER +-- GENERIC map( +-- tech => CFG_MEMTECH, +-- Sample_SZ => Sample_SZ, +-- ChanelsCount => ChanelsCount, +-- Coef_SZ => Coef_SZ, +-- CoefCntPerCel => CoefCntPerCel, +-- Cels_count => Cels_count, +-- Mem_use => use_RAM +-- ) +-- PORT map( +-- reset => reset, +-- clk => clk, +-- sample_clk => LF_ADC_SmplClk, +-- regs_in : IN in_IIR_CEL_reg; +-- regs_out : IN out_IIR_CEL_reg; +-- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); +-- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); +-- GOtest : OUT STD_LOGIC; +-- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0) +-- +-- ); + + + + +end AR_LF_ACQ_TOP; + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd b/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd --- a/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd +++ b/designs/ICI4-Integ1/ICI4HDL/LF_SMPL_CLK.vhd @@ -4,10 +4,11 @@ use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -entity LF_SMPL_CLK is +entity LF_SMPL_CLK is +generic(N : integer range 0 to 4096 :=24); port( - Wclck : in std_logic; - MinF : in std_logic; + reset : in std_logic; + wclk : in std_logic; SMPL_CLK : out std_logic ); end entity; @@ -19,24 +20,25 @@ end entity; architecture ar_LF_SMPL_CLK of LF_SMPL_CLK is -signal cpt : integer range 0 to 23 := 0; +signal cpt : integer range 0 to N-1 := 0; begin -process(Wclck,MinF) +process(reset,wclk) begin -if MinF = '0' then - SMPL_CLK <= '1'; -elsif Wclck'event and Wclck = '1' then - if cpt = 23 then +if reset = '0' then + SMPL_CLK <= '1'; + cpt <= 0; +elsif wclk'event and wclk = '1' then + if cpt = (N-1) then cpt <= 0; else cpt <= cpt+1; end if; if cpt = 0 then SMPL_CLK <= '1'; - elsif cpt = 10 then + elsif cpt = (N/2) then SMPL_CLK <= '0'; end if; end if; diff --git a/designs/ICI4-Integ1/ICI4HDL/MinF_Cntr.vhd b/designs/ICI4-Integ1/ICI4HDL/MinF_Cntr.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/MinF_Cntr.vhd +++ /dev/null @@ -1,68 +0,0 @@ --- MinF_Cntr.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - - - -entity MinF_Cntr is -generic(MinFCount : integer := 64); -port( - clk : in std_logic; - reset : in std_logic; - Cnt_out : out integer range 0 to MinFCount-1 -); -end entity; - - - -architecture ar_MinF_Cntr of MinF_Cntr is - -signal Cnt_int : integer range 0 to MinFCount-1 := 0; -signal MinF_reg : std_logic := '0'; - -begin - -Cnt_out <= Cnt_int; - -process(clk,reset) -begin - if reset = '0' then - Cnt_int <= 0; - elsif clk'event and clk = '1' then - if Cnt_int = MinFCount -1 then - Cnt_int <= 0; - else - Cnt_int <= Cnt_int + 1; - end if; - end if; -end process; -end ar_MinF_Cntr; - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/OneShot.vhd b/designs/ICI4-Integ1/ICI4HDL/OneShot.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/OneShot.vhd @@ -0,0 +1,67 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:06:46 08/22/2013 +-- Design Name: +-- Module Name: OneShot - AR_OneShot +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity OneShot is + Port ( reset : in STD_LOGIC; + clk : in STD_LOGIC; + input : in STD_LOGIC; + output : out STD_LOGIC); +end OneShot; + +architecture AR_OneShot of OneShot is +signal inreg : std_logic; +begin + +process(clk,reset) +begin +if reset = '0' then + output <= '0'; +elsif clk'event and clk = '1' then + inreg <= input; + if inreg = '0' and input = '1' then + output <= '1'; + else + output <= '0'; + end if; +end if; +end process; + +end AR_OneShot; + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver.vhd b/designs/ICI4-Integ1/ICI4HDL/Serial_Driver.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver.vhd +++ /dev/null @@ -1,44 +0,0 @@ --- Serial_Driver.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity Serial_Driver is -generic(size : integer :=8); -port( - sclk : in std_logic; - inputDat: in std_logic_vector(size-1 downto 0); - Gate : in std_logic; - Data : out std_logic -); -end Serial_Driver; - - - - -architecture ar_Serial_Driver of Serial_Driver is -signal Count : integer range 0 to size-1; -signal SR_internal : std_logic_vector(size-1 downto 0):=std_logic_vector(TO_UNSIGNED(165,Size)); -begin -process(sclk) -begin - if SCLK'event and SCLK = '1' then - if gate = '1' then - if Count = size-1 then - Count <= 0; - Data <= SR_internal(size-1); - SR_internal <= inputDat; - else - Count <= Count+1; - Data <= SR_internal(size-1); - SR_internal <= SR_internal(size-2 downto 0) & '0'; - end if; - else - SR_internal <= inputDat; - Data <= '0'; - Count <= 0; - end if; - end if; -end process; -end ar_Serial_Driver; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver_Multiplexor.vhd b/designs/ICI4-Integ1/ICI4HDL/Serial_Driver_Multiplexor.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver_Multiplexor.vhd +++ /dev/null @@ -1,33 +0,0 @@ --- Serial_Driver_Multiplexor.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - - -entity Serial_Driver_Multiplexor is -generic(InputCnt : integer := 2;inputSize : integer:=8); -port( - clk : in std_logic; - Sel : in integer range 0 to InputCnt-1; - input : in std_logic_vector(InputCnt*inputSize-1 downto 0); - output : out std_logic_vector(inputSize-1 downto 0) -); -end entity; - - - -architecture ar_Serial_Driver_Multiplexor of Serial_Driver_Multiplexor is -begin - - -process(clk) -begin -if clk'event and clk = '1' then - output <= input((Sel+1)*inputSize-1 downto (Sel)*inputSize); -end if; -end process; - - -end ar_Serial_Driver_Multiplexor; - diff --git a/designs/ICI4-Integ1/ICI4HDL/Simple_Counter.vhd b/designs/ICI4-Integ1/ICI4HDL/Simple_Counter.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Simple_Counter.vhd +++ /dev/null @@ -1,58 +0,0 @@ --- Simple_Counter.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity Simple_Counter is -generic(N : integer := 8); -port( - clk : in std_logic; - sclk : in std_logic; - Gate : in std_logic; - OV : out std_logic - -); -end entity; - - -architecture ar_Simple_Counter of Simple_Counter is -signal Count : integer range 0 to N-1; -signal Gate_Reg : std_logic:='0'; -signal sclk_Reg : std_logic := '0'; -begin - -process(clk) -begin - if clk'event and clk = '1' then - Gate_Reg <= Gate; - sclk_Reg <= sclk; - if Gate = '1' and Gate_reg = '0' then - Count <= 0; - else - if sclk = '1' and sclk_Reg = '0' then - if Count = N-1 then - Count <= 0; - else - Count <= Count+1; - end if; - end if; - end if; - end if; -end process; - - -OV <= '1' when Count = N-1 and sclk_Reg = '0' and sclk = '1' else '0'; - -end ar_Simple_Counter; - - - - - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/Slow2FastSync.vhd b/designs/ICI4-Integ1/ICI4HDL/Slow2FastSync.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/Slow2FastSync.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@member.fsf.org +------------------------------------------------------------------------------ +-- +-- This module implements the Slow to Slow Fast transfer: +-- Data Transfer between Asynchronous Clock Domains without Pain +-- from Markus Schutti, Markus Pfaff, Richard Hagelauer +-- http://www-micrel.deis.unibo.it/~benini/files/SNUG/paper9_final.pdf +-- see page 5 +-- +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Slow2FastSync is +generic +( + N : integer range 0 to 256:=8 +); +Port +( + Data : in STD_LOGIC_VECTOR (N-1 downto 0); + ClockF : in STD_LOGIC; + ClockS : in STD_LOGIC; + SyncSignal : in STD_LOGIC; + DataSinkS : out STD_LOGIC_VECTOR (N-1 downto 0) +); +end Slow2FastSync; + +architecture AR_Slow2FastSync of Slow2FastSync is + +signal DataS : STD_LOGIC_VECTOR (N-1 downto 0); + + +begin + + + +process(ClockF) +begin + if ClockF'event and ClockF = '1' and SyncSignal = '1' then + DataSinkS <= DataS; + end if; +end process; + +process(ClockS) +begin + if ClockS'event and ClockS = '1' then + DataS <= Data; + end if; +end process; + +end AR_Slow2FastSync; + + + + + + + + + + + + + + + + + + + diff --git a/designs/ICI4-Integ1/ICI4HDL/TM_MODULE.vhd b/designs/ICI4-Integ1/ICI4HDL/TM_MODULE.vhd new file mode 100644 --- /dev/null +++ b/designs/ICI4-Integ1/ICI4HDL/TM_MODULE.vhd @@ -0,0 +1,177 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:03:54 08/21/2013 +-- Design Name: +-- Module Name: TM_MODULE - AR_TM_MODULE +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.general_purpose.all; +use lpp.Rocket_PCM_Encoder.all; + +entity TM_MODULE is +generic( + WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64 +); +port( + + reset : in std_logic; + clk : in std_logic; + MinF : in std_logic; + MajF : in std_logic; + sclk : in std_logic; + gate : in std_logic; + data : out std_logic; + WordClk : out std_logic; + + + LF1 : in std_logic_vector(15 downto 0); + LF2 : in std_logic_vector(15 downto 0); + LF3 : in std_logic_vector(15 downto 0); + + AMR1X : in std_logic_vector(23 downto 0); + AMR1Y : in std_logic_vector(23 downto 0); + AMR1Z : in std_logic_vector(23 downto 0); + + AMR2X : in std_logic_vector(23 downto 0); + AMR2Y : in std_logic_vector(23 downto 0); + AMR2Z : in std_logic_vector(23 downto 0); + + AMR3X : in std_logic_vector(23 downto 0); + AMR3Y : in std_logic_vector(23 downto 0); + AMR3Z : in std_logic_vector(23 downto 0); + + AMR4X : in std_logic_vector(23 downto 0); + AMR4Y : in std_logic_vector(23 downto 0); + AMR4Z : in std_logic_vector(23 downto 0); + + Temp1 : in std_logic_vector(23 downto 0); + Temp2 : in std_logic_vector(23 downto 0); + Temp3 : in std_logic_vector(23 downto 0); + Temp4 : in std_logic_vector(23 downto 0) +); +end TM_MODULE; + +architecture AR_TM_MODULE of TM_MODULE is + +Constant FramePlacerCount : integer := 2; +signal MinFCnt : integer range 0 to MinFCount-1; +signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); + +signal WordCount : integer range 0 to WordCnt-1; + +signal data_int : std_logic; + +signal MuxOUT : std_logic_vector(WordSize-1 downto 0); +signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); +signal Sel : integer range 0 to 1; + + +signal MinF_Inv : std_logic; +signal Gate_Inv : std_logic; +signal sclk_Inv : std_logic; + +begin + + +Gate_Inv <= not Gate; +sclk_Inv <= not Sclk; +MinF_Inv <= not MinF; +data <= data_int; + +SD0 : Serial_Driver +generic map(WordSize) +port map(sclk_Inv,MuxOUT,Gate_inv,data_int); + +WC0 : Word_Cntr +generic map(WordSize,WordCnt) +port map(sclk_Inv,MinF,WordClk,WordCount); + +MFC0 : MinF_Cntr +generic map(MinFCount) +port map( + clk => MinF_Inv, + reset => MajF, + Cnt_out => MinFCnt +); + + +MUX0 : Serial_Driver_Multiplexor +generic map(FramePlacerCount,WordSize) +port map(sclk_Inv,Sel,MuxIN,MuxOUT); + + +DCFP0 : entity work.DC_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + MinFCnt => MinFCnt, + Flag => FramePlacerFlags(0), + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4, + WordOut => MuxIN(7 downto 0)); + + + +LFP0 : entity work.LF_FRAME_PLACER +generic map(WordSize,WordCnt,MinFCount) +port map( + clk => Sclk, + Wcount => WordCount, + Flag => FramePlacerFlags(1), + LF1 => LF1, + LF2 => LF2, + LF3 => LF3, + WordOut => MuxIN(15 downto 8)); + + + +process(clk) +variable SelVar : integer range 0 to 1; +begin + if clk'event and clk ='1' then + Decoder: FOR i IN 0 to FramePlacerCount-1 loop + if FramePlacerFlags(i) = '1' then + SelVar := i; + end if; + END loop Decoder; + Sel <= SelVar; + end if; +end process; + + + +end AR_TM_MODULE; + diff --git a/designs/ICI4-Integ1/ICI4HDL/TOP_ICI3_INTEG1.vhd b/designs/ICI4-Integ1/ICI4HDL/TOP_ICI3_INTEG1.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/TOP_ICI3_INTEG1.vhd +++ /dev/null @@ -1,293 +0,0 @@ --- TOP_ICI3_INTEG1.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; ---library igloo; ---use igloo.all; -use work.Convertisseur_config.all; - -entity TOP_ICI3_INTEG1 is -Generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64); -port( - clk : in std_logic; - reset : in std_logic; - sclk : in std_logic; - Gate : in std_logic; - MinF : in std_logic; - MajF : in std_logic; - Data : out std_logic; - DC_ADC_Sclk : out std_logic; - DC_ADC_IN : in std_logic_vector(3 downto 0); - DC_ADC_FORMAT : out std_logic_vector(2 downto 0); - DC_ADC_Mode : out std_logic_vector(1 downto 0); - DC_ADC_ClkDiv : out std_logic; - DC_ADC_PWDOWN : out std_logic_vector(3 downto 0); - DC_ADC_FSynch : out std_logic; - DC_ADC_Synch : out std_logic; --- DATA_out_Test : out std_logic; --- Sclk_out_test : out std_logic; --- Synch_out_test : out std_logic; - test : out std_logic; - - LF_ADC_Sclk : out std_logic; - LF_ADC_IN : in std_logic_vector(3 downto 0); - LF_ADC_FORMAT : out std_logic_vector(2 downto 0); - LF_ADC_Mode : out std_logic_vector(1 downto 0); - LF_ADC_ClkDiv : out std_logic; - LF_ADC_PWDOWN : out std_logic_vector(3 downto 0); - LF_ADC_FSynch : out std_logic; - LF_ADC_Synch : out std_logic - -); -end entity; - - - - -architecture ar_TOP_ICI3_INTEG1 of TOP_ICI3_INTEG1 is - --- component CLKINT --- port( A : in std_logic := 'U'; --- Y : out std_logic --- ); --- end component; - -signal clk_buf,reset_buf : std_logic; - -Constant FramePlacerCount : integer := 2; - -signal MinF_Inv : std_logic; -signal Gate_Inv : std_logic; -signal sclk_Inv : std_logic; -signal WordCount : integer range 0 to WordCnt-1; -signal WordClk : std_logic; - -signal MuxOUT : std_logic_vector(WordSize-1 downto 0); -signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); -signal Sel : integer range 0 to 1; - -signal DC1 : std_logic_vector(23 downto 0); -signal DC2 : std_logic_vector(23 downto 0); -signal DC3 : std_logic_vector(23 downto 0); - - - -signal LF1 : std_logic_vector(15 downto 0); -signal LF2 : std_logic_vector(15 downto 0); -signal LF3 : std_logic_vector(15 downto 0); - - -signal LF1_int : std_logic_vector(23 downto 0); -signal LF2_int : std_logic_vector(23 downto 0); -signal LF3_int : std_logic_vector(23 downto 0); - ---constant DC1cst : std_logic_vector(23 downto 0) := X"FA5961"; ---constant DC2cst : std_logic_vector(23 downto 0) := X"123456"; ---constant DC3cst : std_logic_vector(23 downto 0) := X"789012"; --- ---constant LF1cst : std_logic_vector(15 downto 0) := X"3210"; ---constant LF2cst : std_logic_vector(15 downto 0) := X"6543"; ---constant LF3cst : std_logic_vector(15 downto 0) := X"3456"; --- - -signal DC_ADC_SmplClk : std_logic; -signal LF_ADC_SmplClk : std_logic; - -signal MinFCnt : integer range 0 to MinFCount-1; - -signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); - -begin - ---CLKINT0 : CLKINT --- port map(clk,clk_buf); --- ---CLKINT1 : CLKINT --- port map(reset,reset_buf); - -clk_buf <= clk; -reset_buf <= reset; --- ---DATA_out_Test <= DC_ADC_IN(0); ---Sclk_out_test <= DC_ADC_Sclk; ---Synch_out_test <= DC_ADC_FSynch; - -Gate_Inv <= not Gate; -sclk_Inv <= not Sclk; -MinF_Inv <= not MinF; - ---DC1 <= DC1cst; ---DC2 <= DC2cst; ---DC3 <= DC3cst; - ---LF1 <= LF1cst; ---LF2 <= LF2cst; ---LF3 <= LF3cst; - -SD0 : entity work.Serial_Driver -generic map(WordSize) -port map(sclk_Inv,MuxOUT,Gate_inv,Data); - -WC0 : entity work.Word_Cntr -generic map(WordSize,WordCnt) -port map(sclk_Inv,MinF,WordClk,WordCount); - -MFC0 : entity work.MinF_Cntr -generic map(MinFCount) -port map( - clk => MinF_Inv, - reset => MajF, - Cnt_out => MinFCnt -); - - -MUX0 : entity work.Serial_Driver_Multiplexor -generic map(FramePlacerCount,WordSize) -port map(sclk_Inv,Sel,MuxIN,MuxOUT); - - -DCFP0 : entity work.DC_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - MinFCnt => MinFCnt, - Flag => FramePlacerFlags(0), - DC1 => DC1, - DC2 => DC2, - DC3 => DC3, - WordOut => MuxIN(7 downto 0)); - - - -LFP0 : entity work.LF_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - Flag => FramePlacerFlags(1), - LF1 => LF1, - LF2 => LF2, - LF3 => LF3, - WordOut => MuxIN(15 downto 8)); - - - -DC_SMPL_CLK0 : entity work.DC_SMPL_CLK -port map(MinF_Inv,DC_ADC_SmplClk); - - -DC_ADC_Synch <= reset; -LF_ADC_Synch <= reset; - -DC_ADC0 : entity work.ADS1274_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin -generic map(MODE_low_power,FSYNC_FORMAT) -port map( - Clk => clk_buf, - reset => reset_buf, - SpiClk => DC_ADC_Sclk, - DIN => DC_ADC_IN, - Ready => '0', - Format => DC_ADC_Format, - Mode => DC_ADC_Mode, - ClkDiv => DC_ADC_ClkDiv, - PWDOWN => DC_ADC_PWDOWN, - SmplClk => DC_ADC_SmplClk, - OUT0 => DC1, - OUT1 => DC2, - OUT2 => DC3, - OUT3 => open, - FSynch => DC_ADC_FSynch, - test => test -); - - -LF_SMPL_CLK0 : entity work.LF_SMPL_CLK -port map( - Wclck => WordClk, - MinF => MinF, - SMPL_CLK => LF_ADC_SmplClk -); - -LF_ADC0 : entity work.ADS1274_DRIVER -generic map(MODE_low_power,FSYNC_FORMAT) -port map( - Clk => clk_buf, - reset => reset_buf, - SpiClk => LF_ADC_Sclk, - DIN => LF_ADC_IN, - Ready => '0', - Format => LF_ADC_Format, - Mode => LF_ADC_Mode, - ClkDiv => LF_ADC_ClkDiv, - PWDOWN => LF_ADC_PWDOWN, - SmplClk => LF_ADC_SmplClk, - OUT0 => LF1_int, - OUT1 => LF2_int, - OUT2 => LF3_int, - OUT3 => open, - FSynch => LF_ADC_FSynch -); - - -LF1 <= LF1_int(23 downto 8); -LF2 <= LF2_int(23 downto 8); -LF3 <= LF3_int(23 downto 8); --- ---DC1 <= LF1_int(23 downto 0); ---DC2 <= LF2_int(23 downto 0); ---DC3 <= LF3_int(23 downto 0); - ---Input Word Selection Decoder - -process(clk) -variable SelVar : integer range 0 to 1; -begin - if clk'event and clk ='1' then - Decoder: FOR i IN 0 to FramePlacerCount-1 loop - if FramePlacerFlags(i) = '1' then - SelVar := i; - end if; - END loop Decoder; - Sel <= SelVar; - end if; -end process; - - -end ar_TOP_ICI3_INTEG1; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver2.vhd b/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver2.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver2.vhd +++ /dev/null @@ -1,65 +0,0 @@ --- TOP_Serial_Driver2.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity TOP_Serial_Driver2 is -port( - clk : in std_logic; - sclk : in std_logic; - Gate : in std_logic; - Data : out std_logic -); -end TOP_Serial_Driver2; - - - - -architecture ar_TOP_Serial_Driver2 of TOP_Serial_Driver2 is -constant Size : integer := 8; -signal MinF_Inv : std_logic; -signal Gate_Inv : std_logic; -signal sclk_Inv : std_logic; -signal OV : std_logic; -signal Word : std_logic_vector(Size-1 downto 0); -constant Word1 : std_logic_vector(Size-1 downto 0) := std_logic_vector(TO_UNSIGNED(36,Size)); -constant Word2 : std_logic_vector(Size-1 downto 0) := std_logic_vector(TO_UNSIGNED(255,Size)); -signal Flag : std_logic :='0'; - -begin -Gate_Inv <= not Gate; -sclk_Inv <= not Sclk; - - -SD0 : entity work.Serial_Driver -generic map(Size) -port map( - sclk_Inv, - Word, - Gate_inv, - Data -); - -cpt : entity work.Simple_Counter -generic map(8) -port map( - clk, - sclk_Inv, - Gate_Inv, - OV); - - -word <= Word1;-- when OV = '1' and Flag = '0' else Word2 when OV = '1' and Flag = '1'; - -process(sclk) -begin -if sclk'event and sclk = '1' then - if OV = '1' then - Flag <= not Flag; - end if; -end if; -end process; - - -end ar_TOP_Serial_Driver2; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver_Wcounter.vhd b/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver_Wcounter.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver_Wcounter.vhd +++ /dev/null @@ -1,177 +0,0 @@ --- TOP_Serial_Driver_Wcounter.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity TOP_Serial_Driver_Wcounter is -Generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64); -port( - clk : in std_logic; - sclk : in std_logic; - Gate : in std_logic; - MinF : in std_logic; - MajF : in std_logic; - Data : out std_logic -); -end entity; - - - - -architecture ar_TOP_Serial_Driver_Wcounter of TOP_Serial_Driver_Wcounter is - - -Constant FramePlacerCount : integer := 2; - -signal MinF_Inv : std_logic; -signal Gate_Inv : std_logic; -signal sclk_Inv : std_logic; -signal WordCount : integer range 0 to WordCnt-1; -signal WordClk : std_logic; - -signal MuxOUT : std_logic_vector(WordSize-1 downto 0); -signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); -signal Sel : integer range 0 to 1; - -signal DC1 : std_logic_vector(23 downto 0); -signal DC2 : std_logic_vector(23 downto 0); -signal DC3 : std_logic_vector(23 downto 0); - - - -signal LF1 : std_logic_vector(15 downto 0); -signal LF2 : std_logic_vector(15 downto 0); -signal LF3 : std_logic_vector(15 downto 0); - -constant DC1cst : std_logic_vector(23 downto 0) := X"FA5961"; -constant DC2cst : std_logic_vector(23 downto 0) := X"123456"; -constant DC3cst : std_logic_vector(23 downto 0) := X"789012"; - -constant LF1cst : std_logic_vector(15 downto 0) := X"3210"; -constant LF2cst : std_logic_vector(15 downto 0) := X"6543"; -constant LF3cst : std_logic_vector(15 downto 0) := X"3456"; - - -signal MinFCnt : integer range 0 to MinFCount-1; - -signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); - -begin - -Gate_Inv <= not Gate; -sclk_Inv <= not Sclk; -MinF_Inv <= not MinF; - -DC1 <= DC1cst; -DC2 <= DC2cst; -DC3 <= DC3cst; - -LF1 <= LF1cst; -LF2 <= LF2cst; -LF3 <= LF3cst; - -SD0 : entity work.Serial_Driver -generic map(WordSize) -port map(sclk_Inv,MuxOUT,Gate_inv,Data); - -WC0 : entity work.Word_Cntr -generic map(WordSize,WordCnt) -port map(sclk_Inv,MinF,WordClk,WordCount); - -MFC0 : entity work.MinF_Cntr -generic map(MinFCount) -port map( - clk => MinF_Inv, - reset => MajF, - Cnt_out => MinFCnt -); - - -MUX0 : entity work.Serial_Driver_Multiplexor -generic map(FramePlacerCount,WordSize) -port map(sclk_Inv,Sel,MuxIN,MuxOUT); - - -DCFP0 : entity work.DC_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - MinFCnt => MinFCnt, - Flag => FramePlacerFlags(0), - DC1 => DC1, - DC2 => DC2, - DC3 => DC3, - WordOut => MuxIN(7 downto 0)); - - - -LFP0 : entity work.LF_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - Flag => FramePlacerFlags(1), - LF1 => LF1, - LF2 => LF2, - LF3 => LF3, - WordOut => MuxIN(15 downto 8)); - --- FramePlacerFlags(1) <= '0'; --- MuxIN(15 downto 8) <= (others =>'0'); - ---Input Word Selection Decoder - -process(clk) -variable SelVar : integer range 0 to 1; -begin - if clk'event and clk ='1' then - Decoder: FOR i IN 0 to FramePlacerCount-1 loop - if FramePlacerFlags(i) = '1' then - SelVar := i; - end if; - END loop Decoder; - Sel <= SelVar; - end if; -end process; - - -end ar_TOP_Serial_Driver_Wcounter; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/Telemetry_config.vhd b/designs/ICI4-Integ1/ICI4HDL/Telemetry_config.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Telemetry_config.vhd +++ /dev/null @@ -1,54 +0,0 @@ --- Telemetry_config.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -package Telemetry_config is - ---===========================================================| ---==================== Géné Signaux =========================| ---===========================================================| -constant Fréq_clk_Hz : integer := 40000000; -constant Débit_Hz : integer := 3300000; -constant Débit_série_bauds : integer := 57600; -constant nb_bits_par_mot : integer := 8; -constant nb_mots_par_Minor : integer := 144; -constant nb_Minor_par_Major : integer := 64; -constant nb_mots_total : integer := nb_mots_par_Minor*nb_Minor_par_Major; -constant nb_compteur_sclk : integer := Fréq_clk_Hz / Débit_Hz; - - ---===========================================================| ---==================== Entêtes UART =========================| ---===========================================================| -constant nb_bit_start : integer := 1; -constant nb_bit_stop : integer := 1; -constant nb_bit_pause : integer := 3; - - ---===========================================================| ---=================== Signal Gate_HF ========================| ---===========================================================| -constant nb_mots_lgt : integer := 8; -constant start_mot : integer := 6; -constant lrg_ON : integer := 2; - - ---===========================================================| ---=================== Signal Gate_LF ========================| ---===========================================================| -type Tbl is array(natural range <>) of integer ; -constant Tablo : Tbl (0 to 7):= (16,17,20,21,24,25,28,29); - - ---===========================================================| ---====================== Pacquage ===========================| ---===========================================================| -constant Start_1 : std_logic_vector(7 downto 0) := X"0F"; -constant Start_0 : std_logic_vector(7 downto 0) := X"A5"; -constant Stop_1 : std_logic_vector(7 downto 0) := X"5A"; -constant Stop_0 : std_logic_vector(7 downto 0) := X"F0"; - - -end; diff --git a/designs/ICI4-Integ1/ICI4HDL/Top_Serial_Driver.vhd b/designs/ICI4-Integ1/ICI4HDL/Top_Serial_Driver.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Top_Serial_Driver.vhd +++ /dev/null @@ -1,42 +0,0 @@ --- Top_Serial_Driver.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity Top_Serial_Driver is -port( - sclk : in std_logic; - Gate : in std_logic; - MinF : in std_logic; - Data : out std_logic -); -end Top_Serial_Driver; - - - - -architecture ar_Top_Serial_Driver of Top_Serial_Driver is -constant Size : integer := 8; -signal MinF_Inv : std_logic; -signal Gate_Inv : std_logic; -signal sclk_Inv : std_logic; -constant Word : std_logic_vector(Size-1 downto 0) := std_logic_vector(TO_UNSIGNED(165,Size)); - - -begin -MinF_Inv <= not MinF; -Gate_Inv <= not Gate; -sclk_Inv <= not Sclk; - - -SD0 : entity work.Serial_Driver -generic map(Size) -port map( - sclk_Inv, - Word, - MinF_Inv, - Gate_Inv, - Data -); -end ar_Top_Serial_Driver; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/Vectorize.vhd b/designs/ICI4-Integ1/ICI4HDL/Vectorize.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Vectorize.vhd +++ /dev/null @@ -1,96 +0,0 @@ --- Vectorize.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - - -entity Vectorize is - -port( - clk,raz : in std_logic; - sclk : in std_logic; - RDY : in std_logic; - In1,In2,In3 : in std_logic; - bit : out std_logic; - Vector_1,Vector_2,Vector_3 : out std_logic_vector(23 downto 0)); - -end Vectorize; - - -architecture ar_Vectorize of Vectorize is - -type etat is (e0,e1,e2); -signal ect : etat; - -signal rdy_reg : std_logic; -signal sclk_reg : std_logic; -signal cpt : integer range 0 to 24; -signal Vect_1 : std_logic_vector(23 downto 0); -signal Vect_2 : std_logic_vector(23 downto 0); -signal Vect_3 : std_logic_vector(23 downto 0); - -begin - process(clk,raz) - begin - if(raz='0')then - Vect_1 <= (others => '0'); - Vect_2 <= (others => '0'); - Vect_3 <= (others => '0'); - rdy_reg <= '1'; - sclk_reg <= '0'; - ect <= e0; - cpt <= 0; - bit <= '0'; - - elsif(clk'event and clk='1')then - rdy_reg <= RDY; - sclk_reg <= sclk; - - case ect is - when e0 => - if(rdy_reg='0' and RDY='1')then - ect <= e1; - else - ect <= e0; - end if; - - when e1 => - bit <= '0'; - if(sclk_reg='0' and sclk='1')then - Vect_1 <= Vect_1(22 downto 0) & In1; - Vect_2 <= Vect_2(22 downto 0) & In2; - Vect_3 <= Vect_3(22 downto 0) & In3; - if(cpt=23)then - cpt <= 0; - bit <= '1'; - ect <= e0; - else - cpt <= cpt + 1; - ect <= e2; - end if; - end if; - - when e2 => - bit <= '0'; - if(sclk_reg='0' and sclk='1')then - Vect_1 <= Vect_1(22 downto 0) & In1; - Vect_2 <= Vect_2(22 downto 0) & In2; - Vect_3 <= Vect_3(22 downto 0) & In3; - if(cpt=23)then - cpt <= 0; - bit <= '1'; - ect <= e0; - else - cpt <= cpt + 1; - ect <= e1; - end if; - end if; - end case; - end if; - end process; - -Vector_1 <= Vect_1; -Vector_2 <= Vect_2; -Vector_3 <= Vect_3; - -end ar_Vectorize; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/Word_Cntr.vhd b/designs/ICI4-Integ1/ICI4HDL/Word_Cntr.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/Word_Cntr.vhd +++ /dev/null @@ -1,70 +0,0 @@ --- Word_Cntr.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - - - -entity Word_Cntr is -generic(WordSize :integer := 8 ;N : integer := 144); -port( - Sclk : in std_logic; - reset : in std_logic; - WordClk : out std_logic; - Cnt_out : out integer range 0 to N-1 -); -end entity; - - - -architecture ar_Word_Cntr of Word_Cntr is - -signal Cnt_int : integer range 0 to N-1 := 0; -signal Wcnt : integer range 0 to WordSize -1 ; - -begin - -Cnt_out <= Cnt_int; - -process(Sclk,reset) -begin - if reset = '0' then - Cnt_int <= 0; - Wcnt <= 0; - WordClk <= '0'; - elsif Sclk'event and Sclk = '1' then - if Wcnt = WordSize - 1 then - Cnt_int <= Cnt_int + 1; - Wcnt <= 0; - WordClk <= '1'; - else - Wcnt <= Wcnt + 1; - WordClk <= '0'; - end if; - end if; -end process; -end ar_Word_Cntr; - - - - - - - - - - - - - - - - - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/integer_to_clk.vhd b/designs/ICI4-Integ1/ICI4HDL/integer_to_clk.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/integer_to_clk.vhd +++ /dev/null @@ -1,48 +0,0 @@ --- integer_to_clk.vhd -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity integer_to_clk is - -generic(N : integer := 144); - -port( - clk,raz : in std_logic; - Compt : in integer range 0 to N; - Clock : out std_logic); - -end integer_to_clk; - - -architecture ar_integer_to_clk of integer_to_clk is - -signal compt_reg : integer range 0 to N; -signal Clock_int : std_logic; - -begin - process(clk, raz) - begin - if (raz='0')then - Clock_int <= '0'; - compt_reg <= 0; - - elsif (clk'event and clk='1') then - compt_reg <= Compt; - if(compt_reg/=Compt)then - Clock_int <= not Clock_int; - end if; - end if; - end process; - -Clock <= Clock_int; -end ar_integer_to_clk; - - - - - - - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/sys_clock.vhd b/designs/ICI4-Integ1/ICI4HDL/sys_clock.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/sys_clock.vhd +++ /dev/null @@ -1,44 +0,0 @@ --- sys_clock.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity Sys_Clock is - -generic(N :integer := 22); - -port( - clk, raz : in std_logic ; - clock : out std_logic); - -end Sys_Clock; - - -architecture ar_Sys_Clock of Sys_Clock is - -signal clockint : std_logic; -signal countint : integer range 0 to N/2-1; - -begin - process (clk,raz) - begin - if(raz = '0') then - countint <= 0; - clockint <= '0'; - elsif (clk' event and clk='1') then - if (countint = N/2-1) then - countint <= 0; - clockint <= not clockint; - else - countint <= countint+1; - end if; - end if; - end process; - -clock <= clockint; - -end ar_Sys_Clock; - - - diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd b/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd +++ /dev/null @@ -1,73 +0,0 @@ --- tb_Serial_Driver.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity tb_Serial_Driver is -end entity; - - - -architecture ar_tb_Serial_Driver of tb_Serial_Driver is - -constant Speed : integer := 4*1000*1000; -constant Tclk : time := real(1000*1000*1000/Speed) * 1 ns; -constant Size : integer := 8; - - -signal sclk : std_logic := '0'; -signal inputDat : std_logic_vector(Size-1 downto 0); -signal load : std_logic:='0'; -signal Gate : std_logic:='0'; -signal Data : std_logic; - -begin - -SD0 : entity work.Serial_Driver -generic map(Size) -port map( - sclk, - inputDat, - load, - Gate, - Data -); - -sclk <= not sclk after Tclk/2; - - - - - -process -begin - -inputDat <= std_logic_vector(TO_UNSIGNED(0,Size)); -wait for 1ns; -load <= '1'; -wait for 1ns; -load <= '0'; -gate <= '1'; -wait for Size * Tclk; -gate <= '0'; -wait for 1ns; - - -inputDat <= std_logic_vector(TO_UNSIGNED(165,Size)); -wait for 1ns; -load <= '1'; -wait for 1ns; -load <= '0'; -gate <= '1'; -wait for Size * Tclk; -gate <= '0'; -wait for 1ns; - - -wait; -end process; - - - -end ar_tb_Serial_Driver; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd.bak b/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd.bak deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd.bak +++ /dev/null @@ -1,73 +0,0 @@ --- tb_Serial_Driver.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity tb_Serial_Driver is -end entity; - - - -architecture ar_tb_Serial_Driver of tb_Serial_Driver is - -constant Speed : integer := 4*1000*1000; -constant Tclk : time := real(1000*1000*1000/Speed) * 1 ns; -constant Size : integer := 8; - - -signal sclk : std_logic := '0'; -signal inputDat : std_logic_vector(Size-1 downto 0); -signal load : std_logic:='0'; -signal Gate : std_logic:='0'; -signal Data : std_logic; - -begin - -SD0 : entity work.Serial_Driver -generic map(Size) -port map( - sclk, - inputDat, - load, - Gate, - Data -); - -sclk <= not sclk after Tclk/2; - - - - - -process -begin - -inputDat <= std_logic_vector(TO_UNSIGNED(0,Size)); -wait for 1ns; -load <= '1'; -wait for 1ns; -load <= '0'; -gate <= '1'; -wait for Size * Tclk/2; -gate <= '0'; -wait for 1ns; - - -inputDat <= std_logic_vector(TO_UNSIGNED(A5,Size)); -wait for 1ns; -load <= '1'; -wait for 1ns; -load <= '0'; -gate <= '1'; -wait for Size * Tclk/2; -gate <= '0'; -wait for 1ns; - - -wait; -end process; - - - -end ar_tb_Serial_Driver; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver2.vhd b/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver2.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver2.vhd +++ /dev/null @@ -1,69 +0,0 @@ --- tb_TOP_Serial_Driver2.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity tb_TOP_Serial_Driver2 is -end entity; - - - -architecture ar_tb_TOP_Serial_Driver2 of tb_TOP_Serial_Driver2 is - -constant Speed : integer := 4*1000*1000; -constant Tclk : time := real(1000*1000*1000/Speed) * 1 ns; -constant Size : integer := 8; - -signal clk : std_logic:='0'; -signal sclk : std_logic := '0'; -signal Gate : std_logic:='1'; -signal Data : std_logic; - -begin - -SD0 : entity work.TOP_Serial_Driver2 -port map(clk,sclk,Gate,Data); - -sclk <= not sclk after Tclk/2; -clk <= not clk after 10ns; - - - - -process -begin -gate <= '1'; -wait for 1us; -gate <= '0'; -wait for Size * Tclk; -gate <= '1'; -wait for 1ns; - -wait for 1us; - -wait for 1ns; - -gate <= '0'; -wait for Size * Tclk; -gate <= '1'; -wait for 1ns; - -gate <= '0'; -wait for Size *4* Tclk; -gate <= '1'; -wait for 10us; - - -gate <= '0'; -wait for Size *2* Tclk; -gate <= '1'; -wait for 1ns; - - -wait; -end process; - - - -end ar_tb_TOP_Serial_Driver2; \ No newline at end of file diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver_Wcounter.vhd b/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver_Wcounter.vhd deleted file mode 100644 --- a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver_Wcounter.vhd +++ /dev/null @@ -1,143 +0,0 @@ --- tb_TOP_Serial_Driver_Wcounter.vhd -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity tb_TOP_Serial_Driver_Wcounter is -end entity; - - - -architecture ar_tb_TOP_Serial_Driver_Wcounter of tb_TOP_Serial_Driver_Wcounter is - -constant Speed : integer := 4*1000*1000; -constant Tclk : time := real(1000*1000*1000/Speed) * 1 ns; -constant Size : integer := 8; -constant MinFCnt: integer := 144; -constant MajFCnt: integer := 64; - -signal clk : std_logic := '0'; -signal sclk : std_logic := '0'; -signal Gate : std_logic:='1'; -signal Data : std_logic; -signal MinF : std_logic:='1'; -signal MajF : std_logic:='1'; -signal flag : std_logic; - -begin - -SD0 : entity work.TOP_Serial_Driver_Wcounter ---generic map(Size,MinFCnt) -generic map(Size,MinFCnt,MajFCnt) -port map(clk,sclk,Gate,MinF,MajF,Data); - -sclk <= not sclk after Tclk/2; - -clk <= not clk after 20ns; - - -process -begin - -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; --1 ADMLF1.1 -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; --2 ADMLF2.1 -wait for (32)*Tclk; -gate <= '1'; -wait for (16)*Tclk; -gate <= '0'; --3 ADMDC1 LSB -wait for (48)*Tclk; -gate <= '1'; -wait for (16)*Tclk; -gate <= '0'; --4 ADMDC2 LSB -wait for (32)*Tclk; -gate <= '1'; - - -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -wait for (48)*Tclk; -gate <= '0'; -wait for (16)*Tclk; -gate <= '1'; -end process; - - - - -process -begin -MinF <= '0'; -wait for Tclk; -MinF <= '1'; -wait for (MinFCnt)*(Size)*Tclk-Tclk; -end process; - - - -process -begin -MajF <= '0'; -wait for Tclk; -MajF <= '1'; -wait for (MajFCnt)*(MinFCnt)*(Size)*Tclk-Tclk; -end process; - - - -end ar_tb_TOP_Serial_Driver_Wcounter; \ No newline at end of file diff --git a/designs/ICI4-Integ1/Makefile b/designs/ICI4-Integ1/Makefile --- a/designs/ICI4-Integ1/Makefile +++ b/designs/ICI4-Integ1/Makefile @@ -4,11 +4,11 @@ include .config TOP=ici4 BOARD=ICI4-main-BD #BOARD=SP601 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc +include ../../boards/$(BOARD)/Makefile.inc DEVICE=$(PART)-$(PACKAGE)$(SPEED) #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf -UCF=$(GRLIB)/boards/$(BOARD)/ICI4-Main-BD.ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf +QSF=../../boards/$(BOARD)/$(TOP).qsf EFFORT=high ISEMAPOPT="-timing" XSTOPT="" @@ -19,7 +19,17 @@ VHDLOPTSYNFILES= \ ICI4HDL/DC_FRAME_PLACER.vhd \ ICI4HDL/DC_SMPL_CLK.vhd \ ICI4HDL/LF_FRAME_PLACER.vhd \ - ICI4HDL/LF_SMPL_CLK.vhd + ICI4HDL/LF_SMPL_CLK.vhd \ + ICI4HDL/Fast2SlowSync.vhd \ + ICI4HDL/Slow2FastSync.vhd \ + ICI4HDL/CrossDomainSyncGen.vhd \ + ICI4HDL/TM_MODULE.vhd \ + ICI4HDL/DC_ACQ_TOP.vhd \ + ICI4HDL/LF_ACQ_TOP.vhd \ + ICI4HDL/FAKE_ADC.vhd \ + ICI4HDL/OneShot.vhd \ + ICI4HDL/IIR_FILTER_TOP.vhd + VHDLSYNFILES= \ config.vhd ici4.vhd @@ -27,7 +37,7 @@ VHDLSIMFILES=testbench.vhd SIMTOP=testbench #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc SDCFILE=default.sdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +BITGEN=../../boards/$(BOARD)/default.ut CLEAN=soft-clean VCOMOPT=-explicit TECHLIBS = secureip unisim @@ -47,4 +57,5 @@ include $(GRLIB)/software/leon3/Makefile ################## project specific targets ########################## - +flash: + xc3sprog -c ftdi -p 1 ici4.bit diff --git a/designs/ICI4-Integ1/config.vhd b/designs/ICI4-Integ1/config.vhd --- a/designs/ICI4-Integ1/config.vhd +++ b/designs/ICI4-Integ1/config.vhd @@ -9,8 +9,10 @@ library techmap; use techmap.gencomp.all; -library ieee; -use ieee.std_logic_1164.all; +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + package config is -- Technology and synthesis options @@ -19,8 +21,8 @@ package config is constant CFG_PADTECH : integer := spartan6; -- Clock generator constant CFG_CLKTECH : integer := spartan6; - constant SEND_CONSTANT_DATA : integer := 1; - constant SEND_MINF_VALUE : integer := 1; + constant SEND_CONSTANT_DATA : integer := 0; + constant SEND_MINF_VALUE : integer := 0; @@ -29,13 +31,13 @@ constant LF2cst : std_logic_vector(15 constant LF3cst : std_logic_vector(15 downto 0) := X"3333"; -constant AMR1Xcst : std_logic_vector(23 downto 0):= X"444444"; -constant AMR1Ycst : std_logic_vector(23 downto 0):= X"555555"; -constant AMR1Zcst : std_logic_vector(23 downto 0):= X"666666"; +constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001"; +constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111"; +constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF"; -constant AMR2Xcst : std_logic_vector(23 downto 0):= X"777777"; -constant AMR2Ycst : std_logic_vector(23 downto 0):= X"888888"; -constant AMR2Zcst : std_logic_vector(23 downto 0):= X"999999"; +constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000"; +constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002"; +constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001"; constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA"; constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB"; @@ -49,4 +51,95 @@ constant Temp1cst : std_logic_vec constant Temp2cst : std_logic_vector(23 downto 0):= X"343434"; constant Temp3cst : std_logic_vector(23 downto 0):= X"565656"; constant Temp4cst : std_logic_vector(23 downto 0):= X"787878"; + + + +--===========================================================| +--========F I L T E R C O N F I G V A L U E S=============| +--===========================================================| +--____________________________ +--Bus Width and chanels number| +--____________________________| +constant ChanelsCount : integer := 3; +constant Sample_SZ : integer := 16; +constant Coef_SZ : integer := 9; +constant CoefCntPerCel: integer := 6; +constant CoefPerCel: integer := 5; +constant Cels_count : integer := 5; +constant virgPos : integer := 7; +constant Mem_use : integer := 1; + + + +--============================================================ +-- create each initial values for each coefs ============ +--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! +--============================================================ +constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); +constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ)); +constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); + +constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); +constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ)); +constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ)); + +constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ)); +constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ)); +constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ)); + +constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); +constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ)); +constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); + +constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); +constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ)); +constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ)); + +--constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ)); +--constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ)); +--constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ)); + +--constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ)); +--constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ)); +--constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ)); + + +constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ)); +constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ)); + +constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ)); +constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ)); + +constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ)); +constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ)); + +constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ)); +constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ)); + +constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ)); +constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ)); + +--constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ)); +--constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +--constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ)); +--constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ)); +--constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ)); +--constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ)); + +constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0); + +constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) := + (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 & + a3_1 & a3_2 & b3_0 & b3_1 & b3_2 & + a2_1 & a2_2 & b2_0 & b2_1 & b2_2 & + a1_1 & a1_2 & b1_0 & b1_1 & b1_2 & + a0_1 & a0_2 & b0_0 & b0_1 & b0_2 ); + + + end; diff --git a/designs/ICI4-Integ1/ici4.vhd b/designs/ICI4-Integ1/ici4.vhd --- a/designs/ICI4-Integ1/ici4.vhd +++ b/designs/ICI4-Integ1/ici4.vhd @@ -1,5 +1,5 @@ library ieee; -use ieee.std_logic_1164.all; +use ieee.std_logic_1164.all; use IEEE.numeric_std.all; library grlib, techmap; use grlib.amba.all; @@ -25,6 +25,14 @@ use work.Convertisseur_config.all; use work.config.all; +--================================================================== +-- +-- +-- FPGA FREQ = 48MHz +-- ADC Oscillator frequency = 12MHz +-- +-- +--================================================================== entity ici4 is generic ( @@ -35,20 +43,25 @@ entity ici4 is WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64 ); port ( - reset : in std_ulogic; - clk : in std_ulogic; - sclk : in std_logic; - Gate : in std_logic; - MinF : in std_logic; - MajF : in std_logic; - Data : out std_logic; - DC_ADC_Sclk : out std_logic; - DC_ADC_IN : in std_logic_vector(1 downto 0); - DC_ADC_ClkDiv : out std_logic; - DC_ADC_FSynch : out std_logic; - SET_RESET0 : out std_logic; - SET_RESET1 : out std_logic; - LED : out std_logic + reset : in std_ulogic; + clk : in std_ulogic; + sclk : in std_logic; + Gate : in std_logic; + MinF : in std_logic; + MajF : in std_logic; + Data : out std_logic; + LF_SCK : out std_logic; + LF_CNV : out std_logic; + LF_SDO1 : in std_logic; + LF_SDO2 : in std_logic; + LF_SDO3 : in std_logic; + DC_ADC_Sclk : out std_logic; + DC_ADC_IN : in std_logic_vector(1 downto 0); + DC_ADC_ClkDiv : out std_logic; + DC_ADC_FSynch : out std_logic; + SET_RESET0 : out std_logic; + SET_RESET1 : out std_logic; + LED : out std_logic ); end; @@ -58,17 +71,10 @@ signal clk_buf,reset_buf : std_logi Constant FramePlacerCount : integer := 2; -signal MinF_Inv : std_logic; -signal Gate_Inv : std_logic; -signal sclk_Inv : std_logic; + signal WordCount : integer range 0 to WordCnt-1; signal WordClk : std_logic; -signal data_int : std_logic; - -signal MuxOUT : std_logic_vector(WordSize-1 downto 0); -signal MuxIN : std_logic_vector((2*WordSize)-1 downto 0); -signal Sel : integer range 0 to 1; signal AMR1X : std_logic_vector(23 downto 0); signal AMR1Y : std_logic_vector(23 downto 0); @@ -86,229 +92,155 @@ signal AMR4X : std_logic_vector(2 signal AMR4Y : std_logic_vector(23 downto 0); signal AMR4Z : std_logic_vector(23 downto 0); -signal Temp1 : std_logic_vector(23 downto 0); -signal Temp2 : std_logic_vector(23 downto 0); -signal Temp3 : std_logic_vector(23 downto 0); -signal Temp4 : std_logic_vector(23 downto 0); +signal TEMP1 : std_logic_vector(23 downto 0); +signal TEMP2 : std_logic_vector(23 downto 0); +signal TEMP3 : std_logic_vector(23 downto 0); +signal TEMP4 : std_logic_vector(23 downto 0); signal LF1 : std_logic_vector(15 downto 0); signal LF2 : std_logic_vector(15 downto 0); signal LF3 : std_logic_vector(15 downto 0); - -signal LF1_int : std_logic_vector(23 downto 0); -signal LF2_int : std_logic_vector(23 downto 0); -signal LF3_int : std_logic_vector(23 downto 0); +signal data_int : std_logic; -signal DC_ADC_SmplClk : std_logic; -signal LF_ADC_SmplClk : std_logic; -signal SET_RESET0_sig : std_logic; -signal SET_RESET1_sig : std_logic; - -signal MinFCnt : integer range 0 to MinFCount-1; - -signal FramePlacerFlags : std_logic_vector(FramePlacerCount-1 downto 0); +signal CrossDomainSync : std_logic; begin -clk_buf <= clk; -reset_buf <= reset; --- - -Gate_Inv <= not Gate; -sclk_Inv <= not Sclk; -MinF_Inv <= not MinF; - LED <= not data_int; -data <= data_int; - - - -SD0 : Serial_Driver -generic map(WordSize) -port map(sclk_Inv,MuxOUT,Gate_inv,data_int); - -WC0 : Word_Cntr -generic map(WordSize,WordCnt) -port map(sclk_Inv,MinF,WordClk,WordCount); - -MFC0 : MinF_Cntr -generic map(MinFCount) -port map( - clk => MinF_Inv, - reset => MajF, - Cnt_out => MinFCnt -); - - -MUX0 : Serial_Driver_Multiplexor -generic map(FramePlacerCount,WordSize) -port map(sclk_Inv,Sel,MuxIN,MuxOUT); - - -DCFP0 : entity work.DC_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - MinFCnt => MinFCnt, - Flag => FramePlacerFlags(0), - AMR1X => AMR1X, - AMR1Y => AMR1Y, - AMR1Z => AMR1Z, - AMR2X => AMR2X, - AMR2Y => AMR2Y, - AMR2Z => AMR2Z, - AMR3X => AMR3X, - AMR3Y => AMR3Y, - AMR3Z => AMR3Z, - AMR4X => AMR4X, - AMR4Y => AMR4Y, - AMR4Z => AMR4Z, - Temp1 => Temp1, - Temp2 => Temp2, - Temp3 => Temp3, - Temp4 => Temp4, - WordOut => MuxIN(7 downto 0)); - - - -LFP0 : entity work.LF_FRAME_PLACER -generic map(WordSize,WordCnt,MinFCount) -port map( - clk => Sclk, - Wcount => WordCount, - Flag => FramePlacerFlags(1), - LF1 => LF1, - LF2 => LF2, - LF3 => LF3, - WordOut => MuxIN(15 downto 8)); - - - -DC_SMPL_CLK0 : entity work.DC_SMPL_CLK -port map(MinF_Inv,DC_ADC_SmplClk); - -process(reset,DC_ADC_SmplClk) -begin -if reset = '0' then - SET_RESET0_sig <= '0'; -elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '1' then - SET_RESET0_sig <= not SET_RESET0_sig; -end if; -end process; - -SET_RESET1_sig <= SET_RESET0_sig; -SET_RESET0 <= SET_RESET0_sig; -SET_RESET1 <= SET_RESET1_sig; --- +data <= data_int; -send_ADC_DATA : IF SEND_CONSTANT_DATA = 0 GENERATE - DC_ADC0 : DUAL_ADS1278_DRIVER --With AMR down ! => 24bits DC TM -> SC high res on Spin - port map( - Clk => clk_buf, - reset => reset_buf, - SpiClk => DC_ADC_Sclk, - DIN => DC_ADC_IN, - SmplClk => DC_ADC_SmplClk, - OUT00 => AMR1X, - OUT01 => AMR1Y, - OUT02 => AMR1Z, - OUT03 => AMR2X, - OUT04 => AMR2Y, - OUT05 => AMR2Z, - OUT06 => Temp1, - OUT07 => Temp2, - OUT10 => AMR3X, - OUT11 => AMR3Y, - OUT12 => AMR3Z, - OUT13 => AMR4X, - OUT14 => AMR4Y, - OUT15 => AMR4Z, - OUT16 => Temp3, - OUT17 => Temp4, - FSynch => DC_ADC_FSynch - ); - LF1 <= LF1cst; - LF2 <= LF2cst; - LF3 <= LF3cst; - END GENERATE; +CDS0 : entity work.CrossDomainSyncGen +Port map( + reset => reset, + ClockS => sclk, + ClockF => clk, + SyncSignal => CrossDomainSync +); -send_CST_DATA : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 0) GENERATE - AMR1X <= AMR1Xcst; - AMR1Y <= AMR1Ycst; - AMR1Z <= AMR1Zcst; - AMR2X <= AMR2Xcst; - AMR2Y <= AMR2Ycst; - AMR2Z <= AMR2Zcst; - Temp1 <= Temp1cst; - Temp2 <= Temp2cst; - AMR3X <= AMR3Xcst; - AMR3Y <= AMR3Ycst; - AMR3Z <= AMR3Zcst; - AMR4X <= AMR4Xcst; - AMR4Y <= AMR4Ycst; - AMR4Z <= AMR4Zcst; - Temp3 <= Temp3cst; - Temp4 <= Temp4cst; - - LF1 <= LF1cst; - LF2 <= LF2cst; - LF3 <= LF3cst; - END GENERATE; - - +TM : entity work.TM_MODULE +generic map( + WordSize => WordSize, + WordCnt => WordCnt, + MinFCount => MinFCount +) +port map( + + reset =>reset, + clk =>clk, + MinF =>MinF, + MajF =>MajF, + sclk =>sclk, + gate =>gate, + data =>data_int, + WordClk =>WordClk, -send_minF_valuelbl : IF (SEND_CONSTANT_DATA = 1) and (SEND_MINF_VALUE = 1) GENERATE - AMR1X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR1Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR1Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR2X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR2Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR2Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp1 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp2 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR3X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR3Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR3Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR4X <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR4Y <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - AMR4Z <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp3 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - Temp4 <= X"000" & "000" & std_logic_vector(TO_UNSIGNED(MinFCnt,9)); - - LF1 <= LF1cst; - LF2 <= LF2cst; - LF3 <= LF3cst; - END GENERATE; + LF1 => LF1, + LF2 => LF2, + LF3 => LF3, + + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4 +); -LF_SMPL_CLK0 : entity work.LF_SMPL_CLK +DC_ADC0:entity work.DC_ACQ_TOP +generic map ( + WordSize => WordSize, + WordCnt => WordCnt, + MinFCount => MinFCount, + EnableSR => 0, + CstDATA => SEND_CONSTANT_DATA, + FakeADC => 0 +) port map( - Wclck => WordClk, - MinF => MinF, - SMPL_CLK => LF_ADC_SmplClk + + reset => reset, + clk => clk, + SyncSig => CrossDomainSync, + minorF => minF, + majorF => majF, + sclk => sclk, + WordClk => WordClk, + + DC_ADC_Sclk => DC_ADC_Sclk, + DC_ADC_IN => DC_ADC_IN, + DC_ADC_ClkDiv => DC_ADC_ClkDiv, + DC_ADC_FSynch => DC_ADC_FSynch, + SET_RESET0 => SET_RESET0, + SET_RESET1 => SET_RESET1, + + AMR1X => AMR1X, + AMR1Y => AMR1Y, + AMR1Z => AMR1Z, + + AMR2X => AMR2X, + AMR2Y => AMR2Y, + AMR2Z => AMR2Z, + + AMR3X => AMR3X, + AMR3Y => AMR3Y, + AMR3Z => AMR3Z, + + AMR4X => AMR4X, + AMR4Y => AMR4Y, + AMR4Z => AMR4Z, + + Temp1 => Temp1, + Temp2 => Temp2, + Temp3 => Temp3, + Temp4 => Temp4 ); +LF: entity work.LF_ACQ_TOP +generic map( + WordSize => WordSize, + WordCnt => WordCnt, + MinFCount => MinFCount, + CstDATA => SEND_CONSTANT_DATA, + IIRFilter => 0 +) +port map( -process(clk) -variable SelVar : integer range 0 to 1; -begin - if clk'event and clk ='1' then - Decoder: FOR i IN 0 to FramePlacerCount-1 loop - if FramePlacerFlags(i) = '1' then - SelVar := i; - end if; - END loop Decoder; - Sel <= SelVar; - end if; -end process; - + reset => reset, + clk => clk, + SyncSig => CrossDomainSync, + minorF => minF, + majorF => majF, + sclk => sclk, + WordClk => WordClk, + LF_SCK => LF_SCK, + LF_CNV => LF_CNV, + LF_SDO1 => LF_SDO1, + LF_SDO2 => LF_SDO2, + LF_SDO3 => LF_SDO3, + LF1 => LF1, + LF2 => LF2, + LF3 => LF3 +); end rtl; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd @@ -137,7 +137,7 @@ port map( -ALU_inst :ALU +ALU_inst : ALU_V0 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ) port map( clk => clk, @@ -178,7 +178,7 @@ if reset = '0' then smpl_clk_old <= '0'; RAM_sample_in <= (others=> '0'); - ALU_ctrl <= IDLE; + ALU_ctrl <= IDLE_V0; ALU_sample_in <= (others=> '0'); ALU_Coef_in <= (others=> '0'); RAM_sample_in_bk<= (others=> '0'); @@ -206,7 +206,7 @@ elsif clk'event and clk = '1' then ALU_sample_in <= std_logic_vector(sample_in_BUFF(0)); else - ALU_ctrl <= IDLE; + ALU_ctrl <= IDLE_V0; smplConnectL0: for i in 0 to ChanelsCount-1 loop smplConnectL1: for j in 0 to Sample_SZ-1 loop sample_in_BUFF(i)(j) <= sample_in(i,j); @@ -219,12 +219,12 @@ elsif clk'event and clk = '1' then when pipe1 => IIR_CEL_STATE <= computeb1; - ALU_ctrl <= MAC_op; + ALU_ctrl <= MAC_op_V0; ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0)); when computeb1 => - ALU_ctrl <= MAC_op; + ALU_ctrl <= MAC_op_V0; ALU_sample_in <= RAM_sample_out; ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1)); IIR_CEL_STATE <= computeb2; @@ -248,7 +248,7 @@ elsif clk'event and clk = '1' then when next_cel => - ALU_ctrl <= clr_mac; + ALU_ctrl <= clr_mac_V0; IIR_CEL_STATE <= pipe2; when pipe2 => @@ -281,7 +281,7 @@ rotate : for i in 1 to ChanelsCount-1 if curentChan = (ChanelsCount-1) then IIR_CEL_STATE <= waiting; - ALU_ctrl <= clr_mac; + ALU_ctrl <= clr_mac_V0; elsif ChanelsCount>1 then curentChan <= curentChan + 1; IIR_CEL_STATE <= pipe1; diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt --- a/lib/lpp/dsp/iir_filter/vhdlsyn.txt +++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt @@ -1,19 +1,19 @@ APB_IIR_CEL.vhd APB_IIR_Filter.vhd -FILTER.vhd -FILTER_RAM_CTRLR.vhd FILTERcfg.vhd FilterCTRLR.vhd -IIR_CEL_CTRLR.vhd -IIR_CEL_CTRLR_v2.vhd +FILTER_RAM_CTRLR.vhd +FILTER.vhd IIR_CEL_CTRLR_v2_CONTROL.vhd IIR_CEL_CTRLR_v2_DATAFLOW.vhd +IIR_CEL_CTRLR_v2.vhd +IIR_CEL_CTRLR.vhd IIR_CEL_FILTER.vhd -RAM.vhd +iir_filter.vhd +RAM_CEL_N.vhd RAM_CEL.vhd -RAM_CEL_N.vhd RAM_CTRLR2.vhd RAM_CTRLR_v2.vhd +RAM.vhd Top_Filtre_IIR.vhd Top_IIR.vhd -iir_filter.vhd diff --git a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt --- a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt +++ b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt @@ -1,10 +1,10 @@ +APB_FFT_half.vhd APB_FFT.vhd -APB_FFT_half.vhd Driver_FFT.vhd +FFTamont.vhd +FFTaval.vhd FFT.vhd FFT.vhd.bak -FFTamont.vhd -FFTaval.vhd Flag_Extremum.vhd Flag_Extremum.vhd.bak Linker_FFT.vhd diff --git a/lib/lpp/general_purpose/ALU_V0.vhd b/lib/lpp/general_purpose/ALU_V0.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/ALU_V0.vhd @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.general_purpose.ALL; +--IDLE = 0000 +--MAC = 0001 +--MULT = 0010 and set MULT in ADD reg +--ADD = 0011 +--CLRMAC = 0100 + + +ENTITY ALU_V0 IS + GENERIC( + Arith_en : INTEGER := 1; + Logic_en : INTEGER := 1; + Input_SZ_1 : INTEGER := 16; + Input_SZ_2 : INTEGER := 9 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE ar_ALU OF ALU_V0 IS + + SIGNAL clr_MAC : STD_LOGIC := '1'; + +BEGIN + clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0'; + + arith : IF Arith_en = 1 GENERATE + MACinst : MAC_V0 + GENERIC MAP(Input_SZ_1, Input_SZ_2) + PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES); + END GENERATE; + +END ARCHITECTURE; diff --git a/lib/lpp/general_purpose/Adder_V0.vhd b/lib/lpp/general_purpose/Adder_V0.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/Adder_V0.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.general_purpose.all; + + + +entity Adder_V0 is +generic( + Input_SZ_A : integer := 16; + Input_SZ_B : integer := 16 + +); +port( + clk : in std_logic; + reset : in std_logic; + clr : in std_logic; + add : in std_logic; + OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); + OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); + RES : out std_logic_vector(Input_SZ_A-1 downto 0) +); +end entity; + + + + +architecture ar_Adder of Adder_V0 is + +signal REG : std_logic_vector(Input_SZ_A-1 downto 0); +signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0); + +begin + +RES <= REG; +RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A)); + +process(clk,reset) +begin +if reset = '0' then + REG <= (others => '0'); +elsif clk'event and clk ='1' then + if clr = '1' then + REG <= (others => '0'); + elsif add = '1' then + REG <= RESADD; + end if; +end if; +end process; +end ar_Adder; diff --git a/lib/lpp/general_purpose/MAC_V0.vhd b/lib/lpp/general_purpose/MAC_V0.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/MAC_V0.vhd @@ -0,0 +1,262 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.general_purpose.all; +--TODO +--terminer le testbensh puis changer le resize dans les instanciations +--par un resize sur un vecteur en combi + + + + + +entity MAC_V0 is +generic( + Input_SZ_A : integer := 8; + Input_SZ_B : integer := 8 + +); +port( + clk : in std_logic; + reset : in std_logic; + clr_MAC : in std_logic; + MAC_MUL_ADD : in std_logic_vector(1 downto 0); + OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); + OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); + RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) +); +end MAC_V0; + + + + +architecture ar_MAC of MAC_V0 is + + + + + +signal add,mult : std_logic; +signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + +signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + + +signal MACMUXsel : std_logic; +signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + + + +signal MACMUX2sel : std_logic; + +signal add_D : std_logic; +signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0); +signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0); +signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal MACMUXsel_D : std_logic; +signal MACMUX2sel_D : std_logic; +signal MACMUX2sel_D_D : std_logic; +signal clr_MAC_D : std_logic; +signal clr_MAC_D_D : std_logic; + + + + + +begin + + + + +--============================================================== +--=============M A C C O N T R O L E R========================= +--============================================================== +MAC_CONTROLER1 : MAC_CONTROLER +port map( + ctrl => MAC_MUL_ADD, + MULT => mult, + ADD => add, + MACMUX_sel => MACMUXsel, + MACMUX2_sel => MACMUX2sel + +); +--============================================================== + + + + +--============================================================== +--=============M U L T I P L I E R============================== +--============================================================== +Multiplieri_nst : Multiplier +generic map( + Input_SZ_A => Input_SZ_A, + Input_SZ_B => Input_SZ_B +) +port map( + clk => clk, + reset => reset, + mult => mult, + OP1 => OP1, + OP2 => OP2, + RES => MULTout +); + +--============================================================== + + + + +--============================================================== +--======================A D D E R ============================== +--============================================================== +adder_inst : Adder_V0 +generic map( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B +) +port map( + clk => clk, + reset => reset, + clr => clr_MAC_D, + add => add_D, + OP1 => ADDERinA, + OP2 => ADDERinB, + RES => ADDERout +); + +--============================================================== + + +clr_MACREG1 : MAC_REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => clr_MAC, + Q(0) => clr_MAC_D +); + +clr_MACREG2 : MAC_REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => clr_MAC_D, + Q(0) => clr_MAC_D_D +); + +addREG : MAC_REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => add, + Q(0) => add_D +); + +OP1REG : MAC_REG +generic map(size => Input_SZ_A) +port map( + reset => reset, + clk => clk, + D => OP1, + Q => OP1_D +); + + +OP2REG : MAC_REG +generic map(size => Input_SZ_B) +port map( + reset => reset, + clk => clk, + D => OP2, + Q => OP2_D +); + + +MULToutREG : MAC_REG +generic map(size => Input_SZ_A+Input_SZ_B) +port map( + reset => reset, + clk => clk, + D => MULTout, + Q => MULTout_D +); + + +MACMUXselREG : MAC_REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => MACMUXsel, + Q(0) => MACMUXsel_D +); + +MACMUX2selREG : MAC_REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => MACMUX2sel, + Q(0) => MACMUX2sel_D +); + +MACMUX2selREG2 : MAC_REG +generic map(size => 1) +port map( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D, + Q(0) => MACMUX2sel_D_D +); + +--============================================================== +--======================M A C M U X =========================== +--============================================================== +MACMUX_inst : MAC_MUX +generic map( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + +) +port map( + sel => MACMUXsel_D, + INA1 => ADDERout, + INA2 => OP2_D_Resz, + INB1 => MULTout, + INB2 => OP1_D_Resz, + OUTA => ADDERinA, + OUTB => ADDERinB +); +OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B)); +OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B)); +--============================================================== + + +--============================================================== +--======================M A C M U X2 ========================== +--============================================================== +MAC_MUX2_inst : MAC_MUX2 +generic map(Input_SZ => Input_SZ_A+Input_SZ_B) +port map( + sel => MACMUX2sel_D_D, + RES2 => MULTout_D, + RES1 => ADDERout, + RES => RES +); + + +--============================================================== + +end ar_MAC; diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -68,6 +68,23 @@ PACKAGE general_purpose IS ); END COMPONENT; +COMPONENT Adder_V0 is +generic( + Input_SZ_A : integer := 16; + Input_SZ_B : integer := 16 + +); +port( + clk : in std_logic; + reset : in std_logic; + clr : in std_logic; + add : in std_logic; + OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); + OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); + RES : out std_logic_vector(Input_SZ_A-1 downto 0) +); +end COMPONENT; + COMPONENT ADDRcntr IS PORT( clk : IN STD_LOGIC; @@ -98,14 +115,56 @@ PACKAGE general_purpose IS ); END COMPONENT; +COMPONENT ALU_V0 IS + GENERIC( + Arith_en : INTEGER := 1; + Logic_en : INTEGER := 1; + Input_SZ_1 : INTEGER := 16; + Input_SZ_2 : INTEGER := 9 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT MAC_V0 is +generic( + Input_SZ_A : integer := 8; + Input_SZ_B : integer := 8 + +); +port( + clk : in std_logic; + reset : in std_logic; + clr_MAC : in std_logic; + MAC_MUL_ADD : in std_logic_vector(1 downto 0); + OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); + OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); + RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) +); +end COMPONENT; + --------------------------------------------------------- --------- // Sélection grace a l'entrée "ctrl" \\ -------- +-------- // Sélection grace a l'entrée "ctrl" \\ -------- --------------------------------------------------------- Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; + + +Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; +Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; +Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; +Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; +Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; --------------------------------------------------------- COMPONENT MAC IS @@ -132,10 +191,10 @@ Constant ctrl_CLRMAC : std_logic_vector( port( clk : in std_logic; --! Horloge du composant reset : in std_logic; --! Reset general du composant - clr : in std_logic; --! Un reset spécifique au programme - TwoComp : in std_logic; --! Autorise l'utilisation du complément - OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée - RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non + clr : in std_logic; --! Un reset spécifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du complément + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée + RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non ); end COMPONENT; diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -1,18 +1,24 @@ +Adder_V0.vhd +Adder.vhd ADDRcntr.vhd +ALU_V0.vhd +ALU_V0.vhd~ ALU.vhd -Adder.vhd Clk_Divider2.vhd +Clk_Divider2.vhd~ Clk_divider.vhd -MAC.vhd +general_purpose.vhd +general_purpose.vhd~ MAC_CONTROLER.vhd +MAC_MUX2.vhd MAC_MUX.vhd -MAC_MUX2.vhd MAC_REG.vhd +MAC_V0.vhd +MAC.vhd +Multiplier.vhd MUX2.vhd MUXN.vhd -Multiplier.vhd REG.vhd +Shifter.vhd SYNC_FF.vhd -Shifter.vhd TwoComplementer.vhd -general_purpose.vhd diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd deleted file mode 100644 --- a/lib/lpp/leon3mp.vhd +++ /dev/null @@ -1,703 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -library techmap; -use techmap.gencomp.all; -library gaisler; -use gaisler.memctrl.all; -use gaisler.leon3.all; -use gaisler.uart.all; -use gaisler.misc.all; -library esa; -use esa.memoryctrl.all; -use work.config.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.lpp_memory.all; -use lpp.lpp_uart.all; -use lpp.lpp_matrix.all; -use lpp.lpp_delay.all; -use lpp.lpp_fft.all; -use lpp.fft_components.all; -use lpp.lpp_ad_conv.all; -use lpp.iir_filter.all; -use lpp.general_purpose.all; -use lpp.Filtercfg.all; -use lpp.lpp_demux.all; -use lpp.lpp_top_lfr_pkg.all; -use lpp.lpp_dma_pkg.all; -use lpp.lpp_Header.all; - -entity leon3mp is - generic ( - fabtech : integer := CFG_FABTECH; - memtech : integer := CFG_MEMTECH; - padtech : integer := CFG_PADTECH; - clktech : integer := CFG_CLKTECH; - disas : integer := CFG_DISAS; -- Enable disassembly to console - dbguart : integer := CFG_DUART; -- Print UART on console - pclow : integer := CFG_PCLOW - ); - port ( - clk50MHz : in std_ulogic; - reset : in std_ulogic; - ramclk : out std_logic; - - ahbrxd : in std_ulogic; -- DSU rx data - ahbtxd : out std_ulogic; -- DSU tx data - dsubre : in std_ulogic; - dsuact : out std_ulogic; - urxd1 : in std_ulogic; -- UART1 rx data - utxd1 : out std_ulogic; -- UART1 tx data - errorn : out std_ulogic; - - address : out std_logic_vector(18 downto 0); - data : inout std_logic_vector(31 downto 0); - gpio : inout std_logic_vector(6 downto 0); -- I/O port - - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - SSRAM_CLK : out std_logic; - ZZ : out std_logic; ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------In/Out----------------------- ---------------------------------------------------------------------- --- UART - UART_RXD : in std_logic; - UART_TXD : out std_logic; --- ACQ - CNV_CH1 : OUT STD_LOGIC; - SCK_CH1 : OUT STD_LOGIC; - SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - Bias_Fails : out std_logic; --- ADC --- ADC_in : in AD7688_in(4 downto 0); --- ADC_out : out AD7688_out; - --- CNA --- DAC_SYNC : out std_logic; --- DAC_SCLK : out std_logic; --- DAC_DATA : out std_logic; --- Diver - SPW1_EN : out std_logic; - SPW2_EN : out std_logic; - TEST : out std_logic_vector(3 downto 0); - - BP : in std_logic; ---------------------------------------------------------------------- - led : out std_logic_vector(1 downto 0) - ); -end; - -architecture Behavioral of leon3mp is - -constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA -constant maxahbm : integer := maxahbmsp; - ---Clk & Rst géné -signal vcc : std_logic_vector(4 downto 0); -signal gnd : std_logic_vector(4 downto 0); -signal resetnl : std_ulogic; -signal clk2x : std_ulogic; -signal lclk : std_ulogic; -signal lclk2x : std_ulogic; -signal clkm : std_ulogic; -signal rstn : std_ulogic; -signal rstraw : std_ulogic; -signal pciclk : std_ulogic; -signal sdclkl : std_ulogic; -signal cgi : clkgen_in_type; -signal cgo : clkgen_out_type; ---- AHB / APB -signal apbi : apb_slv_in_type; -signal apbo : apb_slv_out_vector := (others => apb_none); -signal ahbsi : ahb_slv_in_type; -signal ahbso : ahb_slv_out_vector := (others => ahbs_none); -signal ahbmi : ahb_mst_in_type; -signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); ---UART -signal ahbuarti : uart_in_type; -signal ahbuarto : uart_out_type; -signal apbuarti : uart_in_type; -signal apbuarto : uart_out_type; ---MEM CTRLR -signal memi : memory_in_type; -signal memo : memory_out_type; -signal wpo : wprot_out_type; -signal sdo : sdram_out_type; ---IRQ -signal irqi : irq_in_vector(0 to CFG_NCPU-1); -signal irqo : irq_out_vector(0 to CFG_NCPU-1); ---Timer -signal gpti : gptimer_in_type; -signal gpto : gptimer_out_type; ---GPIO -signal gpioi : gpio_in_type; -signal gpioo : gpio_out_type; ---DSU -signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); -signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); -signal dsui : dsu_in_type; -signal dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- --- FIFOs -signal FifoF0_Empty : std_logic_vector(4 downto 0); -signal FifoF0_Data : std_logic_vector(79 downto 0); -signal FifoF1_Empty : std_logic_vector(4 downto 0); -signal FifoF1_Data : std_logic_vector(79 downto 0); -signal FifoF3_Empty : std_logic_vector(4 downto 0); -signal FifoF3_Data : std_logic_vector(79 downto 0); - -signal FifoINT_Full : std_logic_vector(4 downto 0); -signal FifoINT_Data : std_logic_vector(79 downto 0); - -signal FifoOUT_Full : std_logic_vector(1 downto 0); -signal FifoOUT_Empty : std_logic_vector(1 downto 0); -signal FifoOUT_Data : std_logic_vector(63 downto 0); - - --- MATRICE SPECTRALE -signal SM_FlagError : std_logic; -signal SM_Pong : std_logic; -signal SM_Wen : std_logic; -signal SM_Read : std_logic_vector(4 downto 0); -signal SM_Write : std_logic_vector(1 downto 0); -signal SM_ReUse : std_logic_vector(4 downto 0); -signal SM_Param : std_logic_vector(3 downto 0); -signal SM_Data : std_logic_vector(63 downto 0); - ---signal Dma_acq : std_logic; ---signal Head_Valid : std_logic; - --- FFT -signal FFT_Load : std_logic; -signal FFT_Read : std_logic_vector(4 downto 0); -signal FFT_Write : std_logic_vector(4 downto 0); -signal FFT_ReUse : std_logic_vector(4 downto 0); -signal FFT_Data : std_logic_vector(79 downto 0); - --- DEMUX -signal DMUX_Read : std_logic_vector(14 downto 0); -signal DMUX_Empty : std_logic_vector(4 downto 0); -signal DMUX_Data : std_logic_vector(79 downto 0); -signal DMUX_WorkFreq : std_logic_vector(1 downto 0); - --- ACQ -signal sample_val : STD_LOGIC; -signal sample : Samples(8-1 DOWNTO 0); - -signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - --- Header -signal Head_Read : std_logic_vector(1 downto 0); -signal Head_Data : std_logic_vector(31 downto 0); -signal Head_Empty : std_logic; -signal Head_Header : std_logic_vector(31 DOWNTO 0); -signal Head_Valid : std_logic; -signal Head_Val : std_logic; - ---DMA -signal DMA_Read : std_logic; -signal DMA_ack : std_logic; ---signal AHB_Master_In : AHB_Mst_In_Type; ---signal AHB_Master_Out : AHB_Mst_Out_Type; - - --- ADC ---signal SmplClk : std_logic; ---signal ADC_DataReady : std_logic; ---signal ADC_SmplOut : Samples_out(4 downto 0); ---signal enableADC : std_logic; --- ---signal WG_Write : std_logic_vector(4 downto 0); ---signal WG_ReUse : std_logic_vector(4 downto 0); ---signal WG_DATA : std_logic_vector(79 downto 0); ---signal s_out : std_logic_vector(79 downto 0); --- ---signal fuller : std_logic_vector(4 downto 0); ---signal reader : std_logic_vector(4 downto 0); ---signal try : std_logic_vector(1 downto 0); ---signal TXDint : std_logic; --- ----- IIR Filter ---signal sample_clk_out : std_logic; --- ---signal Rd : std_logic_vector(0 downto 0); ---signal Ept : std_logic_vector(4 downto 0); --- ---signal Bwr : std_logic_vector(0 downto 0); ---signal Bre : std_logic_vector(0 downto 0); ---signal DataTMP : std_logic_vector(15 downto 0); ---signal FullUp : std_logic_vector(0 downto 0); ---signal EmptyUp : std_logic_vector(0 downto 0); ---signal FullDown : std_logic_vector(0 downto 0); ---signal EmptyDown : std_logic_vector(0 downto 0); ---------------------------------------------------------------------- -constant IOAEN : integer := CFG_CAN; -constant boardfreq : integer := 50000; - -begin - ---------------------------------------------------------------------- ---- AJOUT TEST -------------------------------------IPs------------- ---------------------------------------------------------------------- -led(1 downto 0) <= gpio(1 downto 0); - ---- COM USB --------------------------------------------------------- --- MemIn0 : APB_FifoWrite --- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) --- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); --- --- BUF0 : APB_USB --- generic map (6,6,DataMax => 1024) --- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); --- --- MemOut0 : APB_FifoRead --- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) --- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); --- ---slrd <= usb_Read; ---slwr <= usb_Write; - ---- CNA ------------------------------------------------------------- - --- CONV : APB_CNA --- generic map (5,5) --- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); - ---TEST(0) <= SmplClk; ---TEST(1) <= WG_Write(0); ---TEST(2) <= Fuller(0); ---TEST(3) <= s_out(s_out'length-1); - - ---SPW1_EN <= '1'; ---SPW2_EN <= '0'; - ---- CAN ------------------------------------------------------------- - --- Divider : Clk_divider --- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) --- Port map(clkm,rstn,SmplClk); --- --- ADC : AD7688_drvr --- generic map (ChanelCount => 5, clkkHz => 24_576) --- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); --- --- WG : WriteGen_ADC --- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); --- ---enableADC <= gpio(0); - ---WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); --- --- --- MemIn1 : APB_FIFO --- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); - --- DIGITAL_acquisition : ADS7886_drvr --- GENERIC MAP ( --- ChanelCount => 8, --- ncycle_cnv_high => 79, --- ncycle_cnv => 500) --- PORT MAP ( --- cnv_clk => clk50MHz, -- --- cnv_rstn => rstn, -- --- cnv_run => '1', -- --- cnv => CNV_CH1, -- --- clk => clkm, -- --- rstn => rstn, -- --- sck => SCK_CH1, -- --- sdo => SDO_CH1, -- --- sample => sample, --- sample_val => sample_val); --- ---TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val; ---TopACQ_DataF0 <= E & D & C & B & A; - --- ---TEST(0) <= TopACQ_WenF0(1); ---TEST(1) <= SDO_CH1(1); --- ---process(clkm,rstn) ---begin --- if(rstn='0')then --- TopACQ_WenF0a <= (others => '1'); --- --- elsif(clkm'event and clkm='1')then --- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; --- --- end if; ---end process; - - ACQ0 : lpp_top_acq - port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); - -Bias_Fails <= '0'; ---------- FIFO IN ------------------------------------------------------------- ----- --- Memf0 : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9)); --- --- Memf1 : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8)); --- --- Memf3 : APB_FIFO --- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5)); - - Memf0 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); - - Memf1 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); - - Memf3 : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); --- ------ DEMUX ------------------------------------------------------------- - - DMUX0 : DEMUX - generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); - -------- FFT ------------------------------------------------------------- - --- MemIn : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8)); - - FFT0 : FFT - generic map(Data_sz => 16,NbData => 256) - port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); - ---------- LINK MEMORY ------------------------------------------------------- - --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); - - MemInt : lppFIFOxN - generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') - port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); - --- MemIn : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); - ------ MATRICE SPECTRALE ---------------------5 FIFO Input--------------- - - SM0 : MatriceSpectrale - generic map(Input_SZ => 16,Result_SZ => 32) - port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); - - ---DMA_ack <= '1'; ---Head_Valid <= '1'; - --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); - - MemOut : lppFIFOxN - generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); - ------------ Header ------------------------------------------------------- - - Head0 : HeaderBuilder - generic map(Data_sz => 32) - port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); - - ---- DMA ------------------------------------------------------- - - DMA0 : lpp_dma - generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH) - port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); - - ------ FIFO ------------------------------------------------------------- - --- Memtest : APB_FIFO --- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); - ---***************************************TEST DEMI-FIFO******************************************************************************** --- MemIn : APB_FIFO --- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); --- --- Pont : Bridge --- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); --- --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); ---************************************************************************************************************************************* - ---- UART ------------------------------------------------------------- - - COM0 : APB_UART - generic map (pindex => 4, paddr => 4) - port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); - ---- DELAY ------------------------------------------------------------ - --- Delay0 : APB_Delay --- generic map (pindex => 4, paddr => 4) --- port map (clkm,rstn,apbi,apbo(4)); - ---- IIR Filter ------------------------------------------------------- ---Test(0) <= sample_clk_out; --- --- --- IIR1: APB_IIR_Filter --- generic map( --- tech => CFG_MEMTECH, --- pindex => 8, --- paddr => 8, --- Sample_SZ => Sample_SZ, --- ChanelsCount => ChanelsCount, --- Coef_SZ => Coef_SZ, --- CoefCntPerCel => CoefCntPerCel, --- Cels_count => Cels_count, --- virgPos => virgPos --- ) --- port map( --- rst => rstn, --- clk => clkm, --- apbi => apbi, --- apbo => apbo(8), --- sample_clk_out => sample_clk_out, --- GOtest => Test(1), --- CoefsInitVal => (others => '1') --- ); ----------------------------------------------------------------------- - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (others => '1'); gnd <= (others => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); - - clkgen0 : clkgen -- clock generator - generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); - - ramclk <= clkm; -process(lclk2x) -begin - if lclk2x'event and lclk2x = '1' then - lclk <= not lclk; - end if; -end process; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : if CFG_LEON3 = 1 generate - cpu : for i in 0 to CFG_NCPU-1 generate - u0 : leon3s -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; - errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); - - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); --- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); - dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); - end generate; - end generate; - - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; - - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); - end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate - x : for i in 0 to CFG_NCPU-1 generate - irqi(i).irl <= "0000"; - end generate; - apbo(2) <= apb_none; - end generate; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - - memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) - port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); - - memi.brdyn <= '1'; memi.bexcn <= '1'; - memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; - - bdr : for i in 0 to 3 generate - data_pad : iopadv generic map (tech => padtech, width => 8) - port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), - memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); - end generate; - - - addr_pad : outpadv generic map (width => 19, tech => padtech) - port map (address, memo.address(20 downto 2)); - - - SSRAM_0:entity ssram_plugin - generic map (tech => padtech) - port map - (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - - ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => 2, pindex => 7, paddr => 7) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(2)); - dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); --- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; - end generate; - nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - - apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR) - port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - - gpt : if CFG_GPT_ENABLE /= 0 generate - timer0 : gptimer -- timer unit - generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - port map (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; --- led(4) <= gpto.wdog; - end generate; - notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - - ua1 : if CFG_UART1_ENABLE /= 0 generate - uart1 : apbuart -- UART 1 - generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); - apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; --- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; - end generate; - noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - ----------------------------------------------------------------------- ---- GPIO ----------------------------------------------------------- ----------------------------------------------------------------------- - - gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit - grgpio0: grgpio - generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) - port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); - - pio_pads : for i in 0 to 6 generate - pio_pad : iopad generic map (tech => padtech) - port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); - end generate; - end generate; - - -end Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd @@ -1,198 +1,114 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- --- MODIFIED by Jean-christophe PELLION --- jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.general_purpose.SYNC_FF; - -ENTITY AD7688_drvr IS - GENERIC( - ChanelCount : INTEGER; - ncycle_cnv_high : INTEGER := 79; - ncycle_cnv : INTEGER := 500); - PORT ( - -- CONV -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - - -- DATA -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - - sample : OUT Samples(ChanelCount-1 DOWNTO 0); - sample_val : OUT STD_LOGIC - ); -END AD7688_drvr; - -ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS - - COMPONENT SYNC_FF - GENERIC ( - NB_FF_OF_SYNC : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - A : IN STD_LOGIC; - A_sync : OUT STD_LOGIC); - END COMPONENT; - - - SIGNAL cnv_cycle_counter : INTEGER; - SIGNAL cnv_s : STD_LOGIC; - SIGNAL cnv_sync : STD_LOGIC; - SIGNAL cnv_sync_r : STD_LOGIC; - SIGNAL cnv_done : STD_LOGIC; - SIGNAL sample_bit_counter : INTEGER; - SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); - - SIGNAL cnv_run_sync : STD_LOGIC; - -BEGIN - ----------------------------------------------------------------------------- - -- CONV - ----------------------------------------------------------------------------- - PROCESS (cnv_clk, cnv_rstn) - BEGIN -- PROCESS - IF cnv_rstn = '0' THEN -- asynchronous reset (active low) - cnv_cycle_counter <= 0; - cnv_s <= '0'; - ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge - IF cnv_run = '1' THEN - IF cnv_cycle_counter < ncycle_cnv THEN - cnv_cycle_counter <= cnv_cycle_counter +1; - IF cnv_cycle_counter < ncycle_cnv_high THEN - cnv_s <= '1'; - ELSE - cnv_s <= '0'; - END IF; - ELSE - cnv_s <= '1'; - cnv_cycle_counter <= 0; - END IF; - ELSE - cnv_s <= '0'; - cnv_cycle_counter <= 0; - END IF; - END IF; - END PROCESS; - - cnv <= cnv_s; - - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- SYNC CNV - ----------------------------------------------------------------------------- - - SYNC_FF_cnv : SYNC_FF - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk => clk, - rstn => rstn, - A => cnv_s, - A_sync => cnv_sync); - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - cnv_sync_r <= '0'; - cnv_done <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN - cnv_sync_r <= cnv_sync; - cnv_done <= (NOT cnv_sync) AND cnv_sync_r; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - SYNC_FF_run : SYNC_FF - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk => clk, - rstn => rstn, - A => cnv_run, - A_sync => cnv_run_sync); - - - - ----------------------------------------------------------------------------- - -- DATA - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN - FOR l IN 0 TO ChanelCount-1 LOOP - shift_reg(l) <= (OTHERS => '0'); - sample(l)(15 DOWNTO 0) <= (OTHERS => '0'); - END LOOP; - sample_bit_counter <= 0; - sample_val <= '0'; - SCK <= '1'; - - ELSIF clk'EVENT AND clk = '1' THEN - - IF cnv_run_sync = '0' THEN - sample_bit_counter <= 0; - ELSIF cnv_done = '1' THEN - sample_bit_counter <= 1; - ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN - sample_bit_counter <= sample_bit_counter + 1; - END IF; - - IF (sample_bit_counter MOD 2) = 1 THEN - FOR l IN 0 TO ChanelCount-1 LOOP - --shift_reg(l)(15) <= sdo(l); - --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); - shift_reg(l)(0) <= sdo(l); - shift_reg(l)(14 DOWNTO 1) <= shift_reg(l)(13 DOWNTO 0); - END LOOP; - SCK <= '0'; - ELSE - SCK <= '1'; - END IF; - - IF sample_bit_counter = 31 THEN - sample_val <= '1'; - FOR l IN 0 TO ChanelCount-1 LOOP - --sample(l)(15) <= sdo(l); - --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); - sample(l)(0) <= sdo(l); - sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); - END LOOP; - ELSE - sample_val <= '0'; - END IF; - END IF; - END PROCESS; - -END ar_AD7688_drvr; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library lpp; +use lpp.lpp_ad_conv.all; +use lpp.general_purpose.Clk_divider; + +--! \brief AD7688 driver, generates all needed signal to drive this ADC. +--! +--! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr + +entity AD7688_drvr is +generic( + ChanelCount :integer; --! Number of ADC you whant to drive + clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width. + ); +Port( + clk : in STD_LOGIC; --! System clock + rstn : in STD_LOGIC; --! System reset + enable : in std_logic; --! Negative enable + smplClk : in STD_LOGIC; --! Sampling clock + DataReady : out std_logic; --! New sample available + smpout : out Samples(ChanelCount-1 downto 0); --! Samples + AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv + AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv +); +end AD7688_drvr; + +architecture ar_AD7688_drvr of AD7688_drvr is + +constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs + +signal i : integer range 0 to convTrigger :=0; +signal clk_int : std_logic; +signal clk_int_inv : std_logic; +signal smplClk_reg : std_logic; +signal cnv_int : std_logic; +signal reset : std_logic; + +begin + +clkdiv: if clkkHz>=66000 generate + clkdivider: entity work.Clk_divider + generic map(clkkHz*1000,60000000) + Port map( clk ,reset,clk_int); +end generate; + +clknodiv: if clkkHz<66000 generate +nodiv: clk_int <= clk; +end generate; + +clk_int_inv <= not clk_int; + +AD_out.CNV <= cnv_int; +AD_out.SCK <= clk_int; +reset <= rstn and enable; + +sckgen: process(clk,reset) +begin + if reset = '0' then + i <= 0; + cnv_int <= '0'; + smplClk_reg <= '0'; + elsif clk'event and clk = '1' then + if smplClk = '1' and smplClk_reg = '0' then + if i = convTrigger then + smplClk_reg <= '1'; + i <= 0; + cnv_int <= '0'; + else + i <= i+1; + cnv_int <= '1'; + end if; + elsif smplClk = '0' and smplClk_reg = '1' then + smplClk_reg <= '0'; + end if; + end if; +end process; + + + +spidrvr: entity work.AD7688_spi_if + generic map(ChanelCount) + Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout); + + + +end ar_AD7688_drvr; + + + + + + diff --git a/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd b/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_spi_if.vhd @@ -32,13 +32,13 @@ entity AD7688_spi_if is cnv : in STD_LOGIC; DataReady : out std_logic; sdi : in AD7688_in(ChanelCount-1 downto 0); - smpout : out Samples_out(ChanelCount-1 downto 0) + smpout : out Samples(ChanelCount-1 downto 0) ); end AD7688_spi_if; architecture ar_AD7688_spi_if of AD7688_spi_if is -signal shift_reg : Samples_out(ChanelCount-1 downto 0); +signal shift_reg : Samples(ChanelCount-1 downto 0); signal i : integer range 0 to 16 :=0; signal cnv_reg : std_logic := '0'; diff --git a/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd b/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/dual_ADS1278_drvr.vhd @@ -10,13 +10,17 @@ use lpp.general_purpose.all; -entity DUAL_ADS1278_DRIVER is +entity DUAL_ADS1278_DRIVER is +generic +( + SCLKDIV : integer range 2 to 256 :=16 +); port( - Clk : in std_logic; - reset : in std_logic; - SpiClk : out std_logic; - DIN : in std_logic_vector(1 downto 0); - SmplClk : in std_logic; + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(1 downto 0); + SmplClk : in std_logic; OUT00 : out std_logic_vector(23 downto 0); OUT01 : out std_logic_vector(23 downto 0); OUT02 : out std_logic_vector(23 downto 0); @@ -33,7 +37,7 @@ port( OUT15 : out std_logic_vector(23 downto 0); OUT16 : out std_logic_vector(23 downto 0); OUT17 : out std_logic_vector(23 downto 0); - FSynch : out std_logic + FSynch : out std_logic ); end DUAL_ADS1278_DRIVER; @@ -43,10 +47,9 @@ end DUAL_ADS1278_DRIVER; architecture ar_DUAL_ADS1278_DRIVER of DUAL_ADS1278_DRIVER is - -signal Vec00,Vec01,Vec02,Vec03,Vec04,Vec05,Vec06,Vec07,Vec10,Vec11,Vec12,Vec13,Vec14,Vec15,Vec16,Vec17 : std_logic_vector(23 downto 0); +signal ShiftGeg0,ShiftGeg1 : std_logic_vector((8*24)-1 downto 0); signal SmplClk_Reg : std_logic:= '0'; -signal N : integer range 0 to 23*8 := 0; +signal N : integer range 0 to (24*8) := 0; signal SPI_CLk : std_logic; signal SmplClk_clkd : std_logic:= '0'; @@ -54,97 +57,24 @@ begin CLKDIV0 : Clk_Divider2 -generic map(16) +generic map(SCLKDIV) port map(Clk,SPI_CLk); - -FSynch <= SmplClk_clkd; -SpiClk <= SPI_CLk; +SpiClk <= not SPI_CLk; process(reset,SPI_CLk) begin if reset = '0' then - Vec00 <= (others => '0'); - Vec01 <= (others => '0'); - Vec02 <= (others => '0'); - Vec03 <= (others => '0'); - Vec04 <= (others => '0'); - Vec05 <= (others => '0'); - Vec06 <= (others => '0'); - Vec07 <= (others => '0'); - - Vec10 <= (others => '0'); - Vec11 <= (others => '0'); - Vec12 <= (others => '0'); - Vec13 <= (others => '0'); - Vec14 <= (others => '0'); - Vec15 <= (others => '0'); - Vec16 <= (others => '0'); - Vec17 <= (others => '0'); - N <= 0; + ShiftGeg0 <= (others => '0'); + ShiftGeg1 <= (others => '0'); + N <= 0; elsif SPI_CLk'event and SPI_CLk = '1' then --- SmplClk_clkd <= SmplClk; --- SmplClk_Reg <= SmplClk_clkd; - --if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then - if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then - --Vec0(0) <= DIN(0); - --Vec1(0) <= DIN(1); - --Vec2(0) <= DIN(2); - --Vec3(0) <= DIN(3); - --Vec0(23 downto 1) <= Vec0(22 downto 0); - --Vec1(23 downto 1) <= Vec1(22 downto 0); - --Vec2(23 downto 1) <= Vec2(22 downto 0); - --Vec3(23 downto 1) <= Vec3(22 downto 0); - Vec00(0) <= DIN(0); - Vec00(23 downto 1) <= Vec00(22 downto 0); - Vec01(0) <= Vec00(23); - - Vec01(23 downto 1) <= Vec01(22 downto 0); - Vec02(0) <= Vec01(23); - - Vec02(23 downto 1) <= Vec02(22 downto 0); - Vec03(0) <= Vec02(23); - - Vec03(23 downto 1) <= Vec03(22 downto 0); - Vec04(0) <= Vec03(23); - - Vec04(23 downto 1) <= Vec04(22 downto 0); - Vec05(0) <= Vec04(23); - - Vec05(23 downto 1) <= Vec05(22 downto 0); - Vec06(0) <= Vec05(23); - - Vec06(23 downto 1) <= Vec06(22 downto 0); - Vec07(0) <= Vec06(23); - - Vec07(23 downto 1) <= Vec07(22 downto 0); - - - Vec10(0) <= DIN(1); - Vec10(23 downto 1) <= Vec10(22 downto 0); - Vec11(0) <= Vec10(23); - - Vec11(23 downto 1) <= Vec11(22 downto 0); - Vec12(0) <= Vec11(23); - - Vec12(23 downto 1) <= Vec12(22 downto 0); - Vec13(0) <= Vec12(23); - - Vec13(23 downto 1) <= Vec13(22 downto 0); - Vec14(0) <= Vec13(23); - - Vec14(23 downto 1) <= Vec14(22 downto 0); - Vec15(0) <= Vec14(23); - - Vec15(23 downto 1) <= Vec15(22 downto 0); - Vec16(0) <= Vec15(23); - - Vec16(23 downto 1) <= Vec16(22 downto 0); - Vec17(0) <= Vec16(23); - - Vec17(23 downto 1) <= Vec17(22 downto 0); - if N = (23*8) then + FSynch <= SmplClk; + if ((SmplClk_clkd = '1' and SmplClk_Reg = '0') or (N /= 0)) then + ShiftGeg0((8*24)-1 downto 0) <= ShiftGeg0((8*24)-2 downto 0) & DIN(0); + ShiftGeg1((8*24)-1 downto 0) <= ShiftGeg1((8*24)-2 downto 0) & DIN(1); + if N = ((24*8)-1) then N <= 0; else N <= N+1; @@ -163,27 +93,45 @@ begin end process; -process(SPI_CLk) -begin - if SPI_CLk'event and SPI_CLk ='1' then +process(clk,reset) +begin + if reset = '0' then + OUT00 <= (others => '0'); + OUT01 <= (others => '0'); + OUT02 <= (others => '0'); + OUT03 <= (others => '0'); + OUT04 <= (others => '0'); + OUT05 <= (others => '0'); + OUT06 <= (others => '0'); + OUT07 <= (others => '0'); + + OUT10 <= (others => '0'); + OUT11 <= (others => '0'); + OUT12 <= (others => '0'); + OUT13 <= (others => '0'); + OUT14 <= (others => '0'); + OUT15 <= (others => '0'); + OUT16 <= (others => '0'); + OUT17 <= (others => '0'); + elsif clk'event and clk ='1' then if N = 0 then - OUT00 <= Vec00; - OUT01 <= Vec01; - OUT02 <= Vec02; - OUT03 <= Vec03; - OUT04 <= Vec04; - OUT05 <= Vec05; - OUT06 <= Vec06; - OUT07 <= Vec07; + OUT00 <= ShiftGeg0((24*1)-1 downto (24*(1-1))); + OUT01 <= ShiftGeg0((24*2)-1 downto (24*(2-1))); + OUT02 <= ShiftGeg0((24*3)-1 downto (24*(3-1))); + OUT03 <= ShiftGeg0((24*4)-1 downto (24*(4-1))); + OUT04 <= ShiftGeg0((24*5)-1 downto (24*(5-1))); + OUT05 <= ShiftGeg0((24*6)-1 downto (24*(6-1))); + OUT06 <= ShiftGeg0((24*7)-1 downto (24*(7-1))); + OUT07 <= ShiftGeg0((24*8)-1 downto (24*(8-1))); - OUT10 <= Vec10; - OUT11 <= Vec11; - OUT12 <= Vec12; - OUT13 <= Vec13; - OUT14 <= Vec14; - OUT15 <= Vec15; - OUT16 <= Vec16; - OUT17 <= Vec17; + OUT10 <= ShiftGeg1((24*1)-1 downto (24*(1-1))); + OUT11 <= ShiftGeg1((24*2)-1 downto (24*(2-1))); + OUT12 <= ShiftGeg1((24*3)-1 downto (24*(3-1))); + OUT13 <= ShiftGeg1((24*4)-1 downto (24*(4-1))); + OUT14 <= ShiftGeg1((24*5)-1 downto (24*(5-1))); + OUT15 <= ShiftGeg1((24*6)-1 downto (24*(6-1))); + OUT16 <= ShiftGeg1((24*7)-1 downto (24*(7-1))); + OUT17 <= ShiftGeg1((24*8)-1 downto (24*(8-1))); end if; end if; end process; diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd --- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd @@ -35,46 +35,22 @@ PACKAGE lpp_ad_conv IS --CONSTANT ADS7886 : INTEGER := 1; - --TYPE AD7688_out IS - --RECORD - -- CNV : STD_LOGIC; - -- SCK : STD_LOGIC; - --END RECORD; + TYPE AD7688_out IS + RECORD + CNV : STD_LOGIC; + SCK : STD_LOGIC; + END RECORD; - --TYPE AD7688_in_element IS - --RECORD - -- SDI : STD_LOGIC; - --END RECORD; + TYPE AD7688_in_element IS + RECORD + SDI : STD_LOGIC; + END RECORD; - --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; + TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); - SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0); - - SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0); - - SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0); - - SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0); - - SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0); - - SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0); - - TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24; - - TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16; - - TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14; - - TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12; - - TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10; - - TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8; - - COMPONENT AD7688_drvr + COMPONENT ADS7886_drvr GENERIC ( ChanelCount : INTEGER; ncycle_cnv_high : INTEGER := 79; @@ -82,7 +58,7 @@ PACKAGE lpp_ad_conv IS PORT ( cnv_clk : IN STD_LOGIC; cnv_rstn : IN STD_LOGIC; - cnv_run : IN STD_LOGIC; + cnv_run : IN STD_LOGIC; cnv : OUT STD_LOGIC; clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -91,92 +67,32 @@ PACKAGE lpp_ad_conv IS sample : OUT Samples(ChanelCount-1 DOWNTO 0); sample_val : OUT STD_LOGIC); END COMPONENT; - - COMPONENT RHF1401_drvr IS - GENERIC( - ChanelCount : INTEGER := 8); - PORT ( - cnv_clk : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - ADC_data : IN Samples14; - --ADC_smpclk : OUT STD_LOGIC; - ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); - sample_val : OUT STD_LOGIC - ); - END COMPONENT; - - COMPONENT top_ad_conv_RHF1401 - GENERIC ( - ChanelCount : INTEGER; - ncycle_cnv_high : INTEGER := 79; - ncycle_cnv : INTEGER := 500); - PORT ( - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - ADC_data : IN Samples14; - ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); - sample_val : OUT STD_LOGIC); + + COMPONENT AD7688_drvr IS + GENERIC(ChanelCount : INTEGER; + clkkHz : INTEGER); + PORT (clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + enable : IN STD_LOGIC; + smplClk : IN STD_LOGIC; + DataReady : OUT STD_LOGIC; + smpout : OUT Samples(ChanelCount-1 DOWNTO 0); + AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); + AD_out : OUT AD7688_out); END COMPONENT; - COMPONENT AD7688_drvr_sync - GENERIC ( - ChanelCount : INTEGER; - ncycle_cnv_high : INTEGER; - ncycle_cnv : INTEGER); - PORT ( - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - sample : OUT Samples(ChanelCount-1 DOWNTO 0); - sample_val : OUT STD_LOGIC); - END COMPONENT; - - COMPONENT TestModule_RHF1401 - GENERIC ( - freq : INTEGER; - amplitude : INTEGER; - impulsion : INTEGER); - PORT ( - ADC_smpclk : IN STD_LOGIC; - ADC_OEB_bar : IN STD_LOGIC; - ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)); + COMPONENT AD7688_spi_if IS + GENERIC(ChanelCount : INTEGER); + PORT(clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + cnv : IN STD_LOGIC; + DataReady : OUT STD_LOGIC; + sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); + smpout : OUT Samples(ChanelCount-1 DOWNTO 0) + ); END COMPONENT; - --COMPONENT AD7688_drvr IS - -- GENERIC(ChanelCount : INTEGER; - -- clkkHz : INTEGER); - -- PORT (clk : IN STD_LOGIC; - -- rstn : IN STD_LOGIC; - -- enable : IN STD_LOGIC; - -- smplClk : IN STD_LOGIC; - -- DataReady : OUT STD_LOGIC; - -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); - -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); - -- AD_out : OUT AD7688_out); - --END COMPONENT; - - - --COMPONENT AD7688_spi_if IS - -- GENERIC(ChanelCount : INTEGER); - -- PORT(clk : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- cnv : IN STD_LOGIC; - -- DataReady : OUT STD_LOGIC; - -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); - -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0) - -- ); - --END COMPONENT; - --COMPONENT lpp_apb_ad_conv -- GENERIC( @@ -229,72 +145,72 @@ PACKAGE lpp_ad_conv IS --======================= ADS 127X =========================| --===========================================================| - TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC; - CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010"; - CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101"; +Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic; +constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010"; +constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101"; - TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC; - CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10"; - CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11"; - CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01"; +Type ADS127X_MODE_Type is array(1 downto 0) of std_logic; +constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10"; +constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11"; +constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01"; - TYPE ADS127X_config IS - RECORD - SYNC : STD_LOGIC; - CLKDIV : STD_LOGIC; - FORMAT : ADS127X_FORMAT_Type; - MODE : ADS127X_MODE_Type; - END RECORD; +Type ADS127X_config is + record + SYNC : std_logic; + CLKDIV : std_logic; + FORMAT : ADS127X_FORMAT_Type; + MODE : ADS127X_MODE_Type; +end record; - COMPONENT ADS1274_DRIVER IS - GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); - PORT( - Clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - SpiClk : OUT STD_LOGIC; - DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - Ready : IN STD_LOGIC; - Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - ClkDiv : OUT STD_LOGIC; - PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SmplClk : IN STD_LOGIC; - OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - FSynch : OUT STD_LOGIC; - test : OUT STD_LOGIC - ); - END COMPONENT; +COMPONENT ADS1274_DRIVER is +generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); +port( + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(3 downto 0); + Ready : in std_logic; + Format : out std_logic_vector(2 downto 0); + Mode : out std_logic_vector(1 downto 0); + ClkDiv : out std_logic; + PWDOWN : out std_logic_vector(3 downto 0); + SmplClk : in std_logic; + OUT0 : out std_logic_vector(23 downto 0); + OUT1 : out std_logic_vector(23 downto 0); + OUT2 : out std_logic_vector(23 downto 0); + OUT3 : out std_logic_vector(23 downto 0); + FSynch : out std_logic; + test : out std_logic +); +end COMPONENT; -- todo clean file - COMPONENT DUAL_ADS1278_DRIVER IS - PORT( - Clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - SpiClk : OUT STD_LOGIC; - DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - SmplClk : IN STD_LOGIC; - OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - FSynch : OUT STD_LOGIC - ); - END COMPONENT; +COMPONENT DUAL_ADS1278_DRIVER is +port( + Clk : in std_logic; + reset : in std_logic; + SpiClk : out std_logic; + DIN : in std_logic_vector(1 downto 0); + SmplClk : in std_logic; + OUT00 : out std_logic_vector(23 downto 0); + OUT01 : out std_logic_vector(23 downto 0); + OUT02 : out std_logic_vector(23 downto 0); + OUT03 : out std_logic_vector(23 downto 0); + OUT04 : out std_logic_vector(23 downto 0); + OUT05 : out std_logic_vector(23 downto 0); + OUT06 : out std_logic_vector(23 downto 0); + OUT07 : out std_logic_vector(23 downto 0); + OUT10 : out std_logic_vector(23 downto 0); + OUT11 : out std_logic_vector(23 downto 0); + OUT12 : out std_logic_vector(23 downto 0); + OUT13 : out std_logic_vector(23 downto 0); + OUT14 : out std_logic_vector(23 downto 0); + OUT15 : out std_logic_vector(23 downto 0); + OUT16 : out std_logic_vector(23 downto 0); + OUT17 : out std_logic_vector(23 downto 0); + FSynch : out std_logic +); +end COMPONENT; END lpp_ad_conv; diff --git a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt --- a/lib/lpp/lpp_ad_Conv/vhdlsyn.txt +++ b/lib/lpp/lpp_ad_Conv/vhdlsyn.txt @@ -1,13 +1,19 @@ +AD7688_drvr_sync.vhd AD7688_drvr.vhd -AD7688_drvr_sync.vhd +AD7688_drvr.vhd.orig AD7688_spi_if.vhd ADS1274_drvr.vhd +ADS1274_drvr.vhd~ ADS1278_drvr.vhd +ADS1278_drvr.vhd~ ADS7886_drvr.vhd -RHF1401.vhd -WriteGen_ADC.vhd dual_ADS1278_drvr.vhd +dual_ADS1278_drvr.vhd~ lpp_ad_Conv.vhd +lpp_ad_Conv.vhd~ +lpp_ad_Conv.vhd.orig lpp_apb_ad_conv.vhd +RHF1401.vhd +top_ad_conv_RHF1401.vhd top_ad_conv.vhd -top_ad_conv_RHF1401.vhd +WriteGen_ADC.vhd diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt --- a/lib/lpp/lpp_amba/vhdlsyn.txt +++ b/lib/lpp/lpp_amba/vhdlsyn.txt @@ -1,4 +1,4 @@ +apb_devices_list.vhd APB_MULTI_DIODE.vhd APB_SIMPLE_DIODE.vhd -apb_devices_list.vhd lpp_amba.vhd diff --git a/lib/lpp/lpp_bootloader/vhdlsyn.txt b/lib/lpp/lpp_bootloader/vhdlsyn.txt --- a/lib/lpp/lpp_bootloader/vhdlsyn.txt +++ b/lib/lpp/lpp_bootloader/vhdlsyn.txt @@ -1,3 +1,3 @@ bootrom.vhd +lpp_bootloader_pkg.vhd lpp_bootloader.vhd -lpp_bootloader_pkg.vhd diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt --- a/lib/lpp/lpp_dma/vhdlsyn.txt +++ b/lib/lpp/lpp_dma/vhdlsyn.txt @@ -1,8 +1,8 @@ fifo_latency_correction.vhd -lpp_dma.vhd lpp_dma_apbreg.vhd lpp_dma_fsm.vhd lpp_dma_ip.vhd lpp_dma_pkg.vhd lpp_dma_send_16word.vhd lpp_dma_send_1word.vhd +lpp_dma.vhd diff --git a/lib/lpp/lpp_matrix/vhdlsyn.txt b/lib/lpp/lpp_matrix/vhdlsyn.txt --- a/lib/lpp/lpp_matrix/vhdlsyn.txt +++ b/lib/lpp/lpp_matrix/vhdlsyn.txt @@ -4,6 +4,7 @@ APB_Matrix.vhd Dispatch.vhd DriveInputs.vhd GetResult.vhd +lpp_matrix.vhd MatriceSpectrale.vhd MatriceSpectrale.vhd.bak Matrix.vhd @@ -12,6 +13,5 @@ SpectralMatrix.vhd SpectralMatrix.vhd.bak Starter.vhd TopMatrix_PDR.vhd +Top_MatrixSpec.vhd TopSpecMatrix.vhd -Top_MatrixSpec.vhd -lpp_matrix.vhd diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt --- a/lib/lpp/lpp_memory/vhdlsyn.txt +++ b/lib/lpp/lpp_memory/vhdlsyn.txt @@ -2,10 +2,10 @@ APB_FIFO.vhd APB_FIFO.vhd.bak FIFO_pipeline.vhd FillFifo.vhd -SSRAM_plugin.vhd -SSRAM_plugin_vsim.vhd +lpp_FIFO.vhd lppFIFOxN.vhd lppFIFOxN.vhd.bak -lpp_FIFO.vhd lpp_memory.vhd lpp_memory.vhd.bak +SSRAM_plugin.vhd +SSRAM_plugin_vsim.vhd diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -1,15 +1,15 @@ -lpp_lfr.vhd lpp_lfr_apbreg.vhd lpp_lfr_filter.vhd lpp_lfr_ms.vhd lpp_lfr_pkg.vhd +lpp_lfr.vhd lpp_top_acq.vhd lpp_top_acq.vhd.bak lpp_top_apbreg.vhd -lpp_top_lfr.vhd lpp_top_lfr_pkg.vhd lpp_top_lfr_pkg.vhd.bak -lpp_top_lfr_wf_picker.vhd +lpp_top_lfr.vhd lpp_top_lfr_wf_picker_ip.vhd lpp_top_lfr_wf_picker_ip_whitout_filter.vhd +lpp_top_lfr_wf_picker.vhd top_wf_picker.vhd diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt --- a/lib/lpp/lpp_waveform/vhdlsyn.txt +++ b/lib/lpp/lpp_waveform/vhdlsyn.txt @@ -1,13 +1,13 @@ -lpp_waveform.vhd lpp_waveform_burst.vhd -lpp_waveform_dma.vhd lpp_waveform_dma_genvalid.vhd lpp_waveform_dma_selectaddress.vhd lpp_waveform_dma_send_Nword.vhd -lpp_waveform_fifo.vhd +lpp_waveform_dma.vhd lpp_waveform_fifo_arbiter.vhd lpp_waveform_fifo_ctrl.vhd +lpp_waveform_fifo.vhd lpp_waveform_pkg.vhd +lpp_waveform_snapshot_controler.vhd lpp_waveform_snapshot.vhd -lpp_waveform_snapshot_controler.vhd lpp_waveform_valid_ack.vhd +lpp_waveform.vhd