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-- Vectorize.vhd
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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entity Vectorize is
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port(
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clk,raz : in std_logic;
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sclk : in std_logic;
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RDY : in std_logic;
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In1,In2,In3 : in std_logic;
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bit : out std_logic;
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Vector_1,Vector_2,Vector_3 : out std_logic_vector(23 downto 0));
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end Vectorize;
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architecture ar_Vectorize of Vectorize is
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type etat is (e0,e1,e2);
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signal ect : etat;
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signal rdy_reg : std_logic;
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signal sclk_reg : std_logic;
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signal cpt : integer range 0 to 24;
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signal Vect_1 : std_logic_vector(23 downto 0);
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signal Vect_2 : std_logic_vector(23 downto 0);
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signal Vect_3 : std_logic_vector(23 downto 0);
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begin
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process(clk,raz)
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begin
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if(raz='0')then
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Vect_1 <= (others => '0');
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Vect_2 <= (others => '0');
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Vect_3 <= (others => '0');
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rdy_reg <= '1';
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sclk_reg <= '0';
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ect <= e0;
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cpt <= 0;
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bit <= '0';
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elsif(clk'event and clk='1')then
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rdy_reg <= RDY;
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sclk_reg <= sclk;
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case ect is
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when e0 =>
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if(rdy_reg='0' and RDY='1')then
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ect <= e1;
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else
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ect <= e0;
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end if;
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when e1 =>
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bit <= '0';
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if(sclk_reg='0' and sclk='1')then
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Vect_1 <= Vect_1(22 downto 0) & In1;
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Vect_2 <= Vect_2(22 downto 0) & In2;
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Vect_3 <= Vect_3(22 downto 0) & In3;
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if(cpt=23)then
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cpt <= 0;
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bit <= '1';
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ect <= e0;
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else
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cpt <= cpt + 1;
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ect <= e2;
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end if;
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end if;
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when e2 =>
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bit <= '0';
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if(sclk_reg='0' and sclk='1')then
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Vect_1 <= Vect_1(22 downto 0) & In1;
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Vect_2 <= Vect_2(22 downto 0) & In2;
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Vect_3 <= Vect_3(22 downto 0) & In3;
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if(cpt=23)then
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cpt <= 0;
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bit <= '1';
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ect <= e0;
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else
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cpt <= cpt + 1;
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ect <= e1;
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end if;
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end if;
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end case;
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end if;
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end process;
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Vector_1 <= Vect_1;
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Vector_2 <= Vect_2;
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Vector_3 <= Vect_3;
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end ar_Vectorize;
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